13b218baaSKrzysztof Kozlowski# SPDX-License-Identifier: GPL-2.0 2cdb1e8b4SKrzysztof Kozlowskiconfig CLK_INTEL_SOCFPGA 3cdb1e8b4SKrzysztof Kozlowski bool "Intel SoCFPGA family clock support" if COMPILE_TEST && !ARCH_INTEL_SOCFPGA 4cdb1e8b4SKrzysztof Kozlowski default ARCH_INTEL_SOCFPGA 5cdb1e8b4SKrzysztof Kozlowski help 6cdb1e8b4SKrzysztof Kozlowski Support for the clock controllers present on Intel SoCFPGA and eASIC 7*55241865SKrzysztof Kozlowski devices like Aria, Cyclone, Stratix 10, Agilex and N5X eASIC. 8cdb1e8b4SKrzysztof Kozlowski 9cdb1e8b4SKrzysztof Kozlowskiif CLK_INTEL_SOCFPGA 10cdb1e8b4SKrzysztof Kozlowski 11*55241865SKrzysztof Kozlowskiconfig CLK_INTEL_SOCFPGA32 12*55241865SKrzysztof Kozlowski bool "Intel Aria / Cyclone clock controller support" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 13*55241865SKrzysztof Kozlowski default ARM && ARCH_INTEL_SOCFPGA 14*55241865SKrzysztof Kozlowski 153b218baaSKrzysztof Kozlowskiconfig CLK_INTEL_SOCFPGA64 16cdb1e8b4SKrzysztof Kozlowski bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA) 174a9a1a56SKrzysztof Kozlowski default ARM64 && ARCH_INTEL_SOCFPGA 18cdb1e8b4SKrzysztof Kozlowski 19cdb1e8b4SKrzysztof Kozlowskiendif # CLK_INTEL_SOCFPGA 20