1 /*
2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3  * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
4  *
5  * Based on clock drivers for S3C64xx and Exynos4 SoCs.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  * Common Clock Framework support for all S5PC110/S5PV210 SoCs.
12  */
13 
14 #include <linux/clk-provider.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/syscore_ops.h>
18 
19 #include "clk.h"
20 #include "clk-pll.h"
21 
22 #include <dt-bindings/clock/s5pv210.h>
23 
24 /* S5PC110/S5PV210 clock controller register offsets */
25 #define APLL_LOCK		0x0000
26 #define MPLL_LOCK		0x0008
27 #define EPLL_LOCK		0x0010
28 #define VPLL_LOCK		0x0020
29 #define APLL_CON0		0x0100
30 #define APLL_CON1		0x0104
31 #define MPLL_CON		0x0108
32 #define EPLL_CON0		0x0110
33 #define EPLL_CON1		0x0114
34 #define VPLL_CON		0x0120
35 #define CLK_SRC0		0x0200
36 #define CLK_SRC1		0x0204
37 #define CLK_SRC2		0x0208
38 #define CLK_SRC3		0x020c
39 #define CLK_SRC4		0x0210
40 #define CLK_SRC5		0x0214
41 #define CLK_SRC6		0x0218
42 #define CLK_SRC_MASK0		0x0280
43 #define CLK_SRC_MASK1		0x0284
44 #define CLK_DIV0		0x0300
45 #define CLK_DIV1		0x0304
46 #define CLK_DIV2		0x0308
47 #define CLK_DIV3		0x030c
48 #define CLK_DIV4		0x0310
49 #define CLK_DIV5		0x0314
50 #define CLK_DIV6		0x0318
51 #define CLK_DIV7		0x031c
52 #define CLK_GATE_MAIN0		0x0400
53 #define CLK_GATE_MAIN1		0x0404
54 #define CLK_GATE_MAIN2		0x0408
55 #define CLK_GATE_PERI0		0x0420
56 #define CLK_GATE_PERI1		0x0424
57 #define CLK_GATE_SCLK0		0x0440
58 #define CLK_GATE_SCLK1		0x0444
59 #define CLK_GATE_IP0		0x0460
60 #define CLK_GATE_IP1		0x0464
61 #define CLK_GATE_IP2		0x0468
62 #define CLK_GATE_IP3		0x046c
63 #define CLK_GATE_IP4		0x0470
64 #define CLK_GATE_BLOCK		0x0480
65 #define CLK_GATE_IP5		0x0484
66 #define CLK_OUT			0x0500
67 #define MISC			0xe000
68 #define OM_STAT			0xe100
69 
70 /* IDs of PLLs available on S5PV210/S5P6442 SoCs */
71 enum {
72 	apll,
73 	mpll,
74 	epll,
75 	vpll,
76 };
77 
78 /* IDs of external clocks (used for legacy boards) */
79 enum {
80 	xxti,
81 	xusbxti,
82 };
83 
84 static void __iomem *reg_base;
85 
86 #ifdef CONFIG_PM_SLEEP
87 static struct samsung_clk_reg_dump *s5pv210_clk_dump;
88 
89 /* List of registers that need to be preserved across suspend/resume. */
90 static unsigned long s5pv210_clk_regs[] __initdata = {
91 	CLK_SRC0,
92 	CLK_SRC1,
93 	CLK_SRC2,
94 	CLK_SRC3,
95 	CLK_SRC4,
96 	CLK_SRC5,
97 	CLK_SRC6,
98 	CLK_SRC_MASK0,
99 	CLK_SRC_MASK1,
100 	CLK_DIV0,
101 	CLK_DIV1,
102 	CLK_DIV2,
103 	CLK_DIV3,
104 	CLK_DIV4,
105 	CLK_DIV5,
106 	CLK_DIV6,
107 	CLK_DIV7,
108 	CLK_GATE_MAIN0,
109 	CLK_GATE_MAIN1,
110 	CLK_GATE_MAIN2,
111 	CLK_GATE_PERI0,
112 	CLK_GATE_PERI1,
113 	CLK_GATE_SCLK0,
114 	CLK_GATE_SCLK1,
115 	CLK_GATE_IP0,
116 	CLK_GATE_IP1,
117 	CLK_GATE_IP2,
118 	CLK_GATE_IP3,
119 	CLK_GATE_IP4,
120 	CLK_GATE_IP5,
121 	CLK_GATE_BLOCK,
122 	APLL_LOCK,
123 	MPLL_LOCK,
124 	EPLL_LOCK,
125 	VPLL_LOCK,
126 	APLL_CON0,
127 	APLL_CON1,
128 	MPLL_CON,
129 	EPLL_CON0,
130 	EPLL_CON1,
131 	VPLL_CON,
132 	CLK_OUT,
133 };
134 
135 static int s5pv210_clk_suspend(void)
136 {
137 	samsung_clk_save(reg_base, s5pv210_clk_dump,
138 				ARRAY_SIZE(s5pv210_clk_regs));
139 	return 0;
140 }
141 
142 static void s5pv210_clk_resume(void)
143 {
144 	samsung_clk_restore(reg_base, s5pv210_clk_dump,
145 				ARRAY_SIZE(s5pv210_clk_regs));
146 }
147 
148 static struct syscore_ops s5pv210_clk_syscore_ops = {
149 	.suspend = s5pv210_clk_suspend,
150 	.resume = s5pv210_clk_resume,
151 };
152 
153 static void s5pv210_clk_sleep_init(void)
154 {
155 	s5pv210_clk_dump =
156 		samsung_clk_alloc_reg_dump(s5pv210_clk_regs,
157 					   ARRAY_SIZE(s5pv210_clk_regs));
158 	if (!s5pv210_clk_dump) {
159 		pr_warn("%s: Failed to allocate sleep save data\n", __func__);
160 		return;
161 	}
162 
163 	register_syscore_ops(&s5pv210_clk_syscore_ops);
164 }
165 #else
166 static inline void s5pv210_clk_sleep_init(void) { }
167 #endif
168 
169 /* Mux parent lists. */
170 static const char *const fin_pll_p[] __initconst = {
171 	"xxti",
172 	"xusbxti"
173 };
174 
175 static const char *const mout_apll_p[] __initconst = {
176 	"fin_pll",
177 	"fout_apll"
178 };
179 
180 static const char *const mout_mpll_p[] __initconst = {
181 	"fin_pll",
182 	"fout_mpll"
183 };
184 
185 static const char *const mout_epll_p[] __initconst = {
186 	"fin_pll",
187 	"fout_epll"
188 };
189 
190 static const char *const mout_vpllsrc_p[] __initconst = {
191 	"fin_pll",
192 	"sclk_hdmi27m"
193 };
194 
195 static const char *const mout_vpll_p[] __initconst = {
196 	"mout_vpllsrc",
197 	"fout_vpll"
198 };
199 
200 static const char *const mout_group1_p[] __initconst = {
201 	"dout_a2m",
202 	"mout_mpll",
203 	"mout_epll",
204 	"mout_vpll"
205 };
206 
207 static const char *const mout_group2_p[] __initconst = {
208 	"xxti",
209 	"xusbxti",
210 	"sclk_hdmi27m",
211 	"sclk_usbphy0",
212 	"sclk_usbphy1",
213 	"sclk_hdmiphy",
214 	"mout_mpll",
215 	"mout_epll",
216 	"mout_vpll",
217 };
218 
219 static const char *const mout_audio0_p[] __initconst = {
220 	"xxti",
221 	"pcmcdclk0",
222 	"sclk_hdmi27m",
223 	"sclk_usbphy0",
224 	"sclk_usbphy1",
225 	"sclk_hdmiphy",
226 	"mout_mpll",
227 	"mout_epll",
228 	"mout_vpll",
229 };
230 
231 static const char *const mout_audio1_p[] __initconst = {
232 	"i2scdclk1",
233 	"pcmcdclk1",
234 	"sclk_hdmi27m",
235 	"sclk_usbphy0",
236 	"sclk_usbphy1",
237 	"sclk_hdmiphy",
238 	"mout_mpll",
239 	"mout_epll",
240 	"mout_vpll",
241 };
242 
243 static const char *const mout_audio2_p[] __initconst = {
244 	"i2scdclk2",
245 	"pcmcdclk2",
246 	"sclk_hdmi27m",
247 	"sclk_usbphy0",
248 	"sclk_usbphy1",
249 	"sclk_hdmiphy",
250 	"mout_mpll",
251 	"mout_epll",
252 	"mout_vpll",
253 };
254 
255 static const char *const mout_spdif_p[] __initconst = {
256 	"dout_audio0",
257 	"dout_audio1",
258 	"dout_audio3",
259 };
260 
261 static const char *const mout_group3_p[] __initconst = {
262 	"mout_apll",
263 	"mout_mpll"
264 };
265 
266 static const char *const mout_group4_p[] __initconst = {
267 	"mout_mpll",
268 	"dout_a2m"
269 };
270 
271 static const char *const mout_flash_p[] __initconst = {
272 	"dout_hclkd",
273 	"dout_hclkp"
274 };
275 
276 static const char *const mout_dac_p[] __initconst = {
277 	"mout_vpll",
278 	"sclk_hdmiphy"
279 };
280 
281 static const char *const mout_hdmi_p[] __initconst = {
282 	"sclk_hdmiphy",
283 	"dout_tblk"
284 };
285 
286 static const char *const mout_mixer_p[] __initconst = {
287 	"mout_dac",
288 	"mout_hdmi"
289 };
290 
291 static const char *const mout_vpll_6442_p[] __initconst = {
292 	"fin_pll",
293 	"fout_vpll"
294 };
295 
296 static const char *const mout_mixer_6442_p[] __initconst = {
297 	"mout_vpll",
298 	"dout_mixer"
299 };
300 
301 static const char *const mout_d0sync_6442_p[] __initconst = {
302 	"mout_dsys",
303 	"div_apll"
304 };
305 
306 static const char *const mout_d1sync_6442_p[] __initconst = {
307 	"mout_psys",
308 	"div_apll"
309 };
310 
311 static const char *const mout_group2_6442_p[] __initconst = {
312 	"fin_pll",
313 	"none",
314 	"none",
315 	"sclk_usbphy0",
316 	"none",
317 	"none",
318 	"mout_mpll",
319 	"mout_epll",
320 	"mout_vpll",
321 };
322 
323 static const char *const mout_audio0_6442_p[] __initconst = {
324 	"fin_pll",
325 	"pcmcdclk0",
326 	"none",
327 	"sclk_usbphy0",
328 	"none",
329 	"none",
330 	"mout_mpll",
331 	"mout_epll",
332 	"mout_vpll",
333 };
334 
335 static const char *const mout_audio1_6442_p[] __initconst = {
336 	"i2scdclk1",
337 	"pcmcdclk1",
338 	"none",
339 	"sclk_usbphy0",
340 	"none",
341 	"none",
342 	"mout_mpll",
343 	"mout_epll",
344 	"mout_vpll",
345 	"fin_pll",
346 };
347 
348 static const char *const mout_clksel_p[] __initconst = {
349 	"fout_apll_clkout",
350 	"fout_mpll_clkout",
351 	"fout_epll",
352 	"fout_vpll",
353 	"sclk_usbphy0",
354 	"sclk_usbphy1",
355 	"sclk_hdmiphy",
356 	"rtc",
357 	"rtc_tick",
358 	"dout_hclkm",
359 	"dout_pclkm",
360 	"dout_hclkd",
361 	"dout_pclkd",
362 	"dout_hclkp",
363 	"dout_pclkp",
364 	"dout_apll_clkout",
365 	"dout_hpm",
366 	"xxti",
367 	"xusbxti",
368 	"div_dclk"
369 };
370 
371 static const char *const mout_clksel_6442_p[] __initconst = {
372 	"fout_apll_clkout",
373 	"fout_mpll_clkout",
374 	"fout_epll",
375 	"fout_vpll",
376 	"sclk_usbphy0",
377 	"none",
378 	"none",
379 	"rtc",
380 	"rtc_tick",
381 	"none",
382 	"none",
383 	"dout_hclkd",
384 	"dout_pclkd",
385 	"dout_hclkp",
386 	"dout_pclkp",
387 	"dout_apll_clkout",
388 	"none",
389 	"fin_pll",
390 	"none",
391 	"div_dclk"
392 };
393 
394 static const char *const mout_clkout_p[] __initconst = {
395 	"dout_clkout",
396 	"none",
397 	"xxti",
398 	"xusbxti"
399 };
400 
401 /* Common fixed factor clocks. */
402 static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = {
403 	FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0),
404 	FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0),
405 	FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0),
406 };
407 
408 /* PLL input mux (fin_pll), which needs to be registered before PLLs. */
409 static const struct samsung_mux_clock early_mux_clks[] __initconst = {
410 	MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1,
411 					CLK_MUX_READ_ONLY, 0),
412 };
413 
414 /* Common clock muxes. */
415 static const struct samsung_mux_clock mux_clks[] __initconst = {
416 	MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1),
417 	MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1),
418 	MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1),
419 	MUX(MOUT_MSYS, "mout_msys", mout_group3_p, CLK_SRC0, 16, 1),
420 	MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1),
421 	MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1),
422 	MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1),
423 
424 	MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2),
425 };
426 
427 /* S5PV210-specific clock muxes. */
428 static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = {
429 	MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1),
430 
431 	MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1),
432 	MUX(MOUT_CSIS, "mout_csis", mout_group2_p, CLK_SRC1, 24, 4),
433 	MUX(MOUT_FIMD, "mout_fimd", mout_group2_p, CLK_SRC1, 20, 4),
434 	MUX(MOUT_CAM1, "mout_cam1", mout_group2_p, CLK_SRC1, 16, 4),
435 	MUX(MOUT_CAM0, "mout_cam0", mout_group2_p, CLK_SRC1, 12, 4),
436 	MUX(MOUT_DAC, "mout_dac", mout_dac_p, CLK_SRC1, 8, 1),
437 	MUX(MOUT_MIXER, "mout_mixer", mout_mixer_p, CLK_SRC1, 4, 1),
438 	MUX(MOUT_HDMI, "mout_hdmi", mout_hdmi_p, CLK_SRC1, 0, 1),
439 
440 	MUX(MOUT_G2D, "mout_g2d", mout_group1_p, CLK_SRC2, 8, 2),
441 	MUX(MOUT_MFC, "mout_mfc", mout_group1_p, CLK_SRC2, 4, 2),
442 	MUX(MOUT_G3D, "mout_g3d", mout_group1_p, CLK_SRC2, 0, 2),
443 
444 	MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_p, CLK_SRC3, 20, 4),
445 	MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_p, CLK_SRC3, 16, 4),
446 	MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_p, CLK_SRC3, 12, 4),
447 
448 	MUX(MOUT_UART3, "mout_uart3", mout_group2_p, CLK_SRC4, 28, 4),
449 	MUX(MOUT_UART2, "mout_uart2", mout_group2_p, CLK_SRC4, 24, 4),
450 	MUX(MOUT_UART1, "mout_uart1", mout_group2_p, CLK_SRC4, 20, 4),
451 	MUX(MOUT_UART0, "mout_uart0", mout_group2_p, CLK_SRC4, 16, 4),
452 	MUX(MOUT_MMC3, "mout_mmc3", mout_group2_p, CLK_SRC4, 12, 4),
453 	MUX(MOUT_MMC2, "mout_mmc2", mout_group2_p, CLK_SRC4, 8, 4),
454 	MUX(MOUT_MMC1, "mout_mmc1", mout_group2_p, CLK_SRC4, 4, 4),
455 	MUX(MOUT_MMC0, "mout_mmc0", mout_group2_p, CLK_SRC4, 0, 4),
456 
457 	MUX(MOUT_PWM, "mout_pwm", mout_group2_p, CLK_SRC5, 12, 4),
458 	MUX(MOUT_SPI1, "mout_spi1", mout_group2_p, CLK_SRC5, 4, 4),
459 	MUX(MOUT_SPI0, "mout_spi0", mout_group2_p, CLK_SRC5, 0, 4),
460 
461 	MUX(MOUT_DMC0, "mout_dmc0", mout_group1_p, CLK_SRC6, 24, 2),
462 	MUX(MOUT_PWI, "mout_pwi", mout_group2_p, CLK_SRC6, 20, 4),
463 	MUX(MOUT_HPM, "mout_hpm", mout_group3_p, CLK_SRC6, 16, 1),
464 	MUX(MOUT_SPDIF, "mout_spdif", mout_spdif_p, CLK_SRC6, 12, 2),
465 	MUX(MOUT_AUDIO2, "mout_audio2", mout_audio2_p, CLK_SRC6, 8, 4),
466 	MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_p, CLK_SRC6, 4, 4),
467 	MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_p, CLK_SRC6, 0, 4),
468 
469 	MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_p, CLK_OUT, 12, 5),
470 };
471 
472 /* S5P6442-specific clock muxes. */
473 static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = {
474 	MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1),
475 
476 	MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4),
477 	MUX(MOUT_CAM1, "mout_cam1", mout_group2_6442_p, CLK_SRC1, 16, 4),
478 	MUX(MOUT_CAM0, "mout_cam0", mout_group2_6442_p, CLK_SRC1, 12, 4),
479 	MUX(MOUT_MIXER, "mout_mixer", mout_mixer_6442_p, CLK_SRC1, 4, 1),
480 
481 	MUX(MOUT_D0SYNC, "mout_d0sync", mout_d0sync_6442_p, CLK_SRC2, 28, 1),
482 	MUX(MOUT_D1SYNC, "mout_d1sync", mout_d1sync_6442_p, CLK_SRC2, 24, 1),
483 
484 	MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_6442_p, CLK_SRC3, 20, 4),
485 	MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_6442_p, CLK_SRC3, 16, 4),
486 	MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_6442_p, CLK_SRC3, 12, 4),
487 
488 	MUX(MOUT_UART2, "mout_uart2", mout_group2_6442_p, CLK_SRC4, 24, 4),
489 	MUX(MOUT_UART1, "mout_uart1", mout_group2_6442_p, CLK_SRC4, 20, 4),
490 	MUX(MOUT_UART0, "mout_uart0", mout_group2_6442_p, CLK_SRC4, 16, 4),
491 	MUX(MOUT_MMC2, "mout_mmc2", mout_group2_6442_p, CLK_SRC4, 8, 4),
492 	MUX(MOUT_MMC1, "mout_mmc1", mout_group2_6442_p, CLK_SRC4, 4, 4),
493 	MUX(MOUT_MMC0, "mout_mmc0", mout_group2_6442_p, CLK_SRC4, 0, 4),
494 
495 	MUX(MOUT_PWM, "mout_pwm", mout_group2_6442_p, CLK_SRC5, 12, 4),
496 	MUX(MOUT_SPI0, "mout_spi0", mout_group2_6442_p, CLK_SRC5, 0, 4),
497 
498 	MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_6442_p, CLK_SRC6, 4, 4),
499 	MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_6442_p, CLK_SRC6, 0, 4),
500 
501 	MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_6442_p, CLK_OUT, 12, 5),
502 };
503 
504 /* S5PV210-specific fixed rate clocks generated inside the SoC. */
505 static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = {
506 	FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
507 	FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
508 	FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
509 	FRATE(SCLK_USBPHY1, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
510 };
511 
512 /* S5P6442-specific fixed rate clocks generated inside the SoC. */
513 static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = {
514 	FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 30000000),
515 };
516 
517 /* Common clock dividers. */
518 static const struct samsung_div_clock div_clks[] __initconst = {
519 	DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3),
520 	DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3),
521 	DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3),
522 	DIV(DOUT_APLL, "dout_apll", "mout_msys", CLK_DIV0, 0, 3),
523 
524 	DIV(DOUT_FIMD, "dout_fimd", "mout_fimd", CLK_DIV1, 20, 4),
525 	DIV(DOUT_CAM1, "dout_cam1", "mout_cam1", CLK_DIV1, 16, 4),
526 	DIV(DOUT_CAM0, "dout_cam0", "mout_cam0", CLK_DIV1, 12, 4),
527 
528 	DIV(DOUT_FIMC2, "dout_fimc2", "mout_fimc2", CLK_DIV3, 20, 4),
529 	DIV(DOUT_FIMC1, "dout_fimc1", "mout_fimc1", CLK_DIV3, 16, 4),
530 	DIV(DOUT_FIMC0, "dout_fimc0", "mout_fimc0", CLK_DIV3, 12, 4),
531 
532 	DIV(DOUT_UART2, "dout_uart2", "mout_uart2", CLK_DIV4, 24, 4),
533 	DIV(DOUT_UART1, "dout_uart1", "mout_uart1", CLK_DIV4, 20, 4),
534 	DIV(DOUT_UART0, "dout_uart0", "mout_uart0", CLK_DIV4, 16, 4),
535 	DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV4, 8, 4),
536 	DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV4, 4, 4),
537 	DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV4, 0, 4),
538 
539 	DIV(DOUT_PWM, "dout_pwm", "mout_pwm", CLK_DIV5, 12, 4),
540 	DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV5, 0, 4),
541 
542 	DIV(DOUT_FLASH, "dout_flash", "mout_flash", CLK_DIV6, 12, 3),
543 	DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV6, 4, 4),
544 	DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV6, 0, 4),
545 
546 	DIV(DOUT_CLKOUT, "dout_clkout", "mout_clksel", CLK_OUT, 20, 4),
547 };
548 
549 /* S5PV210-specific clock dividers. */
550 static const struct samsung_div_clock s5pv210_div_clks[] __initconst = {
551 	DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4),
552 	DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4),
553 	DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3),
554 	DIV(DOUT_HCLKM, "dout_hclkm", "dout_apll", CLK_DIV0, 8, 3),
555 
556 	DIV(DOUT_CSIS, "dout_csis", "mout_csis", CLK_DIV1, 28, 4),
557 	DIV(DOUT_TBLK, "dout_tblk", "mout_vpll", CLK_DIV1, 0, 4),
558 
559 	DIV(DOUT_G2D, "dout_g2d", "mout_g2d", CLK_DIV2, 8, 4),
560 	DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV2, 4, 4),
561 	DIV(DOUT_G3D, "dout_g3d", "mout_g3d", CLK_DIV2, 0, 4),
562 
563 	DIV(DOUT_UART3, "dout_uart3", "mout_uart3", CLK_DIV4, 28, 4),
564 	DIV(DOUT_MMC3, "dout_mmc3", "mout_mmc3", CLK_DIV4, 12, 4),
565 
566 	DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV5, 4, 4),
567 
568 	DIV(DOUT_DMC0, "dout_dmc0", "mout_dmc0", CLK_DIV6, 28, 4),
569 	DIV(DOUT_PWI, "dout_pwi", "mout_pwi", CLK_DIV6, 24, 4),
570 	DIV(DOUT_HPM, "dout_hpm", "dout_copy", CLK_DIV6, 20, 3),
571 	DIV(DOUT_COPY, "dout_copy", "mout_hpm", CLK_DIV6, 16, 3),
572 	DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV6, 8, 4),
573 
574 	DIV(DOUT_DPM, "dout_dpm", "dout_pclkp", CLK_DIV7, 8, 7),
575 	DIV(DOUT_DVSEM, "dout_dvsem", "dout_pclkp", CLK_DIV7, 0, 7),
576 };
577 
578 /* S5P6442-specific clock dividers. */
579 static const struct samsung_div_clock s5p6442_div_clks[] __initconst = {
580 	DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4),
581 	DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4),
582 
583 	DIV(DOUT_MIXER, "dout_mixer", "mout_vpll", CLK_DIV1, 0, 4),
584 };
585 
586 /* Common clock gates. */
587 static const struct samsung_gate_clock gate_clks[] __initconst = {
588 	GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0),
589 	GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0),
590 	GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0),
591 	GATE(CLK_FIMC0, "fimc0", "dout_hclkd", CLK_GATE_IP0, 24, 0, 0),
592 	GATE(CLK_PDMA0, "pdma0", "dout_hclkp", CLK_GATE_IP0, 3, 0, 0),
593 	GATE(CLK_MDMA, "mdma", "dout_hclkd", CLK_GATE_IP0, 2, 0, 0),
594 
595 	GATE(CLK_SROMC, "sromc", "dout_hclkp", CLK_GATE_IP1, 26, 0, 0),
596 	GATE(CLK_NANDXL, "nandxl", "dout_hclkp", CLK_GATE_IP1, 24, 0, 0),
597 	GATE(CLK_USB_OTG, "usb_otg", "dout_hclkp", CLK_GATE_IP1, 16, 0, 0),
598 	GATE(CLK_TVENC, "tvenc", "dout_hclkd", CLK_GATE_IP1, 10, 0, 0),
599 	GATE(CLK_MIXER, "mixer", "dout_hclkd", CLK_GATE_IP1, 9, 0, 0),
600 	GATE(CLK_VP, "vp", "dout_hclkd", CLK_GATE_IP1, 8, 0, 0),
601 	GATE(CLK_FIMD, "fimd", "dout_hclkd", CLK_GATE_IP1, 0, 0, 0),
602 
603 	GATE(CLK_HSMMC2, "hsmmc2", "dout_hclkp", CLK_GATE_IP2, 18, 0, 0),
604 	GATE(CLK_HSMMC1, "hsmmc1", "dout_hclkp", CLK_GATE_IP2, 17, 0, 0),
605 	GATE(CLK_HSMMC0, "hsmmc0", "dout_hclkp", CLK_GATE_IP2, 16, 0, 0),
606 	GATE(CLK_MODEMIF, "modemif", "dout_hclkp", CLK_GATE_IP2, 9, 0, 0),
607 	GATE(CLK_SECSS, "secss", "dout_hclkp", CLK_GATE_IP2, 0, 0, 0),
608 
609 	GATE(CLK_PCM1, "pcm1", "dout_pclkp", CLK_GATE_IP3, 29, 0, 0),
610 	GATE(CLK_PCM0, "pcm0", "dout_pclkp", CLK_GATE_IP3, 28, 0, 0),
611 	GATE(CLK_TSADC, "tsadc", "dout_pclkp", CLK_GATE_IP3, 24, 0, 0),
612 	GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0),
613 	GATE(CLK_WDT, "watchdog", "dout_pclkp", CLK_GATE_IP3, 22, 0, 0),
614 	GATE(CLK_KEYIF, "keyif", "dout_pclkp", CLK_GATE_IP3, 21, 0, 0),
615 	GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0),
616 	GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0),
617 	GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0),
618 	GATE(CLK_SYSTIMER, "systimer", "dout_pclkp", CLK_GATE_IP3, 16, 0, 0),
619 	GATE(CLK_RTC, "rtc", "dout_pclkp", CLK_GATE_IP3, 15, 0, 0),
620 	GATE(CLK_SPI0, "spi0", "dout_pclkp", CLK_GATE_IP3, 12, 0, 0),
621 	GATE(CLK_I2C2, "i2c2", "dout_pclkp", CLK_GATE_IP3, 9, 0, 0),
622 	GATE(CLK_I2C0, "i2c0", "dout_pclkp", CLK_GATE_IP3, 7, 0, 0),
623 	GATE(CLK_I2S1, "i2s1", "dout_pclkp", CLK_GATE_IP3, 5, 0, 0),
624 	GATE(CLK_I2S0, "i2s0", "dout_pclkp", CLK_GATE_IP3, 4, 0, 0),
625 
626 	GATE(CLK_SECKEY, "seckey", "dout_pclkp", CLK_GATE_IP4, 3, 0, 0),
627 	GATE(CLK_CHIPID, "chipid", "dout_pclkp", CLK_GATE_IP4, 0, 0, 0),
628 
629 	GATE(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", CLK_SRC_MASK0, 25,
630 			CLK_SET_RATE_PARENT, 0),
631 	GATE(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", CLK_SRC_MASK0, 24,
632 			CLK_SET_RATE_PARENT, 0),
633 	GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
634 			CLK_SET_RATE_PARENT, 0),
635 	GATE(SCLK_SPI0, "sclk_spi0", "dout_spi0", CLK_SRC_MASK0, 16,
636 			CLK_SET_RATE_PARENT, 0),
637 	GATE(SCLK_UART2, "sclk_uart2", "dout_uart2", CLK_SRC_MASK0, 14,
638 			CLK_SET_RATE_PARENT, 0),
639 	GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13,
640 			CLK_SET_RATE_PARENT, 0),
641 	GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12,
642 			CLK_SET_RATE_PARENT, 0),
643 	GATE(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", CLK_SRC_MASK0, 10,
644 			CLK_SET_RATE_PARENT, 0),
645 	GATE(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", CLK_SRC_MASK0, 9,
646 			CLK_SET_RATE_PARENT, 0),
647 	GATE(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", CLK_SRC_MASK0, 8,
648 			CLK_SET_RATE_PARENT, 0),
649 	GATE(SCLK_FIMD, "sclk_fimd", "dout_fimd", CLK_SRC_MASK0, 5,
650 			CLK_SET_RATE_PARENT, 0),
651 	GATE(SCLK_CAM1, "sclk_cam1", "dout_cam1", CLK_SRC_MASK0, 4,
652 			CLK_SET_RATE_PARENT, 0),
653 	GATE(SCLK_CAM0, "sclk_cam0", "dout_cam0", CLK_SRC_MASK0, 3,
654 			CLK_SET_RATE_PARENT, 0),
655 	GATE(SCLK_MIXER, "sclk_mixer", "mout_mixer", CLK_SRC_MASK0, 1,
656 			CLK_SET_RATE_PARENT, 0),
657 
658 	GATE(SCLK_FIMC2, "sclk_fimc2", "dout_fimc2", CLK_SRC_MASK1, 4,
659 			CLK_SET_RATE_PARENT, 0),
660 	GATE(SCLK_FIMC1, "sclk_fimc1", "dout_fimc1", CLK_SRC_MASK1, 3,
661 			CLK_SET_RATE_PARENT, 0),
662 	GATE(SCLK_FIMC0, "sclk_fimc0", "dout_fimc0", CLK_SRC_MASK1, 2,
663 			CLK_SET_RATE_PARENT, 0),
664 };
665 
666 /* S5PV210-specific clock gates. */
667 static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = {
668 	GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0),
669 	GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0),
670 	GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
671 	GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0),
672 	GATE(CLK_IMEM, "imem", "dout_hclkm", CLK_GATE_IP0, 5, 0, 0),
673 	GATE(CLK_PDMA1, "pdma1", "dout_hclkp", CLK_GATE_IP0, 4, 0, 0),
674 
675 	GATE(CLK_NFCON, "nfcon", "dout_hclkp", CLK_GATE_IP1, 28, 0, 0),
676 	GATE(CLK_CFCON, "cfcon", "dout_hclkp", CLK_GATE_IP1, 25, 0, 0),
677 	GATE(CLK_USB_HOST, "usb_host", "dout_hclkp", CLK_GATE_IP1, 17, 0, 0),
678 	GATE(CLK_HDMI, "hdmi", "dout_hclkd", CLK_GATE_IP1, 11, 0, 0),
679 	GATE(CLK_DSIM, "dsim", "dout_pclkd", CLK_GATE_IP1, 2, 0, 0),
680 
681 	GATE(CLK_TZIC3, "tzic3", "dout_hclkm", CLK_GATE_IP2, 31, 0, 0),
682 	GATE(CLK_TZIC2, "tzic2", "dout_hclkm", CLK_GATE_IP2, 30, 0, 0),
683 	GATE(CLK_TZIC1, "tzic1", "dout_hclkm", CLK_GATE_IP2, 29, 0, 0),
684 	GATE(CLK_TZIC0, "tzic0", "dout_hclkm", CLK_GATE_IP2, 28, 0, 0),
685 	GATE(CLK_TSI, "tsi", "dout_hclkd", CLK_GATE_IP2, 20, 0, 0),
686 	GATE(CLK_HSMMC3, "hsmmc3", "dout_hclkp", CLK_GATE_IP2, 19, 0, 0),
687 	GATE(CLK_JTAG, "jtag", "dout_hclkp", CLK_GATE_IP2, 11, 0, 0),
688 	GATE(CLK_CORESIGHT, "coresight", "dout_pclkp", CLK_GATE_IP2, 8, 0, 0),
689 	GATE(CLK_SDM, "sdm", "dout_pclkm", CLK_GATE_IP2, 1, 0, 0),
690 
691 	GATE(CLK_PCM2, "pcm2", "dout_pclkp", CLK_GATE_IP3, 30, 0, 0),
692 	GATE(CLK_UART3, "uart3", "dout_pclkp", CLK_GATE_IP3, 20, 0, 0),
693 	GATE(CLK_SPI1, "spi1", "dout_pclkp", CLK_GATE_IP3, 13, 0, 0),
694 	GATE(CLK_I2C_HDMI_PHY, "i2c_hdmi_phy", "dout_pclkd",
695 			CLK_GATE_IP3, 11, 0, 0),
696 	GATE(CLK_I2C1, "i2c1", "dout_pclkd", CLK_GATE_IP3, 10, 0, 0),
697 	GATE(CLK_I2S2, "i2s2", "dout_pclkp", CLK_GATE_IP3, 6, 0, 0),
698 	GATE(CLK_AC97, "ac97", "dout_pclkp", CLK_GATE_IP3, 1, 0, 0),
699 	GATE(CLK_SPDIF, "spdif", "dout_pclkp", CLK_GATE_IP3, 0, 0, 0),
700 
701 	GATE(CLK_TZPC3, "tzpc.3", "dout_pclkd", CLK_GATE_IP4, 8, 0, 0),
702 	GATE(CLK_TZPC2, "tzpc.2", "dout_pclkd", CLK_GATE_IP4, 7, 0, 0),
703 	GATE(CLK_TZPC1, "tzpc.1", "dout_pclkp", CLK_GATE_IP4, 6, 0, 0),
704 	GATE(CLK_TZPC0, "tzpc.0", "dout_pclkm", CLK_GATE_IP4, 5, 0, 0),
705 	GATE(CLK_IEM_APC, "iem_apc", "dout_pclkp", CLK_GATE_IP4, 2, 0, 0),
706 	GATE(CLK_IEM_IEC, "iem_iec", "dout_pclkp", CLK_GATE_IP4, 1, 0, 0),
707 
708 	GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP5, 29, 0, 0),
709 
710 	GATE(SCLK_SPDIF, "sclk_spdif", "mout_spdif", CLK_SRC_MASK0, 27,
711 			CLK_SET_RATE_PARENT, 0),
712 	GATE(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", CLK_SRC_MASK0, 26,
713 			CLK_SET_RATE_PARENT, 0),
714 	GATE(SCLK_SPI1, "sclk_spi1", "dout_spi1", CLK_SRC_MASK0, 17,
715 			CLK_SET_RATE_PARENT, 0),
716 	GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15,
717 			CLK_SET_RATE_PARENT, 0),
718 	GATE(SCLK_MMC3, "sclk_mmc3", "dout_mmc3", CLK_SRC_MASK0, 11,
719 			CLK_SET_RATE_PARENT, 0),
720 	GATE(SCLK_CSIS, "sclk_csis", "dout_csis", CLK_SRC_MASK0, 6,
721 			CLK_SET_RATE_PARENT, 0),
722 	GATE(SCLK_DAC, "sclk_dac", "mout_dac", CLK_SRC_MASK0, 2,
723 			CLK_SET_RATE_PARENT, 0),
724 	GATE(SCLK_HDMI, "sclk_hdmi", "mout_hdmi", CLK_SRC_MASK0, 0,
725 			CLK_SET_RATE_PARENT, 0),
726 };
727 
728 /* S5P6442-specific clock gates. */
729 static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = {
730 	GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0),
731 	GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0),
732 	GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
733 	GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0),
734 	GATE(CLK_IMEM, "imem", "dout_hclkd", CLK_GATE_IP0, 5, 0, 0),
735 
736 	GATE(CLK_ETB, "etb", "dout_hclkd", CLK_GATE_IP1, 31, 0, 0),
737 	GATE(CLK_ETM, "etm", "dout_hclkd", CLK_GATE_IP1, 30, 0, 0),
738 
739 	GATE(CLK_I2C1, "i2c1", "dout_pclkp", CLK_GATE_IP3, 8, 0, 0),
740 
741 	GATE(SCLK_DAC, "sclk_dac", "mout_vpll", CLK_SRC_MASK0, 2,
742 			CLK_SET_RATE_PARENT, 0),
743 };
744 
745 /*
746  * Clock aliases for legacy clkdev look-up.
747  * NOTE: Needed only to support legacy board files.
748  */
749 static const struct samsung_clock_alias s5pv210_aliases[] __initconst = {
750 	ALIAS(DOUT_APLL, NULL, "armclk"),
751 	ALIAS(DOUT_HCLKM, NULL, "hclk_msys"),
752 	ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"),
753 };
754 
755 /* S5PV210-specific PLLs. */
756 static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = {
757 	[apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll",
758 						APLL_LOCK, APLL_CON0, NULL),
759 	[mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
760 						MPLL_LOCK, MPLL_CON, NULL),
761 	[epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll",
762 						EPLL_LOCK, EPLL_CON0, NULL),
763 	[vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
764 						VPLL_LOCK, VPLL_CON, NULL),
765 };
766 
767 /* S5P6442-specific PLLs. */
768 static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = {
769 	[apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll",
770 						APLL_LOCK, APLL_CON0, NULL),
771 	[mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
772 						MPLL_LOCK, MPLL_CON, NULL),
773 	[epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll",
774 						EPLL_LOCK, EPLL_CON0, NULL),
775 	[vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll",
776 						VPLL_LOCK, VPLL_CON, NULL),
777 };
778 
779 static void __init __s5pv210_clk_init(struct device_node *np,
780 				      unsigned long xxti_f,
781 				      unsigned long xusbxti_f,
782 				      bool is_s5p6442)
783 {
784 	struct samsung_clk_provider *ctx;
785 
786 	ctx = samsung_clk_init(np, reg_base, NR_CLKS);
787 	if (!ctx)
788 		panic("%s: unable to allocate context.\n", __func__);
789 
790 	samsung_clk_register_mux(ctx, early_mux_clks,
791 					ARRAY_SIZE(early_mux_clks));
792 
793 	if (is_s5p6442) {
794 		samsung_clk_register_fixed_rate(ctx, s5p6442_frate_clks,
795 			ARRAY_SIZE(s5p6442_frate_clks));
796 		samsung_clk_register_pll(ctx, s5p6442_pll_clks,
797 			ARRAY_SIZE(s5p6442_pll_clks), reg_base);
798 		samsung_clk_register_mux(ctx, s5p6442_mux_clks,
799 				ARRAY_SIZE(s5p6442_mux_clks));
800 		samsung_clk_register_div(ctx, s5p6442_div_clks,
801 				ARRAY_SIZE(s5p6442_div_clks));
802 		samsung_clk_register_gate(ctx, s5p6442_gate_clks,
803 				ARRAY_SIZE(s5p6442_gate_clks));
804 	} else {
805 		samsung_clk_register_fixed_rate(ctx, s5pv210_frate_clks,
806 			ARRAY_SIZE(s5pv210_frate_clks));
807 		samsung_clk_register_pll(ctx, s5pv210_pll_clks,
808 			ARRAY_SIZE(s5pv210_pll_clks), reg_base);
809 		samsung_clk_register_mux(ctx, s5pv210_mux_clks,
810 				ARRAY_SIZE(s5pv210_mux_clks));
811 		samsung_clk_register_div(ctx, s5pv210_div_clks,
812 				ARRAY_SIZE(s5pv210_div_clks));
813 		samsung_clk_register_gate(ctx, s5pv210_gate_clks,
814 				ARRAY_SIZE(s5pv210_gate_clks));
815 	}
816 
817 	samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
818 	samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
819 	samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
820 
821 	samsung_clk_register_fixed_factor(ctx, ffactor_clks,
822 						ARRAY_SIZE(ffactor_clks));
823 
824 	samsung_clk_register_alias(ctx, s5pv210_aliases,
825 						ARRAY_SIZE(s5pv210_aliases));
826 
827 	s5pv210_clk_sleep_init();
828 
829 	samsung_clk_of_add_provider(np, ctx);
830 
831 	pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n"
832 		"\tmout_epll = %ld, mout_vpll = %ld\n",
833 		is_s5p6442 ? "S5P6442" : "S5PV210",
834 		_get_rate("mout_apll"), _get_rate("mout_mpll"),
835 		_get_rate("mout_epll"), _get_rate("mout_vpll"));
836 }
837 
838 static void __init s5pv210_clk_dt_init(struct device_node *np)
839 {
840 	reg_base = of_iomap(np, 0);
841 	if (!reg_base)
842 		panic("%s: failed to map registers\n", __func__);
843 
844 	__s5pv210_clk_init(np, 0, 0, false);
845 }
846 CLK_OF_DECLARE(s5pv210_clk, "samsung,s5pv210-clock", s5pv210_clk_dt_init);
847 
848 static void __init s5p6442_clk_dt_init(struct device_node *np)
849 {
850 	reg_base = of_iomap(np, 0);
851 	if (!reg_base)
852 		panic("%s: failed to map registers\n", __func__);
853 
854 	__s5pv210_clk_init(np, 0, 0, true);
855 }
856 CLK_OF_DECLARE(s5p6442_clk, "samsung,s5p6442-clock", s5p6442_clk_dt_init);
857