1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> 4 * 5 * Based on clock drivers for S3C64xx and Exynos4 SoCs. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Common Clock Framework support for all S5PC110/S5PV210 SoCs. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 18 #include "clk.h" 19 #include "clk-pll.h" 20 21 #include <dt-bindings/clock/s5pv210.h> 22 23 /* S5PC110/S5PV210 clock controller register offsets */ 24 #define APLL_LOCK 0x0000 25 #define MPLL_LOCK 0x0008 26 #define EPLL_LOCK 0x0010 27 #define VPLL_LOCK 0x0020 28 #define APLL_CON0 0x0100 29 #define APLL_CON1 0x0104 30 #define MPLL_CON 0x0108 31 #define EPLL_CON0 0x0110 32 #define EPLL_CON1 0x0114 33 #define VPLL_CON 0x0120 34 #define CLK_SRC0 0x0200 35 #define CLK_SRC1 0x0204 36 #define CLK_SRC2 0x0208 37 #define CLK_SRC3 0x020c 38 #define CLK_SRC4 0x0210 39 #define CLK_SRC5 0x0214 40 #define CLK_SRC6 0x0218 41 #define CLK_SRC_MASK0 0x0280 42 #define CLK_SRC_MASK1 0x0284 43 #define CLK_DIV0 0x0300 44 #define CLK_DIV1 0x0304 45 #define CLK_DIV2 0x0308 46 #define CLK_DIV3 0x030c 47 #define CLK_DIV4 0x0310 48 #define CLK_DIV5 0x0314 49 #define CLK_DIV6 0x0318 50 #define CLK_DIV7 0x031c 51 #define CLK_GATE_MAIN0 0x0400 52 #define CLK_GATE_MAIN1 0x0404 53 #define CLK_GATE_MAIN2 0x0408 54 #define CLK_GATE_PERI0 0x0420 55 #define CLK_GATE_PERI1 0x0424 56 #define CLK_GATE_SCLK0 0x0440 57 #define CLK_GATE_SCLK1 0x0444 58 #define CLK_GATE_IP0 0x0460 59 #define CLK_GATE_IP1 0x0464 60 #define CLK_GATE_IP2 0x0468 61 #define CLK_GATE_IP3 0x046c 62 #define CLK_GATE_IP4 0x0470 63 #define CLK_GATE_BLOCK 0x0480 64 #define CLK_GATE_IP5 0x0484 65 #define CLK_OUT 0x0500 66 #define MISC 0xe000 67 #define OM_STAT 0xe100 68 69 /* IDs of PLLs available on S5PV210/S5P6442 SoCs */ 70 enum { 71 apll, 72 mpll, 73 epll, 74 vpll, 75 }; 76 77 /* IDs of external clocks (used for legacy boards) */ 78 enum { 79 xxti, 80 xusbxti, 81 }; 82 83 static void __iomem *reg_base; 84 85 /* List of registers that need to be preserved across suspend/resume. */ 86 static unsigned long s5pv210_clk_regs[] __initdata = { 87 CLK_SRC0, 88 CLK_SRC1, 89 CLK_SRC2, 90 CLK_SRC3, 91 CLK_SRC4, 92 CLK_SRC5, 93 CLK_SRC6, 94 CLK_SRC_MASK0, 95 CLK_SRC_MASK1, 96 CLK_DIV0, 97 CLK_DIV1, 98 CLK_DIV2, 99 CLK_DIV3, 100 CLK_DIV4, 101 CLK_DIV5, 102 CLK_DIV6, 103 CLK_DIV7, 104 CLK_GATE_MAIN0, 105 CLK_GATE_MAIN1, 106 CLK_GATE_MAIN2, 107 CLK_GATE_PERI0, 108 CLK_GATE_PERI1, 109 CLK_GATE_SCLK0, 110 CLK_GATE_SCLK1, 111 CLK_GATE_IP0, 112 CLK_GATE_IP1, 113 CLK_GATE_IP2, 114 CLK_GATE_IP3, 115 CLK_GATE_IP4, 116 CLK_GATE_IP5, 117 CLK_GATE_BLOCK, 118 APLL_LOCK, 119 MPLL_LOCK, 120 EPLL_LOCK, 121 VPLL_LOCK, 122 APLL_CON0, 123 APLL_CON1, 124 MPLL_CON, 125 EPLL_CON0, 126 EPLL_CON1, 127 VPLL_CON, 128 CLK_OUT, 129 }; 130 131 /* Mux parent lists. */ 132 static const char *const fin_pll_p[] __initconst = { 133 "xxti", 134 "xusbxti" 135 }; 136 137 static const char *const mout_apll_p[] __initconst = { 138 "fin_pll", 139 "fout_apll" 140 }; 141 142 static const char *const mout_mpll_p[] __initconst = { 143 "fin_pll", 144 "fout_mpll" 145 }; 146 147 static const char *const mout_epll_p[] __initconst = { 148 "fin_pll", 149 "fout_epll" 150 }; 151 152 static const char *const mout_vpllsrc_p[] __initconst = { 153 "fin_pll", 154 "sclk_hdmi27m" 155 }; 156 157 static const char *const mout_vpll_p[] __initconst = { 158 "mout_vpllsrc", 159 "fout_vpll" 160 }; 161 162 static const char *const mout_group1_p[] __initconst = { 163 "dout_a2m", 164 "mout_mpll", 165 "mout_epll", 166 "mout_vpll" 167 }; 168 169 static const char *const mout_group2_p[] __initconst = { 170 "xxti", 171 "xusbxti", 172 "sclk_hdmi27m", 173 "sclk_usbphy0", 174 "sclk_usbphy1", 175 "sclk_hdmiphy", 176 "mout_mpll", 177 "mout_epll", 178 "mout_vpll", 179 }; 180 181 static const char *const mout_audio0_p[] __initconst = { 182 "xxti", 183 "pcmcdclk0", 184 "sclk_hdmi27m", 185 "sclk_usbphy0", 186 "sclk_usbphy1", 187 "sclk_hdmiphy", 188 "mout_mpll", 189 "mout_epll", 190 "mout_vpll", 191 }; 192 193 static const char *const mout_audio1_p[] __initconst = { 194 "i2scdclk1", 195 "pcmcdclk1", 196 "sclk_hdmi27m", 197 "sclk_usbphy0", 198 "sclk_usbphy1", 199 "sclk_hdmiphy", 200 "mout_mpll", 201 "mout_epll", 202 "mout_vpll", 203 }; 204 205 static const char *const mout_audio2_p[] __initconst = { 206 "i2scdclk2", 207 "pcmcdclk2", 208 "sclk_hdmi27m", 209 "sclk_usbphy0", 210 "sclk_usbphy1", 211 "sclk_hdmiphy", 212 "mout_mpll", 213 "mout_epll", 214 "mout_vpll", 215 }; 216 217 static const char *const mout_spdif_p[] __initconst = { 218 "dout_audio0", 219 "dout_audio1", 220 "dout_audio3", 221 }; 222 223 static const char *const mout_group3_p[] __initconst = { 224 "mout_apll", 225 "mout_mpll" 226 }; 227 228 static const char *const mout_group4_p[] __initconst = { 229 "mout_mpll", 230 "dout_a2m" 231 }; 232 233 static const char *const mout_flash_p[] __initconst = { 234 "dout_hclkd", 235 "dout_hclkp" 236 }; 237 238 static const char *const mout_dac_p[] __initconst = { 239 "mout_vpll", 240 "sclk_hdmiphy" 241 }; 242 243 static const char *const mout_hdmi_p[] __initconst = { 244 "sclk_hdmiphy", 245 "dout_tblk" 246 }; 247 248 static const char *const mout_mixer_p[] __initconst = { 249 "mout_dac", 250 "mout_hdmi" 251 }; 252 253 static const char *const mout_vpll_6442_p[] __initconst = { 254 "fin_pll", 255 "fout_vpll" 256 }; 257 258 static const char *const mout_mixer_6442_p[] __initconst = { 259 "mout_vpll", 260 "dout_mixer" 261 }; 262 263 static const char *const mout_d0sync_6442_p[] __initconst = { 264 "mout_dsys", 265 "div_apll" 266 }; 267 268 static const char *const mout_d1sync_6442_p[] __initconst = { 269 "mout_psys", 270 "div_apll" 271 }; 272 273 static const char *const mout_group2_6442_p[] __initconst = { 274 "fin_pll", 275 "none", 276 "none", 277 "sclk_usbphy0", 278 "none", 279 "none", 280 "mout_mpll", 281 "mout_epll", 282 "mout_vpll", 283 }; 284 285 static const char *const mout_audio0_6442_p[] __initconst = { 286 "fin_pll", 287 "pcmcdclk0", 288 "none", 289 "sclk_usbphy0", 290 "none", 291 "none", 292 "mout_mpll", 293 "mout_epll", 294 "mout_vpll", 295 }; 296 297 static const char *const mout_audio1_6442_p[] __initconst = { 298 "i2scdclk1", 299 "pcmcdclk1", 300 "none", 301 "sclk_usbphy0", 302 "none", 303 "none", 304 "mout_mpll", 305 "mout_epll", 306 "mout_vpll", 307 "fin_pll", 308 }; 309 310 static const char *const mout_clksel_p[] __initconst = { 311 "fout_apll_clkout", 312 "fout_mpll_clkout", 313 "fout_epll", 314 "fout_vpll", 315 "sclk_usbphy0", 316 "sclk_usbphy1", 317 "sclk_hdmiphy", 318 "rtc", 319 "rtc_tick", 320 "dout_hclkm", 321 "dout_pclkm", 322 "dout_hclkd", 323 "dout_pclkd", 324 "dout_hclkp", 325 "dout_pclkp", 326 "dout_apll_clkout", 327 "dout_hpm", 328 "xxti", 329 "xusbxti", 330 "div_dclk" 331 }; 332 333 static const char *const mout_clksel_6442_p[] __initconst = { 334 "fout_apll_clkout", 335 "fout_mpll_clkout", 336 "fout_epll", 337 "fout_vpll", 338 "sclk_usbphy0", 339 "none", 340 "none", 341 "rtc", 342 "rtc_tick", 343 "none", 344 "none", 345 "dout_hclkd", 346 "dout_pclkd", 347 "dout_hclkp", 348 "dout_pclkp", 349 "dout_apll_clkout", 350 "none", 351 "fin_pll", 352 "none", 353 "div_dclk" 354 }; 355 356 static const char *const mout_clkout_p[] __initconst = { 357 "dout_clkout", 358 "none", 359 "xxti", 360 "xusbxti" 361 }; 362 363 /* Common fixed factor clocks. */ 364 static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = { 365 FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0), 366 FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0), 367 FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0), 368 }; 369 370 /* PLL input mux (fin_pll), which needs to be registered before PLLs. */ 371 static const struct samsung_mux_clock early_mux_clks[] __initconst = { 372 MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1, 373 CLK_MUX_READ_ONLY, 0), 374 }; 375 376 /* Common clock muxes. */ 377 static const struct samsung_mux_clock mux_clks[] __initconst = { 378 MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1), 379 MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1), 380 MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1), 381 MUX(MOUT_MSYS, "mout_msys", mout_group3_p, CLK_SRC0, 16, 1), 382 MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1), 383 MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1), 384 MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1), 385 386 MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2), 387 }; 388 389 /* S5PV210-specific clock muxes. */ 390 static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = { 391 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1), 392 393 MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1), 394 MUX(MOUT_CSIS, "mout_csis", mout_group2_p, CLK_SRC1, 24, 4), 395 MUX(MOUT_FIMD, "mout_fimd", mout_group2_p, CLK_SRC1, 20, 4), 396 MUX(MOUT_CAM1, "mout_cam1", mout_group2_p, CLK_SRC1, 16, 4), 397 MUX(MOUT_CAM0, "mout_cam0", mout_group2_p, CLK_SRC1, 12, 4), 398 MUX(MOUT_DAC, "mout_dac", mout_dac_p, CLK_SRC1, 8, 1), 399 MUX(MOUT_MIXER, "mout_mixer", mout_mixer_p, CLK_SRC1, 4, 1), 400 MUX(MOUT_HDMI, "mout_hdmi", mout_hdmi_p, CLK_SRC1, 0, 1), 401 402 MUX(MOUT_G2D, "mout_g2d", mout_group1_p, CLK_SRC2, 8, 2), 403 MUX(MOUT_MFC, "mout_mfc", mout_group1_p, CLK_SRC2, 4, 2), 404 MUX(MOUT_G3D, "mout_g3d", mout_group1_p, CLK_SRC2, 0, 2), 405 406 MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_p, CLK_SRC3, 20, 4), 407 MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_p, CLK_SRC3, 16, 4), 408 MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_p, CLK_SRC3, 12, 4), 409 410 MUX(MOUT_UART3, "mout_uart3", mout_group2_p, CLK_SRC4, 28, 4), 411 MUX(MOUT_UART2, "mout_uart2", mout_group2_p, CLK_SRC4, 24, 4), 412 MUX(MOUT_UART1, "mout_uart1", mout_group2_p, CLK_SRC4, 20, 4), 413 MUX(MOUT_UART0, "mout_uart0", mout_group2_p, CLK_SRC4, 16, 4), 414 MUX(MOUT_MMC3, "mout_mmc3", mout_group2_p, CLK_SRC4, 12, 4), 415 MUX(MOUT_MMC2, "mout_mmc2", mout_group2_p, CLK_SRC4, 8, 4), 416 MUX(MOUT_MMC1, "mout_mmc1", mout_group2_p, CLK_SRC4, 4, 4), 417 MUX(MOUT_MMC0, "mout_mmc0", mout_group2_p, CLK_SRC4, 0, 4), 418 419 MUX(MOUT_PWM, "mout_pwm", mout_group2_p, CLK_SRC5, 12, 4), 420 MUX(MOUT_SPI1, "mout_spi1", mout_group2_p, CLK_SRC5, 4, 4), 421 MUX(MOUT_SPI0, "mout_spi0", mout_group2_p, CLK_SRC5, 0, 4), 422 423 MUX(MOUT_DMC0, "mout_dmc0", mout_group1_p, CLK_SRC6, 24, 2), 424 MUX(MOUT_PWI, "mout_pwi", mout_group2_p, CLK_SRC6, 20, 4), 425 MUX(MOUT_HPM, "mout_hpm", mout_group3_p, CLK_SRC6, 16, 1), 426 MUX(MOUT_SPDIF, "mout_spdif", mout_spdif_p, CLK_SRC6, 12, 2), 427 MUX(MOUT_AUDIO2, "mout_audio2", mout_audio2_p, CLK_SRC6, 8, 4), 428 MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_p, CLK_SRC6, 4, 4), 429 MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_p, CLK_SRC6, 0, 4), 430 431 MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_p, CLK_OUT, 12, 5), 432 }; 433 434 /* S5P6442-specific clock muxes. */ 435 static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = { 436 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1), 437 438 MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4), 439 MUX(MOUT_CAM1, "mout_cam1", mout_group2_6442_p, CLK_SRC1, 16, 4), 440 MUX(MOUT_CAM0, "mout_cam0", mout_group2_6442_p, CLK_SRC1, 12, 4), 441 MUX(MOUT_MIXER, "mout_mixer", mout_mixer_6442_p, CLK_SRC1, 4, 1), 442 443 MUX(MOUT_D0SYNC, "mout_d0sync", mout_d0sync_6442_p, CLK_SRC2, 28, 1), 444 MUX(MOUT_D1SYNC, "mout_d1sync", mout_d1sync_6442_p, CLK_SRC2, 24, 1), 445 446 MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_6442_p, CLK_SRC3, 20, 4), 447 MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_6442_p, CLK_SRC3, 16, 4), 448 MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_6442_p, CLK_SRC3, 12, 4), 449 450 MUX(MOUT_UART2, "mout_uart2", mout_group2_6442_p, CLK_SRC4, 24, 4), 451 MUX(MOUT_UART1, "mout_uart1", mout_group2_6442_p, CLK_SRC4, 20, 4), 452 MUX(MOUT_UART0, "mout_uart0", mout_group2_6442_p, CLK_SRC4, 16, 4), 453 MUX(MOUT_MMC2, "mout_mmc2", mout_group2_6442_p, CLK_SRC4, 8, 4), 454 MUX(MOUT_MMC1, "mout_mmc1", mout_group2_6442_p, CLK_SRC4, 4, 4), 455 MUX(MOUT_MMC0, "mout_mmc0", mout_group2_6442_p, CLK_SRC4, 0, 4), 456 457 MUX(MOUT_PWM, "mout_pwm", mout_group2_6442_p, CLK_SRC5, 12, 4), 458 MUX(MOUT_SPI0, "mout_spi0", mout_group2_6442_p, CLK_SRC5, 0, 4), 459 460 MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_6442_p, CLK_SRC6, 4, 4), 461 MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_6442_p, CLK_SRC6, 0, 4), 462 463 MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_6442_p, CLK_OUT, 12, 5), 464 }; 465 466 /* S5PV210-specific fixed rate clocks generated inside the SoC. */ 467 static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = { 468 FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, 0, 27000000), 469 FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000), 470 FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 48000000), 471 FRATE(SCLK_USBPHY1, "sclk_usbphy1", NULL, 0, 48000000), 472 }; 473 474 /* S5P6442-specific fixed rate clocks generated inside the SoC. */ 475 static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = { 476 FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 30000000), 477 }; 478 479 /* Common clock dividers. */ 480 static const struct samsung_div_clock div_clks[] __initconst = { 481 DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3), 482 DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3), 483 DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3), 484 DIV(DOUT_APLL, "dout_apll", "mout_msys", CLK_DIV0, 0, 3), 485 486 DIV(DOUT_FIMD, "dout_fimd", "mout_fimd", CLK_DIV1, 20, 4), 487 DIV(DOUT_CAM1, "dout_cam1", "mout_cam1", CLK_DIV1, 16, 4), 488 DIV(DOUT_CAM0, "dout_cam0", "mout_cam0", CLK_DIV1, 12, 4), 489 490 DIV(DOUT_FIMC2, "dout_fimc2", "mout_fimc2", CLK_DIV3, 20, 4), 491 DIV(DOUT_FIMC1, "dout_fimc1", "mout_fimc1", CLK_DIV3, 16, 4), 492 DIV(DOUT_FIMC0, "dout_fimc0", "mout_fimc0", CLK_DIV3, 12, 4), 493 494 DIV(DOUT_UART2, "dout_uart2", "mout_uart2", CLK_DIV4, 24, 4), 495 DIV(DOUT_UART1, "dout_uart1", "mout_uart1", CLK_DIV4, 20, 4), 496 DIV(DOUT_UART0, "dout_uart0", "mout_uart0", CLK_DIV4, 16, 4), 497 DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV4, 8, 4), 498 DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV4, 4, 4), 499 DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV4, 0, 4), 500 501 DIV(DOUT_PWM, "dout_pwm", "mout_pwm", CLK_DIV5, 12, 4), 502 DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV5, 0, 4), 503 504 DIV(DOUT_FLASH, "dout_flash", "mout_flash", CLK_DIV6, 12, 3), 505 DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV6, 4, 4), 506 DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV6, 0, 4), 507 508 DIV(DOUT_CLKOUT, "dout_clkout", "mout_clksel", CLK_OUT, 20, 4), 509 }; 510 511 /* S5PV210-specific clock dividers. */ 512 static const struct samsung_div_clock s5pv210_div_clks[] __initconst = { 513 DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4), 514 DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4), 515 DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3), 516 DIV(DOUT_HCLKM, "dout_hclkm", "dout_apll", CLK_DIV0, 8, 3), 517 518 DIV(DOUT_CSIS, "dout_csis", "mout_csis", CLK_DIV1, 28, 4), 519 DIV(DOUT_TBLK, "dout_tblk", "mout_vpll", CLK_DIV1, 0, 4), 520 521 DIV(DOUT_G2D, "dout_g2d", "mout_g2d", CLK_DIV2, 8, 4), 522 DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV2, 4, 4), 523 DIV(DOUT_G3D, "dout_g3d", "mout_g3d", CLK_DIV2, 0, 4), 524 525 DIV(DOUT_UART3, "dout_uart3", "mout_uart3", CLK_DIV4, 28, 4), 526 DIV(DOUT_MMC3, "dout_mmc3", "mout_mmc3", CLK_DIV4, 12, 4), 527 528 DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV5, 4, 4), 529 530 DIV(DOUT_DMC0, "dout_dmc0", "mout_dmc0", CLK_DIV6, 28, 4), 531 DIV(DOUT_PWI, "dout_pwi", "mout_pwi", CLK_DIV6, 24, 4), 532 DIV(DOUT_HPM, "dout_hpm", "dout_copy", CLK_DIV6, 20, 3), 533 DIV(DOUT_COPY, "dout_copy", "mout_hpm", CLK_DIV6, 16, 3), 534 DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV6, 8, 4), 535 536 DIV(DOUT_DPM, "dout_dpm", "dout_pclkp", CLK_DIV7, 8, 7), 537 DIV(DOUT_DVSEM, "dout_dvsem", "dout_pclkp", CLK_DIV7, 0, 7), 538 }; 539 540 /* S5P6442-specific clock dividers. */ 541 static const struct samsung_div_clock s5p6442_div_clks[] __initconst = { 542 DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4), 543 DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4), 544 545 DIV(DOUT_MIXER, "dout_mixer", "mout_vpll", CLK_DIV1, 0, 4), 546 }; 547 548 /* Common clock gates. */ 549 static const struct samsung_gate_clock gate_clks[] __initconst = { 550 GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0), 551 GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0), 552 GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0), 553 GATE(CLK_FIMC0, "fimc0", "dout_hclkd", CLK_GATE_IP0, 24, 0, 0), 554 GATE(CLK_PDMA0, "pdma0", "dout_hclkp", CLK_GATE_IP0, 3, 0, 0), 555 GATE(CLK_MDMA, "mdma", "dout_hclkd", CLK_GATE_IP0, 2, 0, 0), 556 557 GATE(CLK_SROMC, "sromc", "dout_hclkp", CLK_GATE_IP1, 26, 0, 0), 558 GATE(CLK_NANDXL, "nandxl", "dout_hclkp", CLK_GATE_IP1, 24, 0, 0), 559 GATE(CLK_USB_OTG, "usb_otg", "dout_hclkp", CLK_GATE_IP1, 16, 0, 0), 560 GATE(CLK_TVENC, "tvenc", "dout_hclkd", CLK_GATE_IP1, 10, 0, 0), 561 GATE(CLK_MIXER, "mixer", "dout_hclkd", CLK_GATE_IP1, 9, 0, 0), 562 GATE(CLK_VP, "vp", "dout_hclkd", CLK_GATE_IP1, 8, 0, 0), 563 GATE(CLK_FIMD, "fimd", "dout_hclkd", CLK_GATE_IP1, 0, 0, 0), 564 565 GATE(CLK_HSMMC2, "hsmmc2", "dout_hclkp", CLK_GATE_IP2, 18, 0, 0), 566 GATE(CLK_HSMMC1, "hsmmc1", "dout_hclkp", CLK_GATE_IP2, 17, 0, 0), 567 GATE(CLK_HSMMC0, "hsmmc0", "dout_hclkp", CLK_GATE_IP2, 16, 0, 0), 568 GATE(CLK_MODEMIF, "modemif", "dout_hclkp", CLK_GATE_IP2, 9, 0, 0), 569 GATE(CLK_SECSS, "secss", "dout_hclkp", CLK_GATE_IP2, 0, 0, 0), 570 571 GATE(CLK_PCM1, "pcm1", "dout_pclkp", CLK_GATE_IP3, 29, 0, 0), 572 GATE(CLK_PCM0, "pcm0", "dout_pclkp", CLK_GATE_IP3, 28, 0, 0), 573 GATE(CLK_TSADC, "tsadc", "dout_pclkp", CLK_GATE_IP3, 24, 0, 0), 574 GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0), 575 GATE(CLK_WDT, "watchdog", "dout_pclkp", CLK_GATE_IP3, 22, 0, 0), 576 GATE(CLK_KEYIF, "keyif", "dout_pclkp", CLK_GATE_IP3, 21, 0, 0), 577 GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0), 578 GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0), 579 GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0), 580 GATE(CLK_SYSTIMER, "systimer", "dout_pclkp", CLK_GATE_IP3, 16, 0, 0), 581 GATE(CLK_RTC, "rtc", "dout_pclkp", CLK_GATE_IP3, 15, 0, 0), 582 GATE(CLK_SPI0, "spi0", "dout_pclkp", CLK_GATE_IP3, 12, 0, 0), 583 GATE(CLK_I2C2, "i2c2", "dout_pclkp", CLK_GATE_IP3, 9, 0, 0), 584 GATE(CLK_I2C0, "i2c0", "dout_pclkp", CLK_GATE_IP3, 7, 0, 0), 585 GATE(CLK_I2S1, "i2s1", "dout_pclkp", CLK_GATE_IP3, 5, 0, 0), 586 GATE(CLK_I2S0, "i2s0", "dout_pclkp", CLK_GATE_IP3, 4, 0, 0), 587 588 GATE(CLK_SECKEY, "seckey", "dout_pclkp", CLK_GATE_IP4, 3, 0, 0), 589 GATE(CLK_CHIPID, "chipid", "dout_pclkp", CLK_GATE_IP4, 0, 0, 0), 590 591 GATE(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", CLK_SRC_MASK0, 25, 592 CLK_SET_RATE_PARENT, 0), 593 GATE(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", CLK_SRC_MASK0, 24, 594 CLK_SET_RATE_PARENT, 0), 595 GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19, 596 CLK_SET_RATE_PARENT, 0), 597 GATE(SCLK_SPI0, "sclk_spi0", "dout_spi0", CLK_SRC_MASK0, 16, 598 CLK_SET_RATE_PARENT, 0), 599 GATE(SCLK_UART2, "sclk_uart2", "dout_uart2", CLK_SRC_MASK0, 14, 600 CLK_SET_RATE_PARENT, 0), 601 GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13, 602 CLK_SET_RATE_PARENT, 0), 603 GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12, 604 CLK_SET_RATE_PARENT, 0), 605 GATE(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", CLK_SRC_MASK0, 10, 606 CLK_SET_RATE_PARENT, 0), 607 GATE(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", CLK_SRC_MASK0, 9, 608 CLK_SET_RATE_PARENT, 0), 609 GATE(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", CLK_SRC_MASK0, 8, 610 CLK_SET_RATE_PARENT, 0), 611 GATE(SCLK_FIMD, "sclk_fimd", "dout_fimd", CLK_SRC_MASK0, 5, 612 CLK_SET_RATE_PARENT, 0), 613 GATE(SCLK_CAM1, "sclk_cam1", "dout_cam1", CLK_SRC_MASK0, 4, 614 CLK_SET_RATE_PARENT, 0), 615 GATE(SCLK_CAM0, "sclk_cam0", "dout_cam0", CLK_SRC_MASK0, 3, 616 CLK_SET_RATE_PARENT, 0), 617 GATE(SCLK_MIXER, "sclk_mixer", "mout_mixer", CLK_SRC_MASK0, 1, 618 CLK_SET_RATE_PARENT, 0), 619 620 GATE(SCLK_FIMC2, "sclk_fimc2", "dout_fimc2", CLK_SRC_MASK1, 4, 621 CLK_SET_RATE_PARENT, 0), 622 GATE(SCLK_FIMC1, "sclk_fimc1", "dout_fimc1", CLK_SRC_MASK1, 3, 623 CLK_SET_RATE_PARENT, 0), 624 GATE(SCLK_FIMC0, "sclk_fimc0", "dout_fimc0", CLK_SRC_MASK1, 2, 625 CLK_SET_RATE_PARENT, 0), 626 }; 627 628 /* S5PV210-specific clock gates. */ 629 static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = { 630 GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0), 631 GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0), 632 GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0), 633 GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0), 634 GATE(CLK_IMEM, "imem", "dout_hclkm", CLK_GATE_IP0, 5, 0, 0), 635 GATE(CLK_PDMA1, "pdma1", "dout_hclkp", CLK_GATE_IP0, 4, 0, 0), 636 637 GATE(CLK_NFCON, "nfcon", "dout_hclkp", CLK_GATE_IP1, 28, 0, 0), 638 GATE(CLK_CFCON, "cfcon", "dout_hclkp", CLK_GATE_IP1, 25, 0, 0), 639 GATE(CLK_USB_HOST, "usb_host", "dout_hclkp", CLK_GATE_IP1, 17, 0, 0), 640 GATE(CLK_HDMI, "hdmi", "dout_hclkd", CLK_GATE_IP1, 11, 0, 0), 641 GATE(CLK_DSIM, "dsim", "dout_pclkd", CLK_GATE_IP1, 2, 0, 0), 642 643 GATE(CLK_TZIC3, "tzic3", "dout_hclkm", CLK_GATE_IP2, 31, 0, 0), 644 GATE(CLK_TZIC2, "tzic2", "dout_hclkm", CLK_GATE_IP2, 30, 0, 0), 645 GATE(CLK_TZIC1, "tzic1", "dout_hclkm", CLK_GATE_IP2, 29, 0, 0), 646 GATE(CLK_TZIC0, "tzic0", "dout_hclkm", CLK_GATE_IP2, 28, 0, 0), 647 GATE(CLK_TSI, "tsi", "dout_hclkd", CLK_GATE_IP2, 20, 0, 0), 648 GATE(CLK_HSMMC3, "hsmmc3", "dout_hclkp", CLK_GATE_IP2, 19, 0, 0), 649 GATE(CLK_JTAG, "jtag", "dout_hclkp", CLK_GATE_IP2, 11, 0, 0), 650 GATE(CLK_CORESIGHT, "coresight", "dout_pclkp", CLK_GATE_IP2, 8, 0, 0), 651 GATE(CLK_SDM, "sdm", "dout_pclkm", CLK_GATE_IP2, 1, 0, 0), 652 653 GATE(CLK_PCM2, "pcm2", "dout_pclkp", CLK_GATE_IP3, 30, 0, 0), 654 GATE(CLK_UART3, "uart3", "dout_pclkp", CLK_GATE_IP3, 20, 0, 0), 655 GATE(CLK_SPI1, "spi1", "dout_pclkp", CLK_GATE_IP3, 13, 0, 0), 656 GATE(CLK_I2C_HDMI_PHY, "i2c_hdmi_phy", "dout_pclkd", 657 CLK_GATE_IP3, 11, 0, 0), 658 GATE(CLK_I2C1, "i2c1", "dout_pclkd", CLK_GATE_IP3, 10, 0, 0), 659 GATE(CLK_I2S2, "i2s2", "dout_pclkp", CLK_GATE_IP3, 6, 0, 0), 660 GATE(CLK_AC97, "ac97", "dout_pclkp", CLK_GATE_IP3, 1, 0, 0), 661 GATE(CLK_SPDIF, "spdif", "dout_pclkp", CLK_GATE_IP3, 0, 0, 0), 662 663 GATE(CLK_TZPC3, "tzpc.3", "dout_pclkd", CLK_GATE_IP4, 8, 0, 0), 664 GATE(CLK_TZPC2, "tzpc.2", "dout_pclkd", CLK_GATE_IP4, 7, 0, 0), 665 GATE(CLK_TZPC1, "tzpc.1", "dout_pclkp", CLK_GATE_IP4, 6, 0, 0), 666 GATE(CLK_TZPC0, "tzpc.0", "dout_pclkm", CLK_GATE_IP4, 5, 0, 0), 667 GATE(CLK_IEM_APC, "iem_apc", "dout_pclkp", CLK_GATE_IP4, 2, 0, 0), 668 GATE(CLK_IEM_IEC, "iem_iec", "dout_pclkp", CLK_GATE_IP4, 1, 0, 0), 669 670 GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP5, 29, 0, 0), 671 672 GATE(SCLK_SPDIF, "sclk_spdif", "mout_spdif", CLK_SRC_MASK0, 27, 673 CLK_SET_RATE_PARENT, 0), 674 GATE(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", CLK_SRC_MASK0, 26, 675 CLK_SET_RATE_PARENT, 0), 676 GATE(SCLK_SPI1, "sclk_spi1", "dout_spi1", CLK_SRC_MASK0, 17, 677 CLK_SET_RATE_PARENT, 0), 678 GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15, 679 CLK_SET_RATE_PARENT, 0), 680 GATE(SCLK_MMC3, "sclk_mmc3", "dout_mmc3", CLK_SRC_MASK0, 11, 681 CLK_SET_RATE_PARENT, 0), 682 GATE(SCLK_CSIS, "sclk_csis", "dout_csis", CLK_SRC_MASK0, 6, 683 CLK_SET_RATE_PARENT, 0), 684 GATE(SCLK_DAC, "sclk_dac", "mout_dac", CLK_SRC_MASK0, 2, 685 CLK_SET_RATE_PARENT, 0), 686 GATE(SCLK_HDMI, "sclk_hdmi", "mout_hdmi", CLK_SRC_MASK0, 0, 687 CLK_SET_RATE_PARENT, 0), 688 }; 689 690 /* S5P6442-specific clock gates. */ 691 static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = { 692 GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0), 693 GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0), 694 GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0), 695 GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0), 696 GATE(CLK_IMEM, "imem", "dout_hclkd", CLK_GATE_IP0, 5, 0, 0), 697 698 GATE(CLK_ETB, "etb", "dout_hclkd", CLK_GATE_IP1, 31, 0, 0), 699 GATE(CLK_ETM, "etm", "dout_hclkd", CLK_GATE_IP1, 30, 0, 0), 700 701 GATE(CLK_I2C1, "i2c1", "dout_pclkp", CLK_GATE_IP3, 8, 0, 0), 702 703 GATE(SCLK_DAC, "sclk_dac", "mout_vpll", CLK_SRC_MASK0, 2, 704 CLK_SET_RATE_PARENT, 0), 705 }; 706 707 /* 708 * Clock aliases for legacy clkdev look-up. 709 * NOTE: Needed only to support legacy board files. 710 */ 711 static const struct samsung_clock_alias s5pv210_aliases[] __initconst = { 712 ALIAS(DOUT_APLL, NULL, "armclk"), 713 ALIAS(DOUT_HCLKM, NULL, "hclk_msys"), 714 ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"), 715 }; 716 717 /* S5PV210-specific PLLs. */ 718 static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = { 719 [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll", 720 APLL_LOCK, APLL_CON0, NULL), 721 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", 722 MPLL_LOCK, MPLL_CON, NULL), 723 [epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll", 724 EPLL_LOCK, EPLL_CON0, NULL), 725 [vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc", 726 VPLL_LOCK, VPLL_CON, NULL), 727 }; 728 729 /* S5P6442-specific PLLs. */ 730 static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = { 731 [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll", 732 APLL_LOCK, APLL_CON0, NULL), 733 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", 734 MPLL_LOCK, MPLL_CON, NULL), 735 [epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll", 736 EPLL_LOCK, EPLL_CON0, NULL), 737 [vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll", 738 VPLL_LOCK, VPLL_CON, NULL), 739 }; 740 741 static void __init __s5pv210_clk_init(struct device_node *np, 742 unsigned long xxti_f, 743 unsigned long xusbxti_f, 744 bool is_s5p6442) 745 { 746 struct samsung_clk_provider *ctx; 747 748 ctx = samsung_clk_init(np, reg_base, NR_CLKS); 749 750 samsung_clk_register_mux(ctx, early_mux_clks, 751 ARRAY_SIZE(early_mux_clks)); 752 753 if (is_s5p6442) { 754 samsung_clk_register_fixed_rate(ctx, s5p6442_frate_clks, 755 ARRAY_SIZE(s5p6442_frate_clks)); 756 samsung_clk_register_pll(ctx, s5p6442_pll_clks, 757 ARRAY_SIZE(s5p6442_pll_clks), reg_base); 758 samsung_clk_register_mux(ctx, s5p6442_mux_clks, 759 ARRAY_SIZE(s5p6442_mux_clks)); 760 samsung_clk_register_div(ctx, s5p6442_div_clks, 761 ARRAY_SIZE(s5p6442_div_clks)); 762 samsung_clk_register_gate(ctx, s5p6442_gate_clks, 763 ARRAY_SIZE(s5p6442_gate_clks)); 764 } else { 765 samsung_clk_register_fixed_rate(ctx, s5pv210_frate_clks, 766 ARRAY_SIZE(s5pv210_frate_clks)); 767 samsung_clk_register_pll(ctx, s5pv210_pll_clks, 768 ARRAY_SIZE(s5pv210_pll_clks), reg_base); 769 samsung_clk_register_mux(ctx, s5pv210_mux_clks, 770 ARRAY_SIZE(s5pv210_mux_clks)); 771 samsung_clk_register_div(ctx, s5pv210_div_clks, 772 ARRAY_SIZE(s5pv210_div_clks)); 773 samsung_clk_register_gate(ctx, s5pv210_gate_clks, 774 ARRAY_SIZE(s5pv210_gate_clks)); 775 } 776 777 samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks)); 778 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks)); 779 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks)); 780 781 samsung_clk_register_fixed_factor(ctx, ffactor_clks, 782 ARRAY_SIZE(ffactor_clks)); 783 784 samsung_clk_register_alias(ctx, s5pv210_aliases, 785 ARRAY_SIZE(s5pv210_aliases)); 786 787 samsung_clk_sleep_init(reg_base, s5pv210_clk_regs, 788 ARRAY_SIZE(s5pv210_clk_regs)); 789 790 samsung_clk_of_add_provider(np, ctx); 791 792 pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n" 793 "\tmout_epll = %ld, mout_vpll = %ld\n", 794 is_s5p6442 ? "S5P6442" : "S5PV210", 795 _get_rate("mout_apll"), _get_rate("mout_mpll"), 796 _get_rate("mout_epll"), _get_rate("mout_vpll")); 797 } 798 799 static void __init s5pv210_clk_dt_init(struct device_node *np) 800 { 801 reg_base = of_iomap(np, 0); 802 if (!reg_base) 803 panic("%s: failed to map registers\n", __func__); 804 805 __s5pv210_clk_init(np, 0, 0, false); 806 } 807 CLK_OF_DECLARE(s5pv210_clk, "samsung,s5pv210-clock", s5pv210_clk_dt_init); 808 809 static void __init s5p6442_clk_dt_init(struct device_node *np) 810 { 811 reg_base = of_iomap(np, 0); 812 if (!reg_base) 813 panic("%s: failed to map registers\n", __func__); 814 815 __s5pv210_clk_init(np, 0, 0, true); 816 } 817 CLK_OF_DECLARE(s5p6442_clk, "samsung,s5p6442-clock", s5p6442_clk_dt_init); 818