1 /* 2 * Copyright (c) 2014 Tomasz Figa <t.figa@samsung.com> 3 * 4 * Based on Exynos Audio Subsystem Clock Controller driver: 5 * 6 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 7 * Author: Padmavathi Venna <padma.v@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs. 14 */ 15 16 #include <linux/io.h> 17 #include <linux/clk.h> 18 #include <linux/clk-provider.h> 19 #include <linux/of_address.h> 20 #include <linux/syscore_ops.h> 21 #include <linux/init.h> 22 #include <linux/platform_device.h> 23 24 #include <dt-bindings/clock/s5pv210-audss.h> 25 26 static DEFINE_SPINLOCK(lock); 27 static void __iomem *reg_base; 28 static struct clk_hw_onecell_data *clk_data; 29 30 #define ASS_CLK_SRC 0x0 31 #define ASS_CLK_DIV 0x4 32 #define ASS_CLK_GATE 0x8 33 34 #ifdef CONFIG_PM_SLEEP 35 static unsigned long reg_save[][2] = { 36 {ASS_CLK_SRC, 0}, 37 {ASS_CLK_DIV, 0}, 38 {ASS_CLK_GATE, 0}, 39 }; 40 41 static int s5pv210_audss_clk_suspend(void) 42 { 43 int i; 44 45 for (i = 0; i < ARRAY_SIZE(reg_save); i++) 46 reg_save[i][1] = readl(reg_base + reg_save[i][0]); 47 48 return 0; 49 } 50 51 static void s5pv210_audss_clk_resume(void) 52 { 53 int i; 54 55 for (i = 0; i < ARRAY_SIZE(reg_save); i++) 56 writel(reg_save[i][1], reg_base + reg_save[i][0]); 57 } 58 59 static struct syscore_ops s5pv210_audss_clk_syscore_ops = { 60 .suspend = s5pv210_audss_clk_suspend, 61 .resume = s5pv210_audss_clk_resume, 62 }; 63 #endif /* CONFIG_PM_SLEEP */ 64 65 /* register s5pv210_audss clocks */ 66 static int s5pv210_audss_clk_probe(struct platform_device *pdev) 67 { 68 int i, ret = 0; 69 struct resource *res; 70 const char *mout_audss_p[2]; 71 const char *mout_i2s_p[3]; 72 const char *hclk_p; 73 struct clk_hw **clk_table; 74 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; 75 76 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 77 reg_base = devm_ioremap_resource(&pdev->dev, res); 78 if (IS_ERR(reg_base)) { 79 dev_err(&pdev->dev, "failed to map audss registers\n"); 80 return PTR_ERR(reg_base); 81 } 82 83 clk_data = devm_kzalloc(&pdev->dev, 84 sizeof(*clk_data) + 85 sizeof(*clk_data->hws) * AUDSS_MAX_CLKS, 86 GFP_KERNEL); 87 88 if (!clk_data) 89 return -ENOMEM; 90 91 clk_data->num = AUDSS_MAX_CLKS; 92 clk_table = clk_data->hws; 93 94 hclk = devm_clk_get(&pdev->dev, "hclk"); 95 if (IS_ERR(hclk)) { 96 dev_err(&pdev->dev, "failed to get hclk clock\n"); 97 return PTR_ERR(hclk); 98 } 99 100 pll_in = devm_clk_get(&pdev->dev, "fout_epll"); 101 if (IS_ERR(pll_in)) { 102 dev_err(&pdev->dev, "failed to get fout_epll clock\n"); 103 return PTR_ERR(pll_in); 104 } 105 106 sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio0"); 107 if (IS_ERR(sclk_audio)) { 108 dev_err(&pdev->dev, "failed to get sclk_audio0 clock\n"); 109 return PTR_ERR(sclk_audio); 110 } 111 112 /* iiscdclk0 is an optional external I2S codec clock */ 113 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); 114 pll_ref = devm_clk_get(&pdev->dev, "xxti"); 115 116 if (!IS_ERR(pll_ref)) 117 mout_audss_p[0] = __clk_get_name(pll_ref); 118 else 119 mout_audss_p[0] = "xxti"; 120 mout_audss_p[1] = __clk_get_name(pll_in); 121 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", 122 mout_audss_p, ARRAY_SIZE(mout_audss_p), 123 CLK_SET_RATE_NO_REPARENT, 124 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); 125 126 mout_i2s_p[0] = "mout_audss"; 127 if (!IS_ERR(cdclk)) 128 mout_i2s_p[1] = __clk_get_name(cdclk); 129 else 130 mout_i2s_p[1] = "iiscdclk0"; 131 mout_i2s_p[2] = __clk_get_name(sclk_audio); 132 clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss", 133 mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 134 CLK_SET_RATE_NO_REPARENT, 135 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); 136 137 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, 138 "dout_aud_bus", "mout_audss", 0, 139 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); 140 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, 141 "dout_i2s_audss", "mout_i2s_audss", 0, 142 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); 143 144 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", 145 "dout_i2s_audss", CLK_SET_RATE_PARENT, 146 reg_base + ASS_CLK_GATE, 6, 0, &lock); 147 148 hclk_p = __clk_get_name(hclk); 149 150 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss", 151 hclk_p, CLK_IGNORE_UNUSED, 152 reg_base + ASS_CLK_GATE, 5, 0, &lock); 153 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss", 154 hclk_p, CLK_IGNORE_UNUSED, 155 reg_base + ASS_CLK_GATE, 4, 0, &lock); 156 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss", 157 hclk_p, CLK_IGNORE_UNUSED, 158 reg_base + ASS_CLK_GATE, 3, 0, &lock); 159 clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss", 160 hclk_p, CLK_IGNORE_UNUSED, 161 reg_base + ASS_CLK_GATE, 2, 0, &lock); 162 clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss", 163 hclk_p, CLK_IGNORE_UNUSED, 164 reg_base + ASS_CLK_GATE, 1, 0, &lock); 165 clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss", 166 hclk_p, CLK_IGNORE_UNUSED, 167 reg_base + ASS_CLK_GATE, 0, 0, &lock); 168 169 for (i = 0; i < clk_data->num; i++) { 170 if (IS_ERR(clk_table[i])) { 171 dev_err(&pdev->dev, "failed to register clock %d\n", i); 172 ret = PTR_ERR(clk_table[i]); 173 goto unregister; 174 } 175 } 176 177 ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get, 178 clk_data); 179 if (ret) { 180 dev_err(&pdev->dev, "failed to add clock provider\n"); 181 goto unregister; 182 } 183 184 #ifdef CONFIG_PM_SLEEP 185 register_syscore_ops(&s5pv210_audss_clk_syscore_ops); 186 #endif 187 188 return 0; 189 190 unregister: 191 for (i = 0; i < clk_data->num; i++) { 192 if (!IS_ERR(clk_table[i])) 193 clk_hw_unregister(clk_table[i]); 194 } 195 196 return ret; 197 } 198 199 static const struct of_device_id s5pv210_audss_clk_of_match[] = { 200 { .compatible = "samsung,s5pv210-audss-clock", }, 201 {}, 202 }; 203 204 static struct platform_driver s5pv210_audss_clk_driver = { 205 .driver = { 206 .name = "s5pv210-audss-clk", 207 .suppress_bind_attrs = true, 208 .of_match_table = s5pv210_audss_clk_of_match, 209 }, 210 .probe = s5pv210_audss_clk_probe, 211 }; 212 213 static int __init s5pv210_audss_clk_init(void) 214 { 215 return platform_driver_register(&s5pv210_audss_clk_driver); 216 } 217 core_initcall(s5pv210_audss_clk_init); 218