1 /* 2 * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Common Clock Framework support for all S3C64xx SoCs. 9 */ 10 11 #include <linux/slab.h> 12 #include <linux/clk-provider.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/syscore_ops.h> 16 17 #include <dt-bindings/clock/samsung,s3c64xx-clock.h> 18 19 #include "clk.h" 20 #include "clk-pll.h" 21 22 /* S3C64xx clock controller register offsets. */ 23 #define APLL_LOCK 0x000 24 #define MPLL_LOCK 0x004 25 #define EPLL_LOCK 0x008 26 #define APLL_CON 0x00c 27 #define MPLL_CON 0x010 28 #define EPLL_CON0 0x014 29 #define EPLL_CON1 0x018 30 #define CLK_SRC 0x01c 31 #define CLK_DIV0 0x020 32 #define CLK_DIV1 0x024 33 #define CLK_DIV2 0x028 34 #define HCLK_GATE 0x030 35 #define PCLK_GATE 0x034 36 #define SCLK_GATE 0x038 37 #define MEM0_GATE 0x03c 38 #define CLK_SRC2 0x10c 39 #define OTHERS 0x900 40 41 /* Helper macros to define clock arrays. */ 42 #define FIXED_RATE_CLOCKS(name) \ 43 static struct samsung_fixed_rate_clock name[] 44 #define MUX_CLOCKS(name) \ 45 static struct samsung_mux_clock name[] 46 #define DIV_CLOCKS(name) \ 47 static struct samsung_div_clock name[] 48 #define GATE_CLOCKS(name) \ 49 static struct samsung_gate_clock name[] 50 51 /* Helper macros for gate types present on S3C64xx. */ 52 #define GATE_BUS(_id, cname, pname, o, b) \ 53 GATE(_id, cname, pname, o, b, 0, 0) 54 #define GATE_SCLK(_id, cname, pname, o, b) \ 55 GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0) 56 #define GATE_ON(_id, cname, pname, o, b) \ 57 GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0) 58 59 static void __iomem *reg_base; 60 static bool is_s3c6400; 61 62 #ifdef CONFIG_PM_SLEEP 63 static struct samsung_clk_reg_dump *s3c64xx_save_common; 64 static struct samsung_clk_reg_dump *s3c64xx_save_soc; 65 66 /* 67 * List of controller registers to be saved and restored during 68 * a suspend/resume cycle. 69 */ 70 static unsigned long s3c64xx_clk_regs[] __initdata = { 71 APLL_LOCK, 72 MPLL_LOCK, 73 EPLL_LOCK, 74 APLL_CON, 75 MPLL_CON, 76 EPLL_CON0, 77 EPLL_CON1, 78 CLK_SRC, 79 CLK_DIV0, 80 CLK_DIV1, 81 CLK_DIV2, 82 HCLK_GATE, 83 PCLK_GATE, 84 SCLK_GATE, 85 }; 86 87 static unsigned long s3c6410_clk_regs[] __initdata = { 88 CLK_SRC2, 89 MEM0_GATE, 90 }; 91 92 static int s3c64xx_clk_suspend(void) 93 { 94 samsung_clk_save(reg_base, s3c64xx_save_common, 95 ARRAY_SIZE(s3c64xx_clk_regs)); 96 97 if (!is_s3c6400) 98 samsung_clk_save(reg_base, s3c64xx_save_soc, 99 ARRAY_SIZE(s3c6410_clk_regs)); 100 101 return 0; 102 } 103 104 static void s3c64xx_clk_resume(void) 105 { 106 samsung_clk_restore(reg_base, s3c64xx_save_common, 107 ARRAY_SIZE(s3c64xx_clk_regs)); 108 109 if (!is_s3c6400) 110 samsung_clk_restore(reg_base, s3c64xx_save_soc, 111 ARRAY_SIZE(s3c6410_clk_regs)); 112 } 113 114 static struct syscore_ops s3c64xx_clk_syscore_ops = { 115 .suspend = s3c64xx_clk_suspend, 116 .resume = s3c64xx_clk_resume, 117 }; 118 119 static void __init s3c64xx_clk_sleep_init(void) 120 { 121 s3c64xx_save_common = samsung_clk_alloc_reg_dump(s3c64xx_clk_regs, 122 ARRAY_SIZE(s3c64xx_clk_regs)); 123 if (!s3c64xx_save_common) 124 goto err_warn; 125 126 if (!is_s3c6400) { 127 s3c64xx_save_soc = samsung_clk_alloc_reg_dump(s3c6410_clk_regs, 128 ARRAY_SIZE(s3c6410_clk_regs)); 129 if (!s3c64xx_save_soc) 130 goto err_soc; 131 } 132 133 register_syscore_ops(&s3c64xx_clk_syscore_ops); 134 return; 135 136 err_soc: 137 kfree(s3c64xx_save_common); 138 err_warn: 139 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 140 __func__); 141 } 142 #else 143 static void __init s3c64xx_clk_sleep_init(void) {} 144 #endif 145 146 /* List of parent clocks common for all S3C64xx SoCs. */ 147 PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" }; 148 PNAME(uart_p) = { "mout_epll", "dout_mpll" }; 149 PNAME(audio0_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0", 150 "pcmcdclk0", "none", "none", "none" }; 151 PNAME(audio1_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1", 152 "pcmcdclk0", "none", "none", "none" }; 153 PNAME(mfc_p) = { "hclkx2", "mout_epll" }; 154 PNAME(apll_p) = { "fin_pll", "fout_apll" }; 155 PNAME(mpll_p) = { "fin_pll", "fout_mpll" }; 156 PNAME(epll_p) = { "fin_pll", "fout_epll" }; 157 PNAME(hclkx2_p) = { "mout_mpll", "mout_apll" }; 158 159 /* S3C6400-specific parent clocks. */ 160 PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" }; 161 PNAME(irda_p6400) = { "mout_epll", "dout_mpll", "none", "clk48m" }; 162 PNAME(uhost_p6400) = { "clk48m", "mout_epll", "dout_mpll", "none" }; 163 164 /* S3C6410-specific parent clocks. */ 165 PNAME(clk27_p6410) = { "clk27m", "fin_pll" }; 166 PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" }; 167 PNAME(irda_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" }; 168 PNAME(uhost_p6410) = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" }; 169 PNAME(audio2_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk2", 170 "pcmcdclk1", "none", "none", "none" }; 171 172 /* Fixed rate clocks generated outside the SoC. */ 173 FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = { 174 FRATE(0, "fin_pll", NULL, 0, 0), 175 FRATE(0, "xusbxti", NULL, 0, 0), 176 }; 177 178 /* Fixed rate clocks generated inside the SoC. */ 179 FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = { 180 FRATE(CLK27M, "clk27m", NULL, 0, 27000000), 181 FRATE(CLK48M, "clk48m", NULL, 0, 48000000), 182 }; 183 184 /* List of clock muxes present on all S3C64xx SoCs. */ 185 MUX_CLOCKS(s3c64xx_mux_clks) __initdata = { 186 MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY), 187 MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1), 188 MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1), 189 MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1), 190 MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1), 191 MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3), 192 MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3), 193 MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1), 194 MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2), 195 MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2), 196 MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2), 197 MUX(MOUT_MMC1, "mout_mmc1", spi_mmc_p, CLK_SRC, 20, 2), 198 MUX(MOUT_MMC2, "mout_mmc2", spi_mmc_p, CLK_SRC, 22, 2), 199 }; 200 201 /* List of clock muxes present on S3C6400. */ 202 MUX_CLOCKS(s3c6400_mux_clks) __initdata = { 203 MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2), 204 MUX(MOUT_IRDA, "mout_irda", irda_p6400, CLK_SRC, 24, 2), 205 MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6400, CLK_SRC, 26, 2), 206 MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6400, CLK_SRC, 28, 2), 207 }; 208 209 /* List of clock muxes present on S3C6410. */ 210 MUX_CLOCKS(s3c6410_mux_clks) __initdata = { 211 MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2), 212 MUX(MOUT_IRDA, "mout_irda", irda_p6410, CLK_SRC, 24, 2), 213 MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6410, CLK_SRC, 26, 2), 214 MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6410, CLK_SRC, 28, 2), 215 MUX(MOUT_DAC27, "mout_dac27", clk27_p6410, CLK_SRC, 30, 1), 216 MUX(MOUT_TV27, "mout_tv27", clk27_p6410, CLK_SRC, 31, 1), 217 MUX(MOUT_AUDIO2, "mout_audio2", audio2_p6410, CLK_SRC2, 0, 3), 218 }; 219 220 /* List of clock dividers present on all S3C64xx SoCs. */ 221 DIV_CLOCKS(s3c64xx_div_clks) __initdata = { 222 DIV(DOUT_MPLL, "dout_mpll", "mout_mpll", CLK_DIV0, 4, 1), 223 DIV(HCLKX2, "hclkx2", "mout_syncmux", CLK_DIV0, 9, 3), 224 DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1), 225 DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4), 226 DIV(DOUT_SECUR, "dout_secur", "hclkx2", CLK_DIV0, 18, 2), 227 DIV(DOUT_CAM, "dout_cam", "hclkx2", CLK_DIV0, 20, 4), 228 DIV(DOUT_JPEG, "dout_jpeg", "hclkx2", CLK_DIV0, 24, 4), 229 DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV0, 28, 4), 230 DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV1, 0, 4), 231 DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV1, 4, 4), 232 DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV1, 8, 4), 233 DIV(DOUT_LCD, "dout_lcd", "mout_lcd", CLK_DIV1, 12, 4), 234 DIV(DOUT_SCALER, "dout_scaler", "mout_scaler", CLK_DIV1, 16, 4), 235 DIV(DOUT_UHOST, "dout_uhost", "mout_uhost", CLK_DIV1, 20, 4), 236 DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV2, 0, 4), 237 DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV2, 4, 4), 238 DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV2, 8, 4), 239 DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV2, 12, 4), 240 DIV(DOUT_UART, "dout_uart", "mout_uart", CLK_DIV2, 16, 4), 241 DIV(DOUT_IRDA, "dout_irda", "mout_irda", CLK_DIV2, 20, 4), 242 }; 243 244 /* List of clock dividers present on S3C6400. */ 245 DIV_CLOCKS(s3c6400_div_clks) __initdata = { 246 DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 3), 247 }; 248 249 /* List of clock dividers present on S3C6410. */ 250 DIV_CLOCKS(s3c6410_div_clks) __initdata = { 251 DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 4), 252 DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4), 253 DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV2, 24, 4), 254 }; 255 256 /* List of clock gates present on all S3C64xx SoCs. */ 257 GATE_CLOCKS(s3c64xx_gate_clks) __initdata = { 258 GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29), 259 GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28), 260 GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27), 261 GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26), 262 GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24), 263 GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20), 264 GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19), 265 GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18), 266 GATE_BUS(HCLK_HSMMC0, "hclk_hsmmc0", "hclk", HCLK_GATE, 17), 267 GATE_BUS(HCLK_MDP, "hclk_mdp", "hclk", HCLK_GATE, 16), 268 GATE_BUS(HCLK_DHOST, "hclk_dhost", "hclk", HCLK_GATE, 15), 269 GATE_BUS(HCLK_IHOST, "hclk_ihost", "hclk", HCLK_GATE, 14), 270 GATE_BUS(HCLK_DMA1, "hclk_dma1", "hclk", HCLK_GATE, 13), 271 GATE_BUS(HCLK_DMA0, "hclk_dma0", "hclk", HCLK_GATE, 12), 272 GATE_BUS(HCLK_JPEG, "hclk_jpeg", "hclk", HCLK_GATE, 11), 273 GATE_BUS(HCLK_CAMIF, "hclk_camif", "hclk", HCLK_GATE, 10), 274 GATE_BUS(HCLK_SCALER, "hclk_scaler", "hclk", HCLK_GATE, 9), 275 GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8), 276 GATE_BUS(HCLK_TV, "hclk_tv", "hclk", HCLK_GATE, 7), 277 GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5), 278 GATE_BUS(HCLK_ROT, "hclk_rot", "hclk", HCLK_GATE, 4), 279 GATE_BUS(HCLK_LCD, "hclk_lcd", "hclk", HCLK_GATE, 3), 280 GATE_BUS(HCLK_TZIC, "hclk_tzic", "hclk", HCLK_GATE, 2), 281 GATE_ON(HCLK_INTC, "hclk_intc", "hclk", HCLK_GATE, 1), 282 GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24), 283 GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23), 284 GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22), 285 GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21), 286 GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20), 287 GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19), 288 GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18), 289 GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17), 290 GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16), 291 GATE_BUS(PCLK_IIS0, "pclk_iis0", "pclk", PCLK_GATE, 15), 292 GATE_BUS(PCLK_AC97, "pclk_ac97", "pclk", PCLK_GATE, 14), 293 GATE_BUS(PCLK_TZPC, "pclk_tzpc", "pclk", PCLK_GATE, 13), 294 GATE_BUS(PCLK_TSADC, "pclk_tsadc", "pclk", PCLK_GATE, 12), 295 GATE_BUS(PCLK_KEYPAD, "pclk_keypad", "pclk", PCLK_GATE, 11), 296 GATE_BUS(PCLK_IRDA, "pclk_irda", "pclk", PCLK_GATE, 10), 297 GATE_BUS(PCLK_PCM1, "pclk_pcm1", "pclk", PCLK_GATE, 9), 298 GATE_BUS(PCLK_PCM0, "pclk_pcm0", "pclk", PCLK_GATE, 8), 299 GATE_BUS(PCLK_PWM, "pclk_pwm", "pclk", PCLK_GATE, 7), 300 GATE_BUS(PCLK_RTC, "pclk_rtc", "pclk", PCLK_GATE, 6), 301 GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5), 302 GATE_BUS(PCLK_UART3, "pclk_uart3", "pclk", PCLK_GATE, 4), 303 GATE_BUS(PCLK_UART2, "pclk_uart2", "pclk", PCLK_GATE, 3), 304 GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2), 305 GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1), 306 GATE_BUS(PCLK_MFC, "pclk_mfc", "pclk", PCLK_GATE, 0), 307 GATE_SCLK(SCLK_UHOST, "sclk_uhost", "dout_uhost", SCLK_GATE, 30), 308 GATE_SCLK(SCLK_MMC2_48, "sclk_mmc2_48", "clk48m", SCLK_GATE, 29), 309 GATE_SCLK(SCLK_MMC1_48, "sclk_mmc1_48", "clk48m", SCLK_GATE, 28), 310 GATE_SCLK(SCLK_MMC0_48, "sclk_mmc0_48", "clk48m", SCLK_GATE, 27), 311 GATE_SCLK(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", SCLK_GATE, 26), 312 GATE_SCLK(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", SCLK_GATE, 25), 313 GATE_SCLK(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", SCLK_GATE, 24), 314 GATE_SCLK(SCLK_SPI1_48, "sclk_spi1_48", "clk48m", SCLK_GATE, 23), 315 GATE_SCLK(SCLK_SPI0_48, "sclk_spi0_48", "clk48m", SCLK_GATE, 22), 316 GATE_SCLK(SCLK_SPI1, "sclk_spi1", "dout_spi1", SCLK_GATE, 21), 317 GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20), 318 GATE_SCLK(SCLK_DAC27, "sclk_dac27", "mout_dac27", SCLK_GATE, 19), 319 GATE_SCLK(SCLK_TV27, "sclk_tv27", "mout_tv27", SCLK_GATE, 18), 320 GATE_SCLK(SCLK_SCALER27, "sclk_scaler27", "clk27m", SCLK_GATE, 17), 321 GATE_SCLK(SCLK_SCALER, "sclk_scaler", "dout_scaler", SCLK_GATE, 16), 322 GATE_SCLK(SCLK_LCD27, "sclk_lcd27", "clk27m", SCLK_GATE, 15), 323 GATE_SCLK(SCLK_LCD, "sclk_lcd", "dout_lcd", SCLK_GATE, 14), 324 GATE_SCLK(SCLK_POST0_27, "sclk_post0_27", "clk27m", SCLK_GATE, 12), 325 GATE_SCLK(SCLK_POST0, "sclk_post0", "dout_lcd", SCLK_GATE, 10), 326 GATE_SCLK(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", SCLK_GATE, 9), 327 GATE_SCLK(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", SCLK_GATE, 8), 328 GATE_SCLK(SCLK_SECUR, "sclk_secur", "dout_secur", SCLK_GATE, 7), 329 GATE_SCLK(SCLK_IRDA, "sclk_irda", "dout_irda", SCLK_GATE, 6), 330 GATE_SCLK(SCLK_UART, "sclk_uart", "dout_uart", SCLK_GATE, 5), 331 GATE_SCLK(SCLK_MFC, "sclk_mfc", "dout_mfc", SCLK_GATE, 3), 332 GATE_SCLK(SCLK_CAM, "sclk_cam", "dout_cam", SCLK_GATE, 2), 333 GATE_SCLK(SCLK_JPEG, "sclk_jpeg", "dout_jpeg", SCLK_GATE, 1), 334 }; 335 336 /* List of clock gates present on S3C6400. */ 337 GATE_CLOCKS(s3c6400_gate_clks) __initdata = { 338 GATE_ON(HCLK_DDR0, "hclk_ddr0", "hclk", HCLK_GATE, 23), 339 GATE_SCLK(SCLK_ONENAND, "sclk_onenand", "parent", SCLK_GATE, 4), 340 }; 341 342 /* List of clock gates present on S3C6410. */ 343 GATE_CLOCKS(s3c6410_gate_clks) __initdata = { 344 GATE_BUS(HCLK_3DSE, "hclk_3dse", "hclk", HCLK_GATE, 31), 345 GATE_ON(HCLK_IROM, "hclk_irom", "hclk", HCLK_GATE, 25), 346 GATE_ON(HCLK_MEM1, "hclk_mem1", "hclk", HCLK_GATE, 22), 347 GATE_ON(HCLK_MEM0, "hclk_mem0", "hclk", HCLK_GATE, 21), 348 GATE_BUS(HCLK_MFC, "hclk_mfc", "hclk", HCLK_GATE, 0), 349 GATE_BUS(PCLK_IIC1, "pclk_iic1", "pclk", PCLK_GATE, 27), 350 GATE_BUS(PCLK_IIS2, "pclk_iis2", "pclk", PCLK_GATE, 26), 351 GATE_SCLK(SCLK_FIMC, "sclk_fimc", "dout_fimc", SCLK_GATE, 13), 352 GATE_SCLK(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", SCLK_GATE, 11), 353 GATE_BUS(MEM0_CFCON, "mem0_cfcon", "hclk_mem0", MEM0_GATE, 5), 354 GATE_BUS(MEM0_ONENAND1, "mem0_onenand1", "hclk_mem0", MEM0_GATE, 4), 355 GATE_BUS(MEM0_ONENAND0, "mem0_onenand0", "hclk_mem0", MEM0_GATE, 3), 356 GATE_BUS(MEM0_NFCON, "mem0_nfcon", "hclk_mem0", MEM0_GATE, 2), 357 GATE_ON(MEM0_SROM, "mem0_srom", "hclk_mem0", MEM0_GATE, 1), 358 }; 359 360 /* List of PLL clocks. */ 361 static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = { 362 PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll", 363 APLL_LOCK, APLL_CON, NULL), 364 PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll", 365 MPLL_LOCK, MPLL_CON, NULL), 366 PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll", 367 EPLL_LOCK, EPLL_CON0, NULL), 368 }; 369 370 /* Aliases for common s3c64xx clocks. */ 371 static struct samsung_clock_alias s3c64xx_clock_aliases[] = { 372 ALIAS(FOUT_APLL, NULL, "fout_apll"), 373 ALIAS(FOUT_MPLL, NULL, "fout_mpll"), 374 ALIAS(FOUT_EPLL, NULL, "fout_epll"), 375 ALIAS(MOUT_EPLL, NULL, "mout_epll"), 376 ALIAS(DOUT_MPLL, NULL, "dout_mpll"), 377 ALIAS(HCLKX2, NULL, "hclk2"), 378 ALIAS(HCLK, NULL, "hclk"), 379 ALIAS(PCLK, NULL, "pclk"), 380 ALIAS(PCLK, NULL, "clk_uart_baud2"), 381 ALIAS(ARMCLK, NULL, "armclk"), 382 ALIAS(HCLK_UHOST, "s3c2410-ohci", "usb-host"), 383 ALIAS(HCLK_USB, "s3c-hsotg", "otg"), 384 ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "hsmmc"), 385 ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "mmc_busclk.0"), 386 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"), 387 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"), 388 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"), 389 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"), 390 ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"), 391 ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"), 392 ALIAS(HCLK_CAMIF, "s3c-camif", "camif"), 393 ALIAS(HCLK_LCD, "s3c-fb", "lcd"), 394 ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"), 395 ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi"), 396 ALIAS(PCLK_IIC0, "s3c2440-i2c.0", "i2c"), 397 ALIAS(PCLK_IIS1, "samsung-i2s.1", "iis"), 398 ALIAS(PCLK_IIS0, "samsung-i2s.0", "iis"), 399 ALIAS(PCLK_AC97, "samsung-ac97", "ac97"), 400 ALIAS(PCLK_TSADC, "s3c64xx-adc", "adc"), 401 ALIAS(PCLK_KEYPAD, "samsung-keypad", "keypad"), 402 ALIAS(PCLK_PCM1, "samsung-pcm.1", "pcm"), 403 ALIAS(PCLK_PCM0, "samsung-pcm.0", "pcm"), 404 ALIAS(PCLK_PWM, NULL, "timers"), 405 ALIAS(PCLK_RTC, "s3c64xx-rtc", "rtc"), 406 ALIAS(PCLK_WDT, NULL, "watchdog"), 407 ALIAS(PCLK_UART3, "s3c6400-uart.3", "uart"), 408 ALIAS(PCLK_UART2, "s3c6400-uart.2", "uart"), 409 ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"), 410 ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"), 411 ALIAS(SCLK_UHOST, "s3c2410-ohci", "usb-bus-host"), 412 ALIAS(SCLK_MMC2, "s3c-sdhci.2", "mmc_busclk.2"), 413 ALIAS(SCLK_MMC1, "s3c-sdhci.1", "mmc_busclk.2"), 414 ALIAS(SCLK_MMC0, "s3c-sdhci.0", "mmc_busclk.2"), 415 ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi_busclk0"), 416 ALIAS(SCLK_SPI1, "s3c6410-spi.1", "spi_busclk2"), 417 ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi_busclk0"), 418 ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi_busclk2"), 419 ALIAS(SCLK_AUDIO1, "samsung-pcm.1", "audio-bus"), 420 ALIAS(SCLK_AUDIO1, "samsung-i2s.1", "audio-bus"), 421 ALIAS(SCLK_AUDIO0, "samsung-pcm.0", "audio-bus"), 422 ALIAS(SCLK_AUDIO0, "samsung-i2s.0", "audio-bus"), 423 ALIAS(SCLK_UART, NULL, "clk_uart_baud3"), 424 ALIAS(SCLK_CAM, "s3c-camif", "camera"), 425 }; 426 427 /* Aliases for s3c6400-specific clocks. */ 428 static struct samsung_clock_alias s3c6400_clock_aliases[] = { 429 /* Nothing to place here yet. */ 430 }; 431 432 /* Aliases for s3c6410-specific clocks. */ 433 static struct samsung_clock_alias s3c6410_clock_aliases[] = { 434 ALIAS(PCLK_IIC1, "s3c2440-i2c.1", "i2c"), 435 ALIAS(PCLK_IIS2, "samsung-i2s.2", "iis"), 436 ALIAS(SCLK_FIMC, "s3c-camif", "fimc"), 437 ALIAS(SCLK_AUDIO2, "samsung-i2s.2", "audio-bus"), 438 ALIAS(MEM0_SROM, NULL, "srom"), 439 }; 440 441 static void __init s3c64xx_clk_register_fixed_ext( 442 struct samsung_clk_provider *ctx, 443 unsigned long fin_pll_f, 444 unsigned long xusbxti_f) 445 { 446 s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f; 447 s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f; 448 samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks, 449 ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks)); 450 } 451 452 /* Register s3c64xx clocks. */ 453 void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, 454 unsigned long xusbxti_f, bool s3c6400, 455 void __iomem *base) 456 { 457 struct samsung_clk_provider *ctx; 458 459 reg_base = base; 460 is_s3c6400 = s3c6400; 461 462 if (np) { 463 reg_base = of_iomap(np, 0); 464 if (!reg_base) 465 panic("%s: failed to map registers\n", __func__); 466 } 467 468 ctx = samsung_clk_init(np, reg_base, NR_CLKS); 469 470 /* Register external clocks. */ 471 if (!np) 472 s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f); 473 474 /* Register PLLs. */ 475 samsung_clk_register_pll(ctx, s3c64xx_pll_clks, 476 ARRAY_SIZE(s3c64xx_pll_clks), reg_base); 477 478 /* Register common internal clocks. */ 479 samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks, 480 ARRAY_SIZE(s3c64xx_fixed_rate_clks)); 481 samsung_clk_register_mux(ctx, s3c64xx_mux_clks, 482 ARRAY_SIZE(s3c64xx_mux_clks)); 483 samsung_clk_register_div(ctx, s3c64xx_div_clks, 484 ARRAY_SIZE(s3c64xx_div_clks)); 485 samsung_clk_register_gate(ctx, s3c64xx_gate_clks, 486 ARRAY_SIZE(s3c64xx_gate_clks)); 487 488 /* Register SoC-specific clocks. */ 489 if (is_s3c6400) { 490 samsung_clk_register_mux(ctx, s3c6400_mux_clks, 491 ARRAY_SIZE(s3c6400_mux_clks)); 492 samsung_clk_register_div(ctx, s3c6400_div_clks, 493 ARRAY_SIZE(s3c6400_div_clks)); 494 samsung_clk_register_gate(ctx, s3c6400_gate_clks, 495 ARRAY_SIZE(s3c6400_gate_clks)); 496 samsung_clk_register_alias(ctx, s3c6400_clock_aliases, 497 ARRAY_SIZE(s3c6400_clock_aliases)); 498 } else { 499 samsung_clk_register_mux(ctx, s3c6410_mux_clks, 500 ARRAY_SIZE(s3c6410_mux_clks)); 501 samsung_clk_register_div(ctx, s3c6410_div_clks, 502 ARRAY_SIZE(s3c6410_div_clks)); 503 samsung_clk_register_gate(ctx, s3c6410_gate_clks, 504 ARRAY_SIZE(s3c6410_gate_clks)); 505 samsung_clk_register_alias(ctx, s3c6410_clock_aliases, 506 ARRAY_SIZE(s3c6410_clock_aliases)); 507 } 508 509 samsung_clk_register_alias(ctx, s3c64xx_clock_aliases, 510 ARRAY_SIZE(s3c64xx_clock_aliases)); 511 s3c64xx_clk_sleep_init(); 512 513 samsung_clk_of_add_provider(np, ctx); 514 515 pr_info("%s clocks: apll = %lu, mpll = %lu\n" 516 "\tepll = %lu, arm_clk = %lu\n", 517 is_s3c6400 ? "S3C6400" : "S3C6410", 518 _get_rate("fout_apll"), _get_rate("fout_mpll"), 519 _get_rate("fout_epll"), _get_rate("armclk")); 520 } 521 522 static void __init s3c6400_clk_init(struct device_node *np) 523 { 524 s3c64xx_clk_init(np, 0, 0, true, NULL); 525 } 526 CLK_OF_DECLARE(s3c6400_clk, "samsung,s3c6400-clock", s3c6400_clk_init); 527 528 static void __init s3c6410_clk_init(struct device_node *np) 529 { 530 s3c64xx_clk_init(np, 0, 0, false, NULL); 531 } 532 CLK_OF_DECLARE(s3c6410_clk, "samsung,s3c6410-clock", s3c6410_clk_init); 533