xref: /openbmc/linux/drivers/clk/samsung/clk-pll.h (revision a8a28aff)
1 /*
2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3  * Copyright (c) 2013 Linaro Ltd.
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * Common Clock Framework support for all PLL's in Samsung platforms
10 */
11 
12 #ifndef __SAMSUNG_CLK_PLL_H
13 #define __SAMSUNG_CLK_PLL_H
14 
15 enum samsung_pll_type {
16 	pll_2126,
17 	pll_3000,
18 	pll_35xx,
19 	pll_36xx,
20 	pll_2550,
21 	pll_2650,
22 	pll_4500,
23 	pll_4502,
24 	pll_4508,
25 	pll_4600,
26 	pll_4650,
27 	pll_4650c,
28 	pll_6552,
29 	pll_6552_s3c2416,
30 	pll_6553,
31 	pll_s3c2410_mpll,
32 	pll_s3c2410_upll,
33 	pll_s3c2440_mpll,
34 	pll_2550xx,
35 	pll_2650xx,
36 };
37 
38 #define PLL_35XX_RATE(_rate, _m, _p, _s)			\
39 	{							\
40 		.rate	=	(_rate),				\
41 		.mdiv	=	(_m),				\
42 		.pdiv	=	(_p),				\
43 		.sdiv	=	(_s),				\
44 	}
45 
46 #define PLL_36XX_RATE(_rate, _m, _p, _s, _k)			\
47 	{							\
48 		.rate	=	(_rate),				\
49 		.mdiv	=	(_m),				\
50 		.pdiv	=	(_p),				\
51 		.sdiv	=	(_s),				\
52 		.kdiv	=	(_k),				\
53 	}
54 
55 #define PLL_45XX_RATE(_rate, _m, _p, _s, _afc)			\
56 	{							\
57 		.rate	=	(_rate),			\
58 		.mdiv	=	(_m),				\
59 		.pdiv	=	(_p),				\
60 		.sdiv	=	(_s),				\
61 		.afc	=	(_afc),				\
62 	}
63 
64 #define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel)		\
65 	{							\
66 		.rate	=	(_rate),			\
67 		.mdiv	=	(_m),				\
68 		.pdiv	=	(_p),				\
69 		.sdiv	=	(_s),				\
70 		.kdiv	=	(_k),				\
71 		.vsel	=	(_vsel),			\
72 	}
73 
74 #define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel)	\
75 	{							\
76 		.rate	=	(_rate),			\
77 		.mdiv	=	(_m),				\
78 		.pdiv	=	(_p),				\
79 		.sdiv	=	(_s),				\
80 		.kdiv	=	(_k),				\
81 		.mfr	=	(_mfr),				\
82 		.mrr	=	(_mrr),				\
83 		.vsel	=	(_vsel),			\
84 	}
85 
86 /* NOTE: Rate table should be kept sorted in descending order. */
87 
88 struct samsung_pll_rate_table {
89 	unsigned int rate;
90 	unsigned int pdiv;
91 	unsigned int mdiv;
92 	unsigned int sdiv;
93 	unsigned int kdiv;
94 	unsigned int afc;
95 	unsigned int mfr;
96 	unsigned int mrr;
97 	unsigned int vsel;
98 };
99 
100 extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
101 			const char *pname, const void __iomem *reg_base,
102 			const unsigned long offset);
103 
104 #endif /* __SAMSUNG_CLK_PLL_H */
105