1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2013 Linaro Ltd. 5 * 6 * Common Clock Framework support for all PLL's in Samsung platforms 7 */ 8 9 #ifndef __SAMSUNG_CLK_PLL_H 10 #define __SAMSUNG_CLK_PLL_H 11 12 enum samsung_pll_type { 13 pll_2126, 14 pll_3000, 15 pll_35xx, 16 pll_36xx, 17 pll_2550, 18 pll_2650, 19 pll_4500, 20 pll_4502, 21 pll_4508, 22 pll_4600, 23 pll_4650, 24 pll_4650c, 25 pll_6552, 26 pll_6552_s3c2416, 27 pll_6553, 28 pll_s3c2410_mpll, 29 pll_s3c2410_upll, 30 pll_s3c2440_mpll, 31 pll_2550x, 32 pll_2550xx, 33 pll_2650x, 34 pll_2650xx, 35 pll_1450x, 36 pll_1451x, 37 pll_1452x, 38 pll_1460x, 39 pll_0822x, 40 pll_0831x, 41 }; 42 43 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ 44 ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s))) 45 #define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \ 46 BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout))) 47 48 #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \ 49 { \ 50 .rate = PLL_VALID_RATE(_fin, _rate, \ 51 _m, _p, _s, 0, 16), \ 52 .mdiv = (_m), \ 53 .pdiv = (_p), \ 54 .sdiv = (_s), \ 55 } 56 57 #define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s) \ 58 { \ 59 .rate = PLL_VALID_RATE(_fin, _rate, \ 60 _m + 8, _p + 2, _s, 0, 16), \ 61 .mdiv = (_m), \ 62 .pdiv = (_p), \ 63 .sdiv = (_s), \ 64 } 65 66 #define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s) \ 67 { \ 68 .rate = PLL_VALID_RATE(_fin, _rate, \ 69 2 * (_m + 8), _p + 2, _s, 0, 16), \ 70 .mdiv = (_m), \ 71 .pdiv = (_p), \ 72 .sdiv = (_s), \ 73 } 74 75 #define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \ 76 { \ 77 .rate = PLL_VALID_RATE(_fin, _rate, \ 78 _m, _p, _s, _k, 16), \ 79 .mdiv = (_m), \ 80 .pdiv = (_p), \ 81 .sdiv = (_s), \ 82 .kdiv = (_k), \ 83 } 84 85 #define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc) \ 86 { \ 87 .rate = PLL_VALID_RATE(_fin, _rate, \ 88 _m, _p, _s - 1, 0, 16), \ 89 .mdiv = (_m), \ 90 .pdiv = (_p), \ 91 .sdiv = (_s), \ 92 .afc = (_afc), \ 93 } 94 95 #define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel) \ 96 { \ 97 .rate = PLL_VALID_RATE(_fin, _rate, \ 98 _m, _p, _s, _k, 16), \ 99 .mdiv = (_m), \ 100 .pdiv = (_p), \ 101 .sdiv = (_s), \ 102 .kdiv = (_k), \ 103 .vsel = (_vsel), \ 104 } 105 106 #define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \ 107 { \ 108 .rate = PLL_VALID_RATE(_fin, _rate, \ 109 _m, _p, _s, _k, 10), \ 110 .mdiv = (_m), \ 111 .pdiv = (_p), \ 112 .sdiv = (_s), \ 113 .kdiv = (_k), \ 114 .mfr = (_mfr), \ 115 .mrr = (_mrr), \ 116 .vsel = (_vsel), \ 117 } 118 119 /* NOTE: Rate table should be kept sorted in descending order. */ 120 121 struct samsung_pll_rate_table { 122 unsigned int rate; 123 unsigned int pdiv; 124 unsigned int mdiv; 125 unsigned int sdiv; 126 unsigned int kdiv; 127 unsigned int afc; 128 unsigned int mfr; 129 unsigned int mrr; 130 unsigned int vsel; 131 }; 132 133 #endif /* __SAMSUNG_CLK_PLL_H */ 134