1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. 4 * https://www.samsung.com 5 * Copyright (c) 2017-2022 Tesla, Inc. 6 * https://www.tesla.com 7 * 8 * Common Clock Framework support for FSD SoC. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 20 #include <dt-bindings/clock/fsd-clk.h> 21 22 #include "clk.h" 23 #include "clk-exynos-arm64.h" 24 25 /* Register Offset definitions for CMU_CMU (0x11c10000) */ 26 #define PLL_LOCKTIME_PLL_SHARED0 0x0 27 #define PLL_LOCKTIME_PLL_SHARED1 0x4 28 #define PLL_LOCKTIME_PLL_SHARED2 0x8 29 #define PLL_LOCKTIME_PLL_SHARED3 0xc 30 #define PLL_CON0_PLL_SHARED0 0x100 31 #define PLL_CON0_PLL_SHARED1 0x120 32 #define PLL_CON0_PLL_SHARED2 0x140 33 #define PLL_CON0_PLL_SHARED3 0x160 34 #define MUX_CMU_CIS0_CLKMUX 0x1000 35 #define MUX_CMU_CIS1_CLKMUX 0x1004 36 #define MUX_CMU_CIS2_CLKMUX 0x1008 37 #define MUX_CMU_CPUCL_SWITCHMUX 0x100c 38 #define MUX_CMU_FSYS1_ACLK_MUX 0x1014 39 #define MUX_PLL_SHARED0_MUX 0x1020 40 #define MUX_PLL_SHARED1_MUX 0x1024 41 #define DIV_CMU_CIS0_CLK 0x1800 42 #define DIV_CMU_CIS1_CLK 0x1804 43 #define DIV_CMU_CIS2_CLK 0x1808 44 #define DIV_CMU_CMU_ACLK 0x180c 45 #define DIV_CMU_CPUCL_SWITCH 0x1810 46 #define DIV_CMU_FSYS0_SHARED0DIV4 0x181c 47 #define DIV_CMU_FSYS0_SHARED1DIV3 0x1820 48 #define DIV_CMU_FSYS0_SHARED1DIV4 0x1824 49 #define DIV_CMU_FSYS1_SHARED0DIV4 0x1828 50 #define DIV_CMU_FSYS1_SHARED0DIV8 0x182c 51 #define DIV_CMU_IMEM_ACLK 0x1834 52 #define DIV_CMU_IMEM_DMACLK 0x1838 53 #define DIV_CMU_IMEM_TCUCLK 0x183c 54 #define DIV_CMU_PERIC_SHARED0DIV20 0x1844 55 #define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK 0x1848 56 #define DIV_CMU_PERIC_SHARED1DIV36 0x184c 57 #define DIV_CMU_PERIC_SHARED1DIV4_DMACLK 0x1850 58 #define DIV_PLL_SHARED0_DIV2 0x1858 59 #define DIV_PLL_SHARED0_DIV3 0x185c 60 #define DIV_PLL_SHARED0_DIV4 0x1860 61 #define DIV_PLL_SHARED0_DIV6 0x1864 62 #define DIV_PLL_SHARED1_DIV3 0x1868 63 #define DIV_PLL_SHARED1_DIV36 0x186c 64 #define DIV_PLL_SHARED1_DIV4 0x1870 65 #define DIV_PLL_SHARED1_DIV9 0x1874 66 #define GAT_CMU_CIS0_CLKGATE 0x2000 67 #define GAT_CMU_CIS1_CLKGATE 0x2004 68 #define GAT_CMU_CIS2_CLKGATE 0x2008 69 #define GAT_CMU_CPUCL_SWITCH_GATE 0x200c 70 #define GAT_CMU_FSYS0_SHARED0DIV4_GATE 0x2018 71 #define GAT_CMU_FSYS0_SHARED1DIV4_CLK 0x201c 72 #define GAT_CMU_FSYS0_SHARED1DIV4_GATE 0x2020 73 #define GAT_CMU_FSYS1_SHARED0DIV4_GATE 0x2024 74 #define GAT_CMU_FSYS1_SHARED1DIV4_GATE 0x2028 75 #define GAT_CMU_IMEM_ACLK_GATE 0x2030 76 #define GAT_CMU_IMEM_DMACLK_GATE 0x2034 77 #define GAT_CMU_IMEM_TCUCLK_GATE 0x2038 78 #define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE 0x2040 79 #define GAT_CMU_PERIC_SHARED0DIVE4_GATE 0x2044 80 #define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE 0x2048 81 #define GAT_CMU_PERIC_SHARED1DIVE4_GATE 0x204c 82 #define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK 0x2054 83 #define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK 0x2058 84 #define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c 85 #define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060 86 87 static const unsigned long cmu_clk_regs[] __initconst = { 88 PLL_LOCKTIME_PLL_SHARED0, 89 PLL_LOCKTIME_PLL_SHARED1, 90 PLL_LOCKTIME_PLL_SHARED2, 91 PLL_LOCKTIME_PLL_SHARED3, 92 PLL_CON0_PLL_SHARED0, 93 PLL_CON0_PLL_SHARED1, 94 PLL_CON0_PLL_SHARED2, 95 PLL_CON0_PLL_SHARED3, 96 MUX_CMU_CIS0_CLKMUX, 97 MUX_CMU_CIS1_CLKMUX, 98 MUX_CMU_CIS2_CLKMUX, 99 MUX_CMU_CPUCL_SWITCHMUX, 100 MUX_CMU_FSYS1_ACLK_MUX, 101 MUX_PLL_SHARED0_MUX, 102 MUX_PLL_SHARED1_MUX, 103 DIV_CMU_CIS0_CLK, 104 DIV_CMU_CIS1_CLK, 105 DIV_CMU_CIS2_CLK, 106 DIV_CMU_CMU_ACLK, 107 DIV_CMU_CPUCL_SWITCH, 108 DIV_CMU_FSYS0_SHARED0DIV4, 109 DIV_CMU_FSYS0_SHARED1DIV3, 110 DIV_CMU_FSYS0_SHARED1DIV4, 111 DIV_CMU_FSYS1_SHARED0DIV4, 112 DIV_CMU_FSYS1_SHARED0DIV8, 113 DIV_CMU_IMEM_ACLK, 114 DIV_CMU_IMEM_DMACLK, 115 DIV_CMU_IMEM_TCUCLK, 116 DIV_CMU_PERIC_SHARED0DIV20, 117 DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 118 DIV_CMU_PERIC_SHARED1DIV36, 119 DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 120 DIV_PLL_SHARED0_DIV2, 121 DIV_PLL_SHARED0_DIV3, 122 DIV_PLL_SHARED0_DIV4, 123 DIV_PLL_SHARED0_DIV6, 124 DIV_PLL_SHARED1_DIV3, 125 DIV_PLL_SHARED1_DIV36, 126 DIV_PLL_SHARED1_DIV4, 127 DIV_PLL_SHARED1_DIV9, 128 GAT_CMU_CIS0_CLKGATE, 129 GAT_CMU_CIS1_CLKGATE, 130 GAT_CMU_CIS2_CLKGATE, 131 GAT_CMU_CPUCL_SWITCH_GATE, 132 GAT_CMU_FSYS0_SHARED0DIV4_GATE, 133 GAT_CMU_FSYS0_SHARED1DIV4_CLK, 134 GAT_CMU_FSYS0_SHARED1DIV4_GATE, 135 GAT_CMU_FSYS1_SHARED0DIV4_GATE, 136 GAT_CMU_FSYS1_SHARED1DIV4_GATE, 137 GAT_CMU_IMEM_ACLK_GATE, 138 GAT_CMU_IMEM_DMACLK_GATE, 139 GAT_CMU_IMEM_TCUCLK_GATE, 140 GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 141 GAT_CMU_PERIC_SHARED0DIVE4_GATE, 142 GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 143 GAT_CMU_PERIC_SHARED1DIVE4_GATE, 144 GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 145 GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 146 GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 147 GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 148 }; 149 150 static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = { 151 PLL_35XX_RATE(24 * MHZ, 2000000000U, 250, 3, 0), 152 }; 153 154 static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = { 155 PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0), 156 }; 157 158 static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = { 159 PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0), 160 }; 161 162 static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = { 163 PLL_35XX_RATE(24 * MHZ, 1800000000U, 150, 2, 0), 164 }; 165 166 static const struct samsung_pll_clock cmu_pll_clks[] __initconst = { 167 PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0, 168 PLL_CON0_PLL_SHARED0, pll_shared0_rate_table), 169 PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1, 170 PLL_CON0_PLL_SHARED1, pll_shared1_rate_table), 171 PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2, 172 PLL_CON0_PLL_SHARED2, pll_shared2_rate_table), 173 PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3, 174 PLL_CON0_PLL_SHARED3, pll_shared3_rate_table), 175 }; 176 177 /* List of parent clocks for Muxes in CMU_CMU */ 178 PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" }; 179 PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" }; 180 PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" }; 181 PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" }; 182 PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; 183 PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; 184 PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; 185 PNAME(mout_cmu_cpucl_switchmux_p) = { "mout_cmu_pll_shared2", "mout_cmu_pll_shared0_mux" }; 186 PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" }; 187 PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" }; 188 PNAME(mout_cmu_pll_shared1_mux_p) = { "fin_pll", "mout_cmu_pll_shared1" }; 189 190 static const struct samsung_mux_clock cmu_mux_clks[] __initconst = { 191 MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1), 192 MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1), 193 MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1), 194 MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1), 195 MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1), 196 MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1), 197 MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1), 198 MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p, 199 MUX_CMU_CPUCL_SWITCHMUX, 0, 1), 200 MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1), 201 MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1), 202 MUX(0, "mout_cmu_pll_shared1_mux", mout_cmu_pll_shared1_mux_p, MUX_PLL_SHARED1_MUX, 0, 1), 203 }; 204 205 static const struct samsung_div_clock cmu_div_clks[] __initconst = { 206 DIV(0, "dout_cmu_cis0_clk", "cmu_cis0_clkgate", DIV_CMU_CIS0_CLK, 0, 4), 207 DIV(0, "dout_cmu_cis1_clk", "cmu_cis1_clkgate", DIV_CMU_CIS1_CLK, 0, 4), 208 DIV(0, "dout_cmu_cis2_clk", "cmu_cis2_clkgate", DIV_CMU_CIS2_CLK, 0, 4), 209 DIV(0, "dout_cmu_cmu_aclk", "dout_cmu_pll_shared1_div9", DIV_CMU_CMU_ACLK, 0, 4), 210 DIV(0, "dout_cmu_cpucl_switch", "cmu_cpucl_switch_gate", DIV_CMU_CPUCL_SWITCH, 0, 4), 211 DIV(DOUT_CMU_FSYS0_SHARED0DIV4, "dout_cmu_fsys0_shared0div4", "cmu_fsys0_shared0div4_gate", 212 DIV_CMU_FSYS0_SHARED0DIV4, 0, 4), 213 DIV(0, "dout_cmu_fsys0_shared1div3", "cmu_fsys0_shared1div4_clk", 214 DIV_CMU_FSYS0_SHARED1DIV3, 0, 4), 215 DIV(DOUT_CMU_FSYS0_SHARED1DIV4, "dout_cmu_fsys0_shared1div4", "cmu_fsys0_shared1div4_gate", 216 DIV_CMU_FSYS0_SHARED1DIV4, 0, 4), 217 DIV(DOUT_CMU_FSYS1_SHARED0DIV4, "dout_cmu_fsys1_shared0div4", "cmu_fsys1_shared0div4_gate", 218 DIV_CMU_FSYS1_SHARED0DIV4, 0, 4), 219 DIV(DOUT_CMU_FSYS1_SHARED0DIV8, "dout_cmu_fsys1_shared0div8", "cmu_fsys1_shared1div4_gate", 220 DIV_CMU_FSYS1_SHARED0DIV8, 0, 4), 221 DIV(DOUT_CMU_IMEM_ACLK, "dout_cmu_imem_aclk", "cmu_imem_aclk_gate", 222 DIV_CMU_IMEM_ACLK, 0, 4), 223 DIV(DOUT_CMU_IMEM_DMACLK, "dout_cmu_imem_dmaclk", "cmu_imem_dmaclk_gate", 224 DIV_CMU_IMEM_DMACLK, 0, 4), 225 DIV(DOUT_CMU_IMEM_TCUCLK, "dout_cmu_imem_tcuclk", "cmu_imem_tcuclk_gate", 226 DIV_CMU_IMEM_TCUCLK, 0, 4), 227 DIV(DOUT_CMU_PERIC_SHARED0DIV20, "dout_cmu_peric_shared0div20", 228 "cmu_peric_shared0dive4_gate", DIV_CMU_PERIC_SHARED0DIV20, 0, 4), 229 DIV(DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK, "dout_cmu_peric_shared0div3_tbuclk", 230 "cmu_peric_shared0dive3_tbuclk_gate", DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 0, 4), 231 DIV(DOUT_CMU_PERIC_SHARED1DIV36, "dout_cmu_peric_shared1div36", 232 "cmu_peric_shared1dive4_gate", DIV_CMU_PERIC_SHARED1DIV36, 0, 4), 233 DIV(DOUT_CMU_PERIC_SHARED1DIV4_DMACLK, "dout_cmu_peric_shared1div4_dmaclk", 234 "cmu_peric_shared1div4_dmaclk_gate", DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 0, 4), 235 DIV(0, "dout_cmu_pll_shared0_div2", "mout_cmu_pll_shared0_mux", 236 DIV_PLL_SHARED0_DIV2, 0, 4), 237 DIV(0, "dout_cmu_pll_shared0_div3", "mout_cmu_pll_shared0_mux", 238 DIV_PLL_SHARED0_DIV3, 0, 4), 239 DIV(DOUT_CMU_PLL_SHARED0_DIV4, "dout_cmu_pll_shared0_div4", "dout_cmu_pll_shared0_div2", 240 DIV_PLL_SHARED0_DIV4, 0, 4), 241 DIV(DOUT_CMU_PLL_SHARED0_DIV6, "dout_cmu_pll_shared0_div6", "dout_cmu_pll_shared0_div3", 242 DIV_PLL_SHARED0_DIV6, 0, 4), 243 DIV(0, "dout_cmu_pll_shared1_div3", "mout_cmu_pll_shared1_mux", 244 DIV_PLL_SHARED1_DIV3, 0, 4), 245 DIV(0, "dout_cmu_pll_shared1_div36", "dout_cmu_pll_shared1_div9", 246 DIV_PLL_SHARED1_DIV36, 0, 4), 247 DIV(0, "dout_cmu_pll_shared1_div4", "mout_cmu_pll_shared1_mux", 248 DIV_PLL_SHARED1_DIV4, 0, 4), 249 DIV(0, "dout_cmu_pll_shared1_div9", "dout_cmu_pll_shared1_div3", 250 DIV_PLL_SHARED1_DIV9, 0, 4), 251 }; 252 253 static const struct samsung_gate_clock cmu_gate_clks[] __initconst = { 254 GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21, 255 CLK_IGNORE_UNUSED, 0), 256 GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21, 257 CLK_IGNORE_UNUSED, 0), 258 GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21, 259 CLK_IGNORE_UNUSED, 0), 260 GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux", 261 GAT_CMU_CPUCL_SWITCH_GATE, 21, CLK_IGNORE_UNUSED, 0), 262 GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4", 263 GAT_CMU_FSYS0_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 264 GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3", 265 GAT_CMU_FSYS0_SHARED1DIV4_CLK, 21, CLK_IGNORE_UNUSED, 0), 266 GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4", 267 GAT_CMU_FSYS0_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 268 GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux", 269 GAT_CMU_FSYS1_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 270 GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4", 271 GAT_CMU_FSYS1_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 272 GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21, 273 CLK_IGNORE_UNUSED, 0), 274 GATE(0, "cmu_imem_dmaclk_gate", "mout_cmu_pll_shared1_mux", GAT_CMU_IMEM_DMACLK_GATE, 21, 275 CLK_IGNORE_UNUSED, 0), 276 GATE(0, "cmu_imem_tcuclk_gate", "dout_cmu_pll_shared0_div3", GAT_CMU_IMEM_TCUCLK_GATE, 21, 277 CLK_IGNORE_UNUSED, 0), 278 GATE(0, "cmu_peric_shared0dive3_tbuclk_gate", "dout_cmu_pll_shared0_div3", 279 GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 21, CLK_IGNORE_UNUSED, 0), 280 GATE(0, "cmu_peric_shared0dive4_gate", "dout_cmu_pll_shared0_div4", 281 GAT_CMU_PERIC_SHARED0DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0), 282 GATE(0, "cmu_peric_shared1div4_dmaclk_gate", "dout_cmu_pll_shared1_div4", 283 GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 21, CLK_IGNORE_UNUSED, 0), 284 GATE(0, "cmu_peric_shared1dive4_gate", "dout_cmu_pll_shared1_div36", 285 GAT_CMU_PERIC_SHARED1DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0), 286 GATE(0, "cmu_uid_cmu_cmu_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk", 287 GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 288 GATE(0, "cmu_uid_axi2apb_cmu_ipclkport_aclk", "dout_cmu_cmu_aclk", 289 GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 290 GATE(0, "cmu_uid_ns_brdg_cmu_ipclkport_clk__psoc_cmu__clk_cmu", "dout_cmu_cmu_aclk", 291 GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 21, CLK_IGNORE_UNUSED, 0), 292 GATE(0, "cmu_uid_sysreg_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk", 293 GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 294 }; 295 296 static const struct samsung_cmu_info cmu_cmu_info __initconst = { 297 .pll_clks = cmu_pll_clks, 298 .nr_pll_clks = ARRAY_SIZE(cmu_pll_clks), 299 .mux_clks = cmu_mux_clks, 300 .nr_mux_clks = ARRAY_SIZE(cmu_mux_clks), 301 .div_clks = cmu_div_clks, 302 .nr_div_clks = ARRAY_SIZE(cmu_div_clks), 303 .gate_clks = cmu_gate_clks, 304 .nr_gate_clks = ARRAY_SIZE(cmu_gate_clks), 305 .nr_clk_ids = CMU_NR_CLK, 306 .clk_regs = cmu_clk_regs, 307 .nr_clk_regs = ARRAY_SIZE(cmu_clk_regs), 308 }; 309 310 static void __init fsd_clk_cmu_init(struct device_node *np) 311 { 312 samsung_cmu_register_one(np, &cmu_cmu_info); 313 } 314 315 CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init); 316 317 /* Register Offset definitions for CMU_PERIC (0x14010000) */ 318 #define PLL_CON0_PERIC_DMACLK_MUX 0x100 319 #define PLL_CON0_PERIC_EQOS_BUSCLK_MUX 0x120 320 #define PLL_CON0_PERIC_PCLK_MUX 0x140 321 #define PLL_CON0_PERIC_TBUCLK_MUX 0x160 322 #define PLL_CON0_SPI_CLK 0x180 323 #define PLL_CON0_SPI_PCLK 0x1a0 324 #define PLL_CON0_UART_CLK 0x1c0 325 #define PLL_CON0_UART_PCLK 0x1e0 326 #define MUX_PERIC_EQOS_PHYRXCLK 0x1000 327 #define DIV_EQOS_BUSCLK 0x1800 328 #define DIV_PERIC_MCAN_CLK 0x1804 329 #define DIV_RGMII_CLK 0x1808 330 #define DIV_RII_CLK 0x180c 331 #define DIV_RMII_CLK 0x1810 332 #define DIV_SPI_CLK 0x1814 333 #define DIV_UART_CLK 0x1818 334 #define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 0x2000 335 #define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK 0x2004 336 #define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK 0x2008 337 #define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK 0x200c 338 #define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK 0x2010 339 #define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK 0x2014 340 #define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM 0x2018 341 #define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS 0x201c 342 #define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM 0x2020 343 #define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS 0x2024 344 #define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2028 345 #define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK 0x202c 346 #define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK 0x2030 347 #define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK 0x2034 348 #define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK 0x2038 349 #define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK 0x203c 350 #define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK 0x2040 351 #define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK 0x2044 352 #define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK 0x2048 353 #define GAT_EQOS_TOP_IPCLKPORT_ACLK_I 0x204c 354 #define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I 0x2050 355 #define GAT_EQOS_TOP_IPCLKPORT_HCLK_I 0x2054 356 #define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 0x2058 357 #define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I 0x205c 358 #define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I 0x2060 359 #define GAT_GPIO_PERIC_IPCLKPORT_PCLK 0x2064 360 #define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D 0x2068 361 #define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P 0x206c 362 #define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0 0x2070 363 #define GAT_PERIC_DMA0_IPCLKPORT_ACLK 0x2074 364 #define GAT_PERIC_DMA1_IPCLKPORT_ACLK 0x2078 365 #define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK 0x207c 366 #define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK 0x2080 367 #define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK 0x2084 368 #define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK 0x2088 369 #define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK 0x208c 370 #define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK 0x2090 371 #define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK 0x2094 372 #define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK 0x2098 373 #define GAT_PERIC_MCAN0_IPCLKPORT_CCLK 0x209c 374 #define GAT_PERIC_MCAN0_IPCLKPORT_PCLK 0x20a0 375 #define GAT_PERIC_MCAN1_IPCLKPORT_CCLK 0x20a4 376 #define GAT_PERIC_MCAN1_IPCLKPORT_PCLK 0x20a8 377 #define GAT_PERIC_MCAN2_IPCLKPORT_CCLK 0x20ac 378 #define GAT_PERIC_MCAN2_IPCLKPORT_PCLK 0x20b0 379 #define GAT_PERIC_MCAN3_IPCLKPORT_CCLK 0x20b4 380 #define GAT_PERIC_MCAN3_IPCLKPORT_PCLK 0x20b8 381 #define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0 0x20bc 382 #define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0 0x20c0 383 #define GAT_PERIC_SMMU_IPCLKPORT_CCLK 0x20c4 384 #define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK 0x20c8 385 #define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK 0x20cc 386 #define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI 0x20d0 387 #define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK 0x20d4 388 #define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI 0x20d8 389 #define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK 0x20dc 390 #define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI 0x20e0 391 #define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M 0x20e4 392 #define GAT_PERIC_TDM0_IPCLKPORT_PCLK 0x20e8 393 #define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M 0x20ec 394 #define GAT_PERIC_TDM1_IPCLKPORT_PCLK 0x20f0 395 #define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART 0x20f4 396 #define GAT_PERIC_UART0_IPCLKPORT_PCLK 0x20f8 397 #define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART 0x20fc 398 #define GAT_PERIC_UART1_IPCLKPORT_PCLK 0x2100 399 #define GAT_SYSREG_PERI_IPCLKPORT_PCLK 0x2104 400 401 static const unsigned long peric_clk_regs[] __initconst = { 402 PLL_CON0_PERIC_DMACLK_MUX, 403 PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 404 PLL_CON0_PERIC_PCLK_MUX, 405 PLL_CON0_PERIC_TBUCLK_MUX, 406 PLL_CON0_SPI_CLK, 407 PLL_CON0_SPI_PCLK, 408 PLL_CON0_UART_CLK, 409 PLL_CON0_UART_PCLK, 410 MUX_PERIC_EQOS_PHYRXCLK, 411 DIV_EQOS_BUSCLK, 412 DIV_PERIC_MCAN_CLK, 413 DIV_RGMII_CLK, 414 DIV_RII_CLK, 415 DIV_RMII_CLK, 416 DIV_SPI_CLK, 417 DIV_UART_CLK, 418 GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 419 GAT_GPIO_PERIC_IPCLKPORT_OSCCLK, 420 GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 421 GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 422 GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 423 GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 424 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 425 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 426 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 427 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 428 GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 429 GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 430 GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 431 GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 432 GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 433 GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 434 GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 435 GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 436 GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 437 GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 438 GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 439 GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 440 GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 441 GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 442 GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 443 GAT_GPIO_PERIC_IPCLKPORT_PCLK, 444 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 445 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 446 GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 447 GAT_PERIC_DMA0_IPCLKPORT_ACLK, 448 GAT_PERIC_DMA1_IPCLKPORT_ACLK, 449 GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 450 GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 451 GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 452 GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 453 GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 454 GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 455 GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 456 GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 457 GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 458 GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 459 GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 460 GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 461 GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 462 GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 463 GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 464 GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 465 GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 466 GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 467 GAT_PERIC_SMMU_IPCLKPORT_CCLK, 468 GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 469 GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 470 GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 471 GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 472 GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 473 GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 474 GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 475 GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 476 GAT_PERIC_TDM0_IPCLKPORT_PCLK, 477 GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 478 GAT_PERIC_TDM1_IPCLKPORT_PCLK, 479 GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 480 GAT_PERIC_UART0_IPCLKPORT_PCLK, 481 GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 482 GAT_PERIC_UART1_IPCLKPORT_PCLK, 483 GAT_SYSREG_PERI_IPCLKPORT_PCLK, 484 }; 485 486 static const struct samsung_fixed_rate_clock peric_fixed_clks[] __initconst = { 487 FRATE(PERIC_EQOS_PHYRXCLK, "eqos_phyrxclk", NULL, 0, 125000000), 488 }; 489 490 /* List of parent clocks for Muxes in CMU_PERIC */ 491 PNAME(mout_peric_dmaclk_p) = { "fin_pll", "cmu_peric_shared1div4_dmaclk_gate" }; 492 PNAME(mout_peric_eqos_busclk_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; 493 PNAME(mout_peric_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; 494 PNAME(mout_peric_tbuclk_p) = { "fin_pll", "dout_cmu_peric_shared0div3_tbuclk" }; 495 PNAME(mout_peric_spi_clk_p) = { "fin_pll", "dout_cmu_peric_shared0div20" }; 496 PNAME(mout_peric_spi_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; 497 PNAME(mout_peric_uart_clk_p) = { "fin_pll", "dout_cmu_peric_shared1div4_dmaclk" }; 498 PNAME(mout_peric_uart_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; 499 PNAME(mout_peric_eqos_phyrxclk_p) = { "dout_peric_rgmii_clk", "eqos_phyrxclk" }; 500 501 static const struct samsung_mux_clock peric_mux_clks[] __initconst = { 502 MUX(0, "mout_peric_dmaclk", mout_peric_dmaclk_p, PLL_CON0_PERIC_DMACLK_MUX, 4, 1), 503 MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p, 504 PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 4, 1), 505 MUX(0, "mout_peric_pclk", mout_peric_pclk_p, PLL_CON0_PERIC_PCLK_MUX, 4, 1), 506 MUX(0, "mout_peric_tbuclk", mout_peric_tbuclk_p, PLL_CON0_PERIC_TBUCLK_MUX, 4, 1), 507 MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1), 508 MUX(0, "mout_peric_spi_pclk", mout_peric_spi_pclk_p, PLL_CON0_SPI_PCLK, 4, 1), 509 MUX(0, "mout_peric_uart_clk", mout_peric_uart_clk_p, PLL_CON0_UART_CLK, 4, 1), 510 MUX(0, "mout_peric_uart_pclk", mout_peric_uart_pclk_p, PLL_CON0_UART_PCLK, 4, 1), 511 MUX(PERIC_EQOS_PHYRXCLK_MUX, "mout_peric_eqos_phyrxclk", mout_peric_eqos_phyrxclk_p, 512 MUX_PERIC_EQOS_PHYRXCLK, 0, 1), 513 }; 514 515 static const struct samsung_div_clock peric_div_clks[] __initconst = { 516 DIV(0, "dout_peric_eqos_busclk", "mout_peric_eqos_busclk", DIV_EQOS_BUSCLK, 0, 4), 517 DIV(0, "dout_peric_mcan_clk", "mout_peric_dmaclk", DIV_PERIC_MCAN_CLK, 0, 4), 518 DIV(PERIC_DOUT_RGMII_CLK, "dout_peric_rgmii_clk", "mout_peric_eqos_busclk", 519 DIV_RGMII_CLK, 0, 4), 520 DIV(0, "dout_peric_rii_clk", "dout_peric_rmii_clk", DIV_RII_CLK, 0, 4), 521 DIV(0, "dout_peric_rmii_clk", "dout_peric_rgmii_clk", DIV_RMII_CLK, 0, 4), 522 DIV(0, "dout_peric_spi_clk", "mout_peric_spi_clk", DIV_SPI_CLK, 0, 6), 523 DIV(0, "dout_peric_uart_clk", "mout_peric_uart_clk", DIV_UART_CLK, 0, 6), 524 }; 525 526 static const struct samsung_gate_clock peric_gate_clks[] __initconst = { 527 GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, "peric_eqos_top_ipclkport_clk_ptp_ref_i", 528 "fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0), 529 GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK, 530 21, CLK_IGNORE_UNUSED, 0), 531 GATE(PERIC_PCLK_ADCIF, "peric_adc0_ipclkport_i_oscclk", "fin_pll", 532 GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), 533 GATE(0, "peric_cmu_peric_ipclkport_pclk", "mout_peric_pclk", 534 GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 535 GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21, 536 CLK_IGNORE_UNUSED, 0), 537 GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21, 538 CLK_IGNORE_UNUSED, 0), 539 GATE(0, "peric_async_apb_dma0_ipclkport_pclkm", "mout_peric_dmaclk", 540 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 541 GATE(0, "peric_async_apb_dma0_ipclkport_pclks", "mout_peric_pclk", 542 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 543 GATE(0, "peric_async_apb_dma1_ipclkport_pclkm", "mout_peric_dmaclk", 544 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 545 GATE(0, "peric_async_apb_dma1_ipclkport_pclks", "mout_peric_pclk", 546 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 547 GATE(0, "peric_axi2apb_peric0_ipclkport_aclk", "mout_peric_pclk", 548 GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 549 GATE(0, "peric_axi2apb_peric1_ipclkport_aclk", "mout_peric_pclk", 550 GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 551 GATE(0, "peric_axi2apb_peric2_ipclkport_aclk", "mout_peric_pclk", 552 GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 553 GATE(0, "peric_bus_d_peric_ipclkport_dmaclk", "mout_peric_dmaclk", 554 GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 21, CLK_IGNORE_UNUSED, 0), 555 GATE(PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_d_peric_ipclkport_eqosclk", 556 "dout_peric_eqos_busclk", GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0), 557 GATE(0, "peric_bus_d_peric_ipclkport_mainclk", "mout_peric_tbuclk", 558 GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 559 GATE(PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_p_peric_ipclkport_eqosclk", 560 "dout_peric_eqos_busclk", GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0), 561 GATE(0, "peric_bus_p_peric_ipclkport_mainclk", "mout_peric_pclk", 562 GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 563 GATE(0, "peric_bus_p_peric_ipclkport_smmuclk", "mout_peric_tbuclk", 564 GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 21, CLK_IGNORE_UNUSED, 0), 565 GATE(PERIC_EQOS_TOP_IPCLKPORT_ACLK_I, "peric_eqos_top_ipclkport_aclk_i", 566 "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 21, CLK_IGNORE_UNUSED, 0), 567 GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I, "peric_eqos_top_ipclkport_clk_rx_i", 568 "mout_peric_eqos_phyrxclk", GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 21, CLK_IGNORE_UNUSED, 0), 569 GATE(PERIC_EQOS_TOP_IPCLKPORT_HCLK_I, "peric_eqos_top_ipclkport_hclk_i", 570 "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 21, CLK_IGNORE_UNUSED, 0), 571 GATE(PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, "peric_eqos_top_ipclkport_rgmii_clk_i", 572 "dout_peric_rgmii_clk", GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 573 GATE(0, "peric_eqos_top_ipclkport_rii_clk_i", "dout_peric_rii_clk", 574 GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 575 GATE(0, "peric_eqos_top_ipclkport_rmii_clk_i", "dout_peric_rmii_clk", 576 GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 577 GATE(0, "peric_gpio_peric_ipclkport_pclk", "mout_peric_pclk", 578 GAT_GPIO_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 579 GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_d", "mout_peric_tbuclk", 580 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 21, CLK_IGNORE_UNUSED, 0), 581 GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_p", "mout_peric_pclk", 582 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 21, CLK_IGNORE_UNUSED, 0), 583 GATE(0, "peric_adc0_ipclkport_pclk_s0", "mout_peric_pclk", 584 GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), 585 GATE(PERIC_DMA0_IPCLKPORT_ACLK, "peric_dma0_ipclkport_aclk", "mout_peric_dmaclk", 586 GAT_PERIC_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 587 GATE(PERIC_DMA1_IPCLKPORT_ACLK, "peric_dma1_ipclkport_aclk", "mout_peric_dmaclk", 588 GAT_PERIC_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 589 GATE(PERIC_PCLK_HSI2C0, "peric_i2c0_ipclkport_i_pclk", "mout_peric_pclk", 590 GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 591 GATE(PERIC_PCLK_HSI2C1, "peric_i2c1_ipclkport_i_pclk", "mout_peric_pclk", 592 GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 593 GATE(PERIC_PCLK_HSI2C2, "peric_i2c2_ipclkport_i_pclk", "mout_peric_pclk", 594 GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 595 GATE(PERIC_PCLK_HSI2C3, "peric_i2c3_ipclkport_i_pclk", "mout_peric_pclk", 596 GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 597 GATE(PERIC_PCLK_HSI2C4, "peric_i2c4_ipclkport_i_pclk", "mout_peric_pclk", 598 GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 599 GATE(PERIC_PCLK_HSI2C5, "peric_i2c5_ipclkport_i_pclk", "mout_peric_pclk", 600 GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 601 GATE(PERIC_PCLK_HSI2C6, "peric_i2c6_ipclkport_i_pclk", "mout_peric_pclk", 602 GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 603 GATE(PERIC_PCLK_HSI2C7, "peric_i2c7_ipclkport_i_pclk", "mout_peric_pclk", 604 GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 605 GATE(PERIC_MCAN0_IPCLKPORT_CCLK, "peric_mcan0_ipclkport_cclk", "dout_peric_mcan_clk", 606 GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 607 GATE(PERIC_MCAN0_IPCLKPORT_PCLK, "peric_mcan0_ipclkport_pclk", "mout_peric_pclk", 608 GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 609 GATE(PERIC_MCAN1_IPCLKPORT_CCLK, "peric_mcan1_ipclkport_cclk", "dout_peric_mcan_clk", 610 GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 611 GATE(PERIC_MCAN1_IPCLKPORT_PCLK, "peric_mcan1_ipclkport_pclk", "mout_peric_pclk", 612 GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 613 GATE(PERIC_MCAN2_IPCLKPORT_CCLK, "peric_mcan2_ipclkport_cclk", "dout_peric_mcan_clk", 614 GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 615 GATE(PERIC_MCAN2_IPCLKPORT_PCLK, "peric_mcan2_ipclkport_pclk", "mout_peric_pclk", 616 GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 617 GATE(PERIC_MCAN3_IPCLKPORT_CCLK, "peric_mcan3_ipclkport_cclk", "dout_peric_mcan_clk", 618 GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 619 GATE(PERIC_MCAN3_IPCLKPORT_PCLK, "peric_mcan3_ipclkport_pclk", "mout_peric_pclk", 620 GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 621 GATE(PERIC_PWM0_IPCLKPORT_I_PCLK_S0, "peric_pwm0_ipclkport_i_pclk_s0", "mout_peric_pclk", 622 GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), 623 GATE(PERIC_PWM1_IPCLKPORT_I_PCLK_S0, "peric_pwm1_ipclkport_i_pclk_s0", "mout_peric_pclk", 624 GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), 625 GATE(0, "peric_smmu_ipclkport_cclk", "mout_peric_tbuclk", 626 GAT_PERIC_SMMU_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 627 GATE(0, "peric_smmu_ipclkport_peric_bclk", "mout_peric_tbuclk", 628 GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 21, CLK_IGNORE_UNUSED, 0), 629 GATE(PERIC_PCLK_SPI0, "peric_spi0_ipclkport_i_pclk", "mout_peric_spi_pclk", 630 GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 631 GATE(PERIC_SCLK_SPI0, "peric_spi0_ipclkport_i_sclk_spi", "dout_peric_spi_clk", 632 GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), 633 GATE(PERIC_PCLK_SPI1, "peric_spi1_ipclkport_i_pclk", "mout_peric_spi_pclk", 634 GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 635 GATE(PERIC_SCLK_SPI1, "peric_spi1_ipclkport_i_sclk_spi", "dout_peric_spi_clk", 636 GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), 637 GATE(PERIC_PCLK_SPI2, "peric_spi2_ipclkport_i_pclk", "mout_peric_spi_pclk", 638 GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 639 GATE(PERIC_SCLK_SPI2, "peric_spi2_ipclkport_i_sclk_spi", "dout_peric_spi_clk", 640 GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), 641 GATE(PERIC_HCLK_TDM0, "peric_tdm0_ipclkport_hclk_m", "mout_peric_pclk", 642 GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0), 643 GATE(PERIC_PCLK_TDM0, "peric_tdm0_ipclkport_pclk", "mout_peric_pclk", 644 GAT_PERIC_TDM0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 645 GATE(PERIC_HCLK_TDM1, "peric_tdm1_ipclkport_hclk_m", "mout_peric_pclk", 646 GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0), 647 GATE(PERIC_PCLK_TDM1, "peric_tdm1_ipclkport_pclk", "mout_peric_pclk", 648 GAT_PERIC_TDM1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 649 GATE(PERIC_SCLK_UART0, "peric_uart0_ipclkport_i_sclk_uart", "dout_peric_uart_clk", 650 GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0), 651 GATE(PERIC_PCLK_UART0, "peric_uart0_ipclkport_pclk", "mout_peric_uart_pclk", 652 GAT_PERIC_UART0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 653 GATE(PERIC_SCLK_UART1, "peric_uart1_ipclkport_i_sclk_uart", "dout_peric_uart_clk", 654 GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0), 655 GATE(PERIC_PCLK_UART1, "peric_uart1_ipclkport_pclk", "mout_peric_uart_pclk", 656 GAT_PERIC_UART1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 657 GATE(0, "peric_sysreg_peri_ipclkport_pclk", "mout_peric_pclk", 658 GAT_SYSREG_PERI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 659 }; 660 661 static const struct samsung_cmu_info peric_cmu_info __initconst = { 662 .mux_clks = peric_mux_clks, 663 .nr_mux_clks = ARRAY_SIZE(peric_mux_clks), 664 .div_clks = peric_div_clks, 665 .nr_div_clks = ARRAY_SIZE(peric_div_clks), 666 .gate_clks = peric_gate_clks, 667 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), 668 .fixed_clks = peric_fixed_clks, 669 .nr_fixed_clks = ARRAY_SIZE(peric_fixed_clks), 670 .nr_clk_ids = PERIC_NR_CLK, 671 .clk_regs = peric_clk_regs, 672 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), 673 .clk_name = "dout_cmu_pll_shared0_div4", 674 }; 675 676 /* Register Offset definitions for CMU_FSYS0 (0x15010000) */ 677 #define PLL_CON0_CLKCMU_FSYS0_UNIPRO 0x100 678 #define PLL_CON0_CLK_FSYS0_SLAVEBUSCLK 0x140 679 #define PLL_CON0_EQOS_RGMII_125_MUX1 0x160 680 #define DIV_CLK_UNIPRO 0x1800 681 #define DIV_EQS_RGMII_CLK_125 0x1804 682 #define DIV_PERIBUS_GRP 0x1808 683 #define DIV_EQOS_RII_CLK2O5 0x180c 684 #define DIV_EQOS_RMIICLK_25 0x1810 685 #define DIV_PCIE_PHY_OSCCLK 0x1814 686 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 0x2004 687 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 0x2008 688 #define GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x200c 689 #define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK 0x2010 690 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO 0x2014 691 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK 0x2018 692 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC 0x201c 693 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2020 694 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x2024 695 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2028 696 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x202c 697 #define GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK 0x2038 698 #define GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK 0x203c 699 #define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK 0x2040 700 #define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK 0x2044 701 #define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK 0x2048 702 #define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK 0x204c 703 #define GAT_FSYS0_CPE425_IPCLKPORT_ACLK 0x2050 704 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 0x2054 705 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 0x2058 706 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 0x205c 707 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I 0x2060 708 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I 0x2064 709 #define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK 0x2068 710 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D 0x206c 711 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1 0x2070 712 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P 0x2074 713 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S 0x2078 714 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK 0x207c 715 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL 0x2080 716 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0 0x2084 717 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC 0x2088 718 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x208c 719 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC 0x2090 720 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC 0x2094 721 #define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK 0x2098 722 #define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK 0x209c 723 #define GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK 0x20a0 724 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS 0x20a4 725 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK 0x20a8 726 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO 0x20ac 727 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK 0x20b0 728 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS 0x20b4 729 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK 0x20b8 730 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO 0x20bc 731 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK 0x20c0 732 #define GAT_FSYS0_RII_CLK_DIVGATE 0x20d4 733 734 static const unsigned long fsys0_clk_regs[] __initconst = { 735 PLL_CON0_CLKCMU_FSYS0_UNIPRO, 736 PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 737 PLL_CON0_EQOS_RGMII_125_MUX1, 738 DIV_CLK_UNIPRO, 739 DIV_EQS_RGMII_CLK_125, 740 DIV_PERIBUS_GRP, 741 DIV_EQOS_RII_CLK2O5, 742 DIV_EQOS_RMIICLK_25, 743 DIV_PCIE_PHY_OSCCLK, 744 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 745 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 746 GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 747 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 748 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 749 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 750 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 751 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 752 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 753 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 754 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 755 GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 756 GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 757 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 758 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 759 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 760 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 761 GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 762 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 763 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 764 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 765 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 766 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 767 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 768 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 769 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 770 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 771 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 772 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 773 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL, 774 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 775 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 776 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 777 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 778 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 779 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 780 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 781 GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 782 GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 783 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 784 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 785 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 786 GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 787 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 788 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 789 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 790 GAT_FSYS0_RII_CLK_DIVGATE, 791 }; 792 793 static const struct samsung_fixed_rate_clock fsys0_fixed_clks[] __initconst = { 794 FRATE(0, "pad_eqos0_phyrxclk", NULL, 0, 125000000), 795 FRATE(0, "i_mphy_refclk_ixtal26", NULL, 0, 26000000), 796 FRATE(0, "xtal_clk_pcie_phy", NULL, 0, 100000000), 797 }; 798 799 /* List of parent clocks for Muxes in CMU_FSYS0 */ 800 PNAME(mout_fsys0_clkcmu_fsys0_unipro_p) = { "fin_pll", "dout_cmu_pll_shared0_div6" }; 801 PNAME(mout_fsys0_clk_fsys0_slavebusclk_p) = { "fin_pll", "dout_cmu_fsys0_shared1div4" }; 802 PNAME(mout_fsys0_eqos_rgmii_125_mux1_p) = { "fin_pll", "dout_cmu_fsys0_shared0div4" }; 803 804 static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = { 805 MUX(0, "mout_fsys0_clkcmu_fsys0_unipro", mout_fsys0_clkcmu_fsys0_unipro_p, 806 PLL_CON0_CLKCMU_FSYS0_UNIPRO, 4, 1), 807 MUX(0, "mout_fsys0_clk_fsys0_slavebusclk", mout_fsys0_clk_fsys0_slavebusclk_p, 808 PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 4, 1), 809 MUX(0, "mout_fsys0_eqos_rgmii_125_mux1", mout_fsys0_eqos_rgmii_125_mux1_p, 810 PLL_CON0_EQOS_RGMII_125_MUX1, 4, 1), 811 }; 812 813 static const struct samsung_div_clock fsys0_div_clks[] __initconst = { 814 DIV(0, "dout_fsys0_clk_unipro", "mout_fsys0_clkcmu_fsys0_unipro", DIV_CLK_UNIPRO, 0, 4), 815 DIV(0, "dout_fsys0_eqs_rgmii_clk_125", "mout_fsys0_eqos_rgmii_125_mux1", 816 DIV_EQS_RGMII_CLK_125, 0, 4), 817 DIV(FSYS0_DOUT_FSYS0_PERIBUS_GRP, "dout_fsys0_peribus_grp", 818 "mout_fsys0_clk_fsys0_slavebusclk", DIV_PERIBUS_GRP, 0, 4), 819 DIV(0, "dout_fsys0_eqos_rii_clk2o5", "fsys0_rii_clk_divgate", DIV_EQOS_RII_CLK2O5, 0, 4), 820 DIV(0, "dout_fsys0_eqos_rmiiclk_25", "mout_fsys0_eqos_rgmii_125_mux1", 821 DIV_EQOS_RMIICLK_25, 0, 5), 822 DIV(0, "dout_fsys0_pcie_phy_oscclk", "mout_fsys0_eqos_rgmii_125_mux1", 823 DIV_PCIE_PHY_OSCCLK, 0, 4), 824 }; 825 826 static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = { 827 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, "fsys0_eqos_top0_ipclkport_clk_rx_i", 828 "pad_eqos0_phyrxclk", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 21, 829 CLK_IGNORE_UNUSED, 0), 830 GATE(PCIE_SUBCTRL_INST0_AUX_CLK_SOC, 831 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_aux_clk_soc", "fin_pll", 832 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 21, 833 CLK_IGNORE_UNUSED, 0), 834 GATE(0, "fsys0_fsys0_cmu_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", 835 GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 836 GATE(0, 837 "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_xo", 838 "xtal_clk_pcie_phy", 839 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 21, 840 CLK_IGNORE_UNUSED, 0), 841 GATE(UFS0_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal24", 842 "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21, 843 CLK_IGNORE_UNUSED, 0), 844 GATE(UFS0_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal26", 845 "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21, 846 CLK_IGNORE_UNUSED, 0), 847 GATE(UFS1_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal24", 848 "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21, 849 CLK_IGNORE_UNUSED, 0), 850 GATE(UFS1_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal26", 851 "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21, 852 CLK_IGNORE_UNUSED, 0), 853 GATE(0, "fsys0_ahbbr_fsys0_ipclkport_hclk", "dout_fsys0_peribus_grp", 854 GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 21, CLK_IGNORE_UNUSED, 0), 855 GATE(0, "fsys0_axi2apb_fsys0_ipclkport_aclk", "dout_fsys0_peribus_grp", 856 GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 857 GATE(0, "fsys0_bus_d_fsys0_ipclkport_mainclk", "mout_fsys0_clk_fsys0_slavebusclk", 858 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 859 GATE(0, "fsys0_bus_d_fsys0_ipclkport_periclk", "dout_fsys0_peribus_grp", 860 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0), 861 GATE(0, "fsys0_bus_p_fsys0_ipclkport_mainclk", "dout_fsys0_peribus_grp", 862 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 863 GATE(0, "fsys0_bus_p_fsys0_ipclkport_tcuclk", "mout_fsys0_eqos_rgmii_125_mux1", 864 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0), 865 GATE(0, "fsys0_cpe425_ipclkport_aclk", "mout_fsys0_clk_fsys0_slavebusclk", 866 GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 867 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, "fsys0_eqos_top0_ipclkport_aclk_i", 868 "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 21, 869 CLK_IGNORE_UNUSED, 0), 870 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, "fsys0_eqos_top0_ipclkport_hclk_i", 871 "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 21, 872 CLK_IGNORE_UNUSED, 0), 873 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, "fsys0_eqos_top0_ipclkport_rgmii_clk_i", 874 "dout_fsys0_eqs_rgmii_clk_125", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 21, 875 CLK_IGNORE_UNUSED, 0), 876 GATE(0, "fsys0_eqos_top0_ipclkport_rii_clk_i", "dout_fsys0_eqos_rii_clk2o5", 877 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 878 GATE(0, "fsys0_eqos_top0_ipclkport_rmii_clk_i", "dout_fsys0_eqos_rmiiclk_25", 879 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 880 GATE(0, "fsys0_gpio_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", 881 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 882 GATE(0, "fsys0_gpio_fsys0_ipclkport_oscclk", "fin_pll", 883 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), 884 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d", 885 "mout_fsys0_clk_fsys0_slavebusclk", 886 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 21, 887 CLK_IGNORE_UNUSED, 0), 888 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d1", 889 "mout_fsys0_eqos_rgmii_125_mux1", 890 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 21, 891 CLK_IGNORE_UNUSED, 0), 892 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_p", 893 "dout_fsys0_peribus_grp", 894 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 21, 895 CLK_IGNORE_UNUSED, 0), 896 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_s", 897 "mout_fsys0_clk_fsys0_slavebusclk", 898 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 21, 899 CLK_IGNORE_UNUSED, 0), 900 GATE(0, "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_i_apb_pclk", 901 "dout_fsys0_peribus_grp", 902 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 21, 903 CLK_IGNORE_UNUSED, 0), 904 GATE(0, 905 "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_syspll", 906 "dout_fsys0_pcie_phy_oscclk", 907 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL, 908 21, CLK_IGNORE_UNUSED, 0), 909 GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_apb_pclk_0", "dout_fsys0_peribus_grp", 910 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 21, CLK_IGNORE_UNUSED, 0), 911 GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_immortal_clk", "fin_pll", 912 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 21, CLK_IGNORE_UNUSED, 0), 913 GATE(PCIE_SUBCTRL_INST0_DBI_ACLK_SOC, 914 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_dbi_aclk_soc", 915 "dout_fsys0_peribus_grp", 916 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 21, 917 CLK_IGNORE_UNUSED, 0), 918 GATE(0, "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_i_driver_apb_clk", 919 "dout_fsys0_peribus_grp", 920 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 21, 921 CLK_IGNORE_UNUSED, 0), 922 GATE(PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC, 923 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_mstr_aclk_soc", 924 "mout_fsys0_clk_fsys0_slavebusclk", 925 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 21, 926 CLK_IGNORE_UNUSED, 0), 927 GATE(PCIE_SUBCTRL_INST0_SLV_ACLK_SOC, 928 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_slv_aclk_soc", 929 "mout_fsys0_clk_fsys0_slavebusclk", 930 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 21, 931 CLK_IGNORE_UNUSED, 0), 932 GATE(0, "fsys0_smmu_fsys0_ipclkport_cclk", "mout_fsys0_eqos_rgmii_125_mux1", 933 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 934 GATE(0, "fsys0_smmu_fsys0_ipclkport_fsys0_bclk", "mout_fsys0_clk_fsys0_slavebusclk", 935 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 21, CLK_IGNORE_UNUSED, 0), 936 GATE(0, "fsys0_sysreg_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", 937 GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 938 GATE(UFS0_TOP0_HCLK_BUS, "fsys0_ufs_top0_ipclkport_hclk_bus", "dout_fsys0_peribus_grp", 939 GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0), 940 GATE(UFS0_TOP0_ACLK, "fsys0_ufs_top0_ipclkport_i_aclk", "dout_fsys0_peribus_grp", 941 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 942 GATE(UFS0_TOP0_CLK_UNIPRO, "fsys0_ufs_top0_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro", 943 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0), 944 GATE(UFS0_TOP0_FMP_CLK, "fsys0_ufs_top0_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp", 945 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0), 946 GATE(UFS1_TOP1_HCLK_BUS, "fsys0_ufs_top1_ipclkport_hclk_bus", "dout_fsys0_peribus_grp", 947 GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0), 948 GATE(UFS1_TOP1_ACLK, "fsys0_ufs_top1_ipclkport_i_aclk", "dout_fsys0_peribus_grp", 949 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 950 GATE(UFS1_TOP1_CLK_UNIPRO, "fsys0_ufs_top1_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro", 951 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0), 952 GATE(UFS1_TOP1_FMP_CLK, "fsys0_ufs_top1_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp", 953 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0), 954 GATE(0, "fsys0_rii_clk_divgate", "dout_fsys0_eqos_rmiiclk_25", GAT_FSYS0_RII_CLK_DIVGATE, 955 21, CLK_IGNORE_UNUSED, 0), 956 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, "fsys0_eqos_top0_ipclkport_clk_ptp_ref_i", 957 "fin_pll", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0), 958 }; 959 960 static const struct samsung_cmu_info fsys0_cmu_info __initconst = { 961 .mux_clks = fsys0_mux_clks, 962 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 963 .div_clks = fsys0_div_clks, 964 .nr_div_clks = ARRAY_SIZE(fsys0_div_clks), 965 .gate_clks = fsys0_gate_clks, 966 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 967 .fixed_clks = fsys0_fixed_clks, 968 .nr_fixed_clks = ARRAY_SIZE(fsys0_fixed_clks), 969 .nr_clk_ids = FSYS0_NR_CLK, 970 .clk_regs = fsys0_clk_regs, 971 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 972 .clk_name = "dout_cmu_fsys0_shared1div4", 973 }; 974 975 /* Register Offset definitions for CMU_FSYS1 (0x16810000) */ 976 #define PLL_CON0_ACLK_FSYS1_BUSP_MUX 0x100 977 #define PLL_CON0_PCLKL_FSYS1_BUSP_MUX 0x180 978 #define DIV_CLK_FSYS1_PHY0_OSCCLK 0x1800 979 #define DIV_CLK_FSYS1_PHY1_OSCCLK 0x1804 980 #define GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2000 981 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK 0x2004 982 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK 0x2008 983 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK 0x200c 984 #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL 0x202c 985 #define GAT_FSYS1_PHY0_OSCCLLK 0x2034 986 #define GAT_FSYS1_PHY1_OSCCLK 0x2038 987 #define GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK 0x203c 988 #define GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK 0x2040 989 #define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK 0x2048 990 #define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK 0x204c 991 #define GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK 0x2054 992 #define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0 0x205c 993 #define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0 0x2064 994 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK 0x206c 995 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK 0x2070 996 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK 0x2074 997 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK 0x2078 998 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK 0x207c 999 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK 0x2080 1000 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK 0x2084 1001 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK 0x2088 1002 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK 0x208c 1003 #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK 0x20a4 1004 #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL 0x20a8 1005 #define GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK 0x20b4 1006 #define GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK 0x20b8 1007 1008 static const unsigned long fsys1_clk_regs[] __initconst = { 1009 PLL_CON0_ACLK_FSYS1_BUSP_MUX, 1010 PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 1011 DIV_CLK_FSYS1_PHY0_OSCCLK, 1012 DIV_CLK_FSYS1_PHY1_OSCCLK, 1013 GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 1014 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 1015 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 1016 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 1017 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 1018 GAT_FSYS1_PHY0_OSCCLLK, 1019 GAT_FSYS1_PHY1_OSCCLK, 1020 GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 1021 GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 1022 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 1023 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 1024 GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 1025 GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 1026 GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 1027 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 1028 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 1029 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 1030 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 1031 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 1032 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 1033 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 1034 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 1035 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 1036 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 1037 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 1038 GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 1039 GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 1040 }; 1041 1042 static const struct samsung_fixed_rate_clock fsys1_fixed_clks[] __initconst = { 1043 FRATE(0, "clk_fsys1_phy0_ref", NULL, 0, 100000000), 1044 FRATE(0, "clk_fsys1_phy1_ref", NULL, 0, 100000000), 1045 }; 1046 1047 /* List of parent clocks for Muxes in CMU_FSYS1 */ 1048 PNAME(mout_fsys1_pclkl_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div8" }; 1049 PNAME(mout_fsys1_aclk_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div4" }; 1050 1051 static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = { 1052 MUX(0, "mout_fsys1_pclkl_fsys1_busp_mux", mout_fsys1_pclkl_fsys1_busp_mux_p, 1053 PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 4, 1), 1054 MUX(0, "mout_fsys1_aclk_fsys1_busp_mux", mout_fsys1_aclk_fsys1_busp_mux_p, 1055 PLL_CON0_ACLK_FSYS1_BUSP_MUX, 4, 1), 1056 }; 1057 1058 static const struct samsung_div_clock fsys1_div_clks[] __initconst = { 1059 DIV(0, "dout_fsys1_clk_fsys1_phy0_oscclk", "fsys1_phy0_osccllk", 1060 DIV_CLK_FSYS1_PHY0_OSCCLK, 0, 4), 1061 DIV(0, "dout_fsys1_clk_fsys1_phy1_oscclk", "fsys1_phy1_oscclk", 1062 DIV_CLK_FSYS1_PHY1_OSCCLK, 0, 4), 1063 }; 1064 1065 static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = { 1066 GATE(0, "fsys1_cmu_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux", 1067 GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1068 GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_xtal", "clk_fsys1_phy0_ref", 1069 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 21, CLK_IGNORE_UNUSED, 0), 1070 GATE(0, "fsys1_phy0_osccllk", "mout_fsys1_aclk_fsys1_busp_mux", 1071 GAT_FSYS1_PHY0_OSCCLLK, 21, CLK_IGNORE_UNUSED, 0), 1072 GATE(0, "fsys1_phy1_oscclk", "mout_fsys1_aclk_fsys1_busp_mux", 1073 GAT_FSYS1_PHY1_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), 1074 GATE(0, "fsys1_axi2apb_fsys1_ipclkport_aclk", "mout_fsys1_pclkl_fsys1_busp_mux", 1075 GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1076 GATE(0, "fsys1_bus_d0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux", 1077 GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 1078 GATE(0, "fsys1_bus_s0_fsys1_ipclkport_m250clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1079 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 21, CLK_IGNORE_UNUSED, 0), 1080 GATE(0, "fsys1_bus_s0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux", 1081 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 1082 GATE(0, "fsys1_cpe425_0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux", 1083 GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1084 GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_d0", 1085 "mout_fsys1_aclk_fsys1_busp_mux", 1086 GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 21, 1087 CLK_IGNORE_UNUSED, 0), 1088 GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_s0", 1089 "mout_fsys1_aclk_fsys1_busp_mux", 1090 GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 21, 1091 CLK_IGNORE_UNUSED, 0), 1092 GATE(PCIE_LINK0_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link0_ipclkport_dbi_aclk", 1093 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 21, 1094 CLK_IGNORE_UNUSED, 0), 1095 GATE(0, "fsys1_pcie_link0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1096 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), 1097 GATE(0, "fsys1_pcie_link0_ipclkport_i_soc_ref_clk", "fin_pll", 1098 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 21, CLK_IGNORE_UNUSED, 0), 1099 GATE(0, "fsys1_pcie_link0_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1100 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), 1101 GATE(PCIE_LINK0_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link0_ipclkport_mstr_aclk", 1102 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 21, 1103 CLK_IGNORE_UNUSED, 0), 1104 GATE(PCIE_LINK0_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link0_ipclkport_slv_aclk", 1105 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 21, 1106 CLK_IGNORE_UNUSED, 0), 1107 GATE(PCIE_LINK1_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link1_ipclkport_dbi_aclk", 1108 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 21, 1109 CLK_IGNORE_UNUSED, 0), 1110 GATE(0, "fsys1_pcie_link1_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1111 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), 1112 GATE(PCIE_LINK1_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link1_ipclkport_mstr_aclk", 1113 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 21, 1114 CLK_IGNORE_UNUSED, 0), 1115 GATE(PCIE_LINK1_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link1_ipclkport_slv_aclk", 1116 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 21, 1117 CLK_IGNORE_UNUSED, 0), 1118 GATE(0, "fsys1_pcie_phy0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1119 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), 1120 GATE(PCIE_LINK0_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link0_ipclkport_auxclk", "fin_pll", 1121 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0), 1122 GATE(PCIE_LINK1_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link1_ipclkport_auxclk", "fin_pll", 1123 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0), 1124 GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_soc_pll", "dout_fsys1_clk_fsys1_phy0_oscclk", 1125 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 21, CLK_IGNORE_UNUSED, 0), 1126 GATE(0, "fsys1_sysreg_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux", 1127 GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1128 GATE(0, "fsys1_tbu0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux", 1129 GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1130 }; 1131 1132 static const struct samsung_cmu_info fsys1_cmu_info __initconst = { 1133 .mux_clks = fsys1_mux_clks, 1134 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 1135 .div_clks = fsys1_div_clks, 1136 .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), 1137 .gate_clks = fsys1_gate_clks, 1138 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 1139 .fixed_clks = fsys1_fixed_clks, 1140 .nr_fixed_clks = ARRAY_SIZE(fsys1_fixed_clks), 1141 .nr_clk_ids = FSYS1_NR_CLK, 1142 .clk_regs = fsys1_clk_regs, 1143 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 1144 .clk_name = "dout_cmu_fsys1_shared0div4", 1145 }; 1146 1147 /* Register Offset definitions for CMU_IMEM (0x10010000) */ 1148 #define PLL_CON0_CLK_IMEM_ACLK 0x100 1149 #define PLL_CON0_CLK_IMEM_INTMEMCLK 0x120 1150 #define PLL_CON0_CLK_IMEM_TCUCLK 0x140 1151 #define DIV_OSCCLK_IMEM_TMUTSCLK 0x1800 1152 #define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK 0x2000 1153 #define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO 0x2004 1154 #define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008 1155 #define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK 0x200c 1156 #define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK 0x2010 1157 #define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 0x2014 1158 #define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK 0x2018 1159 #define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 0x201c 1160 #define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK 0x2020 1161 #define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 0x2024 1162 #define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK 0x2028 1163 #define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 0x202c 1164 #define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK 0x2030 1165 #define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 0x2034 1166 #define GAT_IMEM_WDT0_IPCLKPORT_CLK 0x2038 1167 #define GAT_IMEM_WDT1_IPCLKPORT_CLK 0x203c 1168 #define GAT_IMEM_WDT2_IPCLKPORT_CLK 0x2040 1169 #define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM 0x2044 1170 #define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM 0x2048 1171 #define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM 0x204c 1172 #define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS 0x2050 1173 #define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS 0x2054 1174 #define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS 0x2058 1175 #define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM 0x205c 1176 #define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS 0x2060 1177 #define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM 0x2064 1178 #define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS 0x2068 1179 #define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK 0x206c 1180 #define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK 0x2070 1181 #define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK 0x2074 1182 #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK 0x2078 1183 #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK 0x207c 1184 #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK 0x2080 1185 #define GAT_IMEM_DMA0_IPCLKPORT_ACLK 0x2084 1186 #define GAT_IMEM_DMA1_IPCLKPORT_ACLK 0x2088 1187 #define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK 0x208c 1188 #define GAT_IMEM_GIC_IPCLKPORT_CLK 0x2090 1189 #define GAT_IMEM_INTMEM_IPCLKPORT_ACLK 0x2094 1190 #define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK 0x2098 1191 #define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK 0x209c 1192 #define GAT_IMEM_MCT_IPCLKPORT_PCLK 0x20a0 1193 #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D 0x20a4 1194 #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU 0x20a8 1195 #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P 0x20ac 1196 #define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK 0x20b0 1197 #define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK 0x20b4 1198 #define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK 0x20b8 1199 #define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK 0x20bc 1200 #define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK 0x20c0 1201 #define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK 0x20c4 1202 #define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK 0x20c8 1203 #define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK 0x20cc 1204 #define GAT_IMEM_TCU_IPCLKPORT_ACLK 0x20d0 1205 #define GAT_IMEM_WDT0_IPCLKPORT_PCLK 0x20d4 1206 #define GAT_IMEM_WDT1_IPCLKPORT_PCLK 0x20d8 1207 #define GAT_IMEM_WDT2_IPCLKPORT_PCLK 0x20dc 1208 1209 static const unsigned long imem_clk_regs[] __initconst = { 1210 PLL_CON0_CLK_IMEM_ACLK, 1211 PLL_CON0_CLK_IMEM_INTMEMCLK, 1212 PLL_CON0_CLK_IMEM_TCUCLK, 1213 DIV_OSCCLK_IMEM_TMUTSCLK, 1214 GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 1215 GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 1216 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 1217 GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 1218 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 1219 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 1220 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 1221 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 1222 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 1223 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 1224 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 1225 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 1226 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 1227 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 1228 GAT_IMEM_WDT0_IPCLKPORT_CLK, 1229 GAT_IMEM_WDT1_IPCLKPORT_CLK, 1230 GAT_IMEM_WDT2_IPCLKPORT_CLK, 1231 GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 1232 GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 1233 GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 1234 GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 1235 GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 1236 GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 1237 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 1238 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 1239 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 1240 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 1241 GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 1242 GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 1243 GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 1244 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 1245 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 1246 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 1247 GAT_IMEM_DMA0_IPCLKPORT_ACLK, 1248 GAT_IMEM_DMA1_IPCLKPORT_ACLK, 1249 GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 1250 GAT_IMEM_GIC_IPCLKPORT_CLK, 1251 GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 1252 GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 1253 GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 1254 GAT_IMEM_MCT_IPCLKPORT_PCLK, 1255 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 1256 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 1257 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 1258 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 1259 GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 1260 GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 1261 GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 1262 GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 1263 GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 1264 GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 1265 GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 1266 GAT_IMEM_TCU_IPCLKPORT_ACLK, 1267 GAT_IMEM_WDT0_IPCLKPORT_PCLK, 1268 GAT_IMEM_WDT1_IPCLKPORT_PCLK, 1269 GAT_IMEM_WDT2_IPCLKPORT_PCLK, 1270 }; 1271 1272 PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" }; 1273 PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" }; 1274 PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" }; 1275 1276 static const struct samsung_mux_clock imem_mux_clks[] __initconst = { 1277 MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p, 1278 PLL_CON0_CLK_IMEM_TCUCLK, 4, 1), 1279 MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1), 1280 MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p, 1281 PLL_CON0_CLK_IMEM_INTMEMCLK, 4, 1), 1282 }; 1283 1284 static const struct samsung_div_clock imem_div_clks[] __initconst = { 1285 DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4), 1286 }; 1287 1288 static const struct samsung_gate_clock imem_gate_clks[] __initconst = { 1289 GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1290 GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1291 GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll", 1292 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), 1293 GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll", 1294 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1295 GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll", 1296 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1297 GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll", 1298 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1299 GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll", 1300 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1301 GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll", 1302 GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0), 1303 GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll", 1304 GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1305 GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll", 1306 GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1307 GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll", 1308 GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1309 GATE(IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu0_ipclkport_i_clk_ts", 1310 "dout_imem_oscclk_imem_tmutsclk", 1311 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1312 GATE(IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu2_ipclkport_i_clk_ts", 1313 "dout_imem_oscclk_imem_tmutsclk", 1314 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1315 GATE(IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, "imem_tmu_gpu_ipclkport_i_clk_ts", 1316 "dout_imem_oscclk_imem_tmutsclk", 1317 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1318 GATE(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, "imem_tmu_gt_ipclkport_i_clk_ts", 1319 "dout_imem_oscclk_imem_tmutsclk", 1320 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1321 GATE(IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, "imem_tmu_top_ipclkport_i_clk_ts", 1322 "dout_imem_oscclk_imem_tmutsclk", 1323 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1324 GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", 1325 GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), 1326 GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", 1327 GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), 1328 GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", 1329 GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), 1330 GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", 1331 GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), 1332 GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", 1333 GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), 1334 GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", 1335 GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), 1336 GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk", 1337 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 1338 GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk", 1339 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 1340 GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk", 1341 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 1342 GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk", 1343 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 1344 GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk", 1345 GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1346 GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk", 1347 GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1348 GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk", 1349 GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 1350 GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk", 1351 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 1352 GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk", 1353 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0), 1354 GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk", 1355 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0), 1356 GATE(IMEM_DMA0_IPCLKPORT_ACLK, "imem_dma0_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", 1357 GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0), 1358 GATE(IMEM_DMA1_IPCLKPORT_ACLK, "imem_dma1_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", 1359 GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0), 1360 GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk", 1361 GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1362 GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk", 1363 GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1364 GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk", 1365 GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1366 GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1367 GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1368 GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1369 GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1370 GATE(IMEM_MCT_PCLK, "imem_mct_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1371 GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1372 GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d", 1373 "mout_imem_clk_imem_tcuclk", 1374 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0), 1375 GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu", 1376 "mout_imem_clk_imem_tcuclk", 1377 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 21, 1378 CLK_IGNORE_UNUSED, 0), 1379 GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk", 1380 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0), 1381 GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1382 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1383 GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk", 1384 GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1385 GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll", 1386 GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1387 GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk", 1388 GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1389 GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk", 1390 GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1391 GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1392 GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1393 GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1394 GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1395 GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll", 1396 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1397 GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1398 GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1399 GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", 1400 GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1401 GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", 1402 GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1403 GATE(IMEM_WDT0_IPCLKPORT_PCLK, "imem_wdt0_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1404 GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1405 GATE(IMEM_WDT1_IPCLKPORT_PCLK, "imem_wdt1_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1406 GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1407 GATE(IMEM_WDT2_IPCLKPORT_PCLK, "imem_wdt2_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1408 GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1409 }; 1410 1411 static const struct samsung_cmu_info imem_cmu_info __initconst = { 1412 .mux_clks = imem_mux_clks, 1413 .nr_mux_clks = ARRAY_SIZE(imem_mux_clks), 1414 .div_clks = imem_div_clks, 1415 .nr_div_clks = ARRAY_SIZE(imem_div_clks), 1416 .gate_clks = imem_gate_clks, 1417 .nr_gate_clks = ARRAY_SIZE(imem_gate_clks), 1418 .nr_clk_ids = IMEM_NR_CLK, 1419 .clk_regs = imem_clk_regs, 1420 .nr_clk_regs = ARRAY_SIZE(imem_clk_regs), 1421 }; 1422 1423 static void __init fsd_clk_imem_init(struct device_node *np) 1424 { 1425 samsung_cmu_register_one(np, &imem_cmu_info); 1426 } 1427 1428 CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init); 1429 1430 /* Register Offset definitions for CMU_MFC (0x12810000) */ 1431 #define PLL_LOCKTIME_PLL_MFC 0x0 1432 #define PLL_CON0_PLL_MFC 0x100 1433 #define MUX_MFC_BUSD 0x1000 1434 #define MUX_MFC_BUSP 0x1008 1435 #define DIV_MFC_BUSD_DIV4 0x1800 1436 #define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK 0x2000 1437 #define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM 0x2004 1438 #define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS 0x2008 1439 #define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK 0x200c 1440 #define GAT_MFC_MFC_IPCLKPORT_ACLK 0x2010 1441 #define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D 0x2018 1442 #define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P 0x201c 1443 #define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK 0x2028 1444 #define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK 0x202c 1445 #define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK 0x2030 1446 #define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK 0x2034 1447 #define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK 0x2038 1448 #define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK 0x203c 1449 #define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK 0x2040 1450 #define GAT_MFC_BUSD_DIV4_GATE 0x2044 1451 #define GAT_MFC_BUSD_GATE 0x2048 1452 1453 static const unsigned long mfc_clk_regs[] __initconst = { 1454 PLL_LOCKTIME_PLL_MFC, 1455 PLL_CON0_PLL_MFC, 1456 MUX_MFC_BUSD, 1457 MUX_MFC_BUSP, 1458 DIV_MFC_BUSD_DIV4, 1459 GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 1460 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 1461 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 1462 GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 1463 GAT_MFC_MFC_IPCLKPORT_ACLK, 1464 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 1465 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 1466 GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 1467 GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 1468 GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 1469 GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 1470 GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 1471 GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 1472 GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 1473 GAT_MFC_BUSD_DIV4_GATE, 1474 GAT_MFC_BUSD_GATE, 1475 }; 1476 1477 static const struct samsung_pll_rate_table pll_mfc_rate_table[] __initconst = { 1478 PLL_35XX_RATE(24 * MHZ, 666000000U, 111, 4, 0), 1479 }; 1480 1481 static const struct samsung_pll_clock mfc_pll_clks[] __initconst = { 1482 PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll", 1483 PLL_LOCKTIME_PLL_MFC, PLL_CON0_PLL_MFC, pll_mfc_rate_table), 1484 }; 1485 1486 PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_pll_mfc" }; 1487 PNAME(mout_mfc_busp_p) = { "fin_pll", "dout_mfc_busd_div4" }; 1488 PNAME(mout_mfc_busd_p) = { "fin_pll", "mfc_busd_gate" }; 1489 1490 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { 1491 MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1), 1492 MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1), 1493 MUX(0, "mout_mfc_busd", mout_mfc_busd_p, MUX_MFC_BUSD, 0, 1), 1494 }; 1495 1496 static const struct samsung_div_clock mfc_div_clks[] __initconst = { 1497 DIV(0, "dout_mfc_busd_div4", "mfc_busd_div4_gate", DIV_MFC_BUSD_DIV4, 0, 4), 1498 }; 1499 1500 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { 1501 GATE(0, "mfc_cmu_mfc_ipclkport_pclk", "mout_mfc_busp", 1502 GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1503 GATE(0, "mfc_as_p_mfc_ipclkport_pclkm", "mout_mfc_busd", 1504 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 1505 GATE(0, "mfc_as_p_mfc_ipclkport_pclks", "mout_mfc_busp", 1506 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 1507 GATE(0, "mfc_axi2apb_mfc_ipclkport_aclk", "mout_mfc_busp", 1508 GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1509 GATE(MFC_MFC_IPCLKPORT_ACLK, "mfc_mfc_ipclkport_aclk", "mout_mfc_busd", 1510 GAT_MFC_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1511 GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_d", "mout_mfc_busd", 1512 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 21, CLK_IGNORE_UNUSED, 0), 1513 GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_p", "mout_mfc_busp", 1514 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 21, CLK_IGNORE_UNUSED, 0), 1515 GATE(0, "mfc_ppmu_mfcd0_ipclkport_aclk", "mout_mfc_busd", 1516 GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1517 GATE(0, "mfc_ppmu_mfcd0_ipclkport_pclk", "mout_mfc_busp", 1518 GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1519 GATE(0, "mfc_ppmu_mfcd1_ipclkport_aclk", "mout_mfc_busd", 1520 GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1521 GATE(0, "mfc_ppmu_mfcd1_ipclkport_pclk", "mout_mfc_busp", 1522 GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1523 GATE(0, "mfc_sysreg_mfc_ipclkport_pclk", "mout_mfc_busp", 1524 GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1525 GATE(0, "mfc_tbu_mfcd0_ipclkport_clk", "mout_mfc_busd", 1526 GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1527 GATE(0, "mfc_tbu_mfcd1_ipclkport_clk", "mout_mfc_busd", 1528 GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1529 GATE(0, "mfc_busd_div4_gate", "mout_mfc_pll", 1530 GAT_MFC_BUSD_DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 1531 GATE(0, "mfc_busd_gate", "mout_mfc_pll", GAT_MFC_BUSD_GATE, 21, CLK_IS_CRITICAL, 0), 1532 }; 1533 1534 static const struct samsung_cmu_info mfc_cmu_info __initconst = { 1535 .pll_clks = mfc_pll_clks, 1536 .nr_pll_clks = ARRAY_SIZE(mfc_pll_clks), 1537 .mux_clks = mfc_mux_clks, 1538 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), 1539 .div_clks = mfc_div_clks, 1540 .nr_div_clks = ARRAY_SIZE(mfc_div_clks), 1541 .gate_clks = mfc_gate_clks, 1542 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), 1543 .nr_clk_ids = MFC_NR_CLK, 1544 .clk_regs = mfc_clk_regs, 1545 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), 1546 }; 1547 1548 /* Register Offset definitions for CMU_CAM_CSI (0x12610000) */ 1549 #define PLL_LOCKTIME_PLL_CAM_CSI 0x0 1550 #define PLL_CON0_PLL_CAM_CSI 0x100 1551 #define DIV_CAM_CSI0_ACLK 0x1800 1552 #define DIV_CAM_CSI1_ACLK 0x1804 1553 #define DIV_CAM_CSI2_ACLK 0x1808 1554 #define DIV_CAM_CSI_BUSD 0x180c 1555 #define DIV_CAM_CSI_BUSP 0x1810 1556 #define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000 1557 #define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004 1558 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008 1559 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c 1560 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010 1561 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014 1562 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018 1563 #define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c 1564 #define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020 1565 #define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024 1566 #define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028 1567 #define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c 1568 #define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030 1569 #define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034 1570 #define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038 1571 #define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c 1572 #define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040 1573 #define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044 1574 #define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048 1575 #define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c 1576 #define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050 1577 #define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054 1578 #define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058 1579 #define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c 1580 #define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060 1581 #define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064 1582 #define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068 1583 #define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c 1584 #define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070 1585 #define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074 1586 #define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078 1587 #define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c 1588 #define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080 1589 #define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084 1590 #define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088 1591 1592 static const unsigned long cam_csi_clk_regs[] __initconst = { 1593 PLL_LOCKTIME_PLL_CAM_CSI, 1594 PLL_CON0_PLL_CAM_CSI, 1595 DIV_CAM_CSI0_ACLK, 1596 DIV_CAM_CSI1_ACLK, 1597 DIV_CAM_CSI2_ACLK, 1598 DIV_CAM_CSI_BUSD, 1599 DIV_CAM_CSI_BUSP, 1600 GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 1601 GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 1602 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 1603 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 1604 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 1605 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 1606 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 1607 GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 1608 GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 1609 GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 1610 GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 1611 GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 1612 GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 1613 GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 1614 GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 1615 GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 1616 GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 1617 GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 1618 GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 1619 GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 1620 GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 1621 GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 1622 GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 1623 GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 1624 GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 1625 GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 1626 GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 1627 GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 1628 GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 1629 GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 1630 GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 1631 GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 1632 GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 1633 GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 1634 GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 1635 }; 1636 1637 static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = { 1638 PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 12, 0), 1639 }; 1640 1641 static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = { 1642 PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll", 1643 PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table), 1644 }; 1645 1646 PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" }; 1647 1648 static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = { 1649 MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1), 1650 }; 1651 1652 static const struct samsung_div_clock cam_csi_div_clks[] __initconst = { 1653 DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4), 1654 DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4), 1655 DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4), 1656 DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4), 1657 DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4), 1658 }; 1659 1660 static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = { 1661 GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp", 1662 GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1663 GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp", 1664 GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1665 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk", 1666 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0), 1667 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk", 1668 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0), 1669 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk", 1670 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0), 1671 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd", 1672 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21, 1673 CLK_IGNORE_UNUSED, 0), 1674 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd", 1675 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0), 1676 GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk", 1677 GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1678 GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp", 1679 GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1680 GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk", 1681 GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1682 GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp", 1683 GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1684 GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk", 1685 GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1686 GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp", 1687 GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1688 GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk", 1689 GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1690 GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp", 1691 GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1692 GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk", 1693 GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1694 GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp", 1695 GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1696 GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk", 1697 GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1698 GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp", 1699 GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1700 GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk", 1701 GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1702 GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp", 1703 GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1704 GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk", 1705 GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1706 GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp", 1707 GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1708 GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk", 1709 GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1710 GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp", 1711 GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1712 GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk", 1713 GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1714 GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp", 1715 GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1716 GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk", 1717 GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1718 GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp", 1719 GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1720 GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk", 1721 GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1722 GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp", 1723 GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1724 GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d", 1725 "dout_cam_csi_busd", 1726 GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21, 1727 CLK_IGNORE_UNUSED, 0), 1728 GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p", 1729 "dout_cam_csi_busp", 1730 GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21, 1731 CLK_IGNORE_UNUSED, 0), 1732 GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp", 1733 GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1734 GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd", 1735 GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1736 }; 1737 1738 static const struct samsung_cmu_info cam_csi_cmu_info __initconst = { 1739 .pll_clks = cam_csi_pll_clks, 1740 .nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks), 1741 .mux_clks = cam_csi_mux_clks, 1742 .nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks), 1743 .div_clks = cam_csi_div_clks, 1744 .nr_div_clks = ARRAY_SIZE(cam_csi_div_clks), 1745 .gate_clks = cam_csi_gate_clks, 1746 .nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks), 1747 .nr_clk_ids = CAM_CSI_NR_CLK, 1748 .clk_regs = cam_csi_clk_regs, 1749 .nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs), 1750 }; 1751 1752 /** 1753 * fsd_cmu_probe - Probe function for FSD platform clocks 1754 * @pdev: Pointer to platform device 1755 * 1756 * Configure clock hierarchy for clock domains of FSD platform 1757 */ 1758 static int __init fsd_cmu_probe(struct platform_device *pdev) 1759 { 1760 const struct samsung_cmu_info *info; 1761 struct device *dev = &pdev->dev; 1762 1763 info = of_device_get_match_data(dev); 1764 exynos_arm64_register_cmu(dev, dev->of_node, info); 1765 1766 return 0; 1767 } 1768 1769 /* CMUs which belong to Power Domains and need runtime PM to be implemented */ 1770 static const struct of_device_id fsd_cmu_of_match[] = { 1771 { 1772 .compatible = "tesla,fsd-clock-peric", 1773 .data = &peric_cmu_info, 1774 }, { 1775 .compatible = "tesla,fsd-clock-fsys0", 1776 .data = &fsys0_cmu_info, 1777 }, { 1778 .compatible = "tesla,fsd-clock-fsys1", 1779 .data = &fsys1_cmu_info, 1780 }, { 1781 .compatible = "tesla,fsd-clock-mfc", 1782 .data = &mfc_cmu_info, 1783 }, { 1784 .compatible = "tesla,fsd-clock-cam_csi", 1785 .data = &cam_csi_cmu_info, 1786 }, { 1787 }, 1788 }; 1789 1790 static struct platform_driver fsd_cmu_driver __refdata = { 1791 .driver = { 1792 .name = "fsd-cmu", 1793 .of_match_table = fsd_cmu_of_match, 1794 .suppress_bind_attrs = true, 1795 }, 1796 .probe = fsd_cmu_probe, 1797 }; 1798 1799 static int __init fsd_cmu_init(void) 1800 { 1801 return platform_driver_register(&fsd_cmu_driver); 1802 } 1803 core_initcall(fsd_cmu_init); 1804