1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2022 Samsung Electronics Co., Ltd.
4  * Author: Chanho Park <chanho61.park@samsung.com>
5  *
6  * Common Clock Framework support for ExynosAuto V9 SoC.
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 
14 #include <dt-bindings/clock/samsung,exynosautov9.h>
15 
16 #include "clk.h"
17 #include "clk-exynos-arm64.h"
18 
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP			(GOUT_CLKCMU_PERIS_BUS + 1)
21 #define CLKS_NR_BUSMC			(CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
22 #define CLKS_NR_CORE			(CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
23 #define CLKS_NR_FSYS0			(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1)
24 #define CLKS_NR_FSYS1			(CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
25 #define CLKS_NR_FSYS2			(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1)
26 #define CLKS_NR_PERIC0			(CLK_GOUT_PERIC0_PCLK_11 + 1)
27 #define CLKS_NR_PERIC1			(CLK_GOUT_PERIC1_PCLK_11 + 1)
28 #define CLKS_NR_PERIS			(CLK_GOUT_WDT_CLUSTER1 + 1)
29 
30 /* ---- CMU_TOP ------------------------------------------------------------ */
31 
32 /* Register Offset definitions for CMU_TOP (0x1b240000) */
33 #define PLL_LOCKTIME_PLL_SHARED0		0x0000
34 #define PLL_LOCKTIME_PLL_SHARED1		0x0004
35 #define PLL_LOCKTIME_PLL_SHARED2		0x0008
36 #define PLL_LOCKTIME_PLL_SHARED3		0x000c
37 #define PLL_LOCKTIME_PLL_SHARED4		0x0010
38 #define PLL_CON0_PLL_SHARED0			0x0100
39 #define PLL_CON3_PLL_SHARED0			0x010c
40 #define PLL_CON0_PLL_SHARED1			0x0140
41 #define PLL_CON3_PLL_SHARED1			0x014c
42 #define PLL_CON0_PLL_SHARED2			0x0180
43 #define PLL_CON3_PLL_SHARED2			0x018c
44 #define PLL_CON0_PLL_SHARED3			0x01c0
45 #define PLL_CON3_PLL_SHARED3			0x01cc
46 #define PLL_CON0_PLL_SHARED4			0x0200
47 #define PLL_CON3_PLL_SHARED4			0x020c
48 
49 /* MUX */
50 #define CLK_CON_MUX_MUX_CLKCMU_ACC_BUS		0x1000
51 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS		0x1004
52 #define CLK_CON_MUX_MUX_CLKCMU_AUD_BUS		0x1008
53 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU		0x100c
54 #define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS		0x1010
55 #define CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS	0x1018
56 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST	0x101c
57 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS		0x1020
58 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER	0x1024
59 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH	0x102c
60 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER	0x1030
61 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH	0x1034
62 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS		0x1040
63 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC	0x1044
64 #define CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS		0x1048
65 #define CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS	0x104c
66 #define CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS	0x1050
67 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS	0x1054
68 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE	0x1058
69 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS	0x105c
70 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD	0x1060
71 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD	0x1064
72 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS	0x1068
73 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET	0x106c
74 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD	0x1070
75 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D		0x1074
76 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL		0x1078
77 #define CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH	0x107c
78 #define CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH	0x1080
79 #define CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH	0x1084
80 #define CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS		0x108c
81 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC		0x1090
82 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD		0x1094
83 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH	0x109c
84 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP		0x1098
85 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH	0x109c
86 #define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS		0x10a0
87 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS	0x10a4
88 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP	0x10a8
89 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS	0x10ac
90 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP	0x10b0
91 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS	0x10b4
92 #define CLK_CON_MUX_MUX_CMU_CMUREF		0x10c0
93 
94 /* DIV */
95 #define CLK_CON_DIV_CLKCMU_ACC_BUS		0x1800
96 #define CLK_CON_DIV_CLKCMU_APM_BUS		0x1804
97 #define CLK_CON_DIV_CLKCMU_AUD_BUS		0x1808
98 #define CLK_CON_DIV_CLKCMU_AUD_CPU		0x180c
99 #define CLK_CON_DIV_CLKCMU_BUSC_BUS		0x1810
100 #define CLK_CON_DIV_CLKCMU_BUSMC_BUS		0x1818
101 #define CLK_CON_DIV_CLKCMU_CORE_BUS		0x181c
102 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER	0x1820
103 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH	0x1828
104 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER	0x182c
105 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH	0x1830
106 #define CLK_CON_DIV_CLKCMU_DPTX_BUS		0x183c
107 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC		0x1840
108 #define CLK_CON_DIV_CLKCMU_DPUM_BUS		0x1844
109 #define CLK_CON_DIV_CLKCMU_DPUS0_BUS		0x1848
110 #define CLK_CON_DIV_CLKCMU_DPUS1_BUS		0x184c
111 #define CLK_CON_DIV_CLKCMU_FSYS0_BUS		0x1850
112 #define CLK_CON_DIV_CLKCMU_FSYS0_PCIE		0x1854
113 #define CLK_CON_DIV_CLKCMU_FSYS1_BUS		0x1858
114 #define CLK_CON_DIV_CLKCMU_FSYS1_USBDRD		0x185c
115 #define CLK_CON_DIV_CLKCMU_FSYS2_BUS		0x1860
116 #define CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET	0x1864
117 #define CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD	0x1868
118 #define CLK_CON_DIV_CLKCMU_G2D_G2D		0x186c
119 #define CLK_CON_DIV_CLKCMU_G2D_MSCL		0x1870
120 #define CLK_CON_DIV_CLKCMU_G3D00_SWITCH		0x1874
121 #define CLK_CON_DIV_CLKCMU_G3D01_SWITCH		0x1878
122 #define CLK_CON_DIV_CLKCMU_G3D1_SWITCH		0x187c
123 #define CLK_CON_DIV_CLKCMU_ISPB_BUS		0x1884
124 #define CLK_CON_DIV_CLKCMU_MFC_MFC		0x1888
125 #define CLK_CON_DIV_CLKCMU_MFC_WFD		0x188c
126 #define CLK_CON_DIV_CLKCMU_MIF_BUSP		0x1890
127 #define CLK_CON_DIV_CLKCMU_NPU_BUS		0x1894
128 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS		0x1898
129 #define CLK_CON_DIV_CLKCMU_PERIC0_IP		0x189c
130 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS		0x18a0
131 #define CLK_CON_DIV_CLKCMU_PERIC1_IP		0x18a4
132 #define CLK_CON_DIV_CLKCMU_PERIS_BUS		0x18a8
133 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST	0x18b4
134 
135 #define CLK_CON_DIV_PLL_SHARED0_DIV2		0x18b8
136 #define CLK_CON_DIV_PLL_SHARED0_DIV3		0x18bc
137 #define CLK_CON_DIV_PLL_SHARED1_DIV2		0x18c0
138 #define CLK_CON_DIV_PLL_SHARED1_DIV3		0x18c4
139 #define CLK_CON_DIV_PLL_SHARED1_DIV4		0x18c8
140 #define CLK_CON_DIV_PLL_SHARED2_DIV2		0x18cc
141 #define CLK_CON_DIV_PLL_SHARED2_DIV3		0x18d0
142 #define CLK_CON_DIV_PLL_SHARED2_DIV4		0x18d4
143 #define CLK_CON_DIV_PLL_SHARED4_DIV2		0x18d4
144 #define CLK_CON_DIV_PLL_SHARED4_DIV4		0x18d8
145 
146 /* GATE */
147 #define CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST	0x2000
148 #define CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST	0x2004
149 #define CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST	0x2008
150 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST	0x2010
151 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST	0x2018
152 #define CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST	0x2020
153 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD	0x2024
154 #define CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH	0x2028
155 #define CLK_CON_GAT_GATE_CLKCMU_ACC_BUS		0x202c
156 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS		0x2030
157 #define CLK_CON_GAT_GATE_CLKCMU_AUD_BUS		0x2034
158 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU		0x2038
159 #define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS	0x203c
160 #define CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS	0x2044
161 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST	0x2048
162 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS	0x204c
163 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER	0x2050
164 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH	0x2058
165 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER	0x205c
166 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH	0x2060
167 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS	0x206c
168 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC	0x2070
169 #define CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS	0x2060
170 #define CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS	0x2064
171 #define CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS	0x207c
172 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS	0x2080
173 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE	0x2084
174 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS	0x2088
175 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD	0x208c
176 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS	0x2090
177 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET	0x2094
178 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD	0x2098
179 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D		0x209c
180 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL	0x20a0
181 #define CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH	0x20a4
182 #define CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH	0x20a8
183 #define CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH	0x20ac
184 #define CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS	0x20b4
185 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC		0x20b8
186 #define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD		0x20bc
187 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP	0x20c0
188 #define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS		0x20c4
189 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS	0x20c8
190 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP	0x20cc
191 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS	0x20d0
192 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP	0x20d4
193 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS	0x20d8
194 
195 static const unsigned long top_clk_regs[] __initconst = {
196 	PLL_LOCKTIME_PLL_SHARED0,
197 	PLL_LOCKTIME_PLL_SHARED1,
198 	PLL_LOCKTIME_PLL_SHARED2,
199 	PLL_LOCKTIME_PLL_SHARED3,
200 	PLL_LOCKTIME_PLL_SHARED4,
201 	PLL_CON0_PLL_SHARED0,
202 	PLL_CON3_PLL_SHARED0,
203 	PLL_CON0_PLL_SHARED1,
204 	PLL_CON3_PLL_SHARED1,
205 	PLL_CON0_PLL_SHARED2,
206 	PLL_CON3_PLL_SHARED2,
207 	PLL_CON0_PLL_SHARED3,
208 	PLL_CON3_PLL_SHARED3,
209 	PLL_CON0_PLL_SHARED4,
210 	PLL_CON3_PLL_SHARED4,
211 	CLK_CON_MUX_MUX_CLKCMU_ACC_BUS,
212 	CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
213 	CLK_CON_MUX_MUX_CLKCMU_AUD_BUS,
214 	CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
215 	CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS,
216 	CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
217 	CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
218 	CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
219 	CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
220 	CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
221 	CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
222 	CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS,
223 	CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC,
224 	CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS,
225 	CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS,
226 	CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS,
227 	CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS,
228 	CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE,
229 	CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS,
230 	CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD,
231 	CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD,
232 	CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS,
233 	CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET,
234 	CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD,
235 	CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
236 	CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
237 	CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH,
238 	CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH,
239 	CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH,
240 	CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS,
241 	CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
242 	CLK_CON_MUX_MUX_CLKCMU_MFC_WFD,
243 	CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
244 	CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
245 	CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
246 	CLK_CON_MUX_MUX_CLKCMU_NPU_BUS,
247 	CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
248 	CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
249 	CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
250 	CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
251 	CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS,
252 	CLK_CON_MUX_MUX_CMU_CMUREF,
253 	CLK_CON_DIV_CLKCMU_ACC_BUS,
254 	CLK_CON_DIV_CLKCMU_APM_BUS,
255 	CLK_CON_DIV_CLKCMU_AUD_BUS,
256 	CLK_CON_DIV_CLKCMU_AUD_CPU,
257 	CLK_CON_DIV_CLKCMU_BUSC_BUS,
258 	CLK_CON_DIV_CLKCMU_BUSMC_BUS,
259 	CLK_CON_DIV_CLKCMU_CORE_BUS,
260 	CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
261 	CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
262 	CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
263 	CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
264 	CLK_CON_DIV_CLKCMU_DPTX_BUS,
265 	CLK_CON_DIV_CLKCMU_DPTX_DPGTC,
266 	CLK_CON_DIV_CLKCMU_DPUM_BUS,
267 	CLK_CON_DIV_CLKCMU_DPUS0_BUS,
268 	CLK_CON_DIV_CLKCMU_DPUS1_BUS,
269 	CLK_CON_DIV_CLKCMU_FSYS0_BUS,
270 	CLK_CON_DIV_CLKCMU_FSYS0_PCIE,
271 	CLK_CON_DIV_CLKCMU_FSYS1_BUS,
272 	CLK_CON_DIV_CLKCMU_FSYS1_USBDRD,
273 	CLK_CON_DIV_CLKCMU_FSYS2_BUS,
274 	CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
275 	CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
276 	CLK_CON_DIV_CLKCMU_G2D_G2D,
277 	CLK_CON_DIV_CLKCMU_G2D_MSCL,
278 	CLK_CON_DIV_CLKCMU_G3D00_SWITCH,
279 	CLK_CON_DIV_CLKCMU_G3D01_SWITCH,
280 	CLK_CON_DIV_CLKCMU_G3D1_SWITCH,
281 	CLK_CON_DIV_CLKCMU_ISPB_BUS,
282 	CLK_CON_DIV_CLKCMU_MFC_MFC,
283 	CLK_CON_DIV_CLKCMU_MFC_WFD,
284 	CLK_CON_DIV_CLKCMU_MIF_BUSP,
285 	CLK_CON_DIV_CLKCMU_NPU_BUS,
286 	CLK_CON_DIV_CLKCMU_PERIC0_BUS,
287 	CLK_CON_DIV_CLKCMU_PERIC0_IP,
288 	CLK_CON_DIV_CLKCMU_PERIC1_BUS,
289 	CLK_CON_DIV_CLKCMU_PERIC1_IP,
290 	CLK_CON_DIV_CLKCMU_PERIS_BUS,
291 	CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
292 	CLK_CON_DIV_PLL_SHARED0_DIV2,
293 	CLK_CON_DIV_PLL_SHARED0_DIV3,
294 	CLK_CON_DIV_PLL_SHARED1_DIV2,
295 	CLK_CON_DIV_PLL_SHARED1_DIV3,
296 	CLK_CON_DIV_PLL_SHARED1_DIV4,
297 	CLK_CON_DIV_PLL_SHARED2_DIV2,
298 	CLK_CON_DIV_PLL_SHARED2_DIV3,
299 	CLK_CON_DIV_PLL_SHARED2_DIV4,
300 	CLK_CON_DIV_PLL_SHARED4_DIV2,
301 	CLK_CON_DIV_PLL_SHARED4_DIV4,
302 	CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST,
303 	CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST,
304 	CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST,
305 	CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST,
306 	CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST,
307 	CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST,
308 	CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD,
309 	CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
310 	CLK_CON_GAT_GATE_CLKCMU_ACC_BUS,
311 	CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
312 	CLK_CON_GAT_GATE_CLKCMU_AUD_BUS,
313 	CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
314 	CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS,
315 	CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS,
316 	CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
317 	CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
318 	CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER,
319 	CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
320 	CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER,
321 	CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
322 	CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
323 	CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
324 	CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
325 	CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
326 	CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
327 	CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
328 	CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
329 	CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
330 	CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
331 	CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
332 	CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET,
333 	CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD,
334 	CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
335 	CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
336 	CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
337 	CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
338 	CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
339 	CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
340 	CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
341 	CLK_CON_GAT_GATE_CLKCMU_MFC_WFD,
342 	CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
343 	CLK_CON_GAT_GATE_CLKCMU_NPU_BUS,
344 	CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
345 	CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
346 	CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
347 	CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
348 	CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
349 };
350 
351 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
352 	/* CMU_TOP_PURECLKCOMP */
353 	PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
354 	    PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
355 	PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared1_pll", "oscclk",
356 	    PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
357 	PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared2_pll", "oscclk",
358 	    PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
359 	PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared3_pll", "oscclk",
360 	    PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
361 	PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared4_pll", "oscclk",
362 	    PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
363 };
364 
365 /* List of parent clocks for Muxes in CMU_TOP */
366 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
367 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
368 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
369 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
370 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
371 
372 PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4",
373 				   "dout_shared2_div4", "dout_shared4_div4" };
374 PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" };
375 PNAME(mout_clkcmu_acc_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
376 				 "dout_shared1_div4", "dout_shared2_div4" };
377 PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
378 				 "dout_shared2_div4", "dout_shared4_div4" };
379 PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
380 				 "dout_shared2_div2", "dout_shared0_div3",
381 				 "dout_shared4_div2", "dout_shared1_div3",
382 				 "fout_shared3_pll" };
383 PNAME(mout_clkcmu_aud_bus_p) = { "dout_shared4_div2", "dout_shared1_div3",
384 				  "dout_shared2_div3", "dout_shared1_div4" };
385 PNAME(mout_clkcmu_busc_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
386 				  "dout_shared2_div4", "dout_shared4_div4" };
387 PNAME(mout_clkcmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
388 				  "dout_shared2_div2", "dout_shared0_div3",
389 				  "dout_shared4_div2", "dout_shared1_div3",
390 				  "dout_shared2_div3", "fout_shared3_pll" };
391 PNAME(mout_clkcmu_cpucl0_switch_p) = {
392 	"dout_shared0_div2", "dout_shared1_div2",
393 	"dout_shared2_div2", "dout_shared4_div2" };
394 PNAME(mout_clkcmu_cpucl0_cluster_p) = {
395 	"fout_shared2_pll", "fout_shared4_pll",
396 	"dout_shared0_div2", "dout_shared1_div2",
397 	"dout_shared2_div2", "dout_shared4_div2",
398 	"dout_shared2_div3", "fout_shared3_pll" };
399 PNAME(mout_clkcmu_dptx_bus_p) = { "dout_shared4_div2", "dout_shared2_div3",
400 				  "dout_shared1_div4", "dout_shared2_div4" };
401 PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3",
402 				    "dout_shared2_div4", "dout_shared4_div4" };
403 PNAME(mout_clkcmu_dpum_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
404 				  "dout_shared1_div4", "dout_shared2_div4",
405 				  "dout_shared4_div4", "fout_shared3_pll" };
406 PNAME(mout_clkcmu_fsys0_bus_p)	= {
407 	"dout_shared4_div2", "dout_shared2_div3",
408 	"dout_shared1_div4", "dout_shared2_div4" };
409 PNAME(mout_clkcmu_fsys0_pcie_p) = { "oscclk", "dout_shared2_div4" };
410 PNAME(mout_clkcmu_fsys1_bus_p)	= { "dout_shared2_div3", "dout_shared1_div4",
411 				    "dout_shared2_div4", "dout_shared4_div4" };
412 PNAME(mout_clkcmu_fsys1_usbdrd_p) = {
413 	"oscclk", "dout_shared2_div3",
414 	"dout_shared2_div4", "dout_shared4_div4" };
415 PNAME(mout_clkcmu_fsys1_mmc_card_p) = {
416 	"oscclk", "dout_shared2_div2",
417 	"dout_shared4_div2", "dout_shared2_div3" };
418 PNAME(mout_clkcmu_fsys2_ethernet_p) = {
419 	"oscclk", "dout_shared2_div2",
420 	"dout_shared0_div3", "dout_shared2_div3",
421 	"dout_shared1_div4", "fout_shared3_pll" };
422 PNAME(mout_clkcmu_g2d_g2d_p) = { "dout_shared2_div2", "dout_shared0_div3",
423 				 "dout_shared4_div2", "dout_shared1_div3",
424 				 "dout_shared2_div3", "dout_shared1_div4",
425 				 "dout_shared2_div4", "dout_shared4_div4" };
426 PNAME(mout_clkcmu_g3d0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
427 				     "dout_shared2_div2", "dout_shared4_div2" };
428 PNAME(mout_clkcmu_g3d1_switch_p) = { "dout_shared2_div2", "dout_shared4_div2",
429 				     "dout_shared2_div3", "dout_shared1_div4" };
430 PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
431 				    "fout_shared2_pll", "fout_shared4_pll",
432 				    "dout_shared0_div2", "dout_shared1_div2",
433 				    "dout_shared2_div2", "fout_shared3_pll" };
434 PNAME(mout_clkcmu_npu_bus_p) = { "dout_shared1_div2", "dout_shared2_div2",
435 				 "dout_shared0_div3", "dout_shared4_div2",
436 				 "dout_shared1_div3", "dout_shared2_div3",
437 				 "dout_shared1_div4", "fout_shared3_pll" };
438 PNAME(mout_clkcmu_peric0_bus_p) = { "dout_shared2_div3", "dout_shared2_div4" };
439 
440 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
441 	/* CMU_TOP_PURECLKCOMP */
442 	MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
443 	    PLL_CON0_PLL_SHARED0, 4, 1),
444 	MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
445 	    PLL_CON0_PLL_SHARED1, 4, 1),
446 	MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
447 	    PLL_CON0_PLL_SHARED2, 4, 1),
448 	MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
449 	    PLL_CON0_PLL_SHARED3, 4, 1),
450 	MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
451 	    PLL_CON0_PLL_SHARED4, 4, 1),
452 
453 	/* BOOST */
454 	MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost",
455 	    mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
456 	MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref",
457 	    mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
458 
459 	/* ACC */
460 	MUX(MOUT_CLKCMU_ACC_BUS, "mout_clkcmu_acc_bus", mout_clkcmu_acc_bus_p,
461 	    CLK_CON_MUX_MUX_CLKCMU_ACC_BUS, 0, 2),
462 
463 	/* APM */
464 	MUX(MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", mout_clkcmu_apm_bus_p,
465 	    CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 2),
466 
467 	/* AUD */
468 	MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu", mout_clkcmu_aud_cpu_p,
469 	    CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
470 	MUX(MOUT_CLKCMU_AUD_BUS, "mout_clkcmu_aud_bus", mout_clkcmu_aud_bus_p,
471 	    CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 0, 2),
472 
473 	/* BUSC */
474 	MUX(MOUT_CLKCMU_BUSC_BUS, "mout_clkcmu_busc_bus",
475 	    mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0, 2),
476 
477 	/* BUSMC */
478 	MUX(MOUT_CLKCMU_BUSMC_BUS, "mout_clkcmu_busmc_bus",
479 	    mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS, 0, 2),
480 
481 	/* CORE */
482 	MUX(MOUT_CLKCMU_CORE_BUS, "mout_clkcmu_core_bus",
483 	    mout_clkcmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
484 
485 	/* CPUCL0 */
486 	MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch",
487 	    mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
488 	    0, 2),
489 	MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster",
490 	    mout_clkcmu_cpucl0_cluster_p,
491 	    CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 0, 3),
492 
493 	/* CPUCL1 */
494 	MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch",
495 	    mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
496 	    0, 2),
497 	MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster",
498 	    mout_clkcmu_cpucl0_cluster_p,
499 	    CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 0, 3),
500 
501 	/* DPTX */
502 	MUX(MOUT_CLKCMU_DPTX_BUS, "mout_clkcmu_dptx_bus",
503 	    mout_clkcmu_dptx_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS, 0, 2),
504 	MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc",
505 	    mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
506 
507 	/* DPUM */
508 	MUX(MOUT_CLKCMU_DPUM_BUS, "mout_clkcmu_dpum_bus",
509 	    mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS, 0, 3),
510 
511 	/* DPUS */
512 	MUX(MOUT_CLKCMU_DPUS0_BUS, "mout_clkcmu_dpus0_bus",
513 	    mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS, 0, 3),
514 	MUX(MOUT_CLKCMU_DPUS1_BUS, "mout_clkcmu_dpus1_bus",
515 	    mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS, 0, 3),
516 
517 	/* FSYS0 */
518 	MUX(MOUT_CLKCMU_FSYS0_BUS, "mout_clkcmu_fsys0_bus",
519 	    mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0, 2),
520 	MUX(MOUT_CLKCMU_FSYS0_PCIE, "mout_clkcmu_fsys0_pcie",
521 	    mout_clkcmu_fsys0_pcie_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE, 0, 1),
522 
523 	/* FSYS1 */
524 	MUX(MOUT_CLKCMU_FSYS1_BUS, "mout_clkcmu_fsys1_bus",
525 	    mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0, 2),
526 	MUX(MOUT_CLKCMU_FSYS1_USBDRD, "mout_clkcmu_fsys1_usbdrd",
527 	    mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD,
528 	    0, 2),
529 	MUX(MOUT_CLKCMU_FSYS1_MMC_CARD, "mout_clkcmu_fsys1_mmc_card",
530 	    mout_clkcmu_fsys1_mmc_card_p,
531 	    CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 0, 2),
532 
533 	/* FSYS2 */
534 	MUX(MOUT_CLKCMU_FSYS2_BUS, "mout_clkcmu_fsys2_bus",
535 	    mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS, 0, 2),
536 	MUX(MOUT_CLKCMU_FSYS2_UFS_EMBD, "mout_clkcmu_fsys2_ufs_embd",
537 	    mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD,
538 	    0, 2),
539 	MUX(MOUT_CLKCMU_FSYS2_ETHERNET, "mout_clkcmu_fsys2_ethernet",
540 	    mout_clkcmu_fsys2_ethernet_p,
541 	    CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET, 0, 3),
542 
543 	/* G2D */
544 	MUX(MOUT_CLKCMU_G2D_G2D, "mout_clkcmu_g2d_g2d", mout_clkcmu_g2d_g2d_p,
545 	    CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
546 	MUX(MOUT_CLKCMU_G2D_MSCL, "mout_clkcmu_g2d_mscl",
547 	    mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
548 
549 	/* G3D0 */
550 	MUX(MOUT_CLKCMU_G3D00_SWITCH, "mout_clkcmu_g3d00_switch",
551 	    mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH,
552 	    0, 2),
553 	MUX(MOUT_CLKCMU_G3D01_SWITCH, "mout_clkcmu_g3d01_switch",
554 	    mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH,
555 	    0, 2),
556 
557 	/* G3D1 */
558 	MUX(MOUT_CLKCMU_G3D1_SWITCH, "mout_clkcmu_g3d1_switch",
559 	    mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH,
560 	    0, 2),
561 
562 	/* ISPB */
563 	MUX(MOUT_CLKCMU_ISPB_BUS, "mout_clkcmu_ispb_bus",
564 	    mout_clkcmu_acc_bus_p, CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS, 0, 2),
565 
566 	/* MFC */
567 	MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc",
568 	    mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
569 	MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd",
570 	    mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
571 
572 	/* MIF */
573 	MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch",
574 	    mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
575 	MUX(MOUT_CLKCMU_MIF_BUSP, "mout_clkcmu_mif_busp",
576 	    mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
577 
578 	/* NPU */
579 	MUX(MOUT_CLKCMU_NPU_BUS, "mout_clkcmu_npu_bus", mout_clkcmu_npu_bus_p,
580 	    CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
581 
582 	/* PERIC0 */
583 	MUX(MOUT_CLKCMU_PERIC0_BUS, "mout_clkcmu_peric0_bus",
584 	    mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
585 	MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip",
586 	    mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
587 
588 	/* PERIC1 */
589 	MUX(MOUT_CLKCMU_PERIC1_BUS, "mout_clkcmu_peric1_bus",
590 	    mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
591 	MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip",
592 	    mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
593 
594 	/* PERIS */
595 	MUX(MOUT_CLKCMU_PERIS_BUS, "mout_clkcmu_peris_bus",
596 	    mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
597 };
598 
599 static const struct samsung_div_clock top_div_clks[] __initconst = {
600 	/* CMU_TOP_PURECLKCOMP */
601 	DIV(DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
602 	    CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
603 	DIV(DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
604 	    CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
605 
606 	DIV(DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
607 	    CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
608 	DIV(DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
609 	    CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
610 	DIV(DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
611 	    CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
612 
613 	DIV(DOUT_SHARED2_DIV3, "dout_shared2_div3", "mout_shared2_pll",
614 	    CLK_CON_DIV_PLL_SHARED2_DIV3, 0, 2),
615 	DIV(DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
616 	    CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
617 	DIV(DOUT_SHARED2_DIV4, "dout_shared2_div4", "dout_shared2_div2",
618 	    CLK_CON_DIV_PLL_SHARED2_DIV4, 0, 1),
619 
620 	DIV(DOUT_SHARED4_DIV2, "dout_shared4_div2", "mout_shared4_pll",
621 	    CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
622 	DIV(DOUT_SHARED4_DIV4, "dout_shared4_div4", "dout_shared4_div2",
623 	    CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
624 
625 	/* BOOST */
626 	DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost",
627 	    "gout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
628 
629 	/* ACC */
630 	DIV(DOUT_CLKCMU_ACC_BUS, "dout_clkcmu_acc_bus", "gout_clkcmu_acc_bus",
631 	    CLK_CON_DIV_CLKCMU_ACC_BUS, 0, 4),
632 
633 	/* APM */
634 	DIV(DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", "gout_clkcmu_apm_bus",
635 	    CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
636 
637 	/* AUD */
638 	DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu", "gout_clkcmu_aud_cpu",
639 	    CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
640 	DIV(DOUT_CLKCMU_AUD_BUS, "dout_clkcmu_aud_bus", "gout_clkcmu_aud_bus",
641 	    CLK_CON_DIV_CLKCMU_AUD_BUS, 0, 4),
642 
643 	/* BUSC */
644 	DIV(DOUT_CLKCMU_BUSC_BUS, "dout_clkcmu_busc_bus",
645 	    "gout_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4),
646 
647 	/* BUSMC */
648 	DIV(DOUT_CLKCMU_BUSMC_BUS, "dout_clkcmu_busmc_bus",
649 	    "gout_clkcmu_busmc_bus", CLK_CON_DIV_CLKCMU_BUSMC_BUS, 0, 4),
650 
651 	/* CORE */
652 	DIV(DOUT_CLKCMU_CORE_BUS, "dout_clkcmu_core_bus",
653 	    "gout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
654 
655 	/* CPUCL0 */
656 	DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch",
657 	    "gout_clkcmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
658 	    0, 3),
659 	DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster",
660 	    "gout_clkcmu_cpucl0_cluster", CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
661 	    0, 3),
662 
663 	/* CPUCL1 */
664 	DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch",
665 	    "gout_clkcmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
666 	    0, 3),
667 	DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster",
668 	    "gout_clkcmu_cpucl1_cluster", CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
669 	    0, 3),
670 
671 	/* DPTX */
672 	DIV(DOUT_CLKCMU_DPTX_BUS, "dout_clkcmu_dptx_bus",
673 	    "gout_clkcmu_dptx_bus", CLK_CON_DIV_CLKCMU_DPTX_BUS, 0, 4),
674 	DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc",
675 	    "gout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
676 
677 	/* DPUM */
678 	DIV(DOUT_CLKCMU_DPUM_BUS, "dout_clkcmu_dpum_bus",
679 	    "gout_clkcmu_dpum_bus", CLK_CON_DIV_CLKCMU_DPUM_BUS, 0, 4),
680 
681 	/* DPUS */
682 	DIV(DOUT_CLKCMU_DPUS0_BUS, "dout_clkcmu_dpus0_bus",
683 	    "gout_clkcmu_dpus0_bus", CLK_CON_DIV_CLKCMU_DPUS0_BUS, 0, 4),
684 	DIV(DOUT_CLKCMU_DPUS1_BUS, "dout_clkcmu_dpus1_bus",
685 	    "gout_clkcmu_dpus1_bus", CLK_CON_DIV_CLKCMU_DPUS1_BUS, 0, 4),
686 
687 	/* FSYS0 */
688 	DIV(DOUT_CLKCMU_FSYS0_BUS, "dout_clkcmu_fsys0_bus",
689 	    "gout_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
690 
691 	/* FSYS1 */
692 	DIV(DOUT_CLKCMU_FSYS1_BUS, "dout_clkcmu_fsys1_bus",
693 	    "gout_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
694 	DIV(DOUT_CLKCMU_FSYS1_USBDRD, "dout_clkcmu_fsys1_usbdrd",
695 	    "gout_clkcmu_fsys1_usbdrd", CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 0, 4),
696 
697 	/* FSYS2 */
698 	DIV(DOUT_CLKCMU_FSYS2_BUS, "dout_clkcmu_fsys2_bus",
699 	    "gout_clkcmu_fsys2_bus", CLK_CON_DIV_CLKCMU_FSYS2_BUS, 0, 4),
700 	DIV(DOUT_CLKCMU_FSYS2_UFS_EMBD, "dout_clkcmu_fsys2_ufs_embd",
701 	    "gout_clkcmu_fsys2_ufs_embd", CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
702 	    0, 3),
703 	DIV(DOUT_CLKCMU_FSYS2_ETHERNET, "dout_clkcmu_fsys2_ethernet",
704 	    "gout_clkcmu_fsys2_ethernet", CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
705 	    0, 3),
706 
707 	/* G2D */
708 	DIV(DOUT_CLKCMU_G2D_G2D, "dout_clkcmu_g2d_g2d", "gout_clkcmu_g2d_g2d",
709 	    CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
710 	DIV(DOUT_CLKCMU_G2D_MSCL, "dout_clkcmu_g2d_mscl",
711 	    "gout_clkcmu_g2d_mscl", CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
712 
713 	/* G3D0 */
714 	DIV(DOUT_CLKCMU_G3D00_SWITCH, "dout_clkcmu_g3d00_switch",
715 	    "gout_clkcmu_g3d00_switch", CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 0, 3),
716 	DIV(DOUT_CLKCMU_G3D01_SWITCH, "dout_clkcmu_g3d01_switch",
717 	    "gout_clkcmu_g3d01_switch", CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 0, 3),
718 
719 	/* G3D1 */
720 	DIV(DOUT_CLKCMU_G3D1_SWITCH, "dout_clkcmu_g3d1_switch",
721 	    "gout_clkcmu_g3d1_switch", CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 0, 3),
722 
723 	/* ISPB */
724 	DIV(DOUT_CLKCMU_ISPB_BUS, "dout_clkcmu_ispb_bus",
725 	    "gout_clkcmu_ispb_bus", CLK_CON_DIV_CLKCMU_ISPB_BUS, 0, 4),
726 
727 	/* MFC */
728 	DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc", "gout_clkcmu_mfc_mfc",
729 	    CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
730 	DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd", "gout_clkcmu_mfc_wfd",
731 	    CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
732 
733 	/* MIF */
734 	DIV(DOUT_CLKCMU_MIF_BUSP, "dout_clkcmu_mif_busp",
735 	    "gout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
736 
737 	/* NPU */
738 	DIV(DOUT_CLKCMU_NPU_BUS, "dout_clkcmu_npu_bus", "gout_clkcmu_npu_bus",
739 	    CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
740 
741 	/* PERIC0 */
742 	DIV(DOUT_CLKCMU_PERIC0_BUS, "dout_clkcmu_peric0_bus",
743 	    "gout_clkcmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
744 	DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip",
745 	    "gout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
746 
747 	/* PERIC1 */
748 	DIV(DOUT_CLKCMU_PERIC1_BUS, "dout_clkcmu_peric1_bus",
749 	    "gout_clkcmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
750 	DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip",
751 	    "gout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
752 
753 	/* PERIS */
754 	DIV(DOUT_CLKCMU_PERIS_BUS, "dout_clkcmu_peris_bus",
755 	    "gout_clkcmu_peris_bus", CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
756 };
757 
758 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
759 	FFACTOR(DOUT_CLKCMU_FSYS0_PCIE, "dout_clkcmu_fsys0_pcie",
760 		"gout_clkcmu_fsys0_pcie", 1, 4, 0),
761 };
762 
763 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
764 	/* BOOST */
765 	GATE(GOUT_CLKCMU_CMU_BOOST, "gout_clkcmu_cmu_boost",
766 	     "mout_clkcmu_cmu_boost", CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
767 	     21, 0, 0),
768 
769 	GATE(GOUT_CLKCMU_CPUCL0_BOOST, "gout_clkcmu_cpucl0_boost",
770 	     "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 21, 0, 0),
771 	GATE(GOUT_CLKCMU_CPUCL1_BOOST, "gout_clkcmu_cpucl1_boost",
772 	     "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 21, 0, 0),
773 	GATE(GOUT_CLKCMU_CORE_BOOST, "gout_clkcmu_core_boost",
774 	     "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 21, 0, 0),
775 	GATE(GOUT_CLKCMU_BUSC_BOOST, "gout_clkcmu_busc_boost",
776 	     "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 21, 0, 0),
777 
778 	GATE(GOUT_CLKCMU_BUSMC_BOOST, "gout_clkcmu_busmc_boost",
779 	     "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 21, 0, 0),
780 	GATE(GOUT_CLKCMU_MIF_BOOST, "gout_clkcmu_mif_boost", "dout_cmu_boost",
781 	     CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST, 21, 0, 0),
782 
783 	/* ACC */
784 	GATE(GOUT_CLKCMU_ACC_BUS, "gout_clkcmu_acc_bus", "mout_clkcmu_acc_bus",
785 	     CLK_CON_GAT_GATE_CLKCMU_ACC_BUS, 21, 0, 0),
786 
787 	/* APM */
788 	GATE(GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", "mout_clkcmu_apm_bus",
789 	     CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
790 
791 	/* AUD */
792 	GATE(GOUT_CLKCMU_AUD_CPU, "gout_clkcmu_aud_cpu", "mout_clkcmu_aud_cpu",
793 	     CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
794 	GATE(GOUT_CLKCMU_AUD_BUS, "gout_clkcmu_aud_bus", "mout_clkcmu_aud_bus",
795 	     CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 21, 0, 0),
796 
797 	/* BUSC */
798 	GATE(GOUT_CLKCMU_BUSC_BUS, "gout_clkcmu_busc_bus",
799 	     "mout_clkcmu_busc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 21,
800 	     CLK_IS_CRITICAL, 0),
801 
802 	/* BUSMC */
803 	GATE(GOUT_CLKCMU_BUSMC_BUS, "gout_clkcmu_busmc_bus",
804 	     "mout_clkcmu_busmc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS, 21,
805 	     CLK_IS_CRITICAL, 0),
806 
807 	/* CORE */
808 	GATE(GOUT_CLKCMU_CORE_BUS, "gout_clkcmu_core_bus",
809 	     "mout_clkcmu_core_bus", CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
810 	     21, 0, 0),
811 
812 	/* CPUCL0 */
813 	GATE(GOUT_CLKCMU_CPUCL0_SWITCH, "gout_clkcmu_cpucl0_switch",
814 	     "mout_clkcmu_cpucl0_switch",
815 	     CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
816 	GATE(GOUT_CLKCMU_CPUCL0_CLUSTER, "gout_clkcmu_cpucl0_cluster",
817 	     "mout_clkcmu_cpucl0_cluster",
818 	     CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
819 
820 	/* CPUCL1 */
821 	GATE(GOUT_CLKCMU_CPUCL1_SWITCH, "gout_clkcmu_cpucl1_switch",
822 	     "mout_clkcmu_cpucl1_switch",
823 	     CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
824 	GATE(GOUT_CLKCMU_CPUCL1_CLUSTER, "gout_clkcmu_cpucl1_cluster",
825 	     "mout_clkcmu_cpucl1_cluster",
826 	     CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
827 
828 	/* DPTX */
829 	GATE(GOUT_CLKCMU_DPTX_BUS, "gout_clkcmu_dptx_bus",
830 	     "mout_clkcmu_dptx_bus", CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
831 	     21, 0, 0),
832 	GATE(GOUT_CLKCMU_DPTX_DPGTC, "gout_clkcmu_dptx_dpgtc",
833 	     "mout_clkcmu_dptx_dpgtc", CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
834 	     21, 0, 0),
835 
836 	/* DPUM */
837 	GATE(GOUT_CLKCMU_DPUM_BUS, "gout_clkcmu_dpum_bus",
838 	     "mout_clkcmu_dpum_bus", CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
839 	     21, 0, 0),
840 
841 	/* DPUS */
842 	GATE(GOUT_CLKCMU_DPUS0_BUS, "gout_clkcmu_dpus0_bus",
843 	     "mout_clkcmu_dpus0_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
844 	     21, 0, 0),
845 	GATE(GOUT_CLKCMU_DPUS1_BUS, "gout_clkcmu_dpus1_bus",
846 	     "mout_clkcmu_dpus1_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
847 	     21, 0, 0),
848 
849 	/* FSYS0 */
850 	GATE(GOUT_CLKCMU_FSYS0_BUS, "gout_clkcmu_fsys0_bus",
851 	     "mout_clkcmu_fsys0_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
852 	     21, 0, 0),
853 	GATE(GOUT_CLKCMU_FSYS0_PCIE, "gout_clkcmu_fsys0_pcie",
854 	     "mout_clkcmu_fsys0_pcie", CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
855 	     21, 0, 0),
856 
857 	/* FSYS1 */
858 	GATE(GOUT_CLKCMU_FSYS1_BUS, "gout_clkcmu_fsys1_bus",
859 	     "mout_clkcmu_fsys1_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
860 	     21, 0, 0),
861 	GATE(GOUT_CLKCMU_FSYS1_USBDRD, "gout_clkcmu_fsys1_usbdrd",
862 	     "mout_clkcmu_fsys1_usbdrd", CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
863 	     21, 0, 0),
864 	GATE(GOUT_CLKCMU_FSYS1_MMC_CARD, "gout_clkcmu_fsys1_mmc_card",
865 	     "mout_clkcmu_fsys1_mmc_card",
866 	     CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 21, 0, 0),
867 
868 	/* FSYS2 */
869 	GATE(GOUT_CLKCMU_FSYS2_BUS, "gout_clkcmu_fsys2_bus",
870 	     "mout_clkcmu_fsys2_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
871 	     21, 0, 0),
872 	GATE(GOUT_CLKCMU_FSYS2_UFS_EMBD, "gout_clkcmu_fsys2_ufs_embd",
873 	     "mout_clkcmu_fsys2_ufs_embd",
874 	     CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD, 21, 0, 0),
875 	GATE(GOUT_CLKCMU_FSYS2_ETHERNET, "gout_clkcmu_fsys2_ethernet",
876 	     "mout_clkcmu_fsys2_ethernet",
877 	     CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET, 21, 0, 0),
878 
879 	/* G2D */
880 	GATE(GOUT_CLKCMU_G2D_G2D, "gout_clkcmu_g2d_g2d",
881 	     "mout_clkcmu_g2d_g2d", CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
882 	GATE(GOUT_CLKCMU_G2D_MSCL, "gout_clkcmu_g2d_mscl",
883 	     "mout_clkcmu_g2d_mscl", CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
884 	     21, 0, 0),
885 
886 	/* G3D0 */
887 	GATE(GOUT_CLKCMU_G3D00_SWITCH, "gout_clkcmu_g3d00_switch",
888 	     "mout_clkcmu_g3d00_switch", CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
889 	     21, 0, 0),
890 	GATE(GOUT_CLKCMU_G3D01_SWITCH, "gout_clkcmu_g3d01_switch",
891 	     "mout_clkcmu_g3d01_switch", CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
892 	     21, 0, 0),
893 
894 	/* G3D1 */
895 	GATE(GOUT_CLKCMU_G3D1_SWITCH, "gout_clkcmu_g3d1_switch",
896 	     "mout_clkcmu_g3d1_switch", CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
897 	     21, 0, 0),
898 
899 	/* ISPB */
900 	GATE(GOUT_CLKCMU_ISPB_BUS, "gout_clkcmu_ispb_bus",
901 	     "mout_clkcmu_ispb_bus", CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
902 	     21, 0, 0),
903 
904 	/* MFC */
905 	GATE(GOUT_CLKCMU_MFC_MFC, "gout_clkcmu_mfc_mfc", "mout_clkcmu_mfc_mfc",
906 	     CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
907 	GATE(GOUT_CLKCMU_MFC_WFD, "gout_clkcmu_mfc_wfd", "mout_clkcmu_mfc_wfd",
908 	     CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, 0, 0),
909 
910 	/* MIF */
911 	GATE(GOUT_CLKCMU_MIF_SWITCH, "gout_clkcmu_mif_switch",
912 	     "mout_clkcmu_mif_switch", CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
913 	     21, CLK_IGNORE_UNUSED, 0),
914 	GATE(GOUT_CLKCMU_MIF_BUSP, "gout_clkcmu_mif_busp",
915 	     "mout_clkcmu_mif_busp", CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
916 	     21, CLK_IGNORE_UNUSED, 0),
917 
918 	/* NPU */
919 	GATE(GOUT_CLKCMU_NPU_BUS, "gout_clkcmu_npu_bus", "mout_clkcmu_npu_bus",
920 	     CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
921 
922 	/* PERIC0 */
923 	GATE(GOUT_CLKCMU_PERIC0_BUS, "gout_clkcmu_peric0_bus",
924 	     "mout_clkcmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
925 	     21, 0, 0),
926 	GATE(GOUT_CLKCMU_PERIC0_IP, "gout_clkcmu_peric0_ip",
927 	     "mout_clkcmu_peric0_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
928 	     21, 0, 0),
929 
930 	/* PERIC1 */
931 	GATE(GOUT_CLKCMU_PERIC1_BUS, "gout_clkcmu_peric1_bus",
932 	     "mout_clkcmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
933 	     21, 0, 0),
934 	GATE(GOUT_CLKCMU_PERIC1_IP, "gout_clkcmu_peric1_ip",
935 	     "mout_clkcmu_peric1_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
936 	     21, 0, 0),
937 
938 	/* PERIS */
939 	GATE(GOUT_CLKCMU_PERIS_BUS, "gout_clkcmu_peris_bus",
940 	     "mout_clkcmu_peris_bus", CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
941 	     21, CLK_IGNORE_UNUSED, 0),
942 };
943 
944 static const struct samsung_cmu_info top_cmu_info __initconst = {
945 	.pll_clks		= top_pll_clks,
946 	.nr_pll_clks		= ARRAY_SIZE(top_pll_clks),
947 	.mux_clks		= top_mux_clks,
948 	.nr_mux_clks		= ARRAY_SIZE(top_mux_clks),
949 	.div_clks		= top_div_clks,
950 	.nr_div_clks		= ARRAY_SIZE(top_div_clks),
951 	.fixed_factor_clks	= top_fixed_factor_clks,
952 	.nr_fixed_factor_clks	= ARRAY_SIZE(top_fixed_factor_clks),
953 	.gate_clks		= top_gate_clks,
954 	.nr_gate_clks		= ARRAY_SIZE(top_gate_clks),
955 	.nr_clk_ids		= CLKS_NR_TOP,
956 	.clk_regs		= top_clk_regs,
957 	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
958 };
959 
960 static void __init exynosautov9_cmu_top_init(struct device_node *np)
961 {
962 	exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
963 }
964 
965 /* Register CMU_TOP early, as it's a dependency for other early domains */
966 CLK_OF_DECLARE(exynosautov9_cmu_top, "samsung,exynosautov9-cmu-top",
967 	       exynosautov9_cmu_top_init);
968 
969 /* ---- CMU_BUSMC ---------------------------------------------------------- */
970 
971 /* Register Offset definitions for CMU_BUSMC (0x1b200000) */
972 #define PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER				0x0600
973 #define CLK_CON_DIV_DIV_CLK_BUSMC_BUSP					0x1800
974 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK		0x2078
975 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK		0x2080
976 
977 static const unsigned long busmc_clk_regs[] __initconst = {
978 	PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER,
979 	CLK_CON_DIV_DIV_CLK_BUSMC_BUSP,
980 	CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK,
981 	CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK,
982 };
983 
984 /* List of parent clocks for Muxes in CMU_BUSMC */
985 PNAME(mout_busmc_bus_user_p) = { "oscclk", "dout_clkcmu_busmc_bus" };
986 
987 static const struct samsung_mux_clock busmc_mux_clks[] __initconst = {
988 	MUX(CLK_MOUT_BUSMC_BUS_USER, "mout_busmc_bus_user",
989 	    mout_busmc_bus_user_p, PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER, 4, 1),
990 };
991 
992 static const struct samsung_div_clock busmc_div_clks[] __initconst = {
993 	DIV(CLK_DOUT_BUSMC_BUSP, "dout_busmc_busp", "mout_busmc_bus_user",
994 	    CLK_CON_DIV_DIV_CLK_BUSMC_BUSP, 0, 3),
995 };
996 
997 static const struct samsung_gate_clock busmc_gate_clks[] __initconst = {
998 	GATE(CLK_GOUT_BUSMC_PDMA0_PCLK, "gout_busmc_pdma0_pclk",
999 	     "dout_busmc_busp",
1000 	     CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK, 21,
1001 	     0, 0),
1002 	GATE(CLK_GOUT_BUSMC_SPDMA_PCLK, "gout_busmc_spdma_pclk",
1003 	     "dout_busmc_busp",
1004 	     CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK, 21,
1005 	     0, 0),
1006 };
1007 
1008 static const struct samsung_cmu_info busmc_cmu_info __initconst = {
1009 	.mux_clks		= busmc_mux_clks,
1010 	.nr_mux_clks		= ARRAY_SIZE(busmc_mux_clks),
1011 	.div_clks		= busmc_div_clks,
1012 	.nr_div_clks		= ARRAY_SIZE(busmc_div_clks),
1013 	.gate_clks		= busmc_gate_clks,
1014 	.nr_gate_clks		= ARRAY_SIZE(busmc_gate_clks),
1015 	.nr_clk_ids		= CLKS_NR_BUSMC,
1016 	.clk_regs		= busmc_clk_regs,
1017 	.nr_clk_regs		= ARRAY_SIZE(busmc_clk_regs),
1018 	.clk_name		= "dout_clkcmu_busmc_bus",
1019 };
1020 
1021 /* ---- CMU_CORE ----------------------------------------------------------- */
1022 
1023 /* Register Offset definitions for CMU_CORE (0x1b030000) */
1024 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER				0x0600
1025 #define CLK_CON_MUX_MUX_CORE_CMUREF					0x1000
1026 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP					0x1800
1027 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK			0x2000
1028 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK			0x2004
1029 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK	0x2008
1030 
1031 static const unsigned long core_clk_regs[] __initconst = {
1032 	PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
1033 	CLK_CON_MUX_MUX_CORE_CMUREF,
1034 	CLK_CON_DIV_DIV_CLK_CORE_BUSP,
1035 	CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK,
1036 	CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK,
1037 	CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
1038 };
1039 
1040 /* List of parent clocks for Muxes in CMU_CORE */
1041 PNAME(mout_core_bus_user_p) = { "oscclk", "dout_clkcmu_core_bus" };
1042 
1043 static const struct samsung_mux_clock core_mux_clks[] __initconst = {
1044 	MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
1045 	    PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
1046 };
1047 
1048 static const struct samsung_div_clock core_div_clks[] __initconst = {
1049 	DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
1050 	    CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 3),
1051 };
1052 
1053 static const struct samsung_gate_clock core_gate_clks[] __initconst = {
1054 	GATE(CLK_GOUT_CORE_CCI_CLK, "gout_core_cci_clk", "mout_core_bus_user",
1055 	     CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK, 21,
1056 	     CLK_IS_CRITICAL, 0),
1057 	GATE(CLK_GOUT_CORE_CCI_PCLK, "gout_core_cci_pclk", "dout_core_busp",
1058 	     CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, 21,
1059 	     CLK_IS_CRITICAL, 0),
1060 	GATE(CLK_GOUT_CORE_CMU_CORE_PCLK, "gout_core_cmu_core_pclk",
1061 	     "dout_core_busp",
1062 	     CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 21,
1063 	     CLK_IS_CRITICAL, 0),
1064 };
1065 
1066 static const struct samsung_cmu_info core_cmu_info __initconst = {
1067 	.mux_clks		= core_mux_clks,
1068 	.nr_mux_clks		= ARRAY_SIZE(core_mux_clks),
1069 	.div_clks		= core_div_clks,
1070 	.nr_div_clks		= ARRAY_SIZE(core_div_clks),
1071 	.gate_clks		= core_gate_clks,
1072 	.nr_gate_clks		= ARRAY_SIZE(core_gate_clks),
1073 	.nr_clk_ids		= CLKS_NR_CORE,
1074 	.clk_regs		= core_clk_regs,
1075 	.nr_clk_regs		= ARRAY_SIZE(core_clk_regs),
1076 	.clk_name		= "dout_clkcmu_core_bus",
1077 };
1078 
1079 /* ---- CMU_FSYS0 ---------------------------------------------------------- */
1080 
1081 /* Register Offset definitions for CMU_FSYS2 (0x17700000) */
1082 #define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER	0x0600
1083 #define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER	0x0610
1084 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK	0x2000
1085 
1086 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN	0x2004
1087 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN	0x2008
1088 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN	0x200c
1089 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN	0x2010
1090 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN	0x2014
1091 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN	0x2018
1092 
1093 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK	0x205c
1094 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK	0x2060
1095 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK	0x2064
1096 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK	0x206c
1097 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK	0x2070
1098 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK	0x2074
1099 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK	0x207c
1100 
1101 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK	0x2084
1102 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK	0x2088
1103 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK	0x208c
1104 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK	0x2094
1105 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK	0x2098
1106 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK	0x209c
1107 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK	0x20a4
1108 
1109 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK		0x20ac
1110 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK	0x20b0
1111 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK		0x20b4
1112 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK		0x20bc
1113 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK	0x20c0
1114 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK		0x20c4
1115 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK		0x20cc
1116 
1117 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK		0x20d4
1118 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK		0x20d8
1119 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK		0x20dc
1120 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK		0x20e0
1121 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK		0x20e4
1122 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK		0x20e8
1123 
1124 
1125 static const unsigned long fsys0_clk_regs[] __initconst = {
1126 	PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER,
1127 	PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER,
1128 	CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
1129 	CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
1130 	CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
1131 	CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
1132 	CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
1133 	CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
1134 	CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
1135 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
1136 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
1137 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
1138 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
1139 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
1140 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
1141 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK,
1142 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
1143 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
1144 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
1145 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
1146 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
1147 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
1148 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK,
1149 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
1150 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
1151 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
1152 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
1153 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
1154 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
1155 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK,
1156 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
1157 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
1158 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
1159 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
1160 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
1161 	CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
1162 };
1163 
1164 /* List of parent clocks for Muxes in CMU_FSYS0 */
1165 PNAME(mout_fsys0_bus_user_p) = { "oscclk", "dout_clkcmu_fsys0_bus" };
1166 PNAME(mout_fsys0_pcie_user_p) = { "oscclk", "dout_clkcmu_fsys0_pcie" };
1167 
1168 static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
1169 	MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user",
1170 	    mout_fsys0_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 4, 1),
1171 	MUX(CLK_MOUT_FSYS0_PCIE_USER, "mout_fsys0_pcie_user",
1172 	    mout_fsys0_pcie_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER, 4, 1),
1173 };
1174 
1175 static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
1176 	GATE(CLK_GOUT_FSYS0_BUS_PCLK, "gout_fsys0_bus_pclk",
1177 	     "mout_fsys0_bus_user",
1178 	     CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
1179 	     21, CLK_IGNORE_UNUSED, 0),
1180 
1181 	/* Gen3 2L0 */
1182 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK,
1183 	     "gout_fsys0_pcie_gen3_2l0_x1_refclk", "mout_fsys0_pcie_user",
1184 	     CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
1185 	     21, 0, 0),
1186 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK,
1187 	     "gout_fsys0_pcie_gen3_2l0_x2_refclk", "mout_fsys0_pcie_user",
1188 	     CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
1189 	     21, 0, 0),
1190 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK,
1191 	     "gout_fsys0_pcie_gen3_2l0_x1_dbi_aclk", "mout_fsys0_bus_user",
1192 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
1193 	     21, 0, 0),
1194 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK,
1195 	     "gout_fsys0_pcie_gen3_2l0_x1_mstr_aclk", "mout_fsys0_bus_user",
1196 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
1197 	     21, 0, 0),
1198 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK,
1199 	     "gout_fsys0_pcie_gen3_2l0_x1_slv_aclk", "mout_fsys0_bus_user",
1200 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
1201 	     21, 0, 0),
1202 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK,
1203 	     "gout_fsys0_pcie_gen3_2l0_x2_dbi_aclk", "mout_fsys0_bus_user",
1204 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
1205 	     21, 0, 0),
1206 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK,
1207 	     "gout_fsys0_pcie_gen3_2l0_x2_mstr_aclk", "mout_fsys0_bus_user",
1208 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
1209 	     21, 0, 0),
1210 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK,
1211 	     "gout_fsys0_pcie_gen3_2l0_x2_slv_aclk", "mout_fsys0_bus_user",
1212 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
1213 	     21, 0, 0),
1214 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK,
1215 	     "gout_fsys0_pcie_gen3a_2l0_clk", "mout_fsys0_pcie_user",
1216 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
1217 	     21, 0, 0),
1218 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK,
1219 	     "gout_fsys0_pcie_gen3b_2l0_clk", "mout_fsys0_pcie_user",
1220 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
1221 	     21, 0, 0),
1222 
1223 	/* Gen3 2L1 */
1224 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK,
1225 	     "gout_fsys0_pcie_gen3_2l1_x1_refclk", "mout_fsys0_pcie_user",
1226 	     CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
1227 	     21, 0, 0),
1228 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK,
1229 	     "gout_fsys0_pcie_gen3_2l1_x2_refclk", "mout_fsys0_pcie_user",
1230 	     CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
1231 	     21, 0, 0),
1232 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK,
1233 	     "gout_fsys0_pcie_gen3_2l1_x1_dbi_aclk", "mout_fsys0_bus_user",
1234 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
1235 	     21, 0, 0),
1236 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK,
1237 	     "gout_fsys0_pcie_gen3_2l1_x1_mstr_aclk", "mout_fsys0_bus_user",
1238 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
1239 	     21, 0, 0),
1240 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK,
1241 	     "gout_fsys0_pcie_gen3_2l1_x1_slv_aclk", "mout_fsys0_bus_user",
1242 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
1243 	     21, 0, 0),
1244 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK,
1245 	     "gout_fsys0_pcie_gen3_2l1_x2_dbi_aclk", "mout_fsys0_bus_user",
1246 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
1247 	     21, 0, 0),
1248 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK,
1249 	     "gout_fsys0_pcie_gen3_2l1_x2_mstr_aclk", "mout_fsys0_bus_user",
1250 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
1251 	     21, 0, 0),
1252 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK,
1253 	     "gout_fsys0_pcie_gen3_2l1_x2_slv_aclk", "mout_fsys0_bus_user",
1254 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
1255 	     21, 0, 0),
1256 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK,
1257 	     "gout_fsys0_pcie_gen3a_2l1_clk", "mout_fsys0_pcie_user",
1258 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
1259 	     21, 0, 0),
1260 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK,
1261 	     "gout_fsys0_pcie_gen3b_2l1_clk", "mout_fsys0_pcie_user",
1262 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
1263 	     21, 0, 0),
1264 
1265 	/* Gen3 4L */
1266 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK,
1267 	     "gout_fsys0_pcie_gen3_4l_x2_refclk", "mout_fsys0_pcie_user",
1268 	     CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
1269 	     21, 0, 0),
1270 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK,
1271 	     "gout_fsys0_pcie_gen3_4l_x4_refclk", "mout_fsys0_pcie_user",
1272 	     CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
1273 	     21, 0, 0),
1274 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK,
1275 	     "gout_fsys0_pcie_gen3_4l_x2_dbi_aclk", "mout_fsys0_bus_user",
1276 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
1277 	     21, 0, 0),
1278 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK,
1279 	     "gout_fsys0_pcie_gen3_4l_x2_mstr_aclk", "mout_fsys0_bus_user",
1280 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
1281 	     21, 0, 0),
1282 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK,
1283 	     "gout_fsys0_pcie_gen3_4l_x2_slv_aclk", "mout_fsys0_bus_user",
1284 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
1285 	     21, 0, 0),
1286 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK,
1287 	     "gout_fsys0_pcie_gen3_4l_x4_dbi_aclk", "mout_fsys0_bus_user",
1288 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
1289 	     21, 0, 0),
1290 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK,
1291 	     "gout_fsys0_pcie_gen3_4l_x4_mstr_aclk", "mout_fsys0_bus_user",
1292 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
1293 	     21, 0, 0),
1294 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK,
1295 	     "gout_fsys0_pcie_gen3_4l_x4_slv_aclk", "mout_fsys0_bus_user",
1296 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
1297 	     21, 0, 0),
1298 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK,
1299 	     "gout_fsys0_pcie_gen3a_4l_clk", "mout_fsys0_pcie_user",
1300 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
1301 	     21, 0, 0),
1302 	GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK,
1303 	     "gout_fsys0_pcie_gen3b_4l_clk", "mout_fsys0_pcie_user",
1304 	     CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
1305 	     21, 0, 0),
1306 };
1307 
1308 static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
1309 	.mux_clks		= fsys0_mux_clks,
1310 	.nr_mux_clks		= ARRAY_SIZE(fsys0_mux_clks),
1311 	.gate_clks		= fsys0_gate_clks,
1312 	.nr_gate_clks		= ARRAY_SIZE(fsys0_gate_clks),
1313 	.nr_clk_ids		= CLKS_NR_FSYS0,
1314 	.clk_regs		= fsys0_clk_regs,
1315 	.nr_clk_regs		= ARRAY_SIZE(fsys0_clk_regs),
1316 	.clk_name		= "dout_clkcmu_fsys0_bus",
1317 };
1318 
1319 /* ---- CMU_FSYS1 ---------------------------------------------------------- */
1320 
1321 /* Register Offset definitions for CMU_FSYS1 (0x17040000) */
1322 #define PLL_LOCKTIME_PLL_MMC			0x0000
1323 #define PLL_CON0_PLL_MMC			0x0100
1324 #define PLL_CON3_PLL_MMC			0x010c
1325 #define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER	0x0600
1326 #define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER	0x0610
1327 #define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER	0x0620
1328 
1329 #define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD	0x1000
1330 #define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD	0x1800
1331 
1332 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK	0x2018
1333 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN	0x202c
1334 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK	0x2028
1335 
1336 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40		0x204c
1337 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40		0x2058
1338 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40		0x2064
1339 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40		0x2070
1340 
1341 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK	0x2074
1342 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK	0x2078
1343 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK	0x207c
1344 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK	0x2080
1345 
1346 static const unsigned long fsys1_clk_regs[] __initconst = {
1347 	PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
1348 };
1349 
1350 static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = {
1351 	PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
1352 	    PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
1353 };
1354 
1355 /* List of parent clocks for Muxes in CMU_FSYS1 */
1356 PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" };
1357 PNAME(mout_fsys1_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
1358 PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" };
1359 PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" };
1360 PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user",
1361 				 "mout_fsys1_mmc_pll" };
1362 
1363 static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
1364 	MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
1365 	    mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1),
1366 	MUX(CLK_MOUT_FSYS1_MMC_PLL, "mout_fsys1_mmc_pll", mout_fsys1_mmc_pll_p,
1367 	    PLL_CON0_PLL_MMC, 4, 1),
1368 	MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user",
1369 	    mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
1370 	    4, 1),
1371 	MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user",
1372 	    mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER,
1373 	    4, 1),
1374 	MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card",
1375 	    mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD,
1376 	    0, 1),
1377 };
1378 
1379 static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
1380 	DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card",
1381 	    "mout_fsys1_mmc_card",
1382 	    CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
1383 };
1384 
1385 static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
1386 	GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user",
1387 	     CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
1388 	     21, CLK_IGNORE_UNUSED, 0),
1389 	GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
1390 	     "dout_fsys1_mmc_card",
1391 	     CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
1392 	     21, CLK_SET_RATE_PARENT, 0),
1393 	GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk",
1394 	     "dout_fsys1_mmc_card",
1395 	     CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
1396 	     21, 0, 0),
1397 	GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk",
1398 	     "mout_fsys1_usbdrd_user",
1399 	     CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40,
1400 	     21, 0, 0),
1401 	GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk",
1402 	     "mout_fsys1_usbdrd_user",
1403 	     CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40,
1404 	     21, 0, 0),
1405 	GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk",
1406 	     "mout_fsys1_usbdrd_user",
1407 	     CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40,
1408 	     21, 0, 0),
1409 	GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk",
1410 	     "mout_fsys1_usbdrd_user",
1411 	     CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40,
1412 	     21, 0, 0),
1413 	GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk",
1414 	     "mout_fsys1_usbdrd_user",
1415 	     CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK,
1416 	     21, 0, 0),
1417 	GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk",
1418 	     "mout_fsys1_usbdrd_user",
1419 	     CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK,
1420 	     21, 0, 0),
1421 	GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk",
1422 	     "mout_fsys1_usbdrd_user",
1423 	     CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK,
1424 	     21, 0, 0),
1425 	GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk",
1426 	     "mout_fsys1_usbdrd_user",
1427 	     CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK,
1428 	     21, 0, 0),
1429 };
1430 
1431 static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
1432 	.pll_clks		= fsys1_pll_clks,
1433 	.nr_pll_clks		= ARRAY_SIZE(fsys1_pll_clks),
1434 	.mux_clks		= fsys1_mux_clks,
1435 	.nr_mux_clks		= ARRAY_SIZE(fsys1_mux_clks),
1436 	.div_clks		= fsys1_div_clks,
1437 	.nr_div_clks		= ARRAY_SIZE(fsys1_div_clks),
1438 	.gate_clks		= fsys1_gate_clks,
1439 	.nr_gate_clks		= ARRAY_SIZE(fsys1_gate_clks),
1440 	.nr_clk_ids		= CLKS_NR_FSYS1,
1441 	.clk_regs		= fsys1_clk_regs,
1442 	.nr_clk_regs		= ARRAY_SIZE(fsys1_clk_regs),
1443 	.clk_name		= "dout_clkcmu_fsys1_bus",
1444 };
1445 
1446 /* ---- CMU_FSYS2 ---------------------------------------------------------- */
1447 
1448 /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
1449 #define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER	0x0600
1450 #define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER	0x0620
1451 #define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER	0x0610
1452 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK	0x2098
1453 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO	0x209c
1454 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK	0x20a4
1455 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO	0x20a8
1456 
1457 static const unsigned long fsys2_clk_regs[] __initconst = {
1458 	PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER,
1459 	PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER,
1460 	PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER,
1461 	CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK,
1462 	CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO,
1463 	CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK,
1464 	CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO,
1465 };
1466 
1467 /* List of parent clocks for Muxes in CMU_FSYS2 */
1468 PNAME(mout_fsys2_bus_user_p) = { "oscclk", "dout_clkcmu_fsys2_bus" };
1469 PNAME(mout_fsys2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_fsys2_ufs_embd" };
1470 PNAME(mout_fsys2_ethernet_user_p) = { "oscclk", "dout_clkcmu_fsys2_ethernet" };
1471 
1472 static const struct samsung_mux_clock fsys2_mux_clks[] __initconst = {
1473 	MUX(CLK_MOUT_FSYS2_BUS_USER, "mout_fsys2_bus_user",
1474 	    mout_fsys2_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER, 4, 1),
1475 	MUX(CLK_MOUT_FSYS2_UFS_EMBD_USER, "mout_fsys2_ufs_embd_user",
1476 	    mout_fsys2_ufs_embd_user_p,
1477 	    PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER, 4, 1),
1478 	MUX(CLK_MOUT_FSYS2_ETHERNET_USER, "mout_fsys2_ethernet_user",
1479 	    mout_fsys2_ethernet_user_p,
1480 	    PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER, 4, 1),
1481 };
1482 
1483 static const struct samsung_gate_clock fsys2_gate_clks[] __initconst = {
1484 	GATE(CLK_GOUT_FSYS2_UFS_EMBD0_ACLK, "gout_fsys2_ufs_embd0_aclk",
1485 	     "mout_fsys2_ufs_embd_user",
1486 	     CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK, 21,
1487 	     0, 0),
1488 	GATE(CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO, "gout_fsys2_ufs_embd0_unipro",
1489 	     "mout_fsys2_ufs_embd_user",
1490 	     CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO,
1491 	     21, 0, 0),
1492 	GATE(CLK_GOUT_FSYS2_UFS_EMBD1_ACLK, "gout_fsys2_ufs_embd1_aclk",
1493 	     "mout_fsys2_ufs_embd_user",
1494 	     CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK, 21,
1495 	     0, 0),
1496 	GATE(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO, "gout_fsys2_ufs_embd1_unipro",
1497 	     "mout_fsys2_ufs_embd_user",
1498 	     CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO,
1499 	     21, 0, 0),
1500 };
1501 
1502 static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
1503 	.mux_clks		= fsys2_mux_clks,
1504 	.nr_mux_clks		= ARRAY_SIZE(fsys2_mux_clks),
1505 	.gate_clks		= fsys2_gate_clks,
1506 	.nr_gate_clks		= ARRAY_SIZE(fsys2_gate_clks),
1507 	.nr_clk_ids		= CLKS_NR_FSYS2,
1508 	.clk_regs		= fsys2_clk_regs,
1509 	.nr_clk_regs		= ARRAY_SIZE(fsys2_clk_regs),
1510 	.clk_name		= "dout_clkcmu_fsys2_bus",
1511 };
1512 
1513 /* ---- CMU_PERIC0 --------------------------------------------------------- */
1514 
1515 /* Register Offset definitions for CMU_PERIC0 (0x10200000) */
1516 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER	0x0600
1517 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER	0x0610
1518 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI	0x1000
1519 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI	0x1004
1520 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI	0x1008
1521 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI	0x100c
1522 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI	0x1010
1523 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI	0x1014
1524 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C	0x1018
1525 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI	0x1800
1526 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI	0x1804
1527 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI	0x1808
1528 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI	0x180c
1529 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI	0x1810
1530 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI	0x1814
1531 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C	0x1818
1532 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0	0x2014
1533 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1	0x2018
1534 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2	0x2024
1535 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3	0x2028
1536 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4	0x202c
1537 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5	0x2030
1538 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6	0x2034
1539 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7	0x2038
1540 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8	0x203c
1541 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9	0x2040
1542 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10	0x201c
1543 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11	0x2020
1544 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0	0x2044
1545 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1	0x2048
1546 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2	0x2058
1547 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3	0x205c
1548 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4	0x2060
1549 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5	0x2064
1550 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6	0x2068
1551 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7	0x206c
1552 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8	0x2070
1553 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9	0x2074
1554 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10	0x204c
1555 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11	0x2050
1556 
1557 static const unsigned long peric0_clk_regs[] __initconst = {
1558 	PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
1559 	PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,
1560 	CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,
1561 	CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,
1562 	CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,
1563 	CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,
1564 	CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,
1565 	CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,
1566 	CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,
1567 	CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1568 	CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1569 	CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1570 	CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1571 	CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1572 	CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1573 	CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1574 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
1575 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
1576 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
1577 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
1578 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1579 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1580 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1581 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1582 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1583 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1584 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1585 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1586 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
1587 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
1588 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
1589 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
1590 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1591 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1592 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1593 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1594 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1595 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1596 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1597 	CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1598 };
1599 
1600 /* List of parent clocks for Muxes in CMU_PERIC0 */
1601 PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_clkcmu_peric0_bus" };
1602 PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" };
1603 PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" };
1604 
1605 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
1606 	MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
1607 	    mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
1608 	MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user",
1609 	    mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1),
1610 	/* USI00 ~ USI05 */
1611 	MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi",
1612 	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1613 	MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi",
1614 	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1615 	MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi",
1616 	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1617 	MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi",
1618 	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1619 	MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi",
1620 	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1621 	MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi",
1622 	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1623 	/* USI_I2C */
1624 	MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c",
1625 	    mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1626 };
1627 
1628 static const struct samsung_div_clock peric0_div_clks[] __initconst = {
1629 	/* USI00 ~ USI05 */
1630 	DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
1631 	    "mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1632 	    0, 4),
1633 	DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
1634 	    "mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1635 	    0, 4),
1636 	DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
1637 	    "mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1638 	    0, 4),
1639 	DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
1640 	    "mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1641 	    0, 4),
1642 	DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
1643 	    "mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1644 	    0, 4),
1645 	DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
1646 	    "mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1647 	    0, 4),
1648 	/* USI_I2C */
1649 	DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
1650 	    "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1651 };
1652 
1653 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
1654 	/* IPCLK */
1655 	GATE(CLK_GOUT_PERIC0_IPCLK_0, "gout_peric0_ipclk_0",
1656 	     "dout_peric0_usi00_usi",
1657 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
1658 	     21, 0, 0),
1659 	GATE(CLK_GOUT_PERIC0_IPCLK_1, "gout_peric0_ipclk_1",
1660 	     "dout_peric0_usi_i2c",
1661 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
1662 	     21, 0, 0),
1663 	GATE(CLK_GOUT_PERIC0_IPCLK_2, "gout_peric0_ipclk_2",
1664 	     "dout_peric0_usi01_usi",
1665 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
1666 	     21, 0, 0),
1667 	GATE(CLK_GOUT_PERIC0_IPCLK_3, "gout_peric0_ipclk_3",
1668 	     "dout_peric0_usi_i2c",
1669 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
1670 	     21, 0, 0),
1671 	GATE(CLK_GOUT_PERIC0_IPCLK_4, "gout_peric0_ipclk_4",
1672 	     "dout_peric0_usi02_usi",
1673 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1674 	     21, 0, 0),
1675 	GATE(CLK_GOUT_PERIC0_IPCLK_5, "gout_peric0_ipclk_5",
1676 	     "dout_peric0_usi_i2c",
1677 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1678 	     21, 0, 0),
1679 	GATE(CLK_GOUT_PERIC0_IPCLK_6, "gout_peric0_ipclk_6",
1680 	     "dout_peric0_usi03_usi",
1681 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1682 	     21, 0, 0),
1683 	GATE(CLK_GOUT_PERIC0_IPCLK_7, "gout_peric0_ipclk_7",
1684 	     "dout_peric0_usi_i2c",
1685 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1686 	     21, 0, 0),
1687 	GATE(CLK_GOUT_PERIC0_IPCLK_8, "gout_peric0_ipclk_8",
1688 	     "dout_peric0_usi04_usi",
1689 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1690 	     21, 0, 0),
1691 	GATE(CLK_GOUT_PERIC0_IPCLK_9, "gout_peric0_ipclk_9",
1692 	     "dout_peric0_usi_i2c",
1693 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1694 	     21, 0, 0),
1695 	GATE(CLK_GOUT_PERIC0_IPCLK_10, "gout_peric0_ipclk_10",
1696 	     "dout_peric0_usi05_usi",
1697 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1698 	     21, 0, 0),
1699 	GATE(CLK_GOUT_PERIC0_IPCLK_11, "gout_peric0_ipclk_11",
1700 	     "dout_peric0_usi_i2c",
1701 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1702 	     21, 0, 0),
1703 
1704 	/* PCLK */
1705 	GATE(CLK_GOUT_PERIC0_PCLK_0, "gout_peric0_pclk_0",
1706 	     "mout_peric0_bus_user",
1707 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
1708 	     21, 0, 0),
1709 	GATE(CLK_GOUT_PERIC0_PCLK_1, "gout_peric0_pclk_1",
1710 	     "mout_peric0_bus_user",
1711 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
1712 	     21, 0, 0),
1713 	GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",
1714 	     "mout_peric0_bus_user",
1715 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
1716 	     21, 0, 0),
1717 	GATE(CLK_GOUT_PERIC0_PCLK_3, "gout_peric0_pclk_3",
1718 	     "mout_peric0_bus_user",
1719 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
1720 	     21, 0, 0),
1721 	GATE(CLK_GOUT_PERIC0_PCLK_4, "gout_peric0_pclk_4",
1722 	     "mout_peric0_bus_user",
1723 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1724 	     21, 0, 0),
1725 	GATE(CLK_GOUT_PERIC0_PCLK_5, "gout_peric0_pclk_5",
1726 	     "mout_peric0_bus_user",
1727 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1728 	     21, 0, 0),
1729 	GATE(CLK_GOUT_PERIC0_PCLK_6, "gout_peric0_pclk_6",
1730 	     "mout_peric0_bus_user",
1731 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1732 	     21, 0, 0),
1733 	GATE(CLK_GOUT_PERIC0_PCLK_7, "gout_peric0_pclk_7",
1734 	     "mout_peric0_bus_user",
1735 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1736 	     21, 0, 0),
1737 	GATE(CLK_GOUT_PERIC0_PCLK_8, "gout_peric0_pclk_8",
1738 	     "mout_peric0_bus_user",
1739 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1740 	     21, 0, 0),
1741 	GATE(CLK_GOUT_PERIC0_PCLK_9, "gout_peric0_pclk_9",
1742 	     "mout_peric0_bus_user",
1743 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1744 	     21, 0, 0),
1745 	GATE(CLK_GOUT_PERIC0_PCLK_10, "gout_peric0_pclk_10",
1746 	     "mout_peric0_bus_user",
1747 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1748 	     21, 0, 0),
1749 	GATE(CLK_GOUT_PERIC0_PCLK_11, "gout_peric0_pclk_11",
1750 	     "mout_peric0_bus_user",
1751 	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1752 	     21, 0, 0),
1753 };
1754 
1755 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
1756 	.mux_clks		= peric0_mux_clks,
1757 	.nr_mux_clks		= ARRAY_SIZE(peric0_mux_clks),
1758 	.div_clks		= peric0_div_clks,
1759 	.nr_div_clks		= ARRAY_SIZE(peric0_div_clks),
1760 	.gate_clks		= peric0_gate_clks,
1761 	.nr_gate_clks		= ARRAY_SIZE(peric0_gate_clks),
1762 	.nr_clk_ids		= CLKS_NR_PERIC0,
1763 	.clk_regs		= peric0_clk_regs,
1764 	.nr_clk_regs		= ARRAY_SIZE(peric0_clk_regs),
1765 	.clk_name		= "dout_clkcmu_peric0_bus",
1766 };
1767 
1768 /* ---- CMU_PERIC1 --------------------------------------------------------- */
1769 
1770 /* Register Offset definitions for CMU_PERIC1 (0x10800000) */
1771 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER	0x0600
1772 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER	0x0610
1773 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI	0x1000
1774 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI	0x1004
1775 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI	0x1008
1776 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI	0x100c
1777 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI	0x1010
1778 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI	0x1014
1779 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C	0x1018
1780 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI	0x1800
1781 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI	0x1804
1782 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI	0x1808
1783 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI	0x180c
1784 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI	0x1810
1785 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI	0x1814
1786 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C	0x1818
1787 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0	0x2014
1788 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1	0x2018
1789 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2	0x2024
1790 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3	0x2028
1791 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4	0x202c
1792 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5	0x2030
1793 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6	0x2034
1794 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7	0x2038
1795 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8	0x203c
1796 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9	0x2040
1797 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10	0x201c
1798 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11	0x2020
1799 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0	0x2044
1800 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1	0x2048
1801 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2	0x2054
1802 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3	0x2058
1803 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4	0x205c
1804 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5	0x2060
1805 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6	0x2064
1806 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7	0x2068
1807 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8	0x206c
1808 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9	0x2070
1809 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10	0x204c
1810 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11	0x2050
1811 
1812 static const unsigned long peric1_clk_regs[] __initconst = {
1813 	PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
1814 	PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
1815 	CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI,
1816 	CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI,
1817 	CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI,
1818 	CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
1819 	CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
1820 	CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
1821 	CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
1822 	CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
1823 	CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
1824 	CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
1825 	CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1826 	CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1827 	CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1828 	CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
1829 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0,
1830 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
1831 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
1832 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
1833 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
1834 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
1835 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
1836 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7,
1837 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
1838 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9,
1839 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
1840 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
1841 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
1842 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
1843 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
1844 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
1845 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
1846 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
1847 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
1848 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
1849 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
1850 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
1851 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
1852 	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
1853 };
1854 
1855 /* List of parent clocks for Muxes in CMU_PERIC1 */
1856 PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_clkcmu_peric1_bus" };
1857 PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
1858 PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
1859 
1860 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
1861 	MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
1862 	    mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
1863 	MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
1864 	    mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
1865 	/* USI06 ~ USI11 */
1866 	MUX(CLK_MOUT_PERIC1_USI06_USI, "mout_peric1_usi06_usi",
1867 	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI, 0, 1),
1868 	MUX(CLK_MOUT_PERIC1_USI07_USI, "mout_peric1_usi07_usi",
1869 	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI, 0, 1),
1870 	MUX(CLK_MOUT_PERIC1_USI08_USI, "mout_peric1_usi08_usi",
1871 	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI, 0, 1),
1872 	MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
1873 	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
1874 	MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
1875 	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
1876 	MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
1877 	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
1878 	/* USI_I2C */
1879 	MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
1880 	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
1881 };
1882 
1883 static const struct samsung_div_clock peric1_div_clks[] __initconst = {
1884 	/* USI06 ~ USI11 */
1885 	DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi",
1886 	    "mout_peric1_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
1887 	    0, 4),
1888 	DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi",
1889 	    "mout_peric1_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
1890 	    0, 4),
1891 	DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi",
1892 	    "mout_peric1_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
1893 	    0, 4),
1894 	DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
1895 	    "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1896 	    0, 4),
1897 	DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
1898 	    "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1899 	    0, 4),
1900 	DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
1901 	    "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1902 	    0, 4),
1903 	/* USI_I2C */
1904 	DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
1905 	    "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
1906 };
1907 
1908 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
1909 	/* IPCLK */
1910 	GATE(CLK_GOUT_PERIC1_IPCLK_0, "gout_peric1_ipclk_0",
1911 	     "dout_peric1_usi06_usi",
1912 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0,
1913 	     21, 0, 0),
1914 	GATE(CLK_GOUT_PERIC1_IPCLK_1, "gout_peric1_ipclk_1",
1915 	     "dout_peric1_usi_i2c",
1916 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
1917 	     21, 0, 0),
1918 	GATE(CLK_GOUT_PERIC1_IPCLK_2, "gout_peric1_ipclk_2",
1919 	     "dout_peric1_usi07_usi",
1920 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
1921 	     21, 0, 0),
1922 	GATE(CLK_GOUT_PERIC1_IPCLK_3, "gout_peric1_ipclk_3",
1923 	     "dout_peric1_usi_i2c",
1924 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
1925 	     21, 0, 0),
1926 	GATE(CLK_GOUT_PERIC1_IPCLK_4, "gout_peric1_ipclk_4",
1927 	     "dout_peric1_usi08_usi",
1928 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
1929 	     21, 0, 0),
1930 	GATE(CLK_GOUT_PERIC1_IPCLK_5, "gout_peric1_ipclk_5",
1931 	     "dout_peric1_usi_i2c",
1932 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
1933 	     21, 0, 0),
1934 	GATE(CLK_GOUT_PERIC1_IPCLK_6, "gout_peric1_ipclk_6",
1935 	     "dout_peric1_usi09_usi",
1936 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
1937 	     21, 0, 0),
1938 	GATE(CLK_GOUT_PERIC1_IPCLK_7, "gout_peric1_ipclk_7",
1939 	     "dout_peric1_usi_i2c",
1940 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7,
1941 	     21, 0, 0),
1942 	GATE(CLK_GOUT_PERIC1_IPCLK_8, "gout_peric1_ipclk_8",
1943 	     "dout_peric1_usi10_usi",
1944 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
1945 	     21, 0, 0),
1946 	GATE(CLK_GOUT_PERIC1_IPCLK_9, "gout_peric1_ipclk_9",
1947 	     "dout_peric1_usi_i2c",
1948 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9,
1949 	     21, 0, 0),
1950 	GATE(CLK_GOUT_PERIC1_IPCLK_10, "gout_peric1_ipclk_10",
1951 	     "dout_peric1_usi11_usi",
1952 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
1953 	     21, 0, 0),
1954 	GATE(CLK_GOUT_PERIC1_IPCLK_11, "gout_peric1_ipclk_11",
1955 	     "dout_peric1_usi_i2c",
1956 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
1957 	     21, 0, 0),
1958 
1959 	/* PCLK */
1960 	GATE(CLK_GOUT_PERIC1_PCLK_0, "gout_peric1_pclk_0",
1961 	     "mout_peric1_bus_user",
1962 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
1963 	     21, 0, 0),
1964 	GATE(CLK_GOUT_PERIC1_PCLK_1, "gout_peric1_pclk_1",
1965 	     "mout_peric1_bus_user",
1966 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
1967 	     21, 0, 0),
1968 	GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2",
1969 	     "mout_peric1_bus_user",
1970 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
1971 	     21, 0, 0),
1972 	GATE(CLK_GOUT_PERIC1_PCLK_3, "gout_peric1_pclk_3",
1973 	     "mout_peric1_bus_user",
1974 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
1975 	     21, 0, 0),
1976 	GATE(CLK_GOUT_PERIC1_PCLK_4, "gout_peric1_pclk_4",
1977 	     "mout_peric1_bus_user",
1978 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
1979 	     21, 0, 0),
1980 	GATE(CLK_GOUT_PERIC1_PCLK_5, "gout_peric1_pclk_5",
1981 	     "mout_peric1_bus_user",
1982 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
1983 	     21, 0, 0),
1984 	GATE(CLK_GOUT_PERIC1_PCLK_6, "gout_peric1_pclk_6",
1985 	     "mout_peric1_bus_user",
1986 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
1987 	     21, 0, 0),
1988 	GATE(CLK_GOUT_PERIC1_PCLK_7, "gout_peric1_pclk_7",
1989 	     "mout_peric1_bus_user",
1990 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
1991 	     21, 0, 0),
1992 	GATE(CLK_GOUT_PERIC1_PCLK_8, "gout_peric1_pclk_8",
1993 	     "mout_peric1_bus_user",
1994 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
1995 	     21, 0, 0),
1996 	GATE(CLK_GOUT_PERIC1_PCLK_9, "gout_peric1_pclk_9",
1997 	     "mout_peric1_bus_user",
1998 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
1999 	     21, 0, 0),
2000 	GATE(CLK_GOUT_PERIC1_PCLK_10, "gout_peric1_pclk_10",
2001 	     "mout_peric1_bus_user",
2002 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
2003 	     21, 0, 0),
2004 	GATE(CLK_GOUT_PERIC1_PCLK_11, "gout_peric1_pclk_11",
2005 	     "mout_peric1_bus_user",
2006 	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
2007 	     21, 0, 0),
2008 };
2009 
2010 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
2011 	.mux_clks		= peric1_mux_clks,
2012 	.nr_mux_clks		= ARRAY_SIZE(peric1_mux_clks),
2013 	.div_clks		= peric1_div_clks,
2014 	.nr_div_clks		= ARRAY_SIZE(peric1_div_clks),
2015 	.gate_clks		= peric1_gate_clks,
2016 	.nr_gate_clks		= ARRAY_SIZE(peric1_gate_clks),
2017 	.nr_clk_ids		= CLKS_NR_PERIC1,
2018 	.clk_regs		= peric1_clk_regs,
2019 	.nr_clk_regs		= ARRAY_SIZE(peric1_clk_regs),
2020 	.clk_name		= "dout_clkcmu_peric1_bus",
2021 };
2022 
2023 /* ---- CMU_PERIS ---------------------------------------------------------- */
2024 
2025 /* Register Offset definitions for CMU_PERIS (0x10020000) */
2026 #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER	0x0600
2027 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK	0x2058
2028 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK	0x205c
2029 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK	0x2060
2030 
2031 static const unsigned long peris_clk_regs[] __initconst = {
2032 	PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
2033 	CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
2034 	CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
2035 	CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
2036 };
2037 
2038 /* List of parent clocks for Muxes in CMU_PERIS */
2039 PNAME(mout_peris_bus_user_p) = { "oscclk", "dout_clkcmu_peris_bus" };
2040 
2041 static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
2042 	MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",
2043 	    mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, 4, 1),
2044 };
2045 
2046 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
2047 	GATE(CLK_GOUT_SYSREG_PERIS_PCLK, "gout_sysreg_peris_pclk",
2048 	     "mout_peris_bus_user",
2049 	     CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
2050 	     21, CLK_IGNORE_UNUSED, 0),
2051 	GATE(CLK_GOUT_WDT_CLUSTER0, "gout_wdt_cluster0", "mout_peris_bus_user",
2052 	     CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
2053 	     21, 0, 0),
2054 	GATE(CLK_GOUT_WDT_CLUSTER1, "gout_wdt_cluster1", "mout_peris_bus_user",
2055 	     CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
2056 	     21, 0, 0),
2057 };
2058 
2059 static const struct samsung_cmu_info peris_cmu_info __initconst = {
2060 	.mux_clks		= peris_mux_clks,
2061 	.nr_mux_clks		= ARRAY_SIZE(peris_mux_clks),
2062 	.gate_clks		= peris_gate_clks,
2063 	.nr_gate_clks		= ARRAY_SIZE(peris_gate_clks),
2064 	.nr_clk_ids		= CLKS_NR_PERIS,
2065 	.clk_regs		= peris_clk_regs,
2066 	.nr_clk_regs		= ARRAY_SIZE(peris_clk_regs),
2067 	.clk_name		= "dout_clkcmu_peris_bus",
2068 };
2069 
2070 static int __init exynosautov9_cmu_probe(struct platform_device *pdev)
2071 {
2072 	const struct samsung_cmu_info *info;
2073 	struct device *dev = &pdev->dev;
2074 
2075 	info = of_device_get_match_data(dev);
2076 	exynos_arm64_register_cmu(dev, dev->of_node, info);
2077 
2078 	return 0;
2079 }
2080 
2081 static const struct of_device_id exynosautov9_cmu_of_match[] = {
2082 	{
2083 		.compatible = "samsung,exynosautov9-cmu-busmc",
2084 		.data = &busmc_cmu_info,
2085 	}, {
2086 		.compatible = "samsung,exynosautov9-cmu-core",
2087 		.data = &core_cmu_info,
2088 	}, {
2089 		.compatible = "samsung,exynosautov9-cmu-fsys0",
2090 		.data = &fsys0_cmu_info,
2091 	}, {
2092 		.compatible = "samsung,exynosautov9-cmu-fsys1",
2093 		.data = &fsys1_cmu_info,
2094 	}, {
2095 		.compatible = "samsung,exynosautov9-cmu-fsys2",
2096 		.data = &fsys2_cmu_info,
2097 	}, {
2098 		.compatible = "samsung,exynosautov9-cmu-peric0",
2099 		.data = &peric0_cmu_info,
2100 	}, {
2101 		.compatible = "samsung,exynosautov9-cmu-peric1",
2102 		.data = &peric1_cmu_info,
2103 	}, {
2104 		.compatible = "samsung,exynosautov9-cmu-peris",
2105 		.data = &peris_cmu_info,
2106 	}, {
2107 	},
2108 };
2109 
2110 static struct platform_driver exynosautov9_cmu_driver __refdata = {
2111 	.driver = {
2112 		.name = "exynosautov9-cmu",
2113 		.of_match_table = exynosautov9_cmu_of_match,
2114 		.suppress_bind_attrs = true,
2115 	},
2116 	.probe = exynosautov9_cmu_probe,
2117 };
2118 
2119 static int __init exynosautov9_cmu_init(void)
2120 {
2121 	return platform_driver_register(&exynosautov9_cmu_driver);
2122 }
2123 core_initcall(exynosautov9_cmu_init);
2124