1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021 Linaro Ltd. 4 * Author: Sam Protsenko <semen.protsenko@linaro.org> 5 * 6 * Common Clock Framework support for Exynos850 SoC. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 15 #include <dt-bindings/clock/exynos850.h> 16 17 #include "clk.h" 18 #include "clk-exynos-arm64.h" 19 20 /* ---- CMU_TOP ------------------------------------------------------------- */ 21 22 /* Register Offset definitions for CMU_TOP (0x120e0000) */ 23 #define PLL_LOCKTIME_PLL_MMC 0x0000 24 #define PLL_LOCKTIME_PLL_SHARED0 0x0004 25 #define PLL_LOCKTIME_PLL_SHARED1 0x0008 26 #define PLL_CON0_PLL_MMC 0x0100 27 #define PLL_CON3_PLL_MMC 0x010c 28 #define PLL_CON0_PLL_SHARED0 0x0140 29 #define PLL_CON3_PLL_SHARED0 0x014c 30 #define PLL_CON0_PLL_SHARED1 0x0180 31 #define PLL_CON3_PLL_SHARED1 0x018c 32 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000 33 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 34 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 35 #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c 36 #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 37 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 38 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c 39 #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 40 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 41 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 42 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 43 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 44 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c 45 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 46 #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 47 #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 48 #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c 49 #define CLK_CON_DIV_CLKCMU_DPU 0x1840 50 #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 51 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c 52 #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 53 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c 54 #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 55 #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 56 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c 57 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 58 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 59 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 60 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c 61 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 62 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008 63 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 64 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 65 #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 66 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 67 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c 68 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 69 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 70 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c 71 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 72 #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 73 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 74 75 static const unsigned long top_clk_regs[] __initconst = { 76 PLL_LOCKTIME_PLL_MMC, 77 PLL_LOCKTIME_PLL_SHARED0, 78 PLL_LOCKTIME_PLL_SHARED1, 79 PLL_CON0_PLL_MMC, 80 PLL_CON3_PLL_MMC, 81 PLL_CON0_PLL_SHARED0, 82 PLL_CON3_PLL_SHARED0, 83 PLL_CON0_PLL_SHARED1, 84 PLL_CON3_PLL_SHARED1, 85 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 86 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 87 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 88 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 89 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 90 CLK_CON_MUX_MUX_CLKCMU_DPU, 91 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 92 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 93 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 94 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 95 CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 96 CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 97 CLK_CON_DIV_CLKCMU_APM_BUS, 98 CLK_CON_DIV_CLKCMU_CORE_BUS, 99 CLK_CON_DIV_CLKCMU_CORE_CCI, 100 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 101 CLK_CON_DIV_CLKCMU_CORE_SSS, 102 CLK_CON_DIV_CLKCMU_DPU, 103 CLK_CON_DIV_CLKCMU_HSI_BUS, 104 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 105 CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 106 CLK_CON_DIV_CLKCMU_PERI_BUS, 107 CLK_CON_DIV_CLKCMU_PERI_IP, 108 CLK_CON_DIV_CLKCMU_PERI_UART, 109 CLK_CON_DIV_PLL_SHARED0_DIV2, 110 CLK_CON_DIV_PLL_SHARED0_DIV3, 111 CLK_CON_DIV_PLL_SHARED0_DIV4, 112 CLK_CON_DIV_PLL_SHARED1_DIV2, 113 CLK_CON_DIV_PLL_SHARED1_DIV3, 114 CLK_CON_DIV_PLL_SHARED1_DIV4, 115 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 116 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 117 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 118 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 119 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 120 CLK_CON_GAT_GATE_CLKCMU_DPU, 121 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 122 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 123 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 124 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 125 CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 126 CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 127 }; 128 129 /* 130 * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set 131 * for those PLLs by default, so set_rate operation would fail. 132 */ 133 static const struct samsung_pll_clock top_pll_clks[] __initconst = { 134 /* CMU_TOP_PURECLKCOMP */ 135 PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 136 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 137 NULL), 138 PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 139 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 140 NULL), 141 PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 142 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 143 }; 144 145 /* List of parent clocks for Muxes in CMU_TOP */ 146 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 147 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 148 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 149 /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */ 150 PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" }; 151 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 152 PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", 153 "dout_shared1_div3", "dout_shared0_div4" }; 154 PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 155 "dout_shared0_div3", "dout_shared1_div3" }; 156 PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", 157 "dout_shared1_div2", "dout_shared0_div3", 158 "dout_shared1_div3", "mout_mmc_pll", 159 "oscclk", "oscclk" }; 160 PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", 161 "dout_shared0_div4", "dout_shared1_div4" }; 162 /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ 163 PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 164 PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", 165 "dout_shared1_div2", "dout_shared0_div3", 166 "dout_shared1_div3", "mout_mmc_pll", 167 "oscclk", "oscclk" }; 168 PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4", 169 "dout_shared1_div4", "oscclk" }; 170 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 171 PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 172 PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4", 173 "dout_shared1_div4", "oscclk" }; 174 PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4", 175 "dout_shared1_div4", "oscclk" }; 176 /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ 177 PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3", 178 "dout_shared0_div4", "dout_shared1_div4" }; 179 180 static const struct samsung_mux_clock top_mux_clks[] __initconst = { 181 /* CMU_TOP_PURECLKCOMP */ 182 MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 183 PLL_CON0_PLL_SHARED0, 4, 1), 184 MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 185 PLL_CON0_PLL_SHARED1, 4, 1), 186 MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 187 PLL_CON0_PLL_MMC, 4, 1), 188 189 /* APM */ 190 MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", 191 mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), 192 193 /* CORE */ 194 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 195 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 196 MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 197 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 198 MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, 199 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), 200 MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, 201 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), 202 203 /* DPU */ 204 MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, 205 CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), 206 207 /* HSI */ 208 MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, 209 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), 210 MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, 211 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), 212 MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, 213 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), 214 215 /* PERI */ 216 MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 217 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 218 MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, 219 CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), 220 MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, 221 CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), 222 }; 223 224 static const struct samsung_div_clock top_div_clks[] __initconst = { 225 /* CMU_TOP_PURECLKCOMP */ 226 DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 227 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 228 DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 229 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 230 DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 231 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 232 DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 233 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 234 DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 235 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 236 DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 237 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 238 239 /* APM */ 240 DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", 241 "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), 242 243 /* CORE */ 244 DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 245 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 246 DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 247 CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), 248 DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", 249 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), 250 DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", 251 CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), 252 253 /* DPU */ 254 DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", 255 CLK_CON_DIV_CLKCMU_DPU, 0, 4), 256 257 /* HSI */ 258 DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", 259 CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), 260 DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", 261 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), 262 DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", 263 CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), 264 265 /* PERI */ 266 DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 267 CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 268 DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", 269 CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), 270 DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", 271 CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), 272 }; 273 274 static const struct samsung_gate_clock top_gate_clks[] __initconst = { 275 /* CORE */ 276 GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 277 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 278 GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 279 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 280 GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", 281 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), 282 GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", 283 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), 284 285 /* APM */ 286 GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", 287 "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0), 288 289 /* DPU */ 290 GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", 291 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), 292 293 /* HSI */ 294 GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", 295 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), 296 GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", 297 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), 298 GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", 299 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), 300 301 /* PERI */ 302 GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 303 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 304 GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", 305 CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), 306 GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", 307 CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), 308 }; 309 310 static const struct samsung_cmu_info top_cmu_info __initconst = { 311 .pll_clks = top_pll_clks, 312 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 313 .mux_clks = top_mux_clks, 314 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 315 .div_clks = top_div_clks, 316 .nr_div_clks = ARRAY_SIZE(top_div_clks), 317 .gate_clks = top_gate_clks, 318 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 319 .nr_clk_ids = TOP_NR_CLK, 320 .clk_regs = top_clk_regs, 321 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 322 }; 323 324 static void __init exynos850_cmu_top_init(struct device_node *np) 325 { 326 exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 327 } 328 329 /* Register CMU_TOP early, as it's a dependency for other early domains */ 330 CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", 331 exynos850_cmu_top_init); 332 333 /* ---- CMU_APM ------------------------------------------------------------- */ 334 335 /* Register Offset definitions for CMU_APM (0x11800000) */ 336 #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600 337 #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610 338 #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620 339 #define PLL_CON0_MUX_DLL_USER 0x0630 340 #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000 341 #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004 342 #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008 343 #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800 344 #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804 345 #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808 346 #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 347 #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014 348 #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018 349 #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020 350 #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024 351 #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028 352 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034 353 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038 354 #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc 355 #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0 356 357 static const unsigned long apm_clk_regs[] __initconst = { 358 PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 359 PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 360 PLL_CON0_MUX_CLK_RCO_APM_USER, 361 PLL_CON0_MUX_DLL_USER, 362 CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 363 CLK_CON_MUX_MUX_CLK_APM_BUS, 364 CLK_CON_MUX_MUX_CLK_APM_I3C, 365 CLK_CON_DIV_CLKCMU_CHUB_BUS, 366 CLK_CON_DIV_DIV_CLK_APM_BUS, 367 CLK_CON_DIV_DIV_CLK_APM_I3C, 368 CLK_CON_GAT_CLKCMU_CMGP_BUS, 369 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 370 CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 371 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 372 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 373 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 374 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 375 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 376 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 377 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 378 }; 379 380 /* List of parent clocks for Muxes in CMU_APM */ 381 PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" }; 382 PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" }; 383 PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" }; 384 PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" }; 385 PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" }; 386 PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user", 387 "mout_dll_user", "oscclk_rco_apm" }; 388 PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" }; 389 390 static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 391 FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000), 392 FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000), 393 FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000), 394 FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000), 395 }; 396 397 static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 398 MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p, 399 PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1), 400 MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user", 401 mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1), 402 MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p, 403 PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1), 404 MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p, 405 PLL_CON0_MUX_DLL_USER, 4, 1), 406 MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus", 407 mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1), 408 MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p, 409 CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2), 410 MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p, 411 CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1), 412 }; 413 414 static const struct samsung_div_clock apm_div_clks[] __initconst = { 415 DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus", 416 "gout_clkcmu_chub_bus", 417 CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3), 418 DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus", 419 CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3), 420 DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus", 421 CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3), 422 }; 423 424 static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 425 GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus", 426 CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0), 427 GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus", 428 "mout_clkcmu_chub_bus", 429 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0), 430 GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus", 431 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0), 432 GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus", 433 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0), 434 GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus", 435 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0), 436 GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c", 437 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0), 438 GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus", 439 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0), 440 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 441 GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus", 442 CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, 443 0), 444 GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", 445 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0), 446 GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", 447 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), 448 }; 449 450 static const struct samsung_cmu_info apm_cmu_info __initconst = { 451 .mux_clks = apm_mux_clks, 452 .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 453 .div_clks = apm_div_clks, 454 .nr_div_clks = ARRAY_SIZE(apm_div_clks), 455 .gate_clks = apm_gate_clks, 456 .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 457 .fixed_clks = apm_fixed_clks, 458 .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 459 .nr_clk_ids = APM_NR_CLK, 460 .clk_regs = apm_clk_regs, 461 .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 462 .clk_name = "dout_clkcmu_apm_bus", 463 }; 464 465 /* ---- CMU_CMGP ------------------------------------------------------------ */ 466 467 /* Register Offset definitions for CMU_CMGP (0x11c00000) */ 468 #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000 469 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004 470 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008 471 #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800 472 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804 473 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808 474 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c 475 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 476 #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018 477 #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040 478 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044 479 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048 480 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c 481 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050 482 483 static const unsigned long cmgp_clk_regs[] __initconst = { 484 CLK_CON_MUX_CLK_CMGP_ADC, 485 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 486 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 487 CLK_CON_DIV_DIV_CLK_CMGP_ADC, 488 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 489 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 490 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 491 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 492 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 493 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 494 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 495 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 496 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 497 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 498 }; 499 500 /* List of parent clocks for Muxes in CMU_CMGP */ 501 PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 502 PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 503 PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" }; 504 505 static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = { 506 FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000), 507 }; 508 509 static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = { 510 MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p, 511 CLK_CON_MUX_CLK_CMGP_ADC, 0, 1), 512 MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, 513 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1), 514 MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, 515 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1), 516 }; 517 518 static const struct samsung_div_clock cmgp_div_clks[] __initconst = { 519 DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus", 520 CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), 521 DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", 522 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5), 523 DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", 524 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5), 525 }; 526 527 static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { 528 GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk", 529 "gout_clkcmu_cmgp_bus", 530 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0), 531 GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk", 532 "gout_clkcmu_cmgp_bus", 533 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0), 534 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 535 GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk", 536 "gout_clkcmu_cmgp_bus", 537 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0), 538 GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0", 539 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0), 540 GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk", 541 "gout_clkcmu_cmgp_bus", 542 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0), 543 GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1", 544 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0), 545 GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", 546 "gout_clkcmu_cmgp_bus", 547 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), 548 GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk", 549 "gout_clkcmu_cmgp_bus", 550 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0), 551 }; 552 553 static const struct samsung_cmu_info cmgp_cmu_info __initconst = { 554 .mux_clks = cmgp_mux_clks, 555 .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks), 556 .div_clks = cmgp_div_clks, 557 .nr_div_clks = ARRAY_SIZE(cmgp_div_clks), 558 .gate_clks = cmgp_gate_clks, 559 .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks), 560 .fixed_clks = cmgp_fixed_clks, 561 .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks), 562 .nr_clk_ids = CMGP_NR_CLK, 563 .clk_regs = cmgp_clk_regs, 564 .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), 565 .clk_name = "gout_clkcmu_cmgp_bus", 566 }; 567 568 /* ---- CMU_HSI ------------------------------------------------------------- */ 569 570 /* Register Offset definitions for CMU_HSI (0x13400000) */ 571 #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 572 #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 573 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 574 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 575 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 576 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c 577 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 578 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 579 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 580 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 581 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 582 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c 583 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 584 585 static const unsigned long hsi_clk_regs[] __initconst = { 586 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 587 PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 588 PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 589 CLK_CON_MUX_MUX_CLK_HSI_RTC, 590 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 591 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 592 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 593 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 594 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 595 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 596 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 597 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 598 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 599 }; 600 601 /* List of parent clocks for Muxes in CMU_HSI */ 602 PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" }; 603 PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" }; 604 PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" }; 605 PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" }; 606 607 static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { 608 MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, 609 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), 610 MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", 611 mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 612 4, 1, CLK_SET_RATE_PARENT, 0), 613 MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", 614 mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 615 4, 1), 616 MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p, 617 CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1), 618 }; 619 620 static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { 621 GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", 622 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), 623 GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", 624 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), 625 GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk", 626 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), 627 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 628 GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user", 629 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 630 GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", 631 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), 632 GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 633 "mout_hsi_mmc_card_user", 634 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), 635 GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", 636 "mout_hsi_bus_user", 637 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), 638 GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", 639 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), 640 GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", 641 "mout_hsi_bus_user", 642 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), 643 }; 644 645 static const struct samsung_cmu_info hsi_cmu_info __initconst = { 646 .mux_clks = hsi_mux_clks, 647 .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), 648 .gate_clks = hsi_gate_clks, 649 .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), 650 .nr_clk_ids = HSI_NR_CLK, 651 .clk_regs = hsi_clk_regs, 652 .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), 653 .clk_name = "dout_hsi_bus", 654 }; 655 656 /* ---- CMU_PERI ------------------------------------------------------------ */ 657 658 /* Register Offset definitions for CMU_PERI (0x10030000) */ 659 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 660 #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610 661 #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620 662 #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 663 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800 664 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804 665 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808 666 #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c 667 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c 668 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010 669 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014 670 #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020 671 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024 672 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 673 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c 674 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030 675 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034 676 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038 677 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c 678 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040 679 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044 680 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048 681 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c 682 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050 683 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054 684 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c 685 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064 686 #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c 687 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0 688 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4 689 #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 690 #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac 691 #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0 692 #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4 693 694 static const unsigned long peri_clk_regs[] __initconst = { 695 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 696 PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 697 PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 698 PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 699 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 700 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 701 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 702 CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 703 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 704 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 705 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 706 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 707 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 708 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 709 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 710 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 711 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 712 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 713 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 714 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 715 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 716 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 717 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 718 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 719 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 720 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 721 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 722 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 723 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 724 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 725 CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 726 CLK_CON_GAT_GOUT_PERI_UART_PCLK, 727 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 728 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 729 }; 730 731 /* List of parent clocks for Muxes in CMU_PERI */ 732 PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; 733 PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" }; 734 PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" }; 735 PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" }; 736 737 static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 738 MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 739 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 740 MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", 741 mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), 742 MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", 743 mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), 744 MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, 745 PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), 746 }; 747 748 static const struct samsung_div_clock peri_div_clks[] __initconst = { 749 DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0", 750 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5), 751 DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1", 752 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), 753 DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", 754 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), 755 DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", 756 CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), 757 }; 758 759 static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 760 GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user", 761 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0), 762 GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user", 763 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0), 764 GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user", 765 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0), 766 GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0", 767 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0), 768 GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", 769 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), 770 GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1", 771 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0), 772 GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", 773 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), 774 GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2", 775 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0), 776 GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", 777 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), 778 GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", 779 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), 780 GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", 781 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), 782 GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", 783 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), 784 GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", 785 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), 786 GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", 787 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), 788 GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", 789 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), 790 GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", 791 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), 792 GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", 793 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), 794 GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", 795 "mout_peri_bus_user", 796 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), 797 GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", 798 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), 799 GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", 800 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), 801 GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", 802 "mout_peri_bus_user", 803 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), 804 GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", 805 CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), 806 GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", 807 CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), 808 GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", 809 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0), 810 GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", 811 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0), 812 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 813 GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk", 814 "mout_peri_bus_user", 815 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 816 }; 817 818 static const struct samsung_cmu_info peri_cmu_info __initconst = { 819 .mux_clks = peri_mux_clks, 820 .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 821 .div_clks = peri_div_clks, 822 .nr_div_clks = ARRAY_SIZE(peri_div_clks), 823 .gate_clks = peri_gate_clks, 824 .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 825 .nr_clk_ids = PERI_NR_CLK, 826 .clk_regs = peri_clk_regs, 827 .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 828 .clk_name = "dout_peri_bus", 829 }; 830 831 static void __init exynos850_cmu_peri_init(struct device_node *np) 832 { 833 exynos_arm64_register_cmu(NULL, np, &peri_cmu_info); 834 } 835 836 /* Register CMU_PERI early, as it's needed for MCT timer */ 837 CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", 838 exynos850_cmu_peri_init); 839 840 /* ---- CMU_CORE ------------------------------------------------------------ */ 841 842 /* Register Offset definitions for CMU_CORE (0x12000000) */ 843 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 844 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610 845 #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 846 #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630 847 #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 848 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 849 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 850 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 851 #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 852 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 853 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec 854 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 855 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c 856 #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 857 858 static const unsigned long core_clk_regs[] __initconst = { 859 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 860 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 861 PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 862 PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 863 CLK_CON_MUX_MUX_CLK_CORE_GIC, 864 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 865 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 866 CLK_CON_GAT_GOUT_CORE_GIC_CLK, 867 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 868 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 869 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 870 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 871 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 872 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 873 }; 874 875 /* List of parent clocks for Muxes in CMU_CORE */ 876 PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; 877 PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; 878 PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" }; 879 PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" }; 880 PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; 881 882 static const struct samsung_mux_clock core_mux_clks[] __initconst = { 883 MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 884 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 885 MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, 886 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), 887 MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", 888 mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 889 4, 1, CLK_SET_RATE_PARENT, 0), 890 MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p, 891 PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1), 892 MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, 893 CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), 894 }; 895 896 static const struct samsung_div_clock core_div_clks[] __initconst = { 897 DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 898 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 899 }; 900 901 static const struct samsung_gate_clock core_gate_clks[] __initconst = { 902 /* CCI (interconnect) clock must be always running */ 903 GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", 904 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0), 905 /* GIC (interrupt controller) clock must be always running */ 906 GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic", 907 CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0), 908 GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", 909 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), 910 GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 911 "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 912 21, CLK_SET_RATE_PARENT, 0), 913 GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", 914 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), 915 GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", 916 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), 917 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 918 GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp", 919 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0), 920 GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk", 921 "dout_core_busp", 922 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0), 923 }; 924 925 static const struct samsung_cmu_info core_cmu_info __initconst = { 926 .mux_clks = core_mux_clks, 927 .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 928 .div_clks = core_div_clks, 929 .nr_div_clks = ARRAY_SIZE(core_div_clks), 930 .gate_clks = core_gate_clks, 931 .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 932 .nr_clk_ids = CORE_NR_CLK, 933 .clk_regs = core_clk_regs, 934 .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 935 .clk_name = "dout_core_bus", 936 }; 937 938 /* ---- CMU_DPU ------------------------------------------------------------- */ 939 940 /* Register Offset definitions for CMU_DPU (0x13000000) */ 941 #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600 942 #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 943 #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004 944 #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010 945 #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014 946 #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018 947 #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028 948 #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c 949 #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038 950 #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c 951 952 static const unsigned long dpu_clk_regs[] __initconst = { 953 PLL_CON0_MUX_CLKCMU_DPU_USER, 954 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 955 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 956 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 957 CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 958 CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 959 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 960 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 961 CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 962 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 963 }; 964 965 /* List of parent clocks for Muxes in CMU_DPU */ 966 PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" }; 967 968 static const struct samsung_mux_clock dpu_mux_clks[] __initconst = { 969 MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p, 970 PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1), 971 }; 972 973 static const struct samsung_div_clock dpu_div_clks[] __initconst = { 974 DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user", 975 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), 976 }; 977 978 static const struct samsung_gate_clock dpu_gate_clks[] __initconst = { 979 /* TODO: Should be enabled in DSIM driver */ 980 GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk", 981 "dout_dpu_busp", 982 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0), 983 GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user", 984 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0), 985 GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user", 986 CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0), 987 GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user", 988 CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0), 989 GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user", 990 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0), 991 GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp", 992 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0), 993 GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user", 994 CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0), 995 GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp", 996 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0), 997 }; 998 999 static const struct samsung_cmu_info dpu_cmu_info __initconst = { 1000 .mux_clks = dpu_mux_clks, 1001 .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks), 1002 .div_clks = dpu_div_clks, 1003 .nr_div_clks = ARRAY_SIZE(dpu_div_clks), 1004 .gate_clks = dpu_gate_clks, 1005 .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), 1006 .nr_clk_ids = DPU_NR_CLK, 1007 .clk_regs = dpu_clk_regs, 1008 .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), 1009 .clk_name = "dout_dpu", 1010 }; 1011 1012 /* ---- platform_driver ----------------------------------------------------- */ 1013 1014 static int __init exynos850_cmu_probe(struct platform_device *pdev) 1015 { 1016 const struct samsung_cmu_info *info; 1017 struct device *dev = &pdev->dev; 1018 1019 info = of_device_get_match_data(dev); 1020 exynos_arm64_register_cmu(dev, dev->of_node, info); 1021 1022 return 0; 1023 } 1024 1025 static const struct of_device_id exynos850_cmu_of_match[] = { 1026 { 1027 .compatible = "samsung,exynos850-cmu-apm", 1028 .data = &apm_cmu_info, 1029 }, { 1030 .compatible = "samsung,exynos850-cmu-cmgp", 1031 .data = &cmgp_cmu_info, 1032 }, { 1033 .compatible = "samsung,exynos850-cmu-hsi", 1034 .data = &hsi_cmu_info, 1035 }, { 1036 .compatible = "samsung,exynos850-cmu-core", 1037 .data = &core_cmu_info, 1038 }, { 1039 .compatible = "samsung,exynos850-cmu-dpu", 1040 .data = &dpu_cmu_info, 1041 }, { 1042 }, 1043 }; 1044 1045 static struct platform_driver exynos850_cmu_driver __refdata = { 1046 .driver = { 1047 .name = "exynos850-cmu", 1048 .of_match_table = exynos850_cmu_of_match, 1049 .suppress_bind_attrs = true, 1050 }, 1051 .probe = exynos850_cmu_probe, 1052 }; 1053 1054 static int __init exynos850_cmu_init(void) 1055 { 1056 return platform_driver_register(&exynos850_cmu_driver); 1057 } 1058 core_initcall(exynos850_cmu_init); 1059