1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021 Linaro Ltd. 4 * Author: Sam Protsenko <semen.protsenko@linaro.org> 5 * 6 * Common Clock Framework support for Exynos850 SoC. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 15 #include <dt-bindings/clock/exynos850.h> 16 17 #include "clk.h" 18 #include "clk-exynos-arm64.h" 19 20 /* ---- CMU_TOP ------------------------------------------------------------- */ 21 22 /* Register Offset definitions for CMU_TOP (0x120e0000) */ 23 #define PLL_LOCKTIME_PLL_MMC 0x0000 24 #define PLL_LOCKTIME_PLL_SHARED0 0x0004 25 #define PLL_LOCKTIME_PLL_SHARED1 0x0008 26 #define PLL_CON0_PLL_MMC 0x0100 27 #define PLL_CON3_PLL_MMC 0x010c 28 #define PLL_CON0_PLL_SHARED0 0x0140 29 #define PLL_CON3_PLL_SHARED0 0x014c 30 #define PLL_CON0_PLL_SHARED1 0x0180 31 #define PLL_CON3_PLL_SHARED1 0x018c 32 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000 33 #define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004 34 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 35 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 36 #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c 37 #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 38 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 39 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038 40 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c 41 #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 42 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 43 #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048 44 #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c 45 #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050 46 #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054 47 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058 48 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c 49 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060 50 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064 51 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 52 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 53 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 54 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c 55 #define CLK_CON_DIV_CLKCMU_AUD 0x1810 56 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 57 #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 58 #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 59 #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c 60 #define CLK_CON_DIV_CLKCMU_DPU 0x1840 61 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844 62 #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 63 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c 64 #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 65 #define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854 66 #define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858 67 #define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c 68 #define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860 69 #define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864 70 #define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868 71 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c 72 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870 73 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c 74 #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 75 #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 76 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c 77 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 78 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 79 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 80 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c 81 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 82 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008 83 #define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c 84 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 85 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 86 #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 87 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 88 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c 89 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040 90 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 91 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 92 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c 93 #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050 94 #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054 95 #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058 96 #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c 97 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060 98 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064 99 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068 100 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c 101 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 102 #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 103 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 104 105 static const unsigned long top_clk_regs[] __initconst = { 106 PLL_LOCKTIME_PLL_MMC, 107 PLL_LOCKTIME_PLL_SHARED0, 108 PLL_LOCKTIME_PLL_SHARED1, 109 PLL_CON0_PLL_MMC, 110 PLL_CON3_PLL_MMC, 111 PLL_CON0_PLL_SHARED0, 112 PLL_CON3_PLL_SHARED0, 113 PLL_CON0_PLL_SHARED1, 114 PLL_CON3_PLL_SHARED1, 115 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 116 CLK_CON_MUX_MUX_CLKCMU_AUD, 117 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 118 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 119 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 120 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 121 CLK_CON_MUX_MUX_CLKCMU_DPU, 122 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 123 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 124 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 125 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 126 CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 127 CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 128 CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 129 CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 130 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 131 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 132 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 133 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 134 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 135 CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 136 CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 137 CLK_CON_DIV_CLKCMU_APM_BUS, 138 CLK_CON_DIV_CLKCMU_AUD, 139 CLK_CON_DIV_CLKCMU_CORE_BUS, 140 CLK_CON_DIV_CLKCMU_CORE_CCI, 141 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 142 CLK_CON_DIV_CLKCMU_CORE_SSS, 143 CLK_CON_DIV_CLKCMU_DPU, 144 CLK_CON_DIV_CLKCMU_G3D_SWITCH, 145 CLK_CON_DIV_CLKCMU_HSI_BUS, 146 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 147 CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 148 CLK_CON_DIV_CLKCMU_IS_BUS, 149 CLK_CON_DIV_CLKCMU_IS_GDC, 150 CLK_CON_DIV_CLKCMU_IS_ITP, 151 CLK_CON_DIV_CLKCMU_IS_VRA, 152 CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 153 CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 154 CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 155 CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 156 CLK_CON_DIV_CLKCMU_PERI_BUS, 157 CLK_CON_DIV_CLKCMU_PERI_IP, 158 CLK_CON_DIV_CLKCMU_PERI_UART, 159 CLK_CON_DIV_PLL_SHARED0_DIV2, 160 CLK_CON_DIV_PLL_SHARED0_DIV3, 161 CLK_CON_DIV_PLL_SHARED0_DIV4, 162 CLK_CON_DIV_PLL_SHARED1_DIV2, 163 CLK_CON_DIV_PLL_SHARED1_DIV3, 164 CLK_CON_DIV_PLL_SHARED1_DIV4, 165 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 166 CLK_CON_GAT_GATE_CLKCMU_AUD, 167 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 168 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 169 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 170 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 171 CLK_CON_GAT_GATE_CLKCMU_DPU, 172 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 173 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 174 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 175 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 176 CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 177 CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 178 CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 179 CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 180 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 181 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 182 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 183 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 184 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 185 CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 186 CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 187 }; 188 189 /* 190 * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set 191 * for those PLLs by default, so set_rate operation would fail. 192 */ 193 static const struct samsung_pll_clock top_pll_clks[] __initconst = { 194 /* CMU_TOP_PURECLKCOMP */ 195 PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 196 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 197 NULL), 198 PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 199 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 200 NULL), 201 PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 202 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 203 }; 204 205 /* List of parent clocks for Muxes in CMU_TOP */ 206 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 207 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 208 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 209 /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */ 210 PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" }; 211 /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */ 212 PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2", 213 "dout_shared1_div2", "dout_shared0_div3" }; 214 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 215 PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", 216 "dout_shared1_div3", "dout_shared0_div4" }; 217 PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 218 "dout_shared0_div3", "dout_shared1_div3" }; 219 PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", 220 "dout_shared1_div2", "dout_shared0_div3", 221 "dout_shared1_div3", "mout_mmc_pll", 222 "oscclk", "oscclk" }; 223 PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", 224 "dout_shared0_div4", "dout_shared1_div4" }; 225 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */ 226 PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", 227 "dout_shared0_div3", "dout_shared1_div3" }; 228 /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ 229 PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 230 PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", 231 "dout_shared1_div2", "dout_shared0_div3", 232 "dout_shared1_div3", "mout_mmc_pll", 233 "oscclk", "oscclk" }; 234 PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4", 235 "dout_shared1_div4", "oscclk" }; 236 /* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */ 237 PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", 238 "dout_shared0_div3", "dout_shared1_div3" }; 239 PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2", 240 "dout_shared0_div3", "dout_shared1_div3" }; 241 PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2", 242 "dout_shared0_div3", "dout_shared1_div3" }; 243 PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2", 244 "dout_shared0_div3", "dout_shared1_div3" }; 245 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */ 246 PNAME(mout_mfcmscl_mfc_p) = { "dout_shared1_div2", "dout_shared0_div3", 247 "dout_shared1_div3", "dout_shared0_div4" }; 248 PNAME(mout_mfcmscl_m2m_p) = { "dout_shared1_div2", "dout_shared0_div3", 249 "dout_shared1_div3", "dout_shared0_div4" }; 250 PNAME(mout_mfcmscl_mcsc_p) = { "dout_shared1_div2", "dout_shared0_div3", 251 "dout_shared1_div3", "dout_shared0_div4" }; 252 PNAME(mout_mfcmscl_jpeg_p) = { "dout_shared0_div3", "dout_shared1_div3", 253 "dout_shared0_div4", "dout_shared1_div4" }; 254 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 255 PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 256 PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4", 257 "dout_shared1_div4", "oscclk" }; 258 PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4", 259 "dout_shared1_div4", "oscclk" }; 260 /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ 261 PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3", 262 "dout_shared0_div4", "dout_shared1_div4" }; 263 264 static const struct samsung_mux_clock top_mux_clks[] __initconst = { 265 /* CMU_TOP_PURECLKCOMP */ 266 MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 267 PLL_CON0_PLL_SHARED0, 4, 1), 268 MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 269 PLL_CON0_PLL_SHARED1, 4, 1), 270 MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 271 PLL_CON0_PLL_MMC, 4, 1), 272 273 /* APM */ 274 MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", 275 mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), 276 277 /* AUD */ 278 MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p, 279 CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2), 280 281 /* CORE */ 282 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 283 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 284 MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 285 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 286 MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, 287 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), 288 MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, 289 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), 290 291 /* DPU */ 292 MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, 293 CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), 294 295 /* G3D */ 296 MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p, 297 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2), 298 299 /* HSI */ 300 MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, 301 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), 302 MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, 303 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), 304 MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, 305 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), 306 307 /* IS */ 308 MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p, 309 CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2), 310 MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p, 311 CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2), 312 MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p, 313 CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2), 314 MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p, 315 CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2), 316 317 /* MFCMSCL */ 318 MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p, 319 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2), 320 MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p, 321 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2), 322 MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p, 323 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2), 324 MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p, 325 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2), 326 327 /* PERI */ 328 MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 329 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 330 MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, 331 CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), 332 MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, 333 CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), 334 }; 335 336 static const struct samsung_div_clock top_div_clks[] __initconst = { 337 /* CMU_TOP_PURECLKCOMP */ 338 DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 339 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 340 DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 341 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 342 DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 343 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 344 DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 345 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 346 DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 347 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 348 DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 349 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 350 351 /* APM */ 352 DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", 353 "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), 354 355 /* AUD */ 356 DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud", 357 CLK_CON_DIV_CLKCMU_AUD, 0, 4), 358 359 /* CORE */ 360 DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 361 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 362 DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 363 CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), 364 DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", 365 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), 366 DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", 367 CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), 368 369 /* DPU */ 370 DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", 371 CLK_CON_DIV_CLKCMU_DPU, 0, 4), 372 373 /* G3D */ 374 DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch", 375 CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), 376 377 /* HSI */ 378 DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", 379 CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), 380 DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", 381 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), 382 DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", 383 CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), 384 385 /* IS */ 386 DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus", 387 CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4), 388 DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp", 389 CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4), 390 DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra", 391 CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4), 392 DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc", 393 CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4), 394 395 /* MFCMSCL */ 396 DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc", 397 CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4), 398 DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m", 399 CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4), 400 DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc", 401 CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4), 402 DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg", 403 CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4), 404 405 /* PERI */ 406 DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 407 CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 408 DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", 409 CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), 410 DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", 411 CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), 412 }; 413 414 static const struct samsung_gate_clock top_gate_clks[] __initconst = { 415 /* CORE */ 416 GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 417 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 418 GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 419 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 420 GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", 421 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), 422 GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", 423 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), 424 425 /* APM */ 426 GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", 427 "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0), 428 429 /* AUD */ 430 GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud", 431 CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0), 432 433 /* DPU */ 434 GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", 435 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), 436 437 /* G3D */ 438 GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch", 439 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0), 440 441 /* HSI */ 442 GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", 443 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), 444 GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", 445 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), 446 GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", 447 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), 448 449 /* IS */ 450 /* TODO: These clocks have to be always enabled to access CMU_IS regs */ 451 GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus", 452 CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0), 453 GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp", 454 CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0), 455 GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra", 456 CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0), 457 GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc", 458 CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0), 459 460 /* MFCMSCL */ 461 /* TODO: These have to be always enabled to access CMU_MFCMSCL regs */ 462 GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc", 463 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0), 464 GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m", 465 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0), 466 GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc", 467 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0), 468 GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg", 469 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0), 470 471 /* PERI */ 472 GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 473 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 474 GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", 475 CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), 476 GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", 477 CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), 478 }; 479 480 static const struct samsung_cmu_info top_cmu_info __initconst = { 481 .pll_clks = top_pll_clks, 482 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 483 .mux_clks = top_mux_clks, 484 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 485 .div_clks = top_div_clks, 486 .nr_div_clks = ARRAY_SIZE(top_div_clks), 487 .gate_clks = top_gate_clks, 488 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 489 .nr_clk_ids = TOP_NR_CLK, 490 .clk_regs = top_clk_regs, 491 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 492 }; 493 494 static void __init exynos850_cmu_top_init(struct device_node *np) 495 { 496 exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 497 } 498 499 /* Register CMU_TOP early, as it's a dependency for other early domains */ 500 CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", 501 exynos850_cmu_top_init); 502 503 /* ---- CMU_APM ------------------------------------------------------------- */ 504 505 /* Register Offset definitions for CMU_APM (0x11800000) */ 506 #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600 507 #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610 508 #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620 509 #define PLL_CON0_MUX_DLL_USER 0x0630 510 #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000 511 #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004 512 #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008 513 #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800 514 #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804 515 #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808 516 #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 517 #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014 518 #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018 519 #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020 520 #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024 521 #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028 522 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034 523 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038 524 #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc 525 #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0 526 527 static const unsigned long apm_clk_regs[] __initconst = { 528 PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 529 PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 530 PLL_CON0_MUX_CLK_RCO_APM_USER, 531 PLL_CON0_MUX_DLL_USER, 532 CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 533 CLK_CON_MUX_MUX_CLK_APM_BUS, 534 CLK_CON_MUX_MUX_CLK_APM_I3C, 535 CLK_CON_DIV_CLKCMU_CHUB_BUS, 536 CLK_CON_DIV_DIV_CLK_APM_BUS, 537 CLK_CON_DIV_DIV_CLK_APM_I3C, 538 CLK_CON_GAT_CLKCMU_CMGP_BUS, 539 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 540 CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 541 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 542 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 543 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 544 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 545 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 546 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 547 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 548 }; 549 550 /* List of parent clocks for Muxes in CMU_APM */ 551 PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" }; 552 PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" }; 553 PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" }; 554 PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" }; 555 PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" }; 556 PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user", 557 "mout_dll_user", "oscclk_rco_apm" }; 558 PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" }; 559 560 static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 561 FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000), 562 FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000), 563 FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000), 564 FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000), 565 }; 566 567 static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 568 MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p, 569 PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1), 570 MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user", 571 mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1), 572 MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p, 573 PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1), 574 MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p, 575 PLL_CON0_MUX_DLL_USER, 4, 1), 576 MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus", 577 mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1), 578 MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p, 579 CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2), 580 MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p, 581 CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1), 582 }; 583 584 static const struct samsung_div_clock apm_div_clks[] __initconst = { 585 DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus", 586 "gout_clkcmu_chub_bus", 587 CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3), 588 DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus", 589 CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3), 590 DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus", 591 CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3), 592 }; 593 594 static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 595 GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus", 596 CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0), 597 GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus", 598 "mout_clkcmu_chub_bus", 599 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0), 600 GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus", 601 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0), 602 GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus", 603 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0), 604 GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus", 605 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0), 606 GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c", 607 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0), 608 GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus", 609 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0), 610 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 611 GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus", 612 CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, 613 0), 614 GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", 615 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0), 616 GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", 617 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), 618 }; 619 620 static const struct samsung_cmu_info apm_cmu_info __initconst = { 621 .mux_clks = apm_mux_clks, 622 .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 623 .div_clks = apm_div_clks, 624 .nr_div_clks = ARRAY_SIZE(apm_div_clks), 625 .gate_clks = apm_gate_clks, 626 .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 627 .fixed_clks = apm_fixed_clks, 628 .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 629 .nr_clk_ids = APM_NR_CLK, 630 .clk_regs = apm_clk_regs, 631 .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 632 .clk_name = "dout_clkcmu_apm_bus", 633 }; 634 635 /* ---- CMU_AUD ------------------------------------------------------------- */ 636 637 #define PLL_LOCKTIME_PLL_AUD 0x0000 638 #define PLL_CON0_PLL_AUD 0x0100 639 #define PLL_CON3_PLL_AUD 0x010c 640 #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600 641 #define PLL_CON0_MUX_TICK_USB_USER 0x0610 642 #define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000 643 #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004 644 #define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008 645 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c 646 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010 647 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014 648 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018 649 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c 650 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020 651 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024 652 #define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800 653 #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804 654 #define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808 655 #define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c 656 #define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810 657 #define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814 658 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818 659 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c 660 #define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820 661 #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824 662 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828 663 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c 664 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830 665 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834 666 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838 667 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c 668 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840 669 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000 670 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004 671 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008 672 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c 673 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010 674 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 675 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 676 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c 677 #define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020 678 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 679 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c 680 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 681 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054 682 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058 683 #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c 684 #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070 685 #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074 686 #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088 687 #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c 688 #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4 689 #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8 690 #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc 691 692 static const unsigned long aud_clk_regs[] __initconst = { 693 PLL_LOCKTIME_PLL_AUD, 694 PLL_CON0_PLL_AUD, 695 PLL_CON3_PLL_AUD, 696 PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 697 PLL_CON0_MUX_TICK_USB_USER, 698 CLK_CON_MUX_MUX_CLK_AUD_CPU, 699 CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 700 CLK_CON_MUX_MUX_CLK_AUD_FM, 701 CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 702 CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 703 CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 704 CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 705 CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 706 CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 707 CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 708 CLK_CON_DIV_DIV_CLK_AUD_MCLK, 709 CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 710 CLK_CON_DIV_DIV_CLK_AUD_BUSD, 711 CLK_CON_DIV_DIV_CLK_AUD_BUSP, 712 CLK_CON_DIV_DIV_CLK_AUD_CNT, 713 CLK_CON_DIV_DIV_CLK_AUD_CPU, 714 CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 715 CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 716 CLK_CON_DIV_DIV_CLK_AUD_FM, 717 CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 718 CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 719 CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 720 CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 721 CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 722 CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 723 CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 724 CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 725 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 726 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 727 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 728 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 729 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 730 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 731 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 732 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 733 CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 734 CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 735 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 736 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 737 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 738 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 739 CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 740 CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 741 CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 742 CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 743 CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 744 CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 745 CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 746 CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 747 }; 748 749 /* List of parent clocks for Muxes in CMU_AUD */ 750 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" }; 751 PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" }; 752 PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" }; 753 PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" }; 754 PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" }; 755 PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" }; 756 PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" }; 757 PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" }; 758 PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" }; 759 PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" }; 760 PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" }; 761 PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" }; 762 PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" }; 763 764 /* 765 * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set 766 * for that PLL by default, so set_rate operation would fail. 767 */ 768 static const struct samsung_pll_clock aud_pll_clks[] __initconst = { 769 PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 770 PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL), 771 }; 772 773 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { 774 FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000), 775 FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000), 776 FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000), 777 FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000), 778 FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000), 779 FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000), 780 FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000), 781 FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000), 782 }; 783 784 static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 785 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, 786 PLL_CON0_PLL_AUD, 4, 1), 787 MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p, 788 PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1), 789 MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user", 790 mout_aud_tick_usb_user_p, 791 PLL_CON0_MUX_TICK_USB_USER, 4, 1), 792 MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p, 793 CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1), 794 MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p, 795 CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1), 796 MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p, 797 CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1), 798 MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p, 799 CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1), 800 MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p, 801 CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1), 802 MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p, 803 CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1), 804 MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p, 805 CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1), 806 MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p, 807 CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1), 808 MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p, 809 CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1), 810 MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p, 811 CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1), 812 }; 813 814 static const struct samsung_div_clock aud_div_clks[] __initconst = { 815 DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll", 816 CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4), 817 DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll", 818 CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4), 819 DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll", 820 CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4), 821 DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll", 822 CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9), 823 DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch", 824 CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3), 825 DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg", 826 "mout_aud_cpu_hch", 827 CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3), 828 DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif", 829 CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2), 830 DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif", 831 CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10), 832 DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif", 833 CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10), 834 DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif", 835 CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10), 836 DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif", 837 CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10), 838 DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif", 839 CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10), 840 DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif", 841 CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10), 842 DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif", 843 CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10), 844 DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif", 845 CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10), 846 DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user", 847 CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1), 848 DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm", 849 CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10), 850 }; 851 852 static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 853 GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk", 854 "dout_aud_busd", 855 CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0), 856 GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch", 857 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), 858 GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk", 859 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0), 860 GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg", 861 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0), 862 /* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */ 863 GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd", 864 CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0), 865 GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd", 866 CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0), 867 GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd", 868 CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0), 869 GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd", 870 CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0), 871 GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd", 872 CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0), 873 GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd", 874 CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0), 875 GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd", 876 CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0), 877 GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp", 878 CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0), 879 GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk", 880 CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0), 881 GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt", 882 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0), 883 GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0", 884 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0), 885 GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1", 886 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0), 887 GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2", 888 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0), 889 GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3", 890 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0), 891 GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4", 892 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0), 893 GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5", 894 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0), 895 GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6", 896 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0), 897 GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm", 898 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0), 899 }; 900 901 static const struct samsung_cmu_info aud_cmu_info __initconst = { 902 .pll_clks = aud_pll_clks, 903 .nr_pll_clks = ARRAY_SIZE(aud_pll_clks), 904 .mux_clks = aud_mux_clks, 905 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 906 .div_clks = aud_div_clks, 907 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 908 .gate_clks = aud_gate_clks, 909 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 910 .fixed_clks = aud_fixed_clks, 911 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), 912 .nr_clk_ids = AUD_NR_CLK, 913 .clk_regs = aud_clk_regs, 914 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 915 .clk_name = "dout_aud", 916 }; 917 918 /* ---- CMU_CMGP ------------------------------------------------------------ */ 919 920 /* Register Offset definitions for CMU_CMGP (0x11c00000) */ 921 #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000 922 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004 923 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008 924 #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800 925 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804 926 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808 927 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c 928 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 929 #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018 930 #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040 931 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044 932 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048 933 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c 934 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050 935 936 static const unsigned long cmgp_clk_regs[] __initconst = { 937 CLK_CON_MUX_CLK_CMGP_ADC, 938 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 939 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 940 CLK_CON_DIV_DIV_CLK_CMGP_ADC, 941 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 942 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 943 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 944 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 945 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 946 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 947 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 948 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 949 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 950 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 951 }; 952 953 /* List of parent clocks for Muxes in CMU_CMGP */ 954 PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 955 PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 956 PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" }; 957 958 static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = { 959 FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000), 960 }; 961 962 static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = { 963 MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p, 964 CLK_CON_MUX_CLK_CMGP_ADC, 0, 1), 965 MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, 966 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1), 967 MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, 968 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1), 969 }; 970 971 static const struct samsung_div_clock cmgp_div_clks[] __initconst = { 972 DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus", 973 CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), 974 DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", 975 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5), 976 DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", 977 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5), 978 }; 979 980 static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { 981 GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk", 982 "gout_clkcmu_cmgp_bus", 983 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0), 984 GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk", 985 "gout_clkcmu_cmgp_bus", 986 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0), 987 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 988 GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk", 989 "gout_clkcmu_cmgp_bus", 990 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0), 991 GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0", 992 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0), 993 GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk", 994 "gout_clkcmu_cmgp_bus", 995 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0), 996 GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1", 997 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0), 998 GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", 999 "gout_clkcmu_cmgp_bus", 1000 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), 1001 GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk", 1002 "gout_clkcmu_cmgp_bus", 1003 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0), 1004 }; 1005 1006 static const struct samsung_cmu_info cmgp_cmu_info __initconst = { 1007 .mux_clks = cmgp_mux_clks, 1008 .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks), 1009 .div_clks = cmgp_div_clks, 1010 .nr_div_clks = ARRAY_SIZE(cmgp_div_clks), 1011 .gate_clks = cmgp_gate_clks, 1012 .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks), 1013 .fixed_clks = cmgp_fixed_clks, 1014 .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks), 1015 .nr_clk_ids = CMGP_NR_CLK, 1016 .clk_regs = cmgp_clk_regs, 1017 .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), 1018 .clk_name = "gout_clkcmu_cmgp_bus", 1019 }; 1020 1021 /* ---- CMU_G3D ------------------------------------------------------------- */ 1022 1023 /* Register Offset definitions for CMU_G3D (0x11400000) */ 1024 #define PLL_LOCKTIME_PLL_G3D 0x0000 1025 #define PLL_CON0_PLL_G3D 0x0100 1026 #define PLL_CON3_PLL_G3D 0x010c 1027 #define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600 1028 #define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000 1029 #define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804 1030 #define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000 1031 #define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004 1032 #define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c 1033 #define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010 1034 #define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024 1035 #define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028 1036 #define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c 1037 1038 static const unsigned long g3d_clk_regs[] __initconst = { 1039 PLL_LOCKTIME_PLL_G3D, 1040 PLL_CON0_PLL_G3D, 1041 PLL_CON3_PLL_G3D, 1042 PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 1043 CLK_CON_MUX_MUX_CLK_G3D_BUSD, 1044 CLK_CON_DIV_DIV_CLK_G3D_BUSP, 1045 CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 1046 CLK_CON_GAT_CLK_G3D_GPU_CLK, 1047 CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 1048 CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 1049 CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 1050 CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 1051 CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 1052 }; 1053 1054 /* List of parent clocks for Muxes in CMU_G3D */ 1055 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" }; 1056 PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" }; 1057 PNAME(mout_g3d_busd_p) = { "mout_g3d_pll", "mout_g3d_switch_user" }; 1058 1059 /* 1060 * Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set 1061 * for that PLL by default, so set_rate operation would fail. 1062 */ 1063 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { 1064 PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", 1065 PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL), 1066 }; 1067 1068 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { 1069 MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, 1070 PLL_CON0_PLL_G3D, 4, 1), 1071 MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user", 1072 mout_g3d_switch_user_p, 1073 PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1), 1074 MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p, 1075 CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1), 1076 }; 1077 1078 static const struct samsung_div_clock g3d_div_clks[] __initconst = { 1079 DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd", 1080 CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3), 1081 }; 1082 1083 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { 1084 GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk", 1085 "dout_g3d_busp", 1086 CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1087 GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd", 1088 CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0), 1089 GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp", 1090 CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0), 1091 GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk", 1092 "mout_g3d_busd", 1093 CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0), 1094 GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd", 1095 CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0), 1096 GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp", 1097 CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0), 1098 GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp", 1099 CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0), 1100 }; 1101 1102 static const struct samsung_cmu_info g3d_cmu_info __initconst = { 1103 .pll_clks = g3d_pll_clks, 1104 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), 1105 .mux_clks = g3d_mux_clks, 1106 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), 1107 .div_clks = g3d_div_clks, 1108 .nr_div_clks = ARRAY_SIZE(g3d_div_clks), 1109 .gate_clks = g3d_gate_clks, 1110 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), 1111 .nr_clk_ids = G3D_NR_CLK, 1112 .clk_regs = g3d_clk_regs, 1113 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), 1114 .clk_name = "dout_g3d_switch", 1115 }; 1116 1117 /* ---- CMU_HSI ------------------------------------------------------------- */ 1118 1119 /* Register Offset definitions for CMU_HSI (0x13400000) */ 1120 #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 1121 #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 1122 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 1123 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 1124 #define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000 1125 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 1126 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c 1127 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 1128 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 1129 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 1130 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 1131 #define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c 1132 #define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030 1133 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 1134 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c 1135 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 1136 1137 static const unsigned long hsi_clk_regs[] __initconst = { 1138 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 1139 PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 1140 PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 1141 CLK_CON_MUX_MUX_CLK_HSI_RTC, 1142 CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 1143 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 1144 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 1145 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 1146 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 1147 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 1148 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 1149 CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 1150 CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 1151 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 1152 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 1153 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 1154 }; 1155 1156 /* List of parent clocks for Muxes in CMU_HSI */ 1157 PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" }; 1158 PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" }; 1159 PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" }; 1160 PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" }; 1161 1162 static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { 1163 MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, 1164 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), 1165 MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", 1166 mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 1167 4, 1, CLK_SET_RATE_PARENT, 0), 1168 MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", 1169 mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 1170 4, 1), 1171 MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p, 1172 CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1), 1173 }; 1174 1175 static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { 1176 /* TODO: Should be enabled in corresponding driver */ 1177 GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk", 1178 "mout_hsi_bus_user", 1179 CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1180 GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", 1181 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), 1182 GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", 1183 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), 1184 GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk", 1185 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), 1186 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 1187 GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user", 1188 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1189 GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", 1190 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), 1191 GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 1192 "mout_hsi_mmc_card_user", 1193 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), 1194 GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user", 1195 CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0), 1196 GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user", 1197 CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0), 1198 GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", 1199 "mout_hsi_bus_user", 1200 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), 1201 GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", 1202 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), 1203 GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", 1204 "mout_hsi_bus_user", 1205 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), 1206 }; 1207 1208 static const struct samsung_cmu_info hsi_cmu_info __initconst = { 1209 .mux_clks = hsi_mux_clks, 1210 .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), 1211 .gate_clks = hsi_gate_clks, 1212 .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), 1213 .nr_clk_ids = HSI_NR_CLK, 1214 .clk_regs = hsi_clk_regs, 1215 .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), 1216 .clk_name = "dout_hsi_bus", 1217 }; 1218 1219 /* ---- CMU_IS -------------------------------------------------------------- */ 1220 1221 #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600 1222 #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610 1223 #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620 1224 #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630 1225 #define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800 1226 #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000 1227 #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040 1228 #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044 1229 #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048 1230 #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c 1231 #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050 1232 #define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054 1233 #define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058 1234 #define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c 1235 #define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060 1236 #define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064 1237 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074 1238 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078 1239 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c 1240 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080 1241 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098 1242 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c 1243 #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0 1244 1245 static const unsigned long is_clk_regs[] __initconst = { 1246 PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 1247 PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 1248 PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 1249 PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 1250 CLK_CON_DIV_DIV_CLK_IS_BUSP, 1251 CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 1252 CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 1253 CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 1254 CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 1255 CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 1256 CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 1257 CLK_CON_GAT_GOUT_IS_CLK_GDC, 1258 CLK_CON_GAT_GOUT_IS_CLK_IPP, 1259 CLK_CON_GAT_GOUT_IS_CLK_ITP, 1260 CLK_CON_GAT_GOUT_IS_CLK_MCSC, 1261 CLK_CON_GAT_GOUT_IS_CLK_VRA, 1262 CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 1263 CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 1264 CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 1265 CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 1266 CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 1267 CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 1268 CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 1269 }; 1270 1271 /* List of parent clocks for Muxes in CMU_IS */ 1272 PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" }; 1273 PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" }; 1274 PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" }; 1275 PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" }; 1276 1277 static const struct samsung_mux_clock is_mux_clks[] __initconst = { 1278 MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p, 1279 PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1), 1280 MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p, 1281 PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1), 1282 MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p, 1283 PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1), 1284 MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p, 1285 PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1), 1286 }; 1287 1288 static const struct samsung_div_clock is_div_clks[] __initconst = { 1289 DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user", 1290 CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2), 1291 }; 1292 1293 static const struct samsung_gate_clock is_gate_clks[] __initconst = { 1294 /* TODO: Should be enabled in IS driver */ 1295 GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp", 1296 CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1297 GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user", 1298 CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0), 1299 GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user", 1300 CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0), 1301 GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user", 1302 CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0), 1303 GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp", 1304 CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0), 1305 GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk", 1306 "mout_is_bus_user", 1307 CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0), 1308 GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user", 1309 CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0), 1310 GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user", 1311 CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0), 1312 GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user", 1313 CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0), 1314 GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user", 1315 CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0), 1316 GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user", 1317 CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0), 1318 GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk", 1319 "mout_is_bus_user", 1320 CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0), 1321 GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp", 1322 CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0), 1323 GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk", 1324 "mout_is_itp_user", 1325 CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0), 1326 GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp", 1327 CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0), 1328 GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk", 1329 "mout_is_bus_user", 1330 CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0), 1331 GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk", 1332 "mout_is_itp_user", 1333 CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0), 1334 GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp", 1335 CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0), 1336 }; 1337 1338 static const struct samsung_cmu_info is_cmu_info __initconst = { 1339 .mux_clks = is_mux_clks, 1340 .nr_mux_clks = ARRAY_SIZE(is_mux_clks), 1341 .div_clks = is_div_clks, 1342 .nr_div_clks = ARRAY_SIZE(is_div_clks), 1343 .gate_clks = is_gate_clks, 1344 .nr_gate_clks = ARRAY_SIZE(is_gate_clks), 1345 .nr_clk_ids = IS_NR_CLK, 1346 .clk_regs = is_clk_regs, 1347 .nr_clk_regs = ARRAY_SIZE(is_clk_regs), 1348 .clk_name = "dout_is_bus", 1349 }; 1350 1351 /* ---- CMU_MFCMSCL --------------------------------------------------------- */ 1352 1353 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600 1354 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610 1355 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620 1356 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630 1357 #define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800 1358 #define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000 1359 #define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038 1360 #define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c 1361 #define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048 1362 #define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c 1363 #define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050 1364 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054 1365 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058 1366 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074 1367 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078 1368 1369 static const unsigned long mfcmscl_clk_regs[] __initconst = { 1370 PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 1371 PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 1372 PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 1373 PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 1374 CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 1375 CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK, 1376 CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK, 1377 CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK, 1378 CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK, 1379 CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK, 1380 CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK, 1381 CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK, 1382 CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK, 1383 CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1, 1384 CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK, 1385 }; 1386 1387 /* List of parent clocks for Muxes in CMU_MFCMSCL */ 1388 PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" }; 1389 PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" }; 1390 PNAME(mout_mfcmscl_mcsc_user_p) = { "oscclk", "dout_mfcmscl_mcsc" }; 1391 PNAME(mout_mfcmscl_jpeg_user_p) = { "oscclk", "dout_mfcmscl_jpeg" }; 1392 1393 static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = { 1394 MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user", 1395 mout_mfcmscl_mfc_user_p, 1396 PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1), 1397 MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user", 1398 mout_mfcmscl_m2m_user_p, 1399 PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1), 1400 MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user", 1401 mout_mfcmscl_mcsc_user_p, 1402 PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1), 1403 MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user", 1404 mout_mfcmscl_jpeg_user_p, 1405 PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1), 1406 }; 1407 1408 static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = { 1409 DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user", 1410 CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3), 1411 }; 1412 1413 static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = { 1414 /* TODO: Should be enabled in MFC driver */ 1415 GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk", 1416 "dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK, 1417 21, CLK_IGNORE_UNUSED, 0), 1418 GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk", 1419 "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK, 1420 21, 0, 0), 1421 GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk", 1422 "mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK, 1423 21, 0, 0), 1424 GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk", 1425 "mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK, 1426 21, 0, 0), 1427 GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk", 1428 "mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK, 1429 21, 0, 0), 1430 GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk", 1431 "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK, 1432 21, 0, 0), 1433 GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk", 1434 "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK, 1435 21, 0, 0), 1436 GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk", 1437 "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK, 1438 21, 0, 0), 1439 GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk", 1440 "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1, 1441 21, 0, 0), 1442 GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk", 1443 "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK, 1444 21, 0, 0), 1445 }; 1446 1447 static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = { 1448 .mux_clks = mfcmscl_mux_clks, 1449 .nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks), 1450 .div_clks = mfcmscl_div_clks, 1451 .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks), 1452 .gate_clks = mfcmscl_gate_clks, 1453 .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks), 1454 .nr_clk_ids = MFCMSCL_NR_CLK, 1455 .clk_regs = mfcmscl_clk_regs, 1456 .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs), 1457 .clk_name = "dout_mfcmscl_mfc", 1458 }; 1459 1460 /* ---- CMU_PERI ------------------------------------------------------------ */ 1461 1462 /* Register Offset definitions for CMU_PERI (0x10030000) */ 1463 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 1464 #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610 1465 #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620 1466 #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 1467 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800 1468 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804 1469 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808 1470 #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c 1471 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c 1472 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010 1473 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014 1474 #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020 1475 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024 1476 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 1477 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c 1478 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030 1479 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034 1480 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038 1481 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c 1482 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040 1483 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044 1484 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048 1485 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c 1486 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050 1487 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054 1488 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c 1489 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064 1490 #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c 1491 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0 1492 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4 1493 #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 1494 #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac 1495 #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0 1496 #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4 1497 1498 static const unsigned long peri_clk_regs[] __initconst = { 1499 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 1500 PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 1501 PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 1502 PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 1503 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 1504 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 1505 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 1506 CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 1507 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 1508 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 1509 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 1510 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 1511 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 1512 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 1513 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 1514 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 1515 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 1516 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 1517 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 1518 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 1519 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 1520 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 1521 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 1522 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 1523 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 1524 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 1525 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 1526 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 1527 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 1528 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 1529 CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 1530 CLK_CON_GAT_GOUT_PERI_UART_PCLK, 1531 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 1532 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 1533 }; 1534 1535 /* List of parent clocks for Muxes in CMU_PERI */ 1536 PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; 1537 PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" }; 1538 PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" }; 1539 PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" }; 1540 1541 static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 1542 MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 1543 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 1544 MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", 1545 mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), 1546 MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", 1547 mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), 1548 MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, 1549 PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), 1550 }; 1551 1552 static const struct samsung_div_clock peri_div_clks[] __initconst = { 1553 DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0", 1554 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5), 1555 DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1", 1556 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), 1557 DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", 1558 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), 1559 DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", 1560 CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), 1561 }; 1562 1563 static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 1564 GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user", 1565 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0), 1566 GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user", 1567 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0), 1568 GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user", 1569 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0), 1570 GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0", 1571 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0), 1572 GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", 1573 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), 1574 GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1", 1575 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0), 1576 GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", 1577 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), 1578 GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2", 1579 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0), 1580 GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", 1581 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), 1582 GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", 1583 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), 1584 GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", 1585 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), 1586 GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", 1587 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), 1588 GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", 1589 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), 1590 GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", 1591 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), 1592 GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", 1593 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), 1594 GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", 1595 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), 1596 GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", 1597 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), 1598 GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", 1599 "mout_peri_bus_user", 1600 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), 1601 GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", 1602 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), 1603 GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", 1604 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), 1605 GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", 1606 "mout_peri_bus_user", 1607 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), 1608 GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", 1609 CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), 1610 GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", 1611 CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), 1612 GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", 1613 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0), 1614 GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", 1615 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0), 1616 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 1617 GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk", 1618 "mout_peri_bus_user", 1619 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1620 }; 1621 1622 static const struct samsung_cmu_info peri_cmu_info __initconst = { 1623 .mux_clks = peri_mux_clks, 1624 .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 1625 .div_clks = peri_div_clks, 1626 .nr_div_clks = ARRAY_SIZE(peri_div_clks), 1627 .gate_clks = peri_gate_clks, 1628 .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 1629 .nr_clk_ids = PERI_NR_CLK, 1630 .clk_regs = peri_clk_regs, 1631 .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 1632 .clk_name = "dout_peri_bus", 1633 }; 1634 1635 static void __init exynos850_cmu_peri_init(struct device_node *np) 1636 { 1637 exynos_arm64_register_cmu(NULL, np, &peri_cmu_info); 1638 } 1639 1640 /* Register CMU_PERI early, as it's needed for MCT timer */ 1641 CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", 1642 exynos850_cmu_peri_init); 1643 1644 /* ---- CMU_CORE ------------------------------------------------------------ */ 1645 1646 /* Register Offset definitions for CMU_CORE (0x12000000) */ 1647 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 1648 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610 1649 #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 1650 #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630 1651 #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 1652 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 1653 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 1654 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 1655 #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 1656 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 1657 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec 1658 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 1659 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c 1660 #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 1661 1662 static const unsigned long core_clk_regs[] __initconst = { 1663 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 1664 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 1665 PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 1666 PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 1667 CLK_CON_MUX_MUX_CLK_CORE_GIC, 1668 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 1669 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 1670 CLK_CON_GAT_GOUT_CORE_GIC_CLK, 1671 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 1672 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 1673 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 1674 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 1675 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 1676 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 1677 }; 1678 1679 /* List of parent clocks for Muxes in CMU_CORE */ 1680 PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; 1681 PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; 1682 PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" }; 1683 PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" }; 1684 PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; 1685 1686 static const struct samsung_mux_clock core_mux_clks[] __initconst = { 1687 MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 1688 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 1689 MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, 1690 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), 1691 MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", 1692 mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 1693 4, 1, CLK_SET_RATE_PARENT, 0), 1694 MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p, 1695 PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1), 1696 MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, 1697 CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), 1698 }; 1699 1700 static const struct samsung_div_clock core_div_clks[] __initconst = { 1701 DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 1702 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 1703 }; 1704 1705 static const struct samsung_gate_clock core_gate_clks[] __initconst = { 1706 /* CCI (interconnect) clock must be always running */ 1707 GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", 1708 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0), 1709 /* GIC (interrupt controller) clock must be always running */ 1710 GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic", 1711 CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0), 1712 GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", 1713 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), 1714 GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 1715 "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 1716 21, CLK_SET_RATE_PARENT, 0), 1717 GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", 1718 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), 1719 GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", 1720 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), 1721 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 1722 GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp", 1723 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1724 GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk", 1725 "dout_core_busp", 1726 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0), 1727 }; 1728 1729 static const struct samsung_cmu_info core_cmu_info __initconst = { 1730 .mux_clks = core_mux_clks, 1731 .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 1732 .div_clks = core_div_clks, 1733 .nr_div_clks = ARRAY_SIZE(core_div_clks), 1734 .gate_clks = core_gate_clks, 1735 .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 1736 .nr_clk_ids = CORE_NR_CLK, 1737 .clk_regs = core_clk_regs, 1738 .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 1739 .clk_name = "dout_core_bus", 1740 }; 1741 1742 /* ---- CMU_DPU ------------------------------------------------------------- */ 1743 1744 /* Register Offset definitions for CMU_DPU (0x13000000) */ 1745 #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600 1746 #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 1747 #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004 1748 #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010 1749 #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014 1750 #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018 1751 #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028 1752 #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c 1753 #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038 1754 #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c 1755 1756 static const unsigned long dpu_clk_regs[] __initconst = { 1757 PLL_CON0_MUX_CLKCMU_DPU_USER, 1758 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 1759 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 1760 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 1761 CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 1762 CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 1763 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 1764 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 1765 CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 1766 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 1767 }; 1768 1769 /* List of parent clocks for Muxes in CMU_DPU */ 1770 PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" }; 1771 1772 static const struct samsung_mux_clock dpu_mux_clks[] __initconst = { 1773 MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p, 1774 PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1), 1775 }; 1776 1777 static const struct samsung_div_clock dpu_div_clks[] __initconst = { 1778 DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user", 1779 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), 1780 }; 1781 1782 static const struct samsung_gate_clock dpu_gate_clks[] __initconst = { 1783 /* TODO: Should be enabled in DSIM driver */ 1784 GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk", 1785 "dout_dpu_busp", 1786 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1787 GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user", 1788 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0), 1789 GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user", 1790 CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0), 1791 GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user", 1792 CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0), 1793 GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user", 1794 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0), 1795 GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp", 1796 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0), 1797 GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user", 1798 CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0), 1799 GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp", 1800 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0), 1801 }; 1802 1803 static const struct samsung_cmu_info dpu_cmu_info __initconst = { 1804 .mux_clks = dpu_mux_clks, 1805 .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks), 1806 .div_clks = dpu_div_clks, 1807 .nr_div_clks = ARRAY_SIZE(dpu_div_clks), 1808 .gate_clks = dpu_gate_clks, 1809 .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), 1810 .nr_clk_ids = DPU_NR_CLK, 1811 .clk_regs = dpu_clk_regs, 1812 .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), 1813 .clk_name = "dout_dpu", 1814 }; 1815 1816 /* ---- platform_driver ----------------------------------------------------- */ 1817 1818 static int __init exynos850_cmu_probe(struct platform_device *pdev) 1819 { 1820 const struct samsung_cmu_info *info; 1821 struct device *dev = &pdev->dev; 1822 1823 info = of_device_get_match_data(dev); 1824 exynos_arm64_register_cmu(dev, dev->of_node, info); 1825 1826 return 0; 1827 } 1828 1829 static const struct of_device_id exynos850_cmu_of_match[] = { 1830 { 1831 .compatible = "samsung,exynos850-cmu-apm", 1832 .data = &apm_cmu_info, 1833 }, { 1834 .compatible = "samsung,exynos850-cmu-aud", 1835 .data = &aud_cmu_info, 1836 }, { 1837 .compatible = "samsung,exynos850-cmu-cmgp", 1838 .data = &cmgp_cmu_info, 1839 }, { 1840 .compatible = "samsung,exynos850-cmu-g3d", 1841 .data = &g3d_cmu_info, 1842 }, { 1843 .compatible = "samsung,exynos850-cmu-hsi", 1844 .data = &hsi_cmu_info, 1845 }, { 1846 .compatible = "samsung,exynos850-cmu-is", 1847 .data = &is_cmu_info, 1848 }, { 1849 .compatible = "samsung,exynos850-cmu-mfcmscl", 1850 .data = &mfcmscl_cmu_info, 1851 }, { 1852 .compatible = "samsung,exynos850-cmu-core", 1853 .data = &core_cmu_info, 1854 }, { 1855 .compatible = "samsung,exynos850-cmu-dpu", 1856 .data = &dpu_cmu_info, 1857 }, { 1858 }, 1859 }; 1860 1861 static struct platform_driver exynos850_cmu_driver __refdata = { 1862 .driver = { 1863 .name = "exynos850-cmu", 1864 .of_match_table = exynos850_cmu_of_match, 1865 .suppress_bind_attrs = true, 1866 }, 1867 .probe = exynos850_cmu_probe, 1868 }; 1869 1870 static int __init exynos850_cmu_init(void) 1871 { 1872 return platform_driver_register(&exynos850_cmu_driver); 1873 } 1874 core_initcall(exynos850_cmu_init); 1875