17dd05578SSam Protsenko // SPDX-License-Identifier: GPL-2.0-only 27dd05578SSam Protsenko /* 37dd05578SSam Protsenko * Copyright (C) 2021 Linaro Ltd. 47dd05578SSam Protsenko * Author: Sam Protsenko <semen.protsenko@linaro.org> 57dd05578SSam Protsenko * 67dd05578SSam Protsenko * Common Clock Framework support for Exynos850 SoC. 77dd05578SSam Protsenko */ 87dd05578SSam Protsenko 97dd05578SSam Protsenko #include <linux/clk.h> 107dd05578SSam Protsenko #include <linux/clk-provider.h> 117dd05578SSam Protsenko #include <linux/of.h> 127dd05578SSam Protsenko #include <linux/of_device.h> 137dd05578SSam Protsenko #include <linux/platform_device.h> 147dd05578SSam Protsenko 157dd05578SSam Protsenko #include <dt-bindings/clock/exynos850.h> 167dd05578SSam Protsenko 177dd05578SSam Protsenko #include "clk.h" 18cfe238e4SDavid Virag #include "clk-exynos-arm64.h" 19bcda841fSSam Protsenko 207dd05578SSam Protsenko /* ---- CMU_TOP ------------------------------------------------------------- */ 217dd05578SSam Protsenko 227dd05578SSam Protsenko /* Register Offset definitions for CMU_TOP (0x120e0000) */ 237dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_MMC 0x0000 247dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED0 0x0004 257dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED1 0x0008 267dd05578SSam Protsenko #define PLL_CON0_PLL_MMC 0x0100 277dd05578SSam Protsenko #define PLL_CON3_PLL_MMC 0x010c 287dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED0 0x0140 297dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED0 0x014c 307dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED1 0x0180 317dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED1 0x018c 32579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000 337dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 347dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 357dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c 367dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 377dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 387dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c 397dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 407dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 417dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 427dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 437dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 44579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c 457dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 467dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 477dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 487dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c 497dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_DPU 0x1840 507dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 517dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c 527dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 537dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c 547dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 557dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 567dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c 577dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 587dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 597dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 607dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c 617dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 62579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008 637dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 647dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 657dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 667dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 677dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c 687dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 697dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 707dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c 717dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 727dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 737dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 747dd05578SSam Protsenko 757dd05578SSam Protsenko static const unsigned long top_clk_regs[] __initconst = { 767dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, 777dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, 787dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, 797dd05578SSam Protsenko PLL_CON0_PLL_MMC, 807dd05578SSam Protsenko PLL_CON3_PLL_MMC, 817dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 827dd05578SSam Protsenko PLL_CON3_PLL_SHARED0, 837dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 847dd05578SSam Protsenko PLL_CON3_PLL_SHARED1, 85579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 867dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 877dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 887dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 897dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 907dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 917dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 927dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 937dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 947dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 957dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 967dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 97579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_APM_BUS, 987dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 997dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 1007dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 1017dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 1027dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 1037dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 1047dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 1057dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 1067dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 1077dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 1087dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 1097dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 1107dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 1117dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 1127dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 1137dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 1147dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 115579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 1167dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 1177dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 1187dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 1197dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 1207dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 1217dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 1227dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 1237dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 1247dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 1257dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 1267dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 1277dd05578SSam Protsenko }; 1287dd05578SSam Protsenko 1297dd05578SSam Protsenko /* 1307dd05578SSam Protsenko * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set 1317dd05578SSam Protsenko * for those PLLs by default, so set_rate operation would fail. 1327dd05578SSam Protsenko */ 1337dd05578SSam Protsenko static const struct samsung_pll_clock top_pll_clks[] __initconst = { 1347dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 1357dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 1367dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 1377dd05578SSam Protsenko NULL), 1387dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 1397dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 1407dd05578SSam Protsenko NULL), 1417dd05578SSam Protsenko PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 1427dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 1437dd05578SSam Protsenko }; 1447dd05578SSam Protsenko 1457dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP */ 1467dd05578SSam Protsenko PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 1477dd05578SSam Protsenko PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 1487dd05578SSam Protsenko PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 149579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */ 150579839a9SSam Protsenko PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" }; 1517dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 1527dd05578SSam Protsenko PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", 1537dd05578SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 1547dd05578SSam Protsenko PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 1557dd05578SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 1567dd05578SSam Protsenko PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", 1577dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 1587dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 1597dd05578SSam Protsenko "oscclk", "oscclk" }; 1607dd05578SSam Protsenko PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", 1617dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 1627dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ 1637dd05578SSam Protsenko PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 1647dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", 1657dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 1667dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 1677dd05578SSam Protsenko "oscclk", "oscclk" }; 1687dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4", 1697dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 1707dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 1717dd05578SSam Protsenko PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 1727dd05578SSam Protsenko PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4", 1737dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 1747dd05578SSam Protsenko PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4", 1757dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 1767dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ 1777dd05578SSam Protsenko PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3", 1787dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 1797dd05578SSam Protsenko 1807dd05578SSam Protsenko static const struct samsung_mux_clock top_mux_clks[] __initconst = { 1817dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 1827dd05578SSam Protsenko MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 1837dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 4, 1), 1847dd05578SSam Protsenko MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 1857dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 4, 1), 1867dd05578SSam Protsenko MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 1877dd05578SSam Protsenko PLL_CON0_PLL_MMC, 4, 1), 1887dd05578SSam Protsenko 189579839a9SSam Protsenko /* APM */ 190579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", 191579839a9SSam Protsenko mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), 192579839a9SSam Protsenko 1937dd05578SSam Protsenko /* CORE */ 1947dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 1957dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 1967dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 1977dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 1987dd05578SSam Protsenko MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, 1997dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), 2007dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, 2017dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), 2027dd05578SSam Protsenko 2037dd05578SSam Protsenko /* DPU */ 2047dd05578SSam Protsenko MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, 2057dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), 2067dd05578SSam Protsenko 2077dd05578SSam Protsenko /* HSI */ 2087dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, 2097dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), 2107dd05578SSam Protsenko MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, 2117dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), 2127dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, 2137dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), 2147dd05578SSam Protsenko 2157dd05578SSam Protsenko /* PERI */ 2167dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 2177dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 2187dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, 2197dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), 2207dd05578SSam Protsenko MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, 2217dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), 2227dd05578SSam Protsenko }; 2237dd05578SSam Protsenko 2247dd05578SSam Protsenko static const struct samsung_div_clock top_div_clks[] __initconst = { 2257dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 2267dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 2277dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 2287dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 2297dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 2307dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 2317dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 2327dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 2337dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 2347dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 2357dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 2367dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 2377dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 2387dd05578SSam Protsenko 239579839a9SSam Protsenko /* APM */ 240579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", 241579839a9SSam Protsenko "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), 242579839a9SSam Protsenko 2437dd05578SSam Protsenko /* CORE */ 2447dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 2457dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 2467dd05578SSam Protsenko DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 2477dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), 2487dd05578SSam Protsenko DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", 2497dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), 2507dd05578SSam Protsenko DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", 2517dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), 2527dd05578SSam Protsenko 2537dd05578SSam Protsenko /* DPU */ 2547dd05578SSam Protsenko DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", 2557dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 0, 4), 2567dd05578SSam Protsenko 2577dd05578SSam Protsenko /* HSI */ 2587dd05578SSam Protsenko DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", 2597dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), 2607dd05578SSam Protsenko DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", 2617dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), 2627dd05578SSam Protsenko DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", 2637dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), 2647dd05578SSam Protsenko 2657dd05578SSam Protsenko /* PERI */ 2667dd05578SSam Protsenko DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 2677dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 2687dd05578SSam Protsenko DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", 2697dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), 2707dd05578SSam Protsenko DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", 2717dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), 2727dd05578SSam Protsenko }; 2737dd05578SSam Protsenko 2747dd05578SSam Protsenko static const struct samsung_gate_clock top_gate_clks[] __initconst = { 2757dd05578SSam Protsenko /* CORE */ 2767dd05578SSam Protsenko GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 2777dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 2787dd05578SSam Protsenko GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 2797dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 2807dd05578SSam Protsenko GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", 2817dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), 2827dd05578SSam Protsenko GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", 2837dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), 2847dd05578SSam Protsenko 285579839a9SSam Protsenko /* APM */ 286579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", 287579839a9SSam Protsenko "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0), 288579839a9SSam Protsenko 2897dd05578SSam Protsenko /* DPU */ 2907dd05578SSam Protsenko GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", 2917dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), 2927dd05578SSam Protsenko 2937dd05578SSam Protsenko /* HSI */ 2947dd05578SSam Protsenko GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", 2957dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), 2967dd05578SSam Protsenko GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", 2977dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), 2987dd05578SSam Protsenko GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", 2997dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), 3007dd05578SSam Protsenko 3017dd05578SSam Protsenko /* PERI */ 3027dd05578SSam Protsenko GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 3037dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 3047dd05578SSam Protsenko GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", 3057dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), 3067dd05578SSam Protsenko GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", 3077dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), 3087dd05578SSam Protsenko }; 3097dd05578SSam Protsenko 3107dd05578SSam Protsenko static const struct samsung_cmu_info top_cmu_info __initconst = { 3117dd05578SSam Protsenko .pll_clks = top_pll_clks, 3127dd05578SSam Protsenko .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 3137dd05578SSam Protsenko .mux_clks = top_mux_clks, 3147dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 3157dd05578SSam Protsenko .div_clks = top_div_clks, 3167dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(top_div_clks), 3177dd05578SSam Protsenko .gate_clks = top_gate_clks, 3187dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 3197dd05578SSam Protsenko .nr_clk_ids = TOP_NR_CLK, 3207dd05578SSam Protsenko .clk_regs = top_clk_regs, 3217dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 3227dd05578SSam Protsenko }; 3237dd05578SSam Protsenko 3247dd05578SSam Protsenko static void __init exynos850_cmu_top_init(struct device_node *np) 3257dd05578SSam Protsenko { 326cfe238e4SDavid Virag exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 3277dd05578SSam Protsenko } 3287dd05578SSam Protsenko 329bcda841fSSam Protsenko /* Register CMU_TOP early, as it's a dependency for other early domains */ 3307dd05578SSam Protsenko CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", 3317dd05578SSam Protsenko exynos850_cmu_top_init); 3327dd05578SSam Protsenko 333579839a9SSam Protsenko /* ---- CMU_APM ------------------------------------------------------------- */ 334579839a9SSam Protsenko 335579839a9SSam Protsenko /* Register Offset definitions for CMU_APM (0x11800000) */ 336579839a9SSam Protsenko #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600 337579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610 338579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620 339579839a9SSam Protsenko #define PLL_CON0_MUX_DLL_USER 0x0630 340579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000 341579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004 342579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008 343579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800 344579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804 345579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808 346579839a9SSam Protsenko #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 347579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014 348bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018 349bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020 350579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024 351579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028 352579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034 353579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038 354579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc 355bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0 356579839a9SSam Protsenko 357579839a9SSam Protsenko static const unsigned long apm_clk_regs[] __initconst = { 358579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 359579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 360579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 361579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 362579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 363579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 364579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 365579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 366579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 367579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 368579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 369579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 370bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 371bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 372579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 373579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 374579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 375579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 376579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 377bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 378579839a9SSam Protsenko }; 379579839a9SSam Protsenko 380579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_APM */ 381579839a9SSam Protsenko PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" }; 382579839a9SSam Protsenko PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" }; 383579839a9SSam Protsenko PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" }; 384579839a9SSam Protsenko PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" }; 385579839a9SSam Protsenko PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" }; 386579839a9SSam Protsenko PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user", 387579839a9SSam Protsenko "mout_dll_user", "oscclk_rco_apm" }; 388579839a9SSam Protsenko PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" }; 389579839a9SSam Protsenko 390579839a9SSam Protsenko static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 391579839a9SSam Protsenko FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000), 392579839a9SSam Protsenko FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000), 393579839a9SSam Protsenko FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000), 394579839a9SSam Protsenko FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000), 395579839a9SSam Protsenko }; 396579839a9SSam Protsenko 397579839a9SSam Protsenko static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 398579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p, 399579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1), 400579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user", 401579839a9SSam Protsenko mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1), 402579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p, 403579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1), 404579839a9SSam Protsenko MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p, 405579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 4, 1), 406579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus", 407579839a9SSam Protsenko mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1), 408579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p, 409579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2), 410579839a9SSam Protsenko MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p, 411579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1), 412579839a9SSam Protsenko }; 413579839a9SSam Protsenko 414579839a9SSam Protsenko static const struct samsung_div_clock apm_div_clks[] __initconst = { 415579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus", 416579839a9SSam Protsenko "gout_clkcmu_chub_bus", 417579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3), 418579839a9SSam Protsenko DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus", 419579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3), 420579839a9SSam Protsenko DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus", 421579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3), 422579839a9SSam Protsenko }; 423579839a9SSam Protsenko 424579839a9SSam Protsenko static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 425579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus", 426579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0), 427579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus", 428579839a9SSam Protsenko "mout_clkcmu_chub_bus", 429579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0), 430579839a9SSam Protsenko GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus", 431579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0), 432579839a9SSam Protsenko GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus", 433579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0), 434579839a9SSam Protsenko GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus", 435579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0), 436579839a9SSam Protsenko GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c", 437579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0), 438579839a9SSam Protsenko GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus", 439579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0), 440bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 441bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus", 442bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, 443bc471d1fSSam Protsenko 0), 444bc471d1fSSam Protsenko GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", 445bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0), 446bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", 447bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), 448579839a9SSam Protsenko }; 449579839a9SSam Protsenko 450579839a9SSam Protsenko static const struct samsung_cmu_info apm_cmu_info __initconst = { 451579839a9SSam Protsenko .mux_clks = apm_mux_clks, 452579839a9SSam Protsenko .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 453579839a9SSam Protsenko .div_clks = apm_div_clks, 454579839a9SSam Protsenko .nr_div_clks = ARRAY_SIZE(apm_div_clks), 455579839a9SSam Protsenko .gate_clks = apm_gate_clks, 456579839a9SSam Protsenko .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 457579839a9SSam Protsenko .fixed_clks = apm_fixed_clks, 458579839a9SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 459579839a9SSam Protsenko .nr_clk_ids = APM_NR_CLK, 460579839a9SSam Protsenko .clk_regs = apm_clk_regs, 461579839a9SSam Protsenko .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 462579839a9SSam Protsenko .clk_name = "dout_clkcmu_apm_bus", 463579839a9SSam Protsenko }; 464579839a9SSam Protsenko 46562782ba8SSam Protsenko /* ---- CMU_CMGP ------------------------------------------------------------ */ 46662782ba8SSam Protsenko 46762782ba8SSam Protsenko /* Register Offset definitions for CMU_CMGP (0x11c00000) */ 46862782ba8SSam Protsenko #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000 46962782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004 47062782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008 47162782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800 47262782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804 47362782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808 47462782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c 47562782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 47662782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018 477bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040 47862782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044 47962782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048 48062782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c 48162782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050 48262782ba8SSam Protsenko 48362782ba8SSam Protsenko static const unsigned long cmgp_clk_regs[] __initconst = { 48462782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 48562782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 48662782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 48762782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 48862782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 48962782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 49062782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 49162782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 49262782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 493bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 49462782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 49562782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 49662782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 49762782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 49862782ba8SSam Protsenko }; 49962782ba8SSam Protsenko 50062782ba8SSam Protsenko /* List of parent clocks for Muxes in CMU_CMGP */ 50162782ba8SSam Protsenko PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 50262782ba8SSam Protsenko PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 50362782ba8SSam Protsenko PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" }; 50462782ba8SSam Protsenko 50562782ba8SSam Protsenko static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = { 50662782ba8SSam Protsenko FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000), 50762782ba8SSam Protsenko }; 50862782ba8SSam Protsenko 50962782ba8SSam Protsenko static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = { 51062782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p, 51162782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 0, 1), 51262782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, 51362782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1), 51462782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, 51562782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1), 51662782ba8SSam Protsenko }; 51762782ba8SSam Protsenko 51862782ba8SSam Protsenko static const struct samsung_div_clock cmgp_div_clks[] __initconst = { 51962782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus", 52062782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), 52162782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", 52262782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5), 52362782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", 52462782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5), 52562782ba8SSam Protsenko }; 52662782ba8SSam Protsenko 52762782ba8SSam Protsenko static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { 52862782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk", 52962782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 53062782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0), 53162782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk", 53262782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 53362782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0), 5346904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 53562782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk", 53662782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 5376904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0), 53862782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0", 53962782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0), 54062782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk", 54162782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 54262782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0), 54362782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1", 54462782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0), 54562782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", 54662782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 54762782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), 548bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk", 549bc471d1fSSam Protsenko "gout_clkcmu_cmgp_bus", 550bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0), 55162782ba8SSam Protsenko }; 55262782ba8SSam Protsenko 55362782ba8SSam Protsenko static const struct samsung_cmu_info cmgp_cmu_info __initconst = { 55462782ba8SSam Protsenko .mux_clks = cmgp_mux_clks, 55562782ba8SSam Protsenko .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks), 55662782ba8SSam Protsenko .div_clks = cmgp_div_clks, 55762782ba8SSam Protsenko .nr_div_clks = ARRAY_SIZE(cmgp_div_clks), 55862782ba8SSam Protsenko .gate_clks = cmgp_gate_clks, 55962782ba8SSam Protsenko .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks), 56062782ba8SSam Protsenko .fixed_clks = cmgp_fixed_clks, 56162782ba8SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks), 56262782ba8SSam Protsenko .nr_clk_ids = CMGP_NR_CLK, 56362782ba8SSam Protsenko .clk_regs = cmgp_clk_regs, 56462782ba8SSam Protsenko .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), 56562782ba8SSam Protsenko .clk_name = "gout_clkcmu_cmgp_bus", 56662782ba8SSam Protsenko }; 56762782ba8SSam Protsenko 5687dd05578SSam Protsenko /* ---- CMU_HSI ------------------------------------------------------------- */ 5697dd05578SSam Protsenko 5707dd05578SSam Protsenko /* Register Offset definitions for CMU_HSI (0x13400000) */ 5717dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 5727dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 5737dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 5747dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 5757dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 5767dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c 5777dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 5787dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 5797dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 5807dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 5817dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 5827dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c 5837dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 5847dd05578SSam Protsenko 5857dd05578SSam Protsenko static const unsigned long hsi_clk_regs[] __initconst = { 5867dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 5877dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 5887dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 5897dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 5907dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 5917dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 5927dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 5937dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 5947dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 5957dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 5967dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 5977dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 5987dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 5997dd05578SSam Protsenko }; 6007dd05578SSam Protsenko 601*dbaa27ccSSam Protsenko /* List of parent clocks for Muxes in CMU_HSI */ 6027dd05578SSam Protsenko PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" }; 6037dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" }; 6047dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" }; 6057dd05578SSam Protsenko PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" }; 6067dd05578SSam Protsenko 6077dd05578SSam Protsenko static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { 6087dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, 6097dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), 6107dd05578SSam Protsenko MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", 6117dd05578SSam Protsenko mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 6127dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 6137dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", 6147dd05578SSam Protsenko mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 6157dd05578SSam Protsenko 4, 1), 6167dd05578SSam Protsenko MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p, 6177dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1), 6187dd05578SSam Protsenko }; 6197dd05578SSam Protsenko 6207dd05578SSam Protsenko static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { 6217dd05578SSam Protsenko GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", 6227dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), 6237dd05578SSam Protsenko GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", 6247dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), 6257dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk", 6267dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), 6276904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 6287dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user", 6296904d7e5SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 6307dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", 6317dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), 6327dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 6337dd05578SSam Protsenko "mout_hsi_mmc_card_user", 6347dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), 6357dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", 6367dd05578SSam Protsenko "mout_hsi_bus_user", 6377dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), 6387dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", 6397dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), 6407dd05578SSam Protsenko GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", 6417dd05578SSam Protsenko "mout_hsi_bus_user", 6427dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), 6437dd05578SSam Protsenko }; 6447dd05578SSam Protsenko 6457dd05578SSam Protsenko static const struct samsung_cmu_info hsi_cmu_info __initconst = { 6467dd05578SSam Protsenko .mux_clks = hsi_mux_clks, 6477dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), 6487dd05578SSam Protsenko .gate_clks = hsi_gate_clks, 6497dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), 6507dd05578SSam Protsenko .nr_clk_ids = HSI_NR_CLK, 6517dd05578SSam Protsenko .clk_regs = hsi_clk_regs, 6527dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), 6537dd05578SSam Protsenko .clk_name = "dout_hsi_bus", 6547dd05578SSam Protsenko }; 6557dd05578SSam Protsenko 6567dd05578SSam Protsenko /* ---- CMU_PERI ------------------------------------------------------------ */ 6577dd05578SSam Protsenko 6587dd05578SSam Protsenko /* Register Offset definitions for CMU_PERI (0x10030000) */ 6597dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 6607dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610 6617dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620 6627dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 6637dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800 6647dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804 6657dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808 6667dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c 6677dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c 6687dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010 6697dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014 6707dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020 6717dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024 6727dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 6737dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c 6747dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030 6757dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034 6767dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038 6777dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c 6787dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040 6797dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044 6807dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048 6817dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c 6827dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050 6837dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054 6847dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c 6857dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064 6867dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c 6877dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0 6887dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4 6897dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 6907dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac 6917dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0 6927dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4 6937dd05578SSam Protsenko 6947dd05578SSam Protsenko static const unsigned long peri_clk_regs[] __initconst = { 6957dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 6967dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 6977dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 6987dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 6997dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 7007dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 7017dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 7027dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 7037dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 7047dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 7057dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 7067dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 7077dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 7087dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 7097dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 7107dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 7117dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 7127dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 7137dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 7147dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 7157dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 7167dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 7177dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 7187dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 7197dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 7207dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 7217dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 7227dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 7237dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 7247dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 7257dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 7267dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 7277dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 7287dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 7297dd05578SSam Protsenko }; 7307dd05578SSam Protsenko 7317dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_PERI */ 7327dd05578SSam Protsenko PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; 7337dd05578SSam Protsenko PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" }; 7347dd05578SSam Protsenko PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" }; 7357dd05578SSam Protsenko PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" }; 7367dd05578SSam Protsenko 7377dd05578SSam Protsenko static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 7387dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 7397dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 7407dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", 7417dd05578SSam Protsenko mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), 7427dd05578SSam Protsenko MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", 7437dd05578SSam Protsenko mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), 7447dd05578SSam Protsenko MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, 7457dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), 7467dd05578SSam Protsenko }; 7477dd05578SSam Protsenko 7487dd05578SSam Protsenko static const struct samsung_div_clock peri_div_clks[] __initconst = { 7497dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0", 7507dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5), 7517dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1", 7527dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), 7537dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", 7547dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), 7557dd05578SSam Protsenko DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", 7567dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), 7577dd05578SSam Protsenko }; 7587dd05578SSam Protsenko 7597dd05578SSam Protsenko static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 7607dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user", 7617dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0), 7627dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user", 7637dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0), 7647dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user", 7657dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0), 7667dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0", 7677dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0), 7687dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", 7697dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), 7707dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1", 7717dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0), 7727dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", 7737dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), 7747dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2", 7757dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0), 7767dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", 7777dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), 7787dd05578SSam Protsenko GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", 7797dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), 7807dd05578SSam Protsenko GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", 7817dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), 7827dd05578SSam Protsenko GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", 7837dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), 7847dd05578SSam Protsenko GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", 7857dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), 7867dd05578SSam Protsenko GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", 7877dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), 7887dd05578SSam Protsenko GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", 7897dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), 7907dd05578SSam Protsenko GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", 7917dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), 7927dd05578SSam Protsenko GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", 7937dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), 7947dd05578SSam Protsenko GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", 7957dd05578SSam Protsenko "mout_peri_bus_user", 7967dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), 7977dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", 7987dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), 7997dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", 8007dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), 8017dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", 8027dd05578SSam Protsenko "mout_peri_bus_user", 8037dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), 8047dd05578SSam Protsenko GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", 8057dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), 8067dd05578SSam Protsenko GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", 8077dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), 8087dd05578SSam Protsenko GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", 8097dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0), 8107dd05578SSam Protsenko GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", 8117dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0), 8126904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 8137dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk", 8147dd05578SSam Protsenko "mout_peri_bus_user", 8156904d7e5SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 8167dd05578SSam Protsenko }; 8177dd05578SSam Protsenko 8187dd05578SSam Protsenko static const struct samsung_cmu_info peri_cmu_info __initconst = { 8197dd05578SSam Protsenko .mux_clks = peri_mux_clks, 8207dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 8217dd05578SSam Protsenko .div_clks = peri_div_clks, 8227dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(peri_div_clks), 8237dd05578SSam Protsenko .gate_clks = peri_gate_clks, 8247dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 8257dd05578SSam Protsenko .nr_clk_ids = PERI_NR_CLK, 8267dd05578SSam Protsenko .clk_regs = peri_clk_regs, 8277dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 8287dd05578SSam Protsenko .clk_name = "dout_peri_bus", 8297dd05578SSam Protsenko }; 8307dd05578SSam Protsenko 831bcda841fSSam Protsenko static void __init exynos850_cmu_peri_init(struct device_node *np) 832bcda841fSSam Protsenko { 833cfe238e4SDavid Virag exynos_arm64_register_cmu(NULL, np, &peri_cmu_info); 834bcda841fSSam Protsenko } 835bcda841fSSam Protsenko 836bcda841fSSam Protsenko /* Register CMU_PERI early, as it's needed for MCT timer */ 837bcda841fSSam Protsenko CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", 838bcda841fSSam Protsenko exynos850_cmu_peri_init); 839bcda841fSSam Protsenko 8407dd05578SSam Protsenko /* ---- CMU_CORE ------------------------------------------------------------ */ 8417dd05578SSam Protsenko 8427dd05578SSam Protsenko /* Register Offset definitions for CMU_CORE (0x12000000) */ 8437dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 8447dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610 8457dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 8467dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630 8477dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 8487dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 8497dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 8507dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 851bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 8527dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 8537dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec 8547dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 8557dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c 856bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 8577dd05578SSam Protsenko 8587dd05578SSam Protsenko static const unsigned long core_clk_regs[] __initconst = { 8597dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 8607dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 8617dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 8627dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 8637dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 8647dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 8657dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 8667dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 867bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 8687dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 8697dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 8707dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 8717dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 872bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 8737dd05578SSam Protsenko }; 8747dd05578SSam Protsenko 8757dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_CORE */ 8767dd05578SSam Protsenko PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; 8777dd05578SSam Protsenko PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; 8787dd05578SSam Protsenko PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" }; 8797dd05578SSam Protsenko PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" }; 8807dd05578SSam Protsenko PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; 8817dd05578SSam Protsenko 8827dd05578SSam Protsenko static const struct samsung_mux_clock core_mux_clks[] __initconst = { 8837dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 8847dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 8857dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, 8867dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), 8877dd05578SSam Protsenko MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", 8887dd05578SSam Protsenko mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 8897dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 8907dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p, 8917dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1), 8927dd05578SSam Protsenko MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, 8937dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), 8947dd05578SSam Protsenko }; 8957dd05578SSam Protsenko 8967dd05578SSam Protsenko static const struct samsung_div_clock core_div_clks[] __initconst = { 8977dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 8987dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 8997dd05578SSam Protsenko }; 9007dd05578SSam Protsenko 9017dd05578SSam Protsenko static const struct samsung_gate_clock core_gate_clks[] __initconst = { 9026904d7e5SSam Protsenko /* CCI (interconnect) clock must be always running */ 9037dd05578SSam Protsenko GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", 9046904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0), 9056904d7e5SSam Protsenko /* GIC (interrupt controller) clock must be always running */ 9067dd05578SSam Protsenko GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic", 9076904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0), 9087dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", 9097dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), 9107dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 9117dd05578SSam Protsenko "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 9127dd05578SSam Protsenko 21, CLK_SET_RATE_PARENT, 0), 9137dd05578SSam Protsenko GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", 9147dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), 9157dd05578SSam Protsenko GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", 9167dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), 917bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 918bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp", 919bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0), 920bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk", 921bc471d1fSSam Protsenko "dout_core_busp", 922bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0), 9237dd05578SSam Protsenko }; 9247dd05578SSam Protsenko 9257dd05578SSam Protsenko static const struct samsung_cmu_info core_cmu_info __initconst = { 9267dd05578SSam Protsenko .mux_clks = core_mux_clks, 9277dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 9287dd05578SSam Protsenko .div_clks = core_div_clks, 9297dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(core_div_clks), 9307dd05578SSam Protsenko .gate_clks = core_gate_clks, 9317dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 9327dd05578SSam Protsenko .nr_clk_ids = CORE_NR_CLK, 9337dd05578SSam Protsenko .clk_regs = core_clk_regs, 9347dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 9357dd05578SSam Protsenko .clk_name = "dout_core_bus", 9367dd05578SSam Protsenko }; 9377dd05578SSam Protsenko 9387dd05578SSam Protsenko /* ---- CMU_DPU ------------------------------------------------------------- */ 9397dd05578SSam Protsenko 9407dd05578SSam Protsenko /* Register Offset definitions for CMU_DPU (0x13000000) */ 9417dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600 9427dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 9437dd05578SSam Protsenko #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004 9447dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010 9457dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014 9467dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018 9477dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028 9487dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c 9497dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038 9507dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c 9517dd05578SSam Protsenko 9527dd05578SSam Protsenko static const unsigned long dpu_clk_regs[] __initconst = { 9537dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 9547dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 9557dd05578SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 9567dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 9577dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 9587dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 9597dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 9607dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 9617dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 9627dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 9637dd05578SSam Protsenko }; 9647dd05578SSam Protsenko 965*dbaa27ccSSam Protsenko /* List of parent clocks for Muxes in CMU_DPU */ 9667dd05578SSam Protsenko PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" }; 9677dd05578SSam Protsenko 9687dd05578SSam Protsenko static const struct samsung_mux_clock dpu_mux_clks[] __initconst = { 9697dd05578SSam Protsenko MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p, 9707dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1), 9717dd05578SSam Protsenko }; 9727dd05578SSam Protsenko 9737dd05578SSam Protsenko static const struct samsung_div_clock dpu_div_clks[] __initconst = { 9747dd05578SSam Protsenko DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user", 9757dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), 9767dd05578SSam Protsenko }; 9777dd05578SSam Protsenko 9787dd05578SSam Protsenko static const struct samsung_gate_clock dpu_gate_clks[] __initconst = { 9796904d7e5SSam Protsenko /* TODO: Should be enabled in DSIM driver */ 9807dd05578SSam Protsenko GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk", 9816904d7e5SSam Protsenko "dout_dpu_busp", 9826904d7e5SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0), 9837dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user", 9847dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0), 9857dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user", 9867dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0), 9877dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user", 9887dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0), 9897dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user", 9907dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0), 9917dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp", 9927dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0), 9937dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user", 9947dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0), 9957dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp", 9967dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0), 9977dd05578SSam Protsenko }; 9987dd05578SSam Protsenko 9997dd05578SSam Protsenko static const struct samsung_cmu_info dpu_cmu_info __initconst = { 10007dd05578SSam Protsenko .mux_clks = dpu_mux_clks, 10017dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks), 10027dd05578SSam Protsenko .div_clks = dpu_div_clks, 10037dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(dpu_div_clks), 10047dd05578SSam Protsenko .gate_clks = dpu_gate_clks, 10057dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), 10067dd05578SSam Protsenko .nr_clk_ids = DPU_NR_CLK, 10077dd05578SSam Protsenko .clk_regs = dpu_clk_regs, 10087dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), 10097dd05578SSam Protsenko .clk_name = "dout_dpu", 10107dd05578SSam Protsenko }; 10117dd05578SSam Protsenko 10127dd05578SSam Protsenko /* ---- platform_driver ----------------------------------------------------- */ 10137dd05578SSam Protsenko 10147dd05578SSam Protsenko static int __init exynos850_cmu_probe(struct platform_device *pdev) 10157dd05578SSam Protsenko { 10167dd05578SSam Protsenko const struct samsung_cmu_info *info; 10177dd05578SSam Protsenko struct device *dev = &pdev->dev; 10187dd05578SSam Protsenko 10197dd05578SSam Protsenko info = of_device_get_match_data(dev); 1020cfe238e4SDavid Virag exynos_arm64_register_cmu(dev, dev->of_node, info); 10217dd05578SSam Protsenko 10227dd05578SSam Protsenko return 0; 10237dd05578SSam Protsenko } 10247dd05578SSam Protsenko 10257dd05578SSam Protsenko static const struct of_device_id exynos850_cmu_of_match[] = { 10267dd05578SSam Protsenko { 1027579839a9SSam Protsenko .compatible = "samsung,exynos850-cmu-apm", 1028579839a9SSam Protsenko .data = &apm_cmu_info, 1029579839a9SSam Protsenko }, { 103062782ba8SSam Protsenko .compatible = "samsung,exynos850-cmu-cmgp", 103162782ba8SSam Protsenko .data = &cmgp_cmu_info, 103262782ba8SSam Protsenko }, { 10337dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-hsi", 10347dd05578SSam Protsenko .data = &hsi_cmu_info, 10357dd05578SSam Protsenko }, { 10367dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-core", 10377dd05578SSam Protsenko .data = &core_cmu_info, 10387dd05578SSam Protsenko }, { 10397dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-dpu", 10407dd05578SSam Protsenko .data = &dpu_cmu_info, 10417dd05578SSam Protsenko }, { 10427dd05578SSam Protsenko }, 10437dd05578SSam Protsenko }; 10447dd05578SSam Protsenko 10457dd05578SSam Protsenko static struct platform_driver exynos850_cmu_driver __refdata = { 10467dd05578SSam Protsenko .driver = { 10477dd05578SSam Protsenko .name = "exynos850-cmu", 10487dd05578SSam Protsenko .of_match_table = exynos850_cmu_of_match, 10497dd05578SSam Protsenko .suppress_bind_attrs = true, 10507dd05578SSam Protsenko }, 10517dd05578SSam Protsenko .probe = exynos850_cmu_probe, 10527dd05578SSam Protsenko }; 10537dd05578SSam Protsenko 10547dd05578SSam Protsenko static int __init exynos850_cmu_init(void) 10557dd05578SSam Protsenko { 10567dd05578SSam Protsenko return platform_driver_register(&exynos850_cmu_driver); 10577dd05578SSam Protsenko } 10587dd05578SSam Protsenko core_initcall(exynos850_cmu_init); 1059