17dd05578SSam Protsenko // SPDX-License-Identifier: GPL-2.0-only 27dd05578SSam Protsenko /* 37dd05578SSam Protsenko * Copyright (C) 2021 Linaro Ltd. 47dd05578SSam Protsenko * Author: Sam Protsenko <semen.protsenko@linaro.org> 57dd05578SSam Protsenko * 67dd05578SSam Protsenko * Common Clock Framework support for Exynos850 SoC. 77dd05578SSam Protsenko */ 87dd05578SSam Protsenko 97dd05578SSam Protsenko #include <linux/clk.h> 107dd05578SSam Protsenko #include <linux/clk-provider.h> 117dd05578SSam Protsenko #include <linux/of.h> 127dd05578SSam Protsenko #include <linux/of_device.h> 137dd05578SSam Protsenko #include <linux/platform_device.h> 147dd05578SSam Protsenko 157dd05578SSam Protsenko #include <dt-bindings/clock/exynos850.h> 167dd05578SSam Protsenko 177dd05578SSam Protsenko #include "clk.h" 18cfe238e4SDavid Virag #include "clk-exynos-arm64.h" 19bcda841fSSam Protsenko 207dd05578SSam Protsenko /* ---- CMU_TOP ------------------------------------------------------------- */ 217dd05578SSam Protsenko 227dd05578SSam Protsenko /* Register Offset definitions for CMU_TOP (0x120e0000) */ 237dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_MMC 0x0000 247dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED0 0x0004 257dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED1 0x0008 267dd05578SSam Protsenko #define PLL_CON0_PLL_MMC 0x0100 277dd05578SSam Protsenko #define PLL_CON3_PLL_MMC 0x010c 287dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED0 0x0140 297dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED0 0x014c 307dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED1 0x0180 317dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED1 0x018c 32579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000 33b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004 347dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 357dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 367dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c 377dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 387dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 397dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c 407dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 417dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 42*bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048 43*bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c 44*bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050 45*bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054 467dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 477dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 487dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 49579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c 50b73fd95dSSam Protsenko #define CLK_CON_DIV_CLKCMU_AUD 0x1810 517dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 527dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 537dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 547dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c 557dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_DPU 0x1840 567dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 577dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c 587dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 59*bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854 60*bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858 61*bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c 62*bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860 637dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c 647dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 657dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 667dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c 677dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 687dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 697dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 707dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c 717dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 72579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008 73b73fd95dSSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c 747dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 757dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 767dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 777dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 787dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c 797dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 807dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 817dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c 82*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050 83*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054 84*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058 85*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c 867dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 877dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 887dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 897dd05578SSam Protsenko 907dd05578SSam Protsenko static const unsigned long top_clk_regs[] __initconst = { 917dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, 927dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, 937dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, 947dd05578SSam Protsenko PLL_CON0_PLL_MMC, 957dd05578SSam Protsenko PLL_CON3_PLL_MMC, 967dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 977dd05578SSam Protsenko PLL_CON3_PLL_SHARED0, 987dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 997dd05578SSam Protsenko PLL_CON3_PLL_SHARED1, 100579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 101b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLKCMU_AUD, 1027dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 1037dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 1047dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 1057dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 1067dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 1077dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 1087dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 1097dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 110*bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 111*bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 112*bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 113*bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 1147dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 1157dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 1167dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 117579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_APM_BUS, 118b73fd95dSSam Protsenko CLK_CON_DIV_CLKCMU_AUD, 1197dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 1207dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 1217dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 1227dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 1237dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 1247dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 1257dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 1267dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 127*bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_BUS, 128*bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_GDC, 129*bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_ITP, 130*bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_VRA, 1317dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 1327dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 1337dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 1347dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 1357dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 1367dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 1377dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 1387dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 1397dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 140579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 141b73fd95dSSam Protsenko CLK_CON_GAT_GATE_CLKCMU_AUD, 1427dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 1437dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 1447dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 1457dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 1467dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 1477dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 1487dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 1497dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 150*bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 151*bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 152*bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 153*bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 1547dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 1557dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 1567dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 1577dd05578SSam Protsenko }; 1587dd05578SSam Protsenko 1597dd05578SSam Protsenko /* 1607dd05578SSam Protsenko * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set 1617dd05578SSam Protsenko * for those PLLs by default, so set_rate operation would fail. 1627dd05578SSam Protsenko */ 1637dd05578SSam Protsenko static const struct samsung_pll_clock top_pll_clks[] __initconst = { 1647dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 1657dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 1667dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 1677dd05578SSam Protsenko NULL), 1687dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 1697dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 1707dd05578SSam Protsenko NULL), 1717dd05578SSam Protsenko PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 1727dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 1737dd05578SSam Protsenko }; 1747dd05578SSam Protsenko 1757dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP */ 1767dd05578SSam Protsenko PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 1777dd05578SSam Protsenko PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 1787dd05578SSam Protsenko PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 179579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */ 180579839a9SSam Protsenko PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" }; 181b73fd95dSSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */ 182b73fd95dSSam Protsenko PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2", 183b73fd95dSSam Protsenko "dout_shared1_div2", "dout_shared0_div3" }; 1847dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 1857dd05578SSam Protsenko PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", 1867dd05578SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 1877dd05578SSam Protsenko PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 1887dd05578SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 1897dd05578SSam Protsenko PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", 1907dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 1917dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 1927dd05578SSam Protsenko "oscclk", "oscclk" }; 1937dd05578SSam Protsenko PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", 1947dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 1957dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ 1967dd05578SSam Protsenko PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 1977dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", 1987dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 1997dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 2007dd05578SSam Protsenko "oscclk", "oscclk" }; 2017dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4", 2027dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 203*bf3a4c51SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */ 204*bf3a4c51SSam Protsenko PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", 205*bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 206*bf3a4c51SSam Protsenko PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2", 207*bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 208*bf3a4c51SSam Protsenko PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2", 209*bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 210*bf3a4c51SSam Protsenko PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2", 211*bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 2127dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 2137dd05578SSam Protsenko PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 2147dd05578SSam Protsenko PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4", 2157dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2167dd05578SSam Protsenko PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4", 2177dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2187dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ 2197dd05578SSam Protsenko PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3", 2207dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 2217dd05578SSam Protsenko 2227dd05578SSam Protsenko static const struct samsung_mux_clock top_mux_clks[] __initconst = { 2237dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 2247dd05578SSam Protsenko MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 2257dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 4, 1), 2267dd05578SSam Protsenko MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 2277dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 4, 1), 2287dd05578SSam Protsenko MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 2297dd05578SSam Protsenko PLL_CON0_PLL_MMC, 4, 1), 2307dd05578SSam Protsenko 231579839a9SSam Protsenko /* APM */ 232579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", 233579839a9SSam Protsenko mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), 234579839a9SSam Protsenko 235b73fd95dSSam Protsenko /* AUD */ 236b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p, 237b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2), 238b73fd95dSSam Protsenko 2397dd05578SSam Protsenko /* CORE */ 2407dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 2417dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 2427dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 2437dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 2447dd05578SSam Protsenko MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, 2457dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), 2467dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, 2477dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), 2487dd05578SSam Protsenko 2497dd05578SSam Protsenko /* DPU */ 2507dd05578SSam Protsenko MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, 2517dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), 2527dd05578SSam Protsenko 2537dd05578SSam Protsenko /* HSI */ 2547dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, 2557dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), 2567dd05578SSam Protsenko MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, 2577dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), 2587dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, 2597dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), 2607dd05578SSam Protsenko 261*bf3a4c51SSam Protsenko /* IS */ 262*bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p, 263*bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2), 264*bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p, 265*bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2), 266*bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p, 267*bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2), 268*bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p, 269*bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2), 270*bf3a4c51SSam Protsenko 2717dd05578SSam Protsenko /* PERI */ 2727dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 2737dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 2747dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, 2757dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), 2767dd05578SSam Protsenko MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, 2777dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), 2787dd05578SSam Protsenko }; 2797dd05578SSam Protsenko 2807dd05578SSam Protsenko static const struct samsung_div_clock top_div_clks[] __initconst = { 2817dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 2827dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 2837dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 2847dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 2857dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 2867dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 2877dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 2887dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 2897dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 2907dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 2917dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 2927dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 2937dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 2947dd05578SSam Protsenko 295579839a9SSam Protsenko /* APM */ 296579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", 297579839a9SSam Protsenko "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), 298579839a9SSam Protsenko 299b73fd95dSSam Protsenko /* AUD */ 300b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud", 301b73fd95dSSam Protsenko CLK_CON_DIV_CLKCMU_AUD, 0, 4), 302b73fd95dSSam Protsenko 3037dd05578SSam Protsenko /* CORE */ 3047dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 3057dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 3067dd05578SSam Protsenko DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 3077dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), 3087dd05578SSam Protsenko DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", 3097dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), 3107dd05578SSam Protsenko DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", 3117dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), 3127dd05578SSam Protsenko 3137dd05578SSam Protsenko /* DPU */ 3147dd05578SSam Protsenko DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", 3157dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 0, 4), 3167dd05578SSam Protsenko 3177dd05578SSam Protsenko /* HSI */ 3187dd05578SSam Protsenko DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", 3197dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), 3207dd05578SSam Protsenko DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", 3217dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), 3227dd05578SSam Protsenko DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", 3237dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), 3247dd05578SSam Protsenko 325*bf3a4c51SSam Protsenko /* IS */ 326*bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus", 327*bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4), 328*bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp", 329*bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4), 330*bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra", 331*bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4), 332*bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc", 333*bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4), 334*bf3a4c51SSam Protsenko 3357dd05578SSam Protsenko /* PERI */ 3367dd05578SSam Protsenko DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 3377dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 3387dd05578SSam Protsenko DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", 3397dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), 3407dd05578SSam Protsenko DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", 3417dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), 3427dd05578SSam Protsenko }; 3437dd05578SSam Protsenko 3447dd05578SSam Protsenko static const struct samsung_gate_clock top_gate_clks[] __initconst = { 3457dd05578SSam Protsenko /* CORE */ 3467dd05578SSam Protsenko GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 3477dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 3487dd05578SSam Protsenko GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 3497dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 3507dd05578SSam Protsenko GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", 3517dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), 3527dd05578SSam Protsenko GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", 3537dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), 3547dd05578SSam Protsenko 355579839a9SSam Protsenko /* APM */ 356579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", 357579839a9SSam Protsenko "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0), 358579839a9SSam Protsenko 359b73fd95dSSam Protsenko /* AUD */ 360b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud", 361b73fd95dSSam Protsenko CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0), 362b73fd95dSSam Protsenko 3637dd05578SSam Protsenko /* DPU */ 3647dd05578SSam Protsenko GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", 3657dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), 3667dd05578SSam Protsenko 3677dd05578SSam Protsenko /* HSI */ 3687dd05578SSam Protsenko GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", 3697dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), 3707dd05578SSam Protsenko GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", 3717dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), 3727dd05578SSam Protsenko GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", 3737dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), 3747dd05578SSam Protsenko 375*bf3a4c51SSam Protsenko /* IS */ 376*bf3a4c51SSam Protsenko /* TODO: These clocks have to be always enabled to access CMU_IS regs */ 377*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus", 378*bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0), 379*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp", 380*bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0), 381*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra", 382*bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0), 383*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc", 384*bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0), 385*bf3a4c51SSam Protsenko 3867dd05578SSam Protsenko /* PERI */ 3877dd05578SSam Protsenko GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 3887dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 3897dd05578SSam Protsenko GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", 3907dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), 3917dd05578SSam Protsenko GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", 3927dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), 3937dd05578SSam Protsenko }; 3947dd05578SSam Protsenko 3957dd05578SSam Protsenko static const struct samsung_cmu_info top_cmu_info __initconst = { 3967dd05578SSam Protsenko .pll_clks = top_pll_clks, 3977dd05578SSam Protsenko .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 3987dd05578SSam Protsenko .mux_clks = top_mux_clks, 3997dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 4007dd05578SSam Protsenko .div_clks = top_div_clks, 4017dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(top_div_clks), 4027dd05578SSam Protsenko .gate_clks = top_gate_clks, 4037dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 4047dd05578SSam Protsenko .nr_clk_ids = TOP_NR_CLK, 4057dd05578SSam Protsenko .clk_regs = top_clk_regs, 4067dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 4077dd05578SSam Protsenko }; 4087dd05578SSam Protsenko 4097dd05578SSam Protsenko static void __init exynos850_cmu_top_init(struct device_node *np) 4107dd05578SSam Protsenko { 411cfe238e4SDavid Virag exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 4127dd05578SSam Protsenko } 4137dd05578SSam Protsenko 414bcda841fSSam Protsenko /* Register CMU_TOP early, as it's a dependency for other early domains */ 4157dd05578SSam Protsenko CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", 4167dd05578SSam Protsenko exynos850_cmu_top_init); 4177dd05578SSam Protsenko 418579839a9SSam Protsenko /* ---- CMU_APM ------------------------------------------------------------- */ 419579839a9SSam Protsenko 420579839a9SSam Protsenko /* Register Offset definitions for CMU_APM (0x11800000) */ 421579839a9SSam Protsenko #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600 422579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610 423579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620 424579839a9SSam Protsenko #define PLL_CON0_MUX_DLL_USER 0x0630 425579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000 426579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004 427579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008 428579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800 429579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804 430579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808 431579839a9SSam Protsenko #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 432579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014 433bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018 434bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020 435579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024 436579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028 437579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034 438579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038 439579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc 440bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0 441579839a9SSam Protsenko 442579839a9SSam Protsenko static const unsigned long apm_clk_regs[] __initconst = { 443579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 444579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 445579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 446579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 447579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 448579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 449579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 450579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 451579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 452579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 453579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 454579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 455bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 456bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 457579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 458579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 459579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 460579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 461579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 462bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 463579839a9SSam Protsenko }; 464579839a9SSam Protsenko 465579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_APM */ 466579839a9SSam Protsenko PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" }; 467579839a9SSam Protsenko PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" }; 468579839a9SSam Protsenko PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" }; 469579839a9SSam Protsenko PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" }; 470579839a9SSam Protsenko PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" }; 471579839a9SSam Protsenko PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user", 472579839a9SSam Protsenko "mout_dll_user", "oscclk_rco_apm" }; 473579839a9SSam Protsenko PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" }; 474579839a9SSam Protsenko 475579839a9SSam Protsenko static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 476579839a9SSam Protsenko FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000), 477579839a9SSam Protsenko FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000), 478579839a9SSam Protsenko FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000), 479579839a9SSam Protsenko FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000), 480579839a9SSam Protsenko }; 481579839a9SSam Protsenko 482579839a9SSam Protsenko static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 483579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p, 484579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1), 485579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user", 486579839a9SSam Protsenko mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1), 487579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p, 488579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1), 489579839a9SSam Protsenko MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p, 490579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 4, 1), 491579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus", 492579839a9SSam Protsenko mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1), 493579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p, 494579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2), 495579839a9SSam Protsenko MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p, 496579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1), 497579839a9SSam Protsenko }; 498579839a9SSam Protsenko 499579839a9SSam Protsenko static const struct samsung_div_clock apm_div_clks[] __initconst = { 500579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus", 501579839a9SSam Protsenko "gout_clkcmu_chub_bus", 502579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3), 503579839a9SSam Protsenko DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus", 504579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3), 505579839a9SSam Protsenko DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus", 506579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3), 507579839a9SSam Protsenko }; 508579839a9SSam Protsenko 509579839a9SSam Protsenko static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 510579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus", 511579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0), 512579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus", 513579839a9SSam Protsenko "mout_clkcmu_chub_bus", 514579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0), 515579839a9SSam Protsenko GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus", 516579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0), 517579839a9SSam Protsenko GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus", 518579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0), 519579839a9SSam Protsenko GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus", 520579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0), 521579839a9SSam Protsenko GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c", 522579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0), 523579839a9SSam Protsenko GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus", 524579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0), 525bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 526bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus", 527bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, 528bc471d1fSSam Protsenko 0), 529bc471d1fSSam Protsenko GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", 530bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0), 531bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", 532bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), 533579839a9SSam Protsenko }; 534579839a9SSam Protsenko 535579839a9SSam Protsenko static const struct samsung_cmu_info apm_cmu_info __initconst = { 536579839a9SSam Protsenko .mux_clks = apm_mux_clks, 537579839a9SSam Protsenko .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 538579839a9SSam Protsenko .div_clks = apm_div_clks, 539579839a9SSam Protsenko .nr_div_clks = ARRAY_SIZE(apm_div_clks), 540579839a9SSam Protsenko .gate_clks = apm_gate_clks, 541579839a9SSam Protsenko .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 542579839a9SSam Protsenko .fixed_clks = apm_fixed_clks, 543579839a9SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 544579839a9SSam Protsenko .nr_clk_ids = APM_NR_CLK, 545579839a9SSam Protsenko .clk_regs = apm_clk_regs, 546579839a9SSam Protsenko .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 547579839a9SSam Protsenko .clk_name = "dout_clkcmu_apm_bus", 548579839a9SSam Protsenko }; 549579839a9SSam Protsenko 550b73fd95dSSam Protsenko /* ---- CMU_AUD ------------------------------------------------------------- */ 551b73fd95dSSam Protsenko 552b73fd95dSSam Protsenko #define PLL_LOCKTIME_PLL_AUD 0x0000 553b73fd95dSSam Protsenko #define PLL_CON0_PLL_AUD 0x0100 554b73fd95dSSam Protsenko #define PLL_CON3_PLL_AUD 0x010c 555b73fd95dSSam Protsenko #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600 556b73fd95dSSam Protsenko #define PLL_CON0_MUX_TICK_USB_USER 0x0610 557b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000 558b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004 559b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008 560b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c 561b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010 562b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014 563b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018 564b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c 565b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020 566b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024 567b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800 568b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804 569b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808 570b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c 571b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810 572b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814 573b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818 574b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c 575b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820 576b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824 577b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828 578b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c 579b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830 580b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834 581b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838 582b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c 583b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840 584b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000 585b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004 586b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008 587b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c 588b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010 589b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 590b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 591b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c 592b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 593b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c 594b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 595b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054 596b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058 597b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c 598b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070 599b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074 600b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088 601b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c 602b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4 603b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8 604b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc 605b73fd95dSSam Protsenko 606b73fd95dSSam Protsenko static const unsigned long aud_clk_regs[] __initconst = { 607b73fd95dSSam Protsenko PLL_LOCKTIME_PLL_AUD, 608b73fd95dSSam Protsenko PLL_CON0_PLL_AUD, 609b73fd95dSSam Protsenko PLL_CON3_PLL_AUD, 610b73fd95dSSam Protsenko PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 611b73fd95dSSam Protsenko PLL_CON0_MUX_TICK_USB_USER, 612b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU, 613b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 614b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_FM, 615b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 616b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 617b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 618b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 619b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 620b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 621b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 622b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_MCLK, 623b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 624b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSD, 625b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSP, 626b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CNT, 627b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU, 628b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 629b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 630b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM, 631b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 632b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 633b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 634b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 635b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 636b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 637b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 638b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 639b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 640b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 641b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 642b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 643b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 644b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 645b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 646b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 647b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 648b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 649b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 650b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 651b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 652b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 653b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 654b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 655b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 656b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 657b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 658b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 659b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 660b73fd95dSSam Protsenko }; 661b73fd95dSSam Protsenko 662b73fd95dSSam Protsenko /* List of parent clocks for Muxes in CMU_AUD */ 663b73fd95dSSam Protsenko PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" }; 664b73fd95dSSam Protsenko PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" }; 665b73fd95dSSam Protsenko PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" }; 666b73fd95dSSam Protsenko PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" }; 667b73fd95dSSam Protsenko PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" }; 668b73fd95dSSam Protsenko PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" }; 669b73fd95dSSam Protsenko PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" }; 670b73fd95dSSam Protsenko PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" }; 671b73fd95dSSam Protsenko PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" }; 672b73fd95dSSam Protsenko PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" }; 673b73fd95dSSam Protsenko PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" }; 674b73fd95dSSam Protsenko PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" }; 675b73fd95dSSam Protsenko PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" }; 676b73fd95dSSam Protsenko 677b73fd95dSSam Protsenko /* 678b73fd95dSSam Protsenko * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set 679b73fd95dSSam Protsenko * for that PLL by default, so set_rate operation would fail. 680b73fd95dSSam Protsenko */ 681b73fd95dSSam Protsenko static const struct samsung_pll_clock aud_pll_clks[] __initconst = { 682b73fd95dSSam Protsenko PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 683b73fd95dSSam Protsenko PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL), 684b73fd95dSSam Protsenko }; 685b73fd95dSSam Protsenko 686b73fd95dSSam Protsenko static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { 687b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000), 688b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000), 689b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000), 690b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000), 691b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000), 692b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000), 693b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000), 694b73fd95dSSam Protsenko FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000), 695b73fd95dSSam Protsenko }; 696b73fd95dSSam Protsenko 697b73fd95dSSam Protsenko static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 698b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, 699b73fd95dSSam Protsenko PLL_CON0_PLL_AUD, 4, 1), 700b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p, 701b73fd95dSSam Protsenko PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1), 702b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user", 703b73fd95dSSam Protsenko mout_aud_tick_usb_user_p, 704b73fd95dSSam Protsenko PLL_CON0_MUX_TICK_USB_USER, 4, 1), 705b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p, 706b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1), 707b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p, 708b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1), 709b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p, 710b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1), 711b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p, 712b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1), 713b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p, 714b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1), 715b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p, 716b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1), 717b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p, 718b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1), 719b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p, 720b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1), 721b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p, 722b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1), 723b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p, 724b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1), 725b73fd95dSSam Protsenko }; 726b73fd95dSSam Protsenko 727b73fd95dSSam Protsenko static const struct samsung_div_clock aud_div_clks[] __initconst = { 728b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll", 729b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4), 730b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll", 731b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4), 732b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll", 733b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4), 734b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll", 735b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9), 736b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch", 737b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3), 738b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg", 739b73fd95dSSam Protsenko "mout_aud_cpu_hch", 740b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3), 741b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif", 742b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2), 743b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif", 744b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10), 745b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif", 746b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10), 747b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif", 748b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10), 749b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif", 750b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10), 751b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif", 752b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10), 753b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif", 754b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10), 755b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif", 756b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10), 757b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif", 758b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10), 759b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user", 760b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1), 761b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm", 762b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10), 763b73fd95dSSam Protsenko }; 764b73fd95dSSam Protsenko 765b73fd95dSSam Protsenko static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 766b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch", 767b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), 768b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk", 769b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0), 770b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg", 771b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0), 772b73fd95dSSam Protsenko /* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */ 773b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd", 774b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0), 775b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd", 776b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0), 777b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd", 778b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0), 779b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd", 780b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0), 781b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd", 782b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0), 783b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd", 784b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0), 785b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd", 786b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0), 787b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp", 788b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0), 789b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk", 790b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0), 791b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt", 792b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0), 793b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0", 794b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0), 795b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1", 796b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0), 797b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2", 798b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0), 799b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3", 800b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0), 801b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4", 802b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0), 803b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5", 804b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0), 805b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6", 806b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0), 807b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm", 808b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0), 809b73fd95dSSam Protsenko }; 810b73fd95dSSam Protsenko 811b73fd95dSSam Protsenko static const struct samsung_cmu_info aud_cmu_info __initconst = { 812b73fd95dSSam Protsenko .pll_clks = aud_pll_clks, 813b73fd95dSSam Protsenko .nr_pll_clks = ARRAY_SIZE(aud_pll_clks), 814b73fd95dSSam Protsenko .mux_clks = aud_mux_clks, 815b73fd95dSSam Protsenko .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 816b73fd95dSSam Protsenko .div_clks = aud_div_clks, 817b73fd95dSSam Protsenko .nr_div_clks = ARRAY_SIZE(aud_div_clks), 818b73fd95dSSam Protsenko .gate_clks = aud_gate_clks, 819b73fd95dSSam Protsenko .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 820b73fd95dSSam Protsenko .fixed_clks = aud_fixed_clks, 821b73fd95dSSam Protsenko .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), 822b73fd95dSSam Protsenko .nr_clk_ids = AUD_NR_CLK, 823b73fd95dSSam Protsenko .clk_regs = aud_clk_regs, 824b73fd95dSSam Protsenko .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 825b73fd95dSSam Protsenko .clk_name = "dout_aud", 826b73fd95dSSam Protsenko }; 827b73fd95dSSam Protsenko 82862782ba8SSam Protsenko /* ---- CMU_CMGP ------------------------------------------------------------ */ 82962782ba8SSam Protsenko 83062782ba8SSam Protsenko /* Register Offset definitions for CMU_CMGP (0x11c00000) */ 83162782ba8SSam Protsenko #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000 83262782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004 83362782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008 83462782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800 83562782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804 83662782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808 83762782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c 83862782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 83962782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018 840bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040 84162782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044 84262782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048 84362782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c 84462782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050 84562782ba8SSam Protsenko 84662782ba8SSam Protsenko static const unsigned long cmgp_clk_regs[] __initconst = { 84762782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 84862782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 84962782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 85062782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 85162782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 85262782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 85362782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 85462782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 85562782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 856bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 85762782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 85862782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 85962782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 86062782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 86162782ba8SSam Protsenko }; 86262782ba8SSam Protsenko 86362782ba8SSam Protsenko /* List of parent clocks for Muxes in CMU_CMGP */ 86462782ba8SSam Protsenko PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 86562782ba8SSam Protsenko PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 86662782ba8SSam Protsenko PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" }; 86762782ba8SSam Protsenko 86862782ba8SSam Protsenko static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = { 86962782ba8SSam Protsenko FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000), 87062782ba8SSam Protsenko }; 87162782ba8SSam Protsenko 87262782ba8SSam Protsenko static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = { 87362782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p, 87462782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 0, 1), 87562782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, 87662782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1), 87762782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, 87862782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1), 87962782ba8SSam Protsenko }; 88062782ba8SSam Protsenko 88162782ba8SSam Protsenko static const struct samsung_div_clock cmgp_div_clks[] __initconst = { 88262782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus", 88362782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), 88462782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", 88562782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5), 88662782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", 88762782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5), 88862782ba8SSam Protsenko }; 88962782ba8SSam Protsenko 89062782ba8SSam Protsenko static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { 89162782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk", 89262782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 89362782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0), 89462782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk", 89562782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 89662782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0), 8976904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 89862782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk", 89962782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 9006904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0), 90162782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0", 90262782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0), 90362782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk", 90462782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 90562782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0), 90662782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1", 90762782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0), 90862782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", 90962782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 91062782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), 911bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk", 912bc471d1fSSam Protsenko "gout_clkcmu_cmgp_bus", 913bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0), 91462782ba8SSam Protsenko }; 91562782ba8SSam Protsenko 91662782ba8SSam Protsenko static const struct samsung_cmu_info cmgp_cmu_info __initconst = { 91762782ba8SSam Protsenko .mux_clks = cmgp_mux_clks, 91862782ba8SSam Protsenko .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks), 91962782ba8SSam Protsenko .div_clks = cmgp_div_clks, 92062782ba8SSam Protsenko .nr_div_clks = ARRAY_SIZE(cmgp_div_clks), 92162782ba8SSam Protsenko .gate_clks = cmgp_gate_clks, 92262782ba8SSam Protsenko .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks), 92362782ba8SSam Protsenko .fixed_clks = cmgp_fixed_clks, 92462782ba8SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks), 92562782ba8SSam Protsenko .nr_clk_ids = CMGP_NR_CLK, 92662782ba8SSam Protsenko .clk_regs = cmgp_clk_regs, 92762782ba8SSam Protsenko .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), 92862782ba8SSam Protsenko .clk_name = "gout_clkcmu_cmgp_bus", 92962782ba8SSam Protsenko }; 93062782ba8SSam Protsenko 9317dd05578SSam Protsenko /* ---- CMU_HSI ------------------------------------------------------------- */ 9327dd05578SSam Protsenko 9337dd05578SSam Protsenko /* Register Offset definitions for CMU_HSI (0x13400000) */ 9347dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 9357dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 9367dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 9377dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 9387dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 9397dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c 9407dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 9417dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 9427dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 9437dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 9447dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 9457dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c 9467dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 9477dd05578SSam Protsenko 9487dd05578SSam Protsenko static const unsigned long hsi_clk_regs[] __initconst = { 9497dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 9507dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 9517dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 9527dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 9537dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 9547dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 9557dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 9567dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 9577dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 9587dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 9597dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 9607dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 9617dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 9627dd05578SSam Protsenko }; 9637dd05578SSam Protsenko 964dbaa27ccSSam Protsenko /* List of parent clocks for Muxes in CMU_HSI */ 9657dd05578SSam Protsenko PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" }; 9667dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" }; 9677dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" }; 9687dd05578SSam Protsenko PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" }; 9697dd05578SSam Protsenko 9707dd05578SSam Protsenko static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { 9717dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, 9727dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), 9737dd05578SSam Protsenko MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", 9747dd05578SSam Protsenko mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 9757dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 9767dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", 9777dd05578SSam Protsenko mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 9787dd05578SSam Protsenko 4, 1), 9797dd05578SSam Protsenko MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p, 9807dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1), 9817dd05578SSam Protsenko }; 9827dd05578SSam Protsenko 9837dd05578SSam Protsenko static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { 9847dd05578SSam Protsenko GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", 9857dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), 9867dd05578SSam Protsenko GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", 9877dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), 9887dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk", 9897dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), 9906904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 9917dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user", 9926904d7e5SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 9937dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", 9947dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), 9957dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 9967dd05578SSam Protsenko "mout_hsi_mmc_card_user", 9977dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), 9987dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", 9997dd05578SSam Protsenko "mout_hsi_bus_user", 10007dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), 10017dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", 10027dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), 10037dd05578SSam Protsenko GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", 10047dd05578SSam Protsenko "mout_hsi_bus_user", 10057dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), 10067dd05578SSam Protsenko }; 10077dd05578SSam Protsenko 10087dd05578SSam Protsenko static const struct samsung_cmu_info hsi_cmu_info __initconst = { 10097dd05578SSam Protsenko .mux_clks = hsi_mux_clks, 10107dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), 10117dd05578SSam Protsenko .gate_clks = hsi_gate_clks, 10127dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), 10137dd05578SSam Protsenko .nr_clk_ids = HSI_NR_CLK, 10147dd05578SSam Protsenko .clk_regs = hsi_clk_regs, 10157dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), 10167dd05578SSam Protsenko .clk_name = "dout_hsi_bus", 10177dd05578SSam Protsenko }; 10187dd05578SSam Protsenko 1019*bf3a4c51SSam Protsenko /* ---- CMU_IS -------------------------------------------------------------- */ 1020*bf3a4c51SSam Protsenko 1021*bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600 1022*bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610 1023*bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620 1024*bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630 1025*bf3a4c51SSam Protsenko #define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800 1026*bf3a4c51SSam Protsenko #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000 1027*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040 1028*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044 1029*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048 1030*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c 1031*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050 1032*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054 1033*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058 1034*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c 1035*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060 1036*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064 1037*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074 1038*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078 1039*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c 1040*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080 1041*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098 1042*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c 1043*bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0 1044*bf3a4c51SSam Protsenko 1045*bf3a4c51SSam Protsenko static const unsigned long is_clk_regs[] __initconst = { 1046*bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 1047*bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 1048*bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 1049*bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 1050*bf3a4c51SSam Protsenko CLK_CON_DIV_DIV_CLK_IS_BUSP, 1051*bf3a4c51SSam Protsenko CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 1052*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 1053*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 1054*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 1055*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 1056*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 1057*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_GDC, 1058*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_IPP, 1059*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_ITP, 1060*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_MCSC, 1061*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_VRA, 1062*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 1063*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 1064*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 1065*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 1066*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 1067*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 1068*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 1069*bf3a4c51SSam Protsenko }; 1070*bf3a4c51SSam Protsenko 1071*bf3a4c51SSam Protsenko /* List of parent clocks for Muxes in CMU_IS */ 1072*bf3a4c51SSam Protsenko PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" }; 1073*bf3a4c51SSam Protsenko PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" }; 1074*bf3a4c51SSam Protsenko PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" }; 1075*bf3a4c51SSam Protsenko PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" }; 1076*bf3a4c51SSam Protsenko 1077*bf3a4c51SSam Protsenko static const struct samsung_mux_clock is_mux_clks[] __initconst = { 1078*bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p, 1079*bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1), 1080*bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p, 1081*bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1), 1082*bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p, 1083*bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1), 1084*bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p, 1085*bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1), 1086*bf3a4c51SSam Protsenko }; 1087*bf3a4c51SSam Protsenko 1088*bf3a4c51SSam Protsenko static const struct samsung_div_clock is_div_clks[] __initconst = { 1089*bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user", 1090*bf3a4c51SSam Protsenko CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2), 1091*bf3a4c51SSam Protsenko }; 1092*bf3a4c51SSam Protsenko 1093*bf3a4c51SSam Protsenko static const struct samsung_gate_clock is_gate_clks[] __initconst = { 1094*bf3a4c51SSam Protsenko /* TODO: Should be enabled in IS driver */ 1095*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp", 1096*bf3a4c51SSam Protsenko CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1097*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user", 1098*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0), 1099*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user", 1100*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0), 1101*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user", 1102*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0), 1103*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp", 1104*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0), 1105*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk", 1106*bf3a4c51SSam Protsenko "mout_is_bus_user", 1107*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0), 1108*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user", 1109*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0), 1110*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user", 1111*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0), 1112*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user", 1113*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0), 1114*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user", 1115*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0), 1116*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user", 1117*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0), 1118*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk", 1119*bf3a4c51SSam Protsenko "mout_is_bus_user", 1120*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0), 1121*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp", 1122*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0), 1123*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk", 1124*bf3a4c51SSam Protsenko "mout_is_itp_user", 1125*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0), 1126*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp", 1127*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0), 1128*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk", 1129*bf3a4c51SSam Protsenko "mout_is_bus_user", 1130*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0), 1131*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk", 1132*bf3a4c51SSam Protsenko "mout_is_itp_user", 1133*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0), 1134*bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp", 1135*bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0), 1136*bf3a4c51SSam Protsenko }; 1137*bf3a4c51SSam Protsenko 1138*bf3a4c51SSam Protsenko static const struct samsung_cmu_info is_cmu_info __initconst = { 1139*bf3a4c51SSam Protsenko .mux_clks = is_mux_clks, 1140*bf3a4c51SSam Protsenko .nr_mux_clks = ARRAY_SIZE(is_mux_clks), 1141*bf3a4c51SSam Protsenko .div_clks = is_div_clks, 1142*bf3a4c51SSam Protsenko .nr_div_clks = ARRAY_SIZE(is_div_clks), 1143*bf3a4c51SSam Protsenko .gate_clks = is_gate_clks, 1144*bf3a4c51SSam Protsenko .nr_gate_clks = ARRAY_SIZE(is_gate_clks), 1145*bf3a4c51SSam Protsenko .nr_clk_ids = IS_NR_CLK, 1146*bf3a4c51SSam Protsenko .clk_regs = is_clk_regs, 1147*bf3a4c51SSam Protsenko .nr_clk_regs = ARRAY_SIZE(is_clk_regs), 1148*bf3a4c51SSam Protsenko .clk_name = "dout_is_bus", 1149*bf3a4c51SSam Protsenko }; 1150*bf3a4c51SSam Protsenko 11517dd05578SSam Protsenko /* ---- CMU_PERI ------------------------------------------------------------ */ 11527dd05578SSam Protsenko 11537dd05578SSam Protsenko /* Register Offset definitions for CMU_PERI (0x10030000) */ 11547dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 11557dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610 11567dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620 11577dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 11587dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800 11597dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804 11607dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808 11617dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c 11627dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c 11637dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010 11647dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014 11657dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020 11667dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024 11677dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 11687dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c 11697dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030 11707dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034 11717dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038 11727dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c 11737dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040 11747dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044 11757dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048 11767dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c 11777dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050 11787dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054 11797dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c 11807dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064 11817dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c 11827dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0 11837dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4 11847dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 11857dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac 11867dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0 11877dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4 11887dd05578SSam Protsenko 11897dd05578SSam Protsenko static const unsigned long peri_clk_regs[] __initconst = { 11907dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 11917dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 11927dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 11937dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 11947dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 11957dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 11967dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 11977dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 11987dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 11997dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 12007dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 12017dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 12027dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 12037dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 12047dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 12057dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 12067dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 12077dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 12087dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 12097dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 12107dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 12117dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 12127dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 12137dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 12147dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 12157dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 12167dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 12177dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 12187dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 12197dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 12207dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 12217dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 12227dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 12237dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 12247dd05578SSam Protsenko }; 12257dd05578SSam Protsenko 12267dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_PERI */ 12277dd05578SSam Protsenko PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; 12287dd05578SSam Protsenko PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" }; 12297dd05578SSam Protsenko PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" }; 12307dd05578SSam Protsenko PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" }; 12317dd05578SSam Protsenko 12327dd05578SSam Protsenko static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 12337dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 12347dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 12357dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", 12367dd05578SSam Protsenko mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), 12377dd05578SSam Protsenko MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", 12387dd05578SSam Protsenko mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), 12397dd05578SSam Protsenko MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, 12407dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), 12417dd05578SSam Protsenko }; 12427dd05578SSam Protsenko 12437dd05578SSam Protsenko static const struct samsung_div_clock peri_div_clks[] __initconst = { 12447dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0", 12457dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5), 12467dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1", 12477dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), 12487dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", 12497dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), 12507dd05578SSam Protsenko DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", 12517dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), 12527dd05578SSam Protsenko }; 12537dd05578SSam Protsenko 12547dd05578SSam Protsenko static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 12557dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user", 12567dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0), 12577dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user", 12587dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0), 12597dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user", 12607dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0), 12617dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0", 12627dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0), 12637dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", 12647dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), 12657dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1", 12667dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0), 12677dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", 12687dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), 12697dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2", 12707dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0), 12717dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", 12727dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), 12737dd05578SSam Protsenko GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", 12747dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), 12757dd05578SSam Protsenko GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", 12767dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), 12777dd05578SSam Protsenko GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", 12787dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), 12797dd05578SSam Protsenko GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", 12807dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), 12817dd05578SSam Protsenko GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", 12827dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), 12837dd05578SSam Protsenko GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", 12847dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), 12857dd05578SSam Protsenko GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", 12867dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), 12877dd05578SSam Protsenko GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", 12887dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), 12897dd05578SSam Protsenko GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", 12907dd05578SSam Protsenko "mout_peri_bus_user", 12917dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), 12927dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", 12937dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), 12947dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", 12957dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), 12967dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", 12977dd05578SSam Protsenko "mout_peri_bus_user", 12987dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), 12997dd05578SSam Protsenko GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", 13007dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), 13017dd05578SSam Protsenko GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", 13027dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), 13037dd05578SSam Protsenko GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", 13047dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0), 13057dd05578SSam Protsenko GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", 13067dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0), 13076904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 13087dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk", 13097dd05578SSam Protsenko "mout_peri_bus_user", 13106904d7e5SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 13117dd05578SSam Protsenko }; 13127dd05578SSam Protsenko 13137dd05578SSam Protsenko static const struct samsung_cmu_info peri_cmu_info __initconst = { 13147dd05578SSam Protsenko .mux_clks = peri_mux_clks, 13157dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 13167dd05578SSam Protsenko .div_clks = peri_div_clks, 13177dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(peri_div_clks), 13187dd05578SSam Protsenko .gate_clks = peri_gate_clks, 13197dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 13207dd05578SSam Protsenko .nr_clk_ids = PERI_NR_CLK, 13217dd05578SSam Protsenko .clk_regs = peri_clk_regs, 13227dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 13237dd05578SSam Protsenko .clk_name = "dout_peri_bus", 13247dd05578SSam Protsenko }; 13257dd05578SSam Protsenko 1326bcda841fSSam Protsenko static void __init exynos850_cmu_peri_init(struct device_node *np) 1327bcda841fSSam Protsenko { 1328cfe238e4SDavid Virag exynos_arm64_register_cmu(NULL, np, &peri_cmu_info); 1329bcda841fSSam Protsenko } 1330bcda841fSSam Protsenko 1331bcda841fSSam Protsenko /* Register CMU_PERI early, as it's needed for MCT timer */ 1332bcda841fSSam Protsenko CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", 1333bcda841fSSam Protsenko exynos850_cmu_peri_init); 1334bcda841fSSam Protsenko 13357dd05578SSam Protsenko /* ---- CMU_CORE ------------------------------------------------------------ */ 13367dd05578SSam Protsenko 13377dd05578SSam Protsenko /* Register Offset definitions for CMU_CORE (0x12000000) */ 13387dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 13397dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610 13407dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 13417dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630 13427dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 13437dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 13447dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 13457dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 1346bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 13477dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 13487dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec 13497dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 13507dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c 1351bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 13527dd05578SSam Protsenko 13537dd05578SSam Protsenko static const unsigned long core_clk_regs[] __initconst = { 13547dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 13557dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 13567dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 13577dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 13587dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 13597dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 13607dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 13617dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 1362bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 13637dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 13647dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 13657dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 13667dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 1367bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 13687dd05578SSam Protsenko }; 13697dd05578SSam Protsenko 13707dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_CORE */ 13717dd05578SSam Protsenko PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; 13727dd05578SSam Protsenko PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; 13737dd05578SSam Protsenko PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" }; 13747dd05578SSam Protsenko PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" }; 13757dd05578SSam Protsenko PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; 13767dd05578SSam Protsenko 13777dd05578SSam Protsenko static const struct samsung_mux_clock core_mux_clks[] __initconst = { 13787dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 13797dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 13807dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, 13817dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), 13827dd05578SSam Protsenko MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", 13837dd05578SSam Protsenko mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 13847dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 13857dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p, 13867dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1), 13877dd05578SSam Protsenko MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, 13887dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), 13897dd05578SSam Protsenko }; 13907dd05578SSam Protsenko 13917dd05578SSam Protsenko static const struct samsung_div_clock core_div_clks[] __initconst = { 13927dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 13937dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 13947dd05578SSam Protsenko }; 13957dd05578SSam Protsenko 13967dd05578SSam Protsenko static const struct samsung_gate_clock core_gate_clks[] __initconst = { 13976904d7e5SSam Protsenko /* CCI (interconnect) clock must be always running */ 13987dd05578SSam Protsenko GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", 13996904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0), 14006904d7e5SSam Protsenko /* GIC (interrupt controller) clock must be always running */ 14017dd05578SSam Protsenko GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic", 14026904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0), 14037dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", 14047dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), 14057dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 14067dd05578SSam Protsenko "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 14077dd05578SSam Protsenko 21, CLK_SET_RATE_PARENT, 0), 14087dd05578SSam Protsenko GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", 14097dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), 14107dd05578SSam Protsenko GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", 14117dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), 1412bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 1413bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp", 1414bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1415bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk", 1416bc471d1fSSam Protsenko "dout_core_busp", 1417bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0), 14187dd05578SSam Protsenko }; 14197dd05578SSam Protsenko 14207dd05578SSam Protsenko static const struct samsung_cmu_info core_cmu_info __initconst = { 14217dd05578SSam Protsenko .mux_clks = core_mux_clks, 14227dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 14237dd05578SSam Protsenko .div_clks = core_div_clks, 14247dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(core_div_clks), 14257dd05578SSam Protsenko .gate_clks = core_gate_clks, 14267dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 14277dd05578SSam Protsenko .nr_clk_ids = CORE_NR_CLK, 14287dd05578SSam Protsenko .clk_regs = core_clk_regs, 14297dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 14307dd05578SSam Protsenko .clk_name = "dout_core_bus", 14317dd05578SSam Protsenko }; 14327dd05578SSam Protsenko 14337dd05578SSam Protsenko /* ---- CMU_DPU ------------------------------------------------------------- */ 14347dd05578SSam Protsenko 14357dd05578SSam Protsenko /* Register Offset definitions for CMU_DPU (0x13000000) */ 14367dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600 14377dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 14387dd05578SSam Protsenko #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004 14397dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010 14407dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014 14417dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018 14427dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028 14437dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c 14447dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038 14457dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c 14467dd05578SSam Protsenko 14477dd05578SSam Protsenko static const unsigned long dpu_clk_regs[] __initconst = { 14487dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 14497dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 14507dd05578SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 14517dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 14527dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 14537dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 14547dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 14557dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 14567dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 14577dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 14587dd05578SSam Protsenko }; 14597dd05578SSam Protsenko 1460dbaa27ccSSam Protsenko /* List of parent clocks for Muxes in CMU_DPU */ 14617dd05578SSam Protsenko PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" }; 14627dd05578SSam Protsenko 14637dd05578SSam Protsenko static const struct samsung_mux_clock dpu_mux_clks[] __initconst = { 14647dd05578SSam Protsenko MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p, 14657dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1), 14667dd05578SSam Protsenko }; 14677dd05578SSam Protsenko 14687dd05578SSam Protsenko static const struct samsung_div_clock dpu_div_clks[] __initconst = { 14697dd05578SSam Protsenko DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user", 14707dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), 14717dd05578SSam Protsenko }; 14727dd05578SSam Protsenko 14737dd05578SSam Protsenko static const struct samsung_gate_clock dpu_gate_clks[] __initconst = { 14746904d7e5SSam Protsenko /* TODO: Should be enabled in DSIM driver */ 14757dd05578SSam Protsenko GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk", 14766904d7e5SSam Protsenko "dout_dpu_busp", 14776904d7e5SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0), 14787dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user", 14797dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0), 14807dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user", 14817dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0), 14827dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user", 14837dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0), 14847dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user", 14857dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0), 14867dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp", 14877dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0), 14887dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user", 14897dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0), 14907dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp", 14917dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0), 14927dd05578SSam Protsenko }; 14937dd05578SSam Protsenko 14947dd05578SSam Protsenko static const struct samsung_cmu_info dpu_cmu_info __initconst = { 14957dd05578SSam Protsenko .mux_clks = dpu_mux_clks, 14967dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks), 14977dd05578SSam Protsenko .div_clks = dpu_div_clks, 14987dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(dpu_div_clks), 14997dd05578SSam Protsenko .gate_clks = dpu_gate_clks, 15007dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), 15017dd05578SSam Protsenko .nr_clk_ids = DPU_NR_CLK, 15027dd05578SSam Protsenko .clk_regs = dpu_clk_regs, 15037dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), 15047dd05578SSam Protsenko .clk_name = "dout_dpu", 15057dd05578SSam Protsenko }; 15067dd05578SSam Protsenko 15077dd05578SSam Protsenko /* ---- platform_driver ----------------------------------------------------- */ 15087dd05578SSam Protsenko 15097dd05578SSam Protsenko static int __init exynos850_cmu_probe(struct platform_device *pdev) 15107dd05578SSam Protsenko { 15117dd05578SSam Protsenko const struct samsung_cmu_info *info; 15127dd05578SSam Protsenko struct device *dev = &pdev->dev; 15137dd05578SSam Protsenko 15147dd05578SSam Protsenko info = of_device_get_match_data(dev); 1515cfe238e4SDavid Virag exynos_arm64_register_cmu(dev, dev->of_node, info); 15167dd05578SSam Protsenko 15177dd05578SSam Protsenko return 0; 15187dd05578SSam Protsenko } 15197dd05578SSam Protsenko 15207dd05578SSam Protsenko static const struct of_device_id exynos850_cmu_of_match[] = { 15217dd05578SSam Protsenko { 1522579839a9SSam Protsenko .compatible = "samsung,exynos850-cmu-apm", 1523579839a9SSam Protsenko .data = &apm_cmu_info, 1524579839a9SSam Protsenko }, { 1525b73fd95dSSam Protsenko .compatible = "samsung,exynos850-cmu-aud", 1526b73fd95dSSam Protsenko .data = &aud_cmu_info, 1527b73fd95dSSam Protsenko }, { 152862782ba8SSam Protsenko .compatible = "samsung,exynos850-cmu-cmgp", 152962782ba8SSam Protsenko .data = &cmgp_cmu_info, 153062782ba8SSam Protsenko }, { 15317dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-hsi", 15327dd05578SSam Protsenko .data = &hsi_cmu_info, 15337dd05578SSam Protsenko }, { 1534*bf3a4c51SSam Protsenko .compatible = "samsung,exynos850-cmu-is", 1535*bf3a4c51SSam Protsenko .data = &is_cmu_info, 1536*bf3a4c51SSam Protsenko }, { 15377dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-core", 15387dd05578SSam Protsenko .data = &core_cmu_info, 15397dd05578SSam Protsenko }, { 15407dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-dpu", 15417dd05578SSam Protsenko .data = &dpu_cmu_info, 15427dd05578SSam Protsenko }, { 15437dd05578SSam Protsenko }, 15447dd05578SSam Protsenko }; 15457dd05578SSam Protsenko 15467dd05578SSam Protsenko static struct platform_driver exynos850_cmu_driver __refdata = { 15477dd05578SSam Protsenko .driver = { 15487dd05578SSam Protsenko .name = "exynos850-cmu", 15497dd05578SSam Protsenko .of_match_table = exynos850_cmu_of_match, 15507dd05578SSam Protsenko .suppress_bind_attrs = true, 15517dd05578SSam Protsenko }, 15527dd05578SSam Protsenko .probe = exynos850_cmu_probe, 15537dd05578SSam Protsenko }; 15547dd05578SSam Protsenko 15557dd05578SSam Protsenko static int __init exynos850_cmu_init(void) 15567dd05578SSam Protsenko { 15577dd05578SSam Protsenko return platform_driver_register(&exynos850_cmu_driver); 15587dd05578SSam Protsenko } 15597dd05578SSam Protsenko core_initcall(exynos850_cmu_init); 1560