17dd05578SSam Protsenko // SPDX-License-Identifier: GPL-2.0-only 27dd05578SSam Protsenko /* 37dd05578SSam Protsenko * Copyright (C) 2021 Linaro Ltd. 47dd05578SSam Protsenko * Author: Sam Protsenko <semen.protsenko@linaro.org> 57dd05578SSam Protsenko * 67dd05578SSam Protsenko * Common Clock Framework support for Exynos850 SoC. 77dd05578SSam Protsenko */ 87dd05578SSam Protsenko 97dd05578SSam Protsenko #include <linux/clk.h> 107dd05578SSam Protsenko #include <linux/clk-provider.h> 117dd05578SSam Protsenko #include <linux/of.h> 127dd05578SSam Protsenko #include <linux/of_address.h> 137dd05578SSam Protsenko #include <linux/of_device.h> 147dd05578SSam Protsenko #include <linux/platform_device.h> 157dd05578SSam Protsenko 167dd05578SSam Protsenko #include <dt-bindings/clock/exynos850.h> 177dd05578SSam Protsenko 187dd05578SSam Protsenko #include "clk.h" 197dd05578SSam Protsenko 207dd05578SSam Protsenko /* Gate register bits */ 217dd05578SSam Protsenko #define GATE_MANUAL BIT(20) 227dd05578SSam Protsenko #define GATE_ENABLE_HWACG BIT(28) 237dd05578SSam Protsenko 247dd05578SSam Protsenko /* Gate register offsets range */ 257dd05578SSam Protsenko #define GATE_OFF_START 0x2000 267dd05578SSam Protsenko #define GATE_OFF_END 0x2fff 277dd05578SSam Protsenko 287dd05578SSam Protsenko /** 297dd05578SSam Protsenko * exynos850_init_clocks - Set clocks initial configuration 307dd05578SSam Protsenko * @np: CMU device tree node with "reg" property (CMU addr) 317dd05578SSam Protsenko * @reg_offs: Register offsets array for clocks to init 327dd05578SSam Protsenko * @reg_offs_len: Number of register offsets in reg_offs array 337dd05578SSam Protsenko * 347dd05578SSam Protsenko * Set manual control mode for all gate clocks. 357dd05578SSam Protsenko */ 367dd05578SSam Protsenko static void __init exynos850_init_clocks(struct device_node *np, 377dd05578SSam Protsenko const unsigned long *reg_offs, size_t reg_offs_len) 387dd05578SSam Protsenko { 397dd05578SSam Protsenko void __iomem *reg_base; 407dd05578SSam Protsenko size_t i; 417dd05578SSam Protsenko 427dd05578SSam Protsenko reg_base = of_iomap(np, 0); 437dd05578SSam Protsenko if (!reg_base) 447dd05578SSam Protsenko panic("%s: failed to map registers\n", __func__); 457dd05578SSam Protsenko 467dd05578SSam Protsenko for (i = 0; i < reg_offs_len; ++i) { 477dd05578SSam Protsenko void __iomem *reg = reg_base + reg_offs[i]; 487dd05578SSam Protsenko u32 val; 497dd05578SSam Protsenko 507dd05578SSam Protsenko /* Modify only gate clock registers */ 517dd05578SSam Protsenko if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END) 527dd05578SSam Protsenko continue; 537dd05578SSam Protsenko 547dd05578SSam Protsenko val = readl(reg); 557dd05578SSam Protsenko val |= GATE_MANUAL; 567dd05578SSam Protsenko val &= ~GATE_ENABLE_HWACG; 577dd05578SSam Protsenko writel(val, reg); 587dd05578SSam Protsenko } 597dd05578SSam Protsenko 607dd05578SSam Protsenko iounmap(reg_base); 617dd05578SSam Protsenko } 627dd05578SSam Protsenko 63bcda841fSSam Protsenko /** 64bcda841fSSam Protsenko * exynos850_register_cmu - Register specified Exynos850 CMU domain 65bcda841fSSam Protsenko * @dev: Device object; may be NULL if this function is not being 66bcda841fSSam Protsenko * called from platform driver probe function 67bcda841fSSam Protsenko * @np: CMU device tree node 68bcda841fSSam Protsenko * @cmu: CMU data 69bcda841fSSam Protsenko * 70bcda841fSSam Protsenko * Register specified CMU domain, which includes next steps: 71bcda841fSSam Protsenko * 72bcda841fSSam Protsenko * 1. Enable parent clock of @cmu CMU 73bcda841fSSam Protsenko * 2. Set initial registers configuration for @cmu CMU clocks 74bcda841fSSam Protsenko * 3. Register @cmu CMU clocks using Samsung clock framework API 75bcda841fSSam Protsenko */ 76bcda841fSSam Protsenko static void __init exynos850_register_cmu(struct device *dev, 77bcda841fSSam Protsenko struct device_node *np, const struct samsung_cmu_info *cmu) 78bcda841fSSam Protsenko { 79bcda841fSSam Protsenko /* Keep CMU parent clock running (needed for CMU registers access) */ 80bcda841fSSam Protsenko if (cmu->clk_name) { 81bcda841fSSam Protsenko struct clk *parent_clk; 82bcda841fSSam Protsenko 83bcda841fSSam Protsenko if (dev) 84bcda841fSSam Protsenko parent_clk = clk_get(dev, cmu->clk_name); 85bcda841fSSam Protsenko else 86bcda841fSSam Protsenko parent_clk = of_clk_get_by_name(np, cmu->clk_name); 87bcda841fSSam Protsenko 88bcda841fSSam Protsenko if (IS_ERR(parent_clk)) { 89bcda841fSSam Protsenko pr_err("%s: could not find bus clock %s; err = %ld\n", 90bcda841fSSam Protsenko __func__, cmu->clk_name, PTR_ERR(parent_clk)); 91bcda841fSSam Protsenko } else { 92bcda841fSSam Protsenko clk_prepare_enable(parent_clk); 93bcda841fSSam Protsenko } 94bcda841fSSam Protsenko } 95bcda841fSSam Protsenko 96bcda841fSSam Protsenko exynos850_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs); 97bcda841fSSam Protsenko samsung_cmu_register_one(np, cmu); 98bcda841fSSam Protsenko } 99bcda841fSSam Protsenko 1007dd05578SSam Protsenko /* ---- CMU_TOP ------------------------------------------------------------- */ 1017dd05578SSam Protsenko 1027dd05578SSam Protsenko /* Register Offset definitions for CMU_TOP (0x120e0000) */ 1037dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_MMC 0x0000 1047dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED0 0x0004 1057dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED1 0x0008 1067dd05578SSam Protsenko #define PLL_CON0_PLL_MMC 0x0100 1077dd05578SSam Protsenko #define PLL_CON3_PLL_MMC 0x010c 1087dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED0 0x0140 1097dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED0 0x014c 1107dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED1 0x0180 1117dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED1 0x018c 112579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000 1137dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 1147dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 1157dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c 1167dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 1177dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 1187dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c 1197dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 1207dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 1217dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 1227dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 1237dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 124579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c 1257dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 1267dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 1277dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 1287dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c 1297dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_DPU 0x1840 1307dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 1317dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c 1327dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 1337dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c 1347dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 1357dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 1367dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c 1377dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 1387dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 1397dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 1407dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c 1417dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 142579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008 1437dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 1447dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 1457dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 1467dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 1477dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c 1487dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 1497dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 1507dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c 1517dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 1527dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 1537dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 1547dd05578SSam Protsenko 1557dd05578SSam Protsenko static const unsigned long top_clk_regs[] __initconst = { 1567dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, 1577dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, 1587dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, 1597dd05578SSam Protsenko PLL_CON0_PLL_MMC, 1607dd05578SSam Protsenko PLL_CON3_PLL_MMC, 1617dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 1627dd05578SSam Protsenko PLL_CON3_PLL_SHARED0, 1637dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 1647dd05578SSam Protsenko PLL_CON3_PLL_SHARED1, 165579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 1667dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 1677dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 1687dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 1697dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 1707dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 1717dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 1727dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 1737dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 1747dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 1757dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 1767dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 177579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_APM_BUS, 1787dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 1797dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 1807dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 1817dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 1827dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 1837dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 1847dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 1857dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 1867dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 1877dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 1887dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 1897dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 1907dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 1917dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 1927dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 1937dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 1947dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 195579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 1967dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 1977dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 1987dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 1997dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 2007dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 2017dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 2027dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 2037dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 2047dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 2057dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 2067dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 2077dd05578SSam Protsenko }; 2087dd05578SSam Protsenko 2097dd05578SSam Protsenko /* 2107dd05578SSam Protsenko * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set 2117dd05578SSam Protsenko * for those PLLs by default, so set_rate operation would fail. 2127dd05578SSam Protsenko */ 2137dd05578SSam Protsenko static const struct samsung_pll_clock top_pll_clks[] __initconst = { 2147dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 2157dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 2167dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 2177dd05578SSam Protsenko NULL), 2187dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 2197dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 2207dd05578SSam Protsenko NULL), 2217dd05578SSam Protsenko PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 2227dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 2237dd05578SSam Protsenko }; 2247dd05578SSam Protsenko 2257dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP */ 2267dd05578SSam Protsenko PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 2277dd05578SSam Protsenko PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 2287dd05578SSam Protsenko PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 229579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */ 230579839a9SSam Protsenko PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" }; 2317dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 2327dd05578SSam Protsenko PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", 2337dd05578SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 2347dd05578SSam Protsenko PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 2357dd05578SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 2367dd05578SSam Protsenko PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", 2377dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 2387dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 2397dd05578SSam Protsenko "oscclk", "oscclk" }; 2407dd05578SSam Protsenko PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", 2417dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 2427dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ 2437dd05578SSam Protsenko PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 2447dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", 2457dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 2467dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 2477dd05578SSam Protsenko "oscclk", "oscclk" }; 2487dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4", 2497dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2507dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 2517dd05578SSam Protsenko PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 2527dd05578SSam Protsenko PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4", 2537dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2547dd05578SSam Protsenko PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4", 2557dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2567dd05578SSam Protsenko 2577dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ 2587dd05578SSam Protsenko PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3", 2597dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 2607dd05578SSam Protsenko 2617dd05578SSam Protsenko static const struct samsung_mux_clock top_mux_clks[] __initconst = { 2627dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 2637dd05578SSam Protsenko MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 2647dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 4, 1), 2657dd05578SSam Protsenko MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 2667dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 4, 1), 2677dd05578SSam Protsenko MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 2687dd05578SSam Protsenko PLL_CON0_PLL_MMC, 4, 1), 2697dd05578SSam Protsenko 270579839a9SSam Protsenko /* APM */ 271579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", 272579839a9SSam Protsenko mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), 273579839a9SSam Protsenko 2747dd05578SSam Protsenko /* CORE */ 2757dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 2767dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 2777dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 2787dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 2797dd05578SSam Protsenko MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, 2807dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), 2817dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, 2827dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), 2837dd05578SSam Protsenko 2847dd05578SSam Protsenko /* DPU */ 2857dd05578SSam Protsenko MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, 2867dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), 2877dd05578SSam Protsenko 2887dd05578SSam Protsenko /* HSI */ 2897dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, 2907dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), 2917dd05578SSam Protsenko MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, 2927dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), 2937dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, 2947dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), 2957dd05578SSam Protsenko 2967dd05578SSam Protsenko /* PERI */ 2977dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 2987dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 2997dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, 3007dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), 3017dd05578SSam Protsenko MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, 3027dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), 3037dd05578SSam Protsenko }; 3047dd05578SSam Protsenko 3057dd05578SSam Protsenko static const struct samsung_div_clock top_div_clks[] __initconst = { 3067dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 3077dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 3087dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 3097dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 3107dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 3117dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 3127dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 3137dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 3147dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 3157dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 3167dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 3177dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 3187dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 3197dd05578SSam Protsenko 320579839a9SSam Protsenko /* APM */ 321579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", 322579839a9SSam Protsenko "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), 323579839a9SSam Protsenko 3247dd05578SSam Protsenko /* CORE */ 3257dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 3267dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 3277dd05578SSam Protsenko DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 3287dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), 3297dd05578SSam Protsenko DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", 3307dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), 3317dd05578SSam Protsenko DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", 3327dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), 3337dd05578SSam Protsenko 3347dd05578SSam Protsenko /* DPU */ 3357dd05578SSam Protsenko DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", 3367dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 0, 4), 3377dd05578SSam Protsenko 3387dd05578SSam Protsenko /* HSI */ 3397dd05578SSam Protsenko DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", 3407dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), 3417dd05578SSam Protsenko DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", 3427dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), 3437dd05578SSam Protsenko DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", 3447dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), 3457dd05578SSam Protsenko 3467dd05578SSam Protsenko /* PERI */ 3477dd05578SSam Protsenko DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 3487dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 3497dd05578SSam Protsenko DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", 3507dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), 3517dd05578SSam Protsenko DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", 3527dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), 3537dd05578SSam Protsenko }; 3547dd05578SSam Protsenko 3557dd05578SSam Protsenko static const struct samsung_gate_clock top_gate_clks[] __initconst = { 3567dd05578SSam Protsenko /* CORE */ 3577dd05578SSam Protsenko GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 3587dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 3597dd05578SSam Protsenko GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 3607dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 3617dd05578SSam Protsenko GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", 3627dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), 3637dd05578SSam Protsenko GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", 3647dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), 3657dd05578SSam Protsenko 366579839a9SSam Protsenko /* APM */ 367579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", 368579839a9SSam Protsenko "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0), 369579839a9SSam Protsenko 3707dd05578SSam Protsenko /* DPU */ 3717dd05578SSam Protsenko GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", 3727dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), 3737dd05578SSam Protsenko 3747dd05578SSam Protsenko /* HSI */ 3757dd05578SSam Protsenko GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", 3767dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), 3777dd05578SSam Protsenko GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", 3787dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), 3797dd05578SSam Protsenko GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", 3807dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), 3817dd05578SSam Protsenko 3827dd05578SSam Protsenko /* PERI */ 3837dd05578SSam Protsenko GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 3847dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 3857dd05578SSam Protsenko GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", 3867dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), 3877dd05578SSam Protsenko GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", 3887dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), 3897dd05578SSam Protsenko }; 3907dd05578SSam Protsenko 3917dd05578SSam Protsenko static const struct samsung_cmu_info top_cmu_info __initconst = { 3927dd05578SSam Protsenko .pll_clks = top_pll_clks, 3937dd05578SSam Protsenko .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 3947dd05578SSam Protsenko .mux_clks = top_mux_clks, 3957dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 3967dd05578SSam Protsenko .div_clks = top_div_clks, 3977dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(top_div_clks), 3987dd05578SSam Protsenko .gate_clks = top_gate_clks, 3997dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 4007dd05578SSam Protsenko .nr_clk_ids = TOP_NR_CLK, 4017dd05578SSam Protsenko .clk_regs = top_clk_regs, 4027dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 4037dd05578SSam Protsenko }; 4047dd05578SSam Protsenko 4057dd05578SSam Protsenko static void __init exynos850_cmu_top_init(struct device_node *np) 4067dd05578SSam Protsenko { 407bcda841fSSam Protsenko exynos850_register_cmu(NULL, np, &top_cmu_info); 4087dd05578SSam Protsenko } 4097dd05578SSam Protsenko 410bcda841fSSam Protsenko /* Register CMU_TOP early, as it's a dependency for other early domains */ 4117dd05578SSam Protsenko CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", 4127dd05578SSam Protsenko exynos850_cmu_top_init); 4137dd05578SSam Protsenko 414579839a9SSam Protsenko /* ---- CMU_APM ------------------------------------------------------------- */ 415579839a9SSam Protsenko 416579839a9SSam Protsenko /* Register Offset definitions for CMU_APM (0x11800000) */ 417579839a9SSam Protsenko #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600 418579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610 419579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620 420579839a9SSam Protsenko #define PLL_CON0_MUX_DLL_USER 0x0630 421579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000 422579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004 423579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008 424579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800 425579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804 426579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808 427579839a9SSam Protsenko #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 428579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014 429*bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018 430*bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020 431579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024 432579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028 433579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034 434579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038 435579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc 436*bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0 437579839a9SSam Protsenko 438579839a9SSam Protsenko static const unsigned long apm_clk_regs[] __initconst = { 439579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 440579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 441579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 442579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 443579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 444579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 445579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 446579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 447579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 448579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 449579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 450579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 451*bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 452*bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 453579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 454579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 455579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 456579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 457579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 458*bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 459579839a9SSam Protsenko }; 460579839a9SSam Protsenko 461579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_APM */ 462579839a9SSam Protsenko PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" }; 463579839a9SSam Protsenko PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" }; 464579839a9SSam Protsenko PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" }; 465579839a9SSam Protsenko PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" }; 466579839a9SSam Protsenko PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" }; 467579839a9SSam Protsenko PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user", 468579839a9SSam Protsenko "mout_dll_user", "oscclk_rco_apm" }; 469579839a9SSam Protsenko PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" }; 470579839a9SSam Protsenko 471579839a9SSam Protsenko static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 472579839a9SSam Protsenko FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000), 473579839a9SSam Protsenko FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000), 474579839a9SSam Protsenko FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000), 475579839a9SSam Protsenko FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000), 476579839a9SSam Protsenko }; 477579839a9SSam Protsenko 478579839a9SSam Protsenko static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 479579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p, 480579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1), 481579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user", 482579839a9SSam Protsenko mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1), 483579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p, 484579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1), 485579839a9SSam Protsenko MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p, 486579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 4, 1), 487579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus", 488579839a9SSam Protsenko mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1), 489579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p, 490579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2), 491579839a9SSam Protsenko MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p, 492579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1), 493579839a9SSam Protsenko }; 494579839a9SSam Protsenko 495579839a9SSam Protsenko static const struct samsung_div_clock apm_div_clks[] __initconst = { 496579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus", 497579839a9SSam Protsenko "gout_clkcmu_chub_bus", 498579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3), 499579839a9SSam Protsenko DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus", 500579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3), 501579839a9SSam Protsenko DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus", 502579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3), 503579839a9SSam Protsenko }; 504579839a9SSam Protsenko 505579839a9SSam Protsenko static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 506579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus", 507579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0), 508579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus", 509579839a9SSam Protsenko "mout_clkcmu_chub_bus", 510579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0), 511579839a9SSam Protsenko GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus", 512579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0), 513579839a9SSam Protsenko GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus", 514579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0), 515579839a9SSam Protsenko GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus", 516579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0), 517579839a9SSam Protsenko GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c", 518579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0), 519579839a9SSam Protsenko GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus", 520579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0), 521*bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 522*bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus", 523*bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, 524*bc471d1fSSam Protsenko 0), 525*bc471d1fSSam Protsenko GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", 526*bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0), 527*bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", 528*bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), 529579839a9SSam Protsenko }; 530579839a9SSam Protsenko 531579839a9SSam Protsenko static const struct samsung_cmu_info apm_cmu_info __initconst = { 532579839a9SSam Protsenko .mux_clks = apm_mux_clks, 533579839a9SSam Protsenko .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 534579839a9SSam Protsenko .div_clks = apm_div_clks, 535579839a9SSam Protsenko .nr_div_clks = ARRAY_SIZE(apm_div_clks), 536579839a9SSam Protsenko .gate_clks = apm_gate_clks, 537579839a9SSam Protsenko .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 538579839a9SSam Protsenko .fixed_clks = apm_fixed_clks, 539579839a9SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 540579839a9SSam Protsenko .nr_clk_ids = APM_NR_CLK, 541579839a9SSam Protsenko .clk_regs = apm_clk_regs, 542579839a9SSam Protsenko .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 543579839a9SSam Protsenko .clk_name = "dout_clkcmu_apm_bus", 544579839a9SSam Protsenko }; 545579839a9SSam Protsenko 54662782ba8SSam Protsenko /* ---- CMU_CMGP ------------------------------------------------------------ */ 54762782ba8SSam Protsenko 54862782ba8SSam Protsenko /* Register Offset definitions for CMU_CMGP (0x11c00000) */ 54962782ba8SSam Protsenko #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000 55062782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004 55162782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008 55262782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800 55362782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804 55462782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808 55562782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c 55662782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 55762782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018 558*bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040 55962782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044 56062782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048 56162782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c 56262782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050 56362782ba8SSam Protsenko 56462782ba8SSam Protsenko static const unsigned long cmgp_clk_regs[] __initconst = { 56562782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 56662782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 56762782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 56862782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 56962782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 57062782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 57162782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 57262782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 57362782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 574*bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 57562782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 57662782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 57762782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 57862782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 57962782ba8SSam Protsenko }; 58062782ba8SSam Protsenko 58162782ba8SSam Protsenko /* List of parent clocks for Muxes in CMU_CMGP */ 58262782ba8SSam Protsenko PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 58362782ba8SSam Protsenko PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 58462782ba8SSam Protsenko PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" }; 58562782ba8SSam Protsenko 58662782ba8SSam Protsenko static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = { 58762782ba8SSam Protsenko FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000), 58862782ba8SSam Protsenko }; 58962782ba8SSam Protsenko 59062782ba8SSam Protsenko static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = { 59162782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p, 59262782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 0, 1), 59362782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, 59462782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1), 59562782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, 59662782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1), 59762782ba8SSam Protsenko }; 59862782ba8SSam Protsenko 59962782ba8SSam Protsenko static const struct samsung_div_clock cmgp_div_clks[] __initconst = { 60062782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus", 60162782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), 60262782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", 60362782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5), 60462782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", 60562782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5), 60662782ba8SSam Protsenko }; 60762782ba8SSam Protsenko 60862782ba8SSam Protsenko static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { 60962782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk", 61062782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 61162782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0), 61262782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk", 61362782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 61462782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0), 6156904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 61662782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk", 61762782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 6186904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0), 61962782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0", 62062782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0), 62162782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk", 62262782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 62362782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0), 62462782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1", 62562782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0), 62662782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", 62762782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 62862782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), 629*bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk", 630*bc471d1fSSam Protsenko "gout_clkcmu_cmgp_bus", 631*bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0), 63262782ba8SSam Protsenko }; 63362782ba8SSam Protsenko 63462782ba8SSam Protsenko static const struct samsung_cmu_info cmgp_cmu_info __initconst = { 63562782ba8SSam Protsenko .mux_clks = cmgp_mux_clks, 63662782ba8SSam Protsenko .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks), 63762782ba8SSam Protsenko .div_clks = cmgp_div_clks, 63862782ba8SSam Protsenko .nr_div_clks = ARRAY_SIZE(cmgp_div_clks), 63962782ba8SSam Protsenko .gate_clks = cmgp_gate_clks, 64062782ba8SSam Protsenko .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks), 64162782ba8SSam Protsenko .fixed_clks = cmgp_fixed_clks, 64262782ba8SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks), 64362782ba8SSam Protsenko .nr_clk_ids = CMGP_NR_CLK, 64462782ba8SSam Protsenko .clk_regs = cmgp_clk_regs, 64562782ba8SSam Protsenko .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), 64662782ba8SSam Protsenko .clk_name = "gout_clkcmu_cmgp_bus", 64762782ba8SSam Protsenko }; 64862782ba8SSam Protsenko 6497dd05578SSam Protsenko /* ---- CMU_HSI ------------------------------------------------------------- */ 6507dd05578SSam Protsenko 6517dd05578SSam Protsenko /* Register Offset definitions for CMU_HSI (0x13400000) */ 6527dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 6537dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 6547dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 6557dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 6567dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 6577dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c 6587dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 6597dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 6607dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 6617dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 6627dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 6637dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c 6647dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 6657dd05578SSam Protsenko 6667dd05578SSam Protsenko static const unsigned long hsi_clk_regs[] __initconst = { 6677dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 6687dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 6697dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 6707dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 6717dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 6727dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 6737dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 6747dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 6757dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 6767dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 6777dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 6787dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 6797dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 6807dd05578SSam Protsenko }; 6817dd05578SSam Protsenko 6827dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_PERI */ 6837dd05578SSam Protsenko PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" }; 6847dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" }; 6857dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" }; 6867dd05578SSam Protsenko PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" }; 6877dd05578SSam Protsenko 6887dd05578SSam Protsenko static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { 6897dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, 6907dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), 6917dd05578SSam Protsenko MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", 6927dd05578SSam Protsenko mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 6937dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 6947dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", 6957dd05578SSam Protsenko mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 6967dd05578SSam Protsenko 4, 1), 6977dd05578SSam Protsenko MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p, 6987dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1), 6997dd05578SSam Protsenko }; 7007dd05578SSam Protsenko 7017dd05578SSam Protsenko static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { 7027dd05578SSam Protsenko GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", 7037dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), 7047dd05578SSam Protsenko GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", 7057dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), 7067dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk", 7077dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), 7086904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 7097dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user", 7106904d7e5SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 7117dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", 7127dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), 7137dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 7147dd05578SSam Protsenko "mout_hsi_mmc_card_user", 7157dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), 7167dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", 7177dd05578SSam Protsenko "mout_hsi_bus_user", 7187dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), 7197dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", 7207dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), 7217dd05578SSam Protsenko GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", 7227dd05578SSam Protsenko "mout_hsi_bus_user", 7237dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), 7247dd05578SSam Protsenko }; 7257dd05578SSam Protsenko 7267dd05578SSam Protsenko static const struct samsung_cmu_info hsi_cmu_info __initconst = { 7277dd05578SSam Protsenko .mux_clks = hsi_mux_clks, 7287dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), 7297dd05578SSam Protsenko .gate_clks = hsi_gate_clks, 7307dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), 7317dd05578SSam Protsenko .nr_clk_ids = HSI_NR_CLK, 7327dd05578SSam Protsenko .clk_regs = hsi_clk_regs, 7337dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), 7347dd05578SSam Protsenko .clk_name = "dout_hsi_bus", 7357dd05578SSam Protsenko }; 7367dd05578SSam Protsenko 7377dd05578SSam Protsenko /* ---- CMU_PERI ------------------------------------------------------------ */ 7387dd05578SSam Protsenko 7397dd05578SSam Protsenko /* Register Offset definitions for CMU_PERI (0x10030000) */ 7407dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 7417dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610 7427dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620 7437dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 7447dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800 7457dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804 7467dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808 7477dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c 7487dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c 7497dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010 7507dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014 7517dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020 7527dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024 7537dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 7547dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c 7557dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030 7567dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034 7577dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038 7587dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c 7597dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040 7607dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044 7617dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048 7627dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c 7637dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050 7647dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054 7657dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c 7667dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064 7677dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c 7687dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0 7697dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4 7707dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 7717dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac 7727dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0 7737dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4 7747dd05578SSam Protsenko 7757dd05578SSam Protsenko static const unsigned long peri_clk_regs[] __initconst = { 7767dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 7777dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 7787dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 7797dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 7807dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 7817dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 7827dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 7837dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 7847dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 7857dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 7867dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 7877dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 7887dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 7897dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 7907dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 7917dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 7927dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 7937dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 7947dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 7957dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 7967dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 7977dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 7987dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 7997dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 8007dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 8017dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 8027dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 8037dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 8047dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 8057dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 8067dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 8077dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 8087dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 8097dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 8107dd05578SSam Protsenko }; 8117dd05578SSam Protsenko 8127dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_PERI */ 8137dd05578SSam Protsenko PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; 8147dd05578SSam Protsenko PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" }; 8157dd05578SSam Protsenko PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" }; 8167dd05578SSam Protsenko PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" }; 8177dd05578SSam Protsenko 8187dd05578SSam Protsenko static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 8197dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 8207dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 8217dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", 8227dd05578SSam Protsenko mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), 8237dd05578SSam Protsenko MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", 8247dd05578SSam Protsenko mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), 8257dd05578SSam Protsenko MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, 8267dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), 8277dd05578SSam Protsenko }; 8287dd05578SSam Protsenko 8297dd05578SSam Protsenko static const struct samsung_div_clock peri_div_clks[] __initconst = { 8307dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0", 8317dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5), 8327dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1", 8337dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), 8347dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", 8357dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), 8367dd05578SSam Protsenko DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", 8377dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), 8387dd05578SSam Protsenko }; 8397dd05578SSam Protsenko 8407dd05578SSam Protsenko static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 8417dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user", 8427dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0), 8437dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user", 8447dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0), 8457dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user", 8467dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0), 8477dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0", 8487dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0), 8497dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", 8507dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), 8517dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1", 8527dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0), 8537dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", 8547dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), 8557dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2", 8567dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0), 8577dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", 8587dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), 8597dd05578SSam Protsenko GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", 8607dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), 8617dd05578SSam Protsenko GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", 8627dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), 8637dd05578SSam Protsenko GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", 8647dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), 8657dd05578SSam Protsenko GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", 8667dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), 8677dd05578SSam Protsenko GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", 8687dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), 8697dd05578SSam Protsenko GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", 8707dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), 8717dd05578SSam Protsenko GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", 8727dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), 8737dd05578SSam Protsenko GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", 8747dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), 8757dd05578SSam Protsenko GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", 8767dd05578SSam Protsenko "mout_peri_bus_user", 8777dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), 8787dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", 8797dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), 8807dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", 8817dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), 8827dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", 8837dd05578SSam Protsenko "mout_peri_bus_user", 8847dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), 8857dd05578SSam Protsenko GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", 8867dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), 8877dd05578SSam Protsenko GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", 8887dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), 8897dd05578SSam Protsenko GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", 8907dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0), 8917dd05578SSam Protsenko GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", 8927dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0), 8936904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 8947dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk", 8957dd05578SSam Protsenko "mout_peri_bus_user", 8966904d7e5SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 8977dd05578SSam Protsenko }; 8987dd05578SSam Protsenko 8997dd05578SSam Protsenko static const struct samsung_cmu_info peri_cmu_info __initconst = { 9007dd05578SSam Protsenko .mux_clks = peri_mux_clks, 9017dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 9027dd05578SSam Protsenko .div_clks = peri_div_clks, 9037dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(peri_div_clks), 9047dd05578SSam Protsenko .gate_clks = peri_gate_clks, 9057dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 9067dd05578SSam Protsenko .nr_clk_ids = PERI_NR_CLK, 9077dd05578SSam Protsenko .clk_regs = peri_clk_regs, 9087dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 9097dd05578SSam Protsenko .clk_name = "dout_peri_bus", 9107dd05578SSam Protsenko }; 9117dd05578SSam Protsenko 912bcda841fSSam Protsenko static void __init exynos850_cmu_peri_init(struct device_node *np) 913bcda841fSSam Protsenko { 914bcda841fSSam Protsenko exynos850_register_cmu(NULL, np, &peri_cmu_info); 915bcda841fSSam Protsenko } 916bcda841fSSam Protsenko 917bcda841fSSam Protsenko /* Register CMU_PERI early, as it's needed for MCT timer */ 918bcda841fSSam Protsenko CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", 919bcda841fSSam Protsenko exynos850_cmu_peri_init); 920bcda841fSSam Protsenko 9217dd05578SSam Protsenko /* ---- CMU_CORE ------------------------------------------------------------ */ 9227dd05578SSam Protsenko 9237dd05578SSam Protsenko /* Register Offset definitions for CMU_CORE (0x12000000) */ 9247dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 9257dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610 9267dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 9277dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630 9287dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 9297dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 9307dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 9317dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 932*bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 9337dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 9347dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec 9357dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 9367dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c 937*bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 9387dd05578SSam Protsenko 9397dd05578SSam Protsenko static const unsigned long core_clk_regs[] __initconst = { 9407dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 9417dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 9427dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 9437dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 9447dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 9457dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 9467dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 9477dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 948*bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 9497dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 9507dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 9517dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 9527dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 953*bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 9547dd05578SSam Protsenko }; 9557dd05578SSam Protsenko 9567dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_CORE */ 9577dd05578SSam Protsenko PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; 9587dd05578SSam Protsenko PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; 9597dd05578SSam Protsenko PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" }; 9607dd05578SSam Protsenko PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" }; 9617dd05578SSam Protsenko PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; 9627dd05578SSam Protsenko 9637dd05578SSam Protsenko static const struct samsung_mux_clock core_mux_clks[] __initconst = { 9647dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 9657dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 9667dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, 9677dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), 9687dd05578SSam Protsenko MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", 9697dd05578SSam Protsenko mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 9707dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 9717dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p, 9727dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1), 9737dd05578SSam Protsenko MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, 9747dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), 9757dd05578SSam Protsenko }; 9767dd05578SSam Protsenko 9777dd05578SSam Protsenko static const struct samsung_div_clock core_div_clks[] __initconst = { 9787dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 9797dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 9807dd05578SSam Protsenko }; 9817dd05578SSam Protsenko 9827dd05578SSam Protsenko static const struct samsung_gate_clock core_gate_clks[] __initconst = { 9836904d7e5SSam Protsenko /* CCI (interconnect) clock must be always running */ 9847dd05578SSam Protsenko GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", 9856904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0), 9866904d7e5SSam Protsenko /* GIC (interrupt controller) clock must be always running */ 9877dd05578SSam Protsenko GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic", 9886904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0), 9897dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", 9907dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), 9917dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 9927dd05578SSam Protsenko "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 9937dd05578SSam Protsenko 21, CLK_SET_RATE_PARENT, 0), 9947dd05578SSam Protsenko GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", 9957dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), 9967dd05578SSam Protsenko GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", 9977dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), 998*bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 999*bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp", 1000*bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1001*bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk", 1002*bc471d1fSSam Protsenko "dout_core_busp", 1003*bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0), 10047dd05578SSam Protsenko }; 10057dd05578SSam Protsenko 10067dd05578SSam Protsenko static const struct samsung_cmu_info core_cmu_info __initconst = { 10077dd05578SSam Protsenko .mux_clks = core_mux_clks, 10087dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 10097dd05578SSam Protsenko .div_clks = core_div_clks, 10107dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(core_div_clks), 10117dd05578SSam Protsenko .gate_clks = core_gate_clks, 10127dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 10137dd05578SSam Protsenko .nr_clk_ids = CORE_NR_CLK, 10147dd05578SSam Protsenko .clk_regs = core_clk_regs, 10157dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 10167dd05578SSam Protsenko .clk_name = "dout_core_bus", 10177dd05578SSam Protsenko }; 10187dd05578SSam Protsenko 10197dd05578SSam Protsenko /* ---- CMU_DPU ------------------------------------------------------------- */ 10207dd05578SSam Protsenko 10217dd05578SSam Protsenko /* Register Offset definitions for CMU_DPU (0x13000000) */ 10227dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600 10237dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 10247dd05578SSam Protsenko #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004 10257dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010 10267dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014 10277dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018 10287dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028 10297dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c 10307dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038 10317dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c 10327dd05578SSam Protsenko 10337dd05578SSam Protsenko static const unsigned long dpu_clk_regs[] __initconst = { 10347dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 10357dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 10367dd05578SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 10377dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 10387dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 10397dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 10407dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 10417dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 10427dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 10437dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 10447dd05578SSam Protsenko }; 10457dd05578SSam Protsenko 10467dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_CORE */ 10477dd05578SSam Protsenko PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" }; 10487dd05578SSam Protsenko 10497dd05578SSam Protsenko static const struct samsung_mux_clock dpu_mux_clks[] __initconst = { 10507dd05578SSam Protsenko MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p, 10517dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1), 10527dd05578SSam Protsenko }; 10537dd05578SSam Protsenko 10547dd05578SSam Protsenko static const struct samsung_div_clock dpu_div_clks[] __initconst = { 10557dd05578SSam Protsenko DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user", 10567dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), 10577dd05578SSam Protsenko }; 10587dd05578SSam Protsenko 10597dd05578SSam Protsenko static const struct samsung_gate_clock dpu_gate_clks[] __initconst = { 10606904d7e5SSam Protsenko /* TODO: Should be enabled in DSIM driver */ 10617dd05578SSam Protsenko GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk", 10626904d7e5SSam Protsenko "dout_dpu_busp", 10636904d7e5SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0), 10647dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user", 10657dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0), 10667dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user", 10677dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0), 10687dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user", 10697dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0), 10707dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user", 10717dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0), 10727dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp", 10737dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0), 10747dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user", 10757dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0), 10767dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp", 10777dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0), 10787dd05578SSam Protsenko }; 10797dd05578SSam Protsenko 10807dd05578SSam Protsenko static const struct samsung_cmu_info dpu_cmu_info __initconst = { 10817dd05578SSam Protsenko .mux_clks = dpu_mux_clks, 10827dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks), 10837dd05578SSam Protsenko .div_clks = dpu_div_clks, 10847dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(dpu_div_clks), 10857dd05578SSam Protsenko .gate_clks = dpu_gate_clks, 10867dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), 10877dd05578SSam Protsenko .nr_clk_ids = DPU_NR_CLK, 10887dd05578SSam Protsenko .clk_regs = dpu_clk_regs, 10897dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), 10907dd05578SSam Protsenko .clk_name = "dout_dpu", 10917dd05578SSam Protsenko }; 10927dd05578SSam Protsenko 10937dd05578SSam Protsenko /* ---- platform_driver ----------------------------------------------------- */ 10947dd05578SSam Protsenko 10957dd05578SSam Protsenko static int __init exynos850_cmu_probe(struct platform_device *pdev) 10967dd05578SSam Protsenko { 10977dd05578SSam Protsenko const struct samsung_cmu_info *info; 10987dd05578SSam Protsenko struct device *dev = &pdev->dev; 10997dd05578SSam Protsenko 11007dd05578SSam Protsenko info = of_device_get_match_data(dev); 1101bcda841fSSam Protsenko exynos850_register_cmu(dev, dev->of_node, info); 11027dd05578SSam Protsenko 11037dd05578SSam Protsenko return 0; 11047dd05578SSam Protsenko } 11057dd05578SSam Protsenko 11067dd05578SSam Protsenko static const struct of_device_id exynos850_cmu_of_match[] = { 11077dd05578SSam Protsenko { 1108579839a9SSam Protsenko .compatible = "samsung,exynos850-cmu-apm", 1109579839a9SSam Protsenko .data = &apm_cmu_info, 1110579839a9SSam Protsenko }, { 111162782ba8SSam Protsenko .compatible = "samsung,exynos850-cmu-cmgp", 111262782ba8SSam Protsenko .data = &cmgp_cmu_info, 111362782ba8SSam Protsenko }, { 11147dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-hsi", 11157dd05578SSam Protsenko .data = &hsi_cmu_info, 11167dd05578SSam Protsenko }, { 11177dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-core", 11187dd05578SSam Protsenko .data = &core_cmu_info, 11197dd05578SSam Protsenko }, { 11207dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-dpu", 11217dd05578SSam Protsenko .data = &dpu_cmu_info, 11227dd05578SSam Protsenko }, { 11237dd05578SSam Protsenko }, 11247dd05578SSam Protsenko }; 11257dd05578SSam Protsenko 11267dd05578SSam Protsenko static struct platform_driver exynos850_cmu_driver __refdata = { 11277dd05578SSam Protsenko .driver = { 11287dd05578SSam Protsenko .name = "exynos850-cmu", 11297dd05578SSam Protsenko .of_match_table = exynos850_cmu_of_match, 11307dd05578SSam Protsenko .suppress_bind_attrs = true, 11317dd05578SSam Protsenko }, 11327dd05578SSam Protsenko .probe = exynos850_cmu_probe, 11337dd05578SSam Protsenko }; 11347dd05578SSam Protsenko 11357dd05578SSam Protsenko static int __init exynos850_cmu_init(void) 11367dd05578SSam Protsenko { 11377dd05578SSam Protsenko return platform_driver_register(&exynos850_cmu_driver); 11387dd05578SSam Protsenko } 11397dd05578SSam Protsenko core_initcall(exynos850_cmu_init); 1140