17dd05578SSam Protsenko // SPDX-License-Identifier: GPL-2.0-only 27dd05578SSam Protsenko /* 37dd05578SSam Protsenko * Copyright (C) 2021 Linaro Ltd. 47dd05578SSam Protsenko * Author: Sam Protsenko <semen.protsenko@linaro.org> 57dd05578SSam Protsenko * 67dd05578SSam Protsenko * Common Clock Framework support for Exynos850 SoC. 77dd05578SSam Protsenko */ 87dd05578SSam Protsenko 97dd05578SSam Protsenko #include <linux/clk.h> 107dd05578SSam Protsenko #include <linux/clk-provider.h> 117dd05578SSam Protsenko #include <linux/of.h> 127dd05578SSam Protsenko #include <linux/of_device.h> 137dd05578SSam Protsenko #include <linux/platform_device.h> 147dd05578SSam Protsenko 157dd05578SSam Protsenko #include <dt-bindings/clock/exynos850.h> 167dd05578SSam Protsenko 177dd05578SSam Protsenko #include "clk.h" 18cfe238e4SDavid Virag #include "clk-exynos-arm64.h" 19bcda841fSSam Protsenko 207dd05578SSam Protsenko /* ---- CMU_TOP ------------------------------------------------------------- */ 217dd05578SSam Protsenko 227dd05578SSam Protsenko /* Register Offset definitions for CMU_TOP (0x120e0000) */ 237dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_MMC 0x0000 247dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED0 0x0004 257dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED1 0x0008 267dd05578SSam Protsenko #define PLL_CON0_PLL_MMC 0x0100 277dd05578SSam Protsenko #define PLL_CON3_PLL_MMC 0x010c 287dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED0 0x0140 297dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED0 0x014c 307dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED1 0x0180 317dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED1 0x018c 32579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000 33*b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004 347dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 357dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 367dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c 377dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 387dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 397dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c 407dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 417dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 427dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 437dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 447dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 45579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c 46*b73fd95dSSam Protsenko #define CLK_CON_DIV_CLKCMU_AUD 0x1810 477dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 487dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 497dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 507dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c 517dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_DPU 0x1840 527dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 537dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c 547dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 557dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c 567dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 577dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 587dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c 597dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 607dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 617dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 627dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c 637dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 64579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008 65*b73fd95dSSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c 667dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 677dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 687dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 697dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 707dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c 717dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 727dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 737dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c 747dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 757dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 767dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 777dd05578SSam Protsenko 787dd05578SSam Protsenko static const unsigned long top_clk_regs[] __initconst = { 797dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, 807dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, 817dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, 827dd05578SSam Protsenko PLL_CON0_PLL_MMC, 837dd05578SSam Protsenko PLL_CON3_PLL_MMC, 847dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 857dd05578SSam Protsenko PLL_CON3_PLL_SHARED0, 867dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 877dd05578SSam Protsenko PLL_CON3_PLL_SHARED1, 88579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 89*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLKCMU_AUD, 907dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 917dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 927dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 937dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 947dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 957dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 967dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 977dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 987dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 997dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 1007dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 101579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_APM_BUS, 102*b73fd95dSSam Protsenko CLK_CON_DIV_CLKCMU_AUD, 1037dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 1047dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 1057dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 1067dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 1077dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 1087dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 1097dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 1107dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 1117dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 1127dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 1137dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 1147dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 1157dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 1167dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 1177dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 1187dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 1197dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 120579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 121*b73fd95dSSam Protsenko CLK_CON_GAT_GATE_CLKCMU_AUD, 1227dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 1237dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 1247dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 1257dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 1267dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 1277dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 1287dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 1297dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 1307dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 1317dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 1327dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 1337dd05578SSam Protsenko }; 1347dd05578SSam Protsenko 1357dd05578SSam Protsenko /* 1367dd05578SSam Protsenko * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set 1377dd05578SSam Protsenko * for those PLLs by default, so set_rate operation would fail. 1387dd05578SSam Protsenko */ 1397dd05578SSam Protsenko static const struct samsung_pll_clock top_pll_clks[] __initconst = { 1407dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 1417dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 1427dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 1437dd05578SSam Protsenko NULL), 1447dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 1457dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 1467dd05578SSam Protsenko NULL), 1477dd05578SSam Protsenko PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 1487dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 1497dd05578SSam Protsenko }; 1507dd05578SSam Protsenko 1517dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP */ 1527dd05578SSam Protsenko PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 1537dd05578SSam Protsenko PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 1547dd05578SSam Protsenko PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 155579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */ 156579839a9SSam Protsenko PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" }; 157*b73fd95dSSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */ 158*b73fd95dSSam Protsenko PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2", 159*b73fd95dSSam Protsenko "dout_shared1_div2", "dout_shared0_div3" }; 1607dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 1617dd05578SSam Protsenko PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", 1627dd05578SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 1637dd05578SSam Protsenko PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 1647dd05578SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 1657dd05578SSam Protsenko PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", 1667dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 1677dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 1687dd05578SSam Protsenko "oscclk", "oscclk" }; 1697dd05578SSam Protsenko PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", 1707dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 1717dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ 1727dd05578SSam Protsenko PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 1737dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", 1747dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 1757dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 1767dd05578SSam Protsenko "oscclk", "oscclk" }; 1777dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4", 1787dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 1797dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 1807dd05578SSam Protsenko PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 1817dd05578SSam Protsenko PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4", 1827dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 1837dd05578SSam Protsenko PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4", 1847dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 1857dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ 1867dd05578SSam Protsenko PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3", 1877dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 1887dd05578SSam Protsenko 1897dd05578SSam Protsenko static const struct samsung_mux_clock top_mux_clks[] __initconst = { 1907dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 1917dd05578SSam Protsenko MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 1927dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 4, 1), 1937dd05578SSam Protsenko MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 1947dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 4, 1), 1957dd05578SSam Protsenko MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 1967dd05578SSam Protsenko PLL_CON0_PLL_MMC, 4, 1), 1977dd05578SSam Protsenko 198579839a9SSam Protsenko /* APM */ 199579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", 200579839a9SSam Protsenko mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), 201579839a9SSam Protsenko 202*b73fd95dSSam Protsenko /* AUD */ 203*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p, 204*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2), 205*b73fd95dSSam Protsenko 2067dd05578SSam Protsenko /* CORE */ 2077dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 2087dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 2097dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 2107dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 2117dd05578SSam Protsenko MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, 2127dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), 2137dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, 2147dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), 2157dd05578SSam Protsenko 2167dd05578SSam Protsenko /* DPU */ 2177dd05578SSam Protsenko MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, 2187dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), 2197dd05578SSam Protsenko 2207dd05578SSam Protsenko /* HSI */ 2217dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, 2227dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), 2237dd05578SSam Protsenko MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, 2247dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), 2257dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, 2267dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), 2277dd05578SSam Protsenko 2287dd05578SSam Protsenko /* PERI */ 2297dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 2307dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 2317dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, 2327dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), 2337dd05578SSam Protsenko MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, 2347dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), 2357dd05578SSam Protsenko }; 2367dd05578SSam Protsenko 2377dd05578SSam Protsenko static const struct samsung_div_clock top_div_clks[] __initconst = { 2387dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 2397dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 2407dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 2417dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 2427dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 2437dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 2447dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 2457dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 2467dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 2477dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 2487dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 2497dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 2507dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 2517dd05578SSam Protsenko 252579839a9SSam Protsenko /* APM */ 253579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", 254579839a9SSam Protsenko "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), 255579839a9SSam Protsenko 256*b73fd95dSSam Protsenko /* AUD */ 257*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud", 258*b73fd95dSSam Protsenko CLK_CON_DIV_CLKCMU_AUD, 0, 4), 259*b73fd95dSSam Protsenko 2607dd05578SSam Protsenko /* CORE */ 2617dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 2627dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 2637dd05578SSam Protsenko DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 2647dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), 2657dd05578SSam Protsenko DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", 2667dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), 2677dd05578SSam Protsenko DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", 2687dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), 2697dd05578SSam Protsenko 2707dd05578SSam Protsenko /* DPU */ 2717dd05578SSam Protsenko DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", 2727dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 0, 4), 2737dd05578SSam Protsenko 2747dd05578SSam Protsenko /* HSI */ 2757dd05578SSam Protsenko DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", 2767dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), 2777dd05578SSam Protsenko DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", 2787dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), 2797dd05578SSam Protsenko DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", 2807dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), 2817dd05578SSam Protsenko 2827dd05578SSam Protsenko /* PERI */ 2837dd05578SSam Protsenko DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 2847dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 2857dd05578SSam Protsenko DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", 2867dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), 2877dd05578SSam Protsenko DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", 2887dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), 2897dd05578SSam Protsenko }; 2907dd05578SSam Protsenko 2917dd05578SSam Protsenko static const struct samsung_gate_clock top_gate_clks[] __initconst = { 2927dd05578SSam Protsenko /* CORE */ 2937dd05578SSam Protsenko GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 2947dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 2957dd05578SSam Protsenko GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 2967dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 2977dd05578SSam Protsenko GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", 2987dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), 2997dd05578SSam Protsenko GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", 3007dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), 3017dd05578SSam Protsenko 302579839a9SSam Protsenko /* APM */ 303579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", 304579839a9SSam Protsenko "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0), 305579839a9SSam Protsenko 306*b73fd95dSSam Protsenko /* AUD */ 307*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud", 308*b73fd95dSSam Protsenko CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0), 309*b73fd95dSSam Protsenko 3107dd05578SSam Protsenko /* DPU */ 3117dd05578SSam Protsenko GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", 3127dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), 3137dd05578SSam Protsenko 3147dd05578SSam Protsenko /* HSI */ 3157dd05578SSam Protsenko GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", 3167dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), 3177dd05578SSam Protsenko GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", 3187dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), 3197dd05578SSam Protsenko GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", 3207dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), 3217dd05578SSam Protsenko 3227dd05578SSam Protsenko /* PERI */ 3237dd05578SSam Protsenko GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 3247dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 3257dd05578SSam Protsenko GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", 3267dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), 3277dd05578SSam Protsenko GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", 3287dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), 3297dd05578SSam Protsenko }; 3307dd05578SSam Protsenko 3317dd05578SSam Protsenko static const struct samsung_cmu_info top_cmu_info __initconst = { 3327dd05578SSam Protsenko .pll_clks = top_pll_clks, 3337dd05578SSam Protsenko .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 3347dd05578SSam Protsenko .mux_clks = top_mux_clks, 3357dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 3367dd05578SSam Protsenko .div_clks = top_div_clks, 3377dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(top_div_clks), 3387dd05578SSam Protsenko .gate_clks = top_gate_clks, 3397dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 3407dd05578SSam Protsenko .nr_clk_ids = TOP_NR_CLK, 3417dd05578SSam Protsenko .clk_regs = top_clk_regs, 3427dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 3437dd05578SSam Protsenko }; 3447dd05578SSam Protsenko 3457dd05578SSam Protsenko static void __init exynos850_cmu_top_init(struct device_node *np) 3467dd05578SSam Protsenko { 347cfe238e4SDavid Virag exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 3487dd05578SSam Protsenko } 3497dd05578SSam Protsenko 350bcda841fSSam Protsenko /* Register CMU_TOP early, as it's a dependency for other early domains */ 3517dd05578SSam Protsenko CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", 3527dd05578SSam Protsenko exynos850_cmu_top_init); 3537dd05578SSam Protsenko 354579839a9SSam Protsenko /* ---- CMU_APM ------------------------------------------------------------- */ 355579839a9SSam Protsenko 356579839a9SSam Protsenko /* Register Offset definitions for CMU_APM (0x11800000) */ 357579839a9SSam Protsenko #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600 358579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610 359579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620 360579839a9SSam Protsenko #define PLL_CON0_MUX_DLL_USER 0x0630 361579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000 362579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004 363579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008 364579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800 365579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804 366579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808 367579839a9SSam Protsenko #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 368579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014 369bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018 370bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020 371579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024 372579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028 373579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034 374579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038 375579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc 376bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0 377579839a9SSam Protsenko 378579839a9SSam Protsenko static const unsigned long apm_clk_regs[] __initconst = { 379579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 380579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 381579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 382579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 383579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 384579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 385579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 386579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 387579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 388579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 389579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 390579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 391bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 392bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 393579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 394579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 395579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 396579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 397579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 398bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 399579839a9SSam Protsenko }; 400579839a9SSam Protsenko 401579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_APM */ 402579839a9SSam Protsenko PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" }; 403579839a9SSam Protsenko PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" }; 404579839a9SSam Protsenko PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" }; 405579839a9SSam Protsenko PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" }; 406579839a9SSam Protsenko PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" }; 407579839a9SSam Protsenko PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user", 408579839a9SSam Protsenko "mout_dll_user", "oscclk_rco_apm" }; 409579839a9SSam Protsenko PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" }; 410579839a9SSam Protsenko 411579839a9SSam Protsenko static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 412579839a9SSam Protsenko FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000), 413579839a9SSam Protsenko FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000), 414579839a9SSam Protsenko FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000), 415579839a9SSam Protsenko FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000), 416579839a9SSam Protsenko }; 417579839a9SSam Protsenko 418579839a9SSam Protsenko static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 419579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p, 420579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1), 421579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user", 422579839a9SSam Protsenko mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1), 423579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p, 424579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1), 425579839a9SSam Protsenko MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p, 426579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 4, 1), 427579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus", 428579839a9SSam Protsenko mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1), 429579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p, 430579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2), 431579839a9SSam Protsenko MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p, 432579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1), 433579839a9SSam Protsenko }; 434579839a9SSam Protsenko 435579839a9SSam Protsenko static const struct samsung_div_clock apm_div_clks[] __initconst = { 436579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus", 437579839a9SSam Protsenko "gout_clkcmu_chub_bus", 438579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3), 439579839a9SSam Protsenko DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus", 440579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3), 441579839a9SSam Protsenko DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus", 442579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3), 443579839a9SSam Protsenko }; 444579839a9SSam Protsenko 445579839a9SSam Protsenko static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 446579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus", 447579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0), 448579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus", 449579839a9SSam Protsenko "mout_clkcmu_chub_bus", 450579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0), 451579839a9SSam Protsenko GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus", 452579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0), 453579839a9SSam Protsenko GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus", 454579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0), 455579839a9SSam Protsenko GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus", 456579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0), 457579839a9SSam Protsenko GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c", 458579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0), 459579839a9SSam Protsenko GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus", 460579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0), 461bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 462bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus", 463bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, 464bc471d1fSSam Protsenko 0), 465bc471d1fSSam Protsenko GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", 466bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0), 467bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", 468bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), 469579839a9SSam Protsenko }; 470579839a9SSam Protsenko 471579839a9SSam Protsenko static const struct samsung_cmu_info apm_cmu_info __initconst = { 472579839a9SSam Protsenko .mux_clks = apm_mux_clks, 473579839a9SSam Protsenko .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 474579839a9SSam Protsenko .div_clks = apm_div_clks, 475579839a9SSam Protsenko .nr_div_clks = ARRAY_SIZE(apm_div_clks), 476579839a9SSam Protsenko .gate_clks = apm_gate_clks, 477579839a9SSam Protsenko .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 478579839a9SSam Protsenko .fixed_clks = apm_fixed_clks, 479579839a9SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 480579839a9SSam Protsenko .nr_clk_ids = APM_NR_CLK, 481579839a9SSam Protsenko .clk_regs = apm_clk_regs, 482579839a9SSam Protsenko .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 483579839a9SSam Protsenko .clk_name = "dout_clkcmu_apm_bus", 484579839a9SSam Protsenko }; 485579839a9SSam Protsenko 486*b73fd95dSSam Protsenko /* ---- CMU_AUD ------------------------------------------------------------- */ 487*b73fd95dSSam Protsenko 488*b73fd95dSSam Protsenko #define PLL_LOCKTIME_PLL_AUD 0x0000 489*b73fd95dSSam Protsenko #define PLL_CON0_PLL_AUD 0x0100 490*b73fd95dSSam Protsenko #define PLL_CON3_PLL_AUD 0x010c 491*b73fd95dSSam Protsenko #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600 492*b73fd95dSSam Protsenko #define PLL_CON0_MUX_TICK_USB_USER 0x0610 493*b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000 494*b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004 495*b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008 496*b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c 497*b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010 498*b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014 499*b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018 500*b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c 501*b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020 502*b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024 503*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800 504*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804 505*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808 506*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c 507*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810 508*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814 509*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818 510*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c 511*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820 512*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824 513*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828 514*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c 515*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830 516*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834 517*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838 518*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c 519*b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840 520*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000 521*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004 522*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008 523*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c 524*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010 525*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 526*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 527*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c 528*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 529*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c 530*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 531*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054 532*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058 533*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c 534*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070 535*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074 536*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088 537*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c 538*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4 539*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8 540*b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc 541*b73fd95dSSam Protsenko 542*b73fd95dSSam Protsenko static const unsigned long aud_clk_regs[] __initconst = { 543*b73fd95dSSam Protsenko PLL_LOCKTIME_PLL_AUD, 544*b73fd95dSSam Protsenko PLL_CON0_PLL_AUD, 545*b73fd95dSSam Protsenko PLL_CON3_PLL_AUD, 546*b73fd95dSSam Protsenko PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 547*b73fd95dSSam Protsenko PLL_CON0_MUX_TICK_USB_USER, 548*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU, 549*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 550*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_FM, 551*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 552*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 553*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 554*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 555*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 556*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 557*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 558*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_MCLK, 559*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 560*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSD, 561*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSP, 562*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CNT, 563*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU, 564*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 565*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 566*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM, 567*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 568*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 569*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 570*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 571*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 572*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 573*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 574*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 575*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 576*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 577*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 578*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 579*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 580*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 581*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 582*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 583*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 584*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 585*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 586*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 587*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 588*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 589*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 590*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 591*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 592*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 593*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 594*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 595*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 596*b73fd95dSSam Protsenko }; 597*b73fd95dSSam Protsenko 598*b73fd95dSSam Protsenko /* List of parent clocks for Muxes in CMU_AUD */ 599*b73fd95dSSam Protsenko PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" }; 600*b73fd95dSSam Protsenko PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" }; 601*b73fd95dSSam Protsenko PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" }; 602*b73fd95dSSam Protsenko PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" }; 603*b73fd95dSSam Protsenko PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" }; 604*b73fd95dSSam Protsenko PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" }; 605*b73fd95dSSam Protsenko PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" }; 606*b73fd95dSSam Protsenko PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" }; 607*b73fd95dSSam Protsenko PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" }; 608*b73fd95dSSam Protsenko PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" }; 609*b73fd95dSSam Protsenko PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" }; 610*b73fd95dSSam Protsenko PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" }; 611*b73fd95dSSam Protsenko PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" }; 612*b73fd95dSSam Protsenko 613*b73fd95dSSam Protsenko /* 614*b73fd95dSSam Protsenko * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set 615*b73fd95dSSam Protsenko * for that PLL by default, so set_rate operation would fail. 616*b73fd95dSSam Protsenko */ 617*b73fd95dSSam Protsenko static const struct samsung_pll_clock aud_pll_clks[] __initconst = { 618*b73fd95dSSam Protsenko PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 619*b73fd95dSSam Protsenko PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL), 620*b73fd95dSSam Protsenko }; 621*b73fd95dSSam Protsenko 622*b73fd95dSSam Protsenko static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { 623*b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000), 624*b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000), 625*b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000), 626*b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000), 627*b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000), 628*b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000), 629*b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000), 630*b73fd95dSSam Protsenko FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000), 631*b73fd95dSSam Protsenko }; 632*b73fd95dSSam Protsenko 633*b73fd95dSSam Protsenko static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 634*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, 635*b73fd95dSSam Protsenko PLL_CON0_PLL_AUD, 4, 1), 636*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p, 637*b73fd95dSSam Protsenko PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1), 638*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user", 639*b73fd95dSSam Protsenko mout_aud_tick_usb_user_p, 640*b73fd95dSSam Protsenko PLL_CON0_MUX_TICK_USB_USER, 4, 1), 641*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p, 642*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1), 643*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p, 644*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1), 645*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p, 646*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1), 647*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p, 648*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1), 649*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p, 650*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1), 651*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p, 652*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1), 653*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p, 654*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1), 655*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p, 656*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1), 657*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p, 658*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1), 659*b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p, 660*b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1), 661*b73fd95dSSam Protsenko }; 662*b73fd95dSSam Protsenko 663*b73fd95dSSam Protsenko static const struct samsung_div_clock aud_div_clks[] __initconst = { 664*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll", 665*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4), 666*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll", 667*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4), 668*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll", 669*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4), 670*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll", 671*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9), 672*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch", 673*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3), 674*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg", 675*b73fd95dSSam Protsenko "mout_aud_cpu_hch", 676*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3), 677*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif", 678*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2), 679*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif", 680*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10), 681*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif", 682*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10), 683*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif", 684*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10), 685*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif", 686*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10), 687*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif", 688*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10), 689*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif", 690*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10), 691*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif", 692*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10), 693*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif", 694*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10), 695*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user", 696*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1), 697*b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm", 698*b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10), 699*b73fd95dSSam Protsenko }; 700*b73fd95dSSam Protsenko 701*b73fd95dSSam Protsenko static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 702*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch", 703*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), 704*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk", 705*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0), 706*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg", 707*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0), 708*b73fd95dSSam Protsenko /* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */ 709*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd", 710*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0), 711*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd", 712*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0), 713*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd", 714*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0), 715*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd", 716*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0), 717*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd", 718*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0), 719*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd", 720*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0), 721*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd", 722*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0), 723*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp", 724*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0), 725*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk", 726*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0), 727*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt", 728*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0), 729*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0", 730*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0), 731*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1", 732*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0), 733*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2", 734*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0), 735*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3", 736*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0), 737*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4", 738*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0), 739*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5", 740*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0), 741*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6", 742*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0), 743*b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm", 744*b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0), 745*b73fd95dSSam Protsenko }; 746*b73fd95dSSam Protsenko 747*b73fd95dSSam Protsenko static const struct samsung_cmu_info aud_cmu_info __initconst = { 748*b73fd95dSSam Protsenko .pll_clks = aud_pll_clks, 749*b73fd95dSSam Protsenko .nr_pll_clks = ARRAY_SIZE(aud_pll_clks), 750*b73fd95dSSam Protsenko .mux_clks = aud_mux_clks, 751*b73fd95dSSam Protsenko .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 752*b73fd95dSSam Protsenko .div_clks = aud_div_clks, 753*b73fd95dSSam Protsenko .nr_div_clks = ARRAY_SIZE(aud_div_clks), 754*b73fd95dSSam Protsenko .gate_clks = aud_gate_clks, 755*b73fd95dSSam Protsenko .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 756*b73fd95dSSam Protsenko .fixed_clks = aud_fixed_clks, 757*b73fd95dSSam Protsenko .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), 758*b73fd95dSSam Protsenko .nr_clk_ids = AUD_NR_CLK, 759*b73fd95dSSam Protsenko .clk_regs = aud_clk_regs, 760*b73fd95dSSam Protsenko .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 761*b73fd95dSSam Protsenko .clk_name = "dout_aud", 762*b73fd95dSSam Protsenko }; 763*b73fd95dSSam Protsenko 76462782ba8SSam Protsenko /* ---- CMU_CMGP ------------------------------------------------------------ */ 76562782ba8SSam Protsenko 76662782ba8SSam Protsenko /* Register Offset definitions for CMU_CMGP (0x11c00000) */ 76762782ba8SSam Protsenko #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000 76862782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004 76962782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008 77062782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800 77162782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804 77262782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808 77362782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c 77462782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 77562782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018 776bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040 77762782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044 77862782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048 77962782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c 78062782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050 78162782ba8SSam Protsenko 78262782ba8SSam Protsenko static const unsigned long cmgp_clk_regs[] __initconst = { 78362782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 78462782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 78562782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 78662782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 78762782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 78862782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 78962782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 79062782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 79162782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 792bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 79362782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 79462782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 79562782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 79662782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 79762782ba8SSam Protsenko }; 79862782ba8SSam Protsenko 79962782ba8SSam Protsenko /* List of parent clocks for Muxes in CMU_CMGP */ 80062782ba8SSam Protsenko PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 80162782ba8SSam Protsenko PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 80262782ba8SSam Protsenko PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" }; 80362782ba8SSam Protsenko 80462782ba8SSam Protsenko static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = { 80562782ba8SSam Protsenko FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000), 80662782ba8SSam Protsenko }; 80762782ba8SSam Protsenko 80862782ba8SSam Protsenko static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = { 80962782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p, 81062782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 0, 1), 81162782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, 81262782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1), 81362782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, 81462782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1), 81562782ba8SSam Protsenko }; 81662782ba8SSam Protsenko 81762782ba8SSam Protsenko static const struct samsung_div_clock cmgp_div_clks[] __initconst = { 81862782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus", 81962782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), 82062782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", 82162782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5), 82262782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", 82362782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5), 82462782ba8SSam Protsenko }; 82562782ba8SSam Protsenko 82662782ba8SSam Protsenko static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { 82762782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk", 82862782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 82962782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0), 83062782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk", 83162782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 83262782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0), 8336904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 83462782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk", 83562782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 8366904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0), 83762782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0", 83862782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0), 83962782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk", 84062782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 84162782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0), 84262782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1", 84362782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0), 84462782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", 84562782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 84662782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), 847bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk", 848bc471d1fSSam Protsenko "gout_clkcmu_cmgp_bus", 849bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0), 85062782ba8SSam Protsenko }; 85162782ba8SSam Protsenko 85262782ba8SSam Protsenko static const struct samsung_cmu_info cmgp_cmu_info __initconst = { 85362782ba8SSam Protsenko .mux_clks = cmgp_mux_clks, 85462782ba8SSam Protsenko .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks), 85562782ba8SSam Protsenko .div_clks = cmgp_div_clks, 85662782ba8SSam Protsenko .nr_div_clks = ARRAY_SIZE(cmgp_div_clks), 85762782ba8SSam Protsenko .gate_clks = cmgp_gate_clks, 85862782ba8SSam Protsenko .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks), 85962782ba8SSam Protsenko .fixed_clks = cmgp_fixed_clks, 86062782ba8SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks), 86162782ba8SSam Protsenko .nr_clk_ids = CMGP_NR_CLK, 86262782ba8SSam Protsenko .clk_regs = cmgp_clk_regs, 86362782ba8SSam Protsenko .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), 86462782ba8SSam Protsenko .clk_name = "gout_clkcmu_cmgp_bus", 86562782ba8SSam Protsenko }; 86662782ba8SSam Protsenko 8677dd05578SSam Protsenko /* ---- CMU_HSI ------------------------------------------------------------- */ 8687dd05578SSam Protsenko 8697dd05578SSam Protsenko /* Register Offset definitions for CMU_HSI (0x13400000) */ 8707dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 8717dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 8727dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 8737dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 8747dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 8757dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c 8767dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 8777dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 8787dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 8797dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 8807dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 8817dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c 8827dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 8837dd05578SSam Protsenko 8847dd05578SSam Protsenko static const unsigned long hsi_clk_regs[] __initconst = { 8857dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 8867dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 8877dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 8887dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 8897dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 8907dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 8917dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 8927dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 8937dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 8947dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 8957dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 8967dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 8977dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 8987dd05578SSam Protsenko }; 8997dd05578SSam Protsenko 900dbaa27ccSSam Protsenko /* List of parent clocks for Muxes in CMU_HSI */ 9017dd05578SSam Protsenko PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" }; 9027dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" }; 9037dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" }; 9047dd05578SSam Protsenko PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" }; 9057dd05578SSam Protsenko 9067dd05578SSam Protsenko static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { 9077dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, 9087dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), 9097dd05578SSam Protsenko MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", 9107dd05578SSam Protsenko mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 9117dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 9127dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", 9137dd05578SSam Protsenko mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 9147dd05578SSam Protsenko 4, 1), 9157dd05578SSam Protsenko MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p, 9167dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1), 9177dd05578SSam Protsenko }; 9187dd05578SSam Protsenko 9197dd05578SSam Protsenko static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { 9207dd05578SSam Protsenko GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", 9217dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), 9227dd05578SSam Protsenko GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", 9237dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), 9247dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk", 9257dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), 9266904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 9277dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user", 9286904d7e5SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 9297dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", 9307dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), 9317dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 9327dd05578SSam Protsenko "mout_hsi_mmc_card_user", 9337dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), 9347dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", 9357dd05578SSam Protsenko "mout_hsi_bus_user", 9367dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), 9377dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", 9387dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), 9397dd05578SSam Protsenko GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", 9407dd05578SSam Protsenko "mout_hsi_bus_user", 9417dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), 9427dd05578SSam Protsenko }; 9437dd05578SSam Protsenko 9447dd05578SSam Protsenko static const struct samsung_cmu_info hsi_cmu_info __initconst = { 9457dd05578SSam Protsenko .mux_clks = hsi_mux_clks, 9467dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), 9477dd05578SSam Protsenko .gate_clks = hsi_gate_clks, 9487dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), 9497dd05578SSam Protsenko .nr_clk_ids = HSI_NR_CLK, 9507dd05578SSam Protsenko .clk_regs = hsi_clk_regs, 9517dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), 9527dd05578SSam Protsenko .clk_name = "dout_hsi_bus", 9537dd05578SSam Protsenko }; 9547dd05578SSam Protsenko 9557dd05578SSam Protsenko /* ---- CMU_PERI ------------------------------------------------------------ */ 9567dd05578SSam Protsenko 9577dd05578SSam Protsenko /* Register Offset definitions for CMU_PERI (0x10030000) */ 9587dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 9597dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610 9607dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620 9617dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 9627dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800 9637dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804 9647dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808 9657dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c 9667dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c 9677dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010 9687dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014 9697dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020 9707dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024 9717dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 9727dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c 9737dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030 9747dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034 9757dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038 9767dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c 9777dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040 9787dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044 9797dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048 9807dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c 9817dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050 9827dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054 9837dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c 9847dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064 9857dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c 9867dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0 9877dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4 9887dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 9897dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac 9907dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0 9917dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4 9927dd05578SSam Protsenko 9937dd05578SSam Protsenko static const unsigned long peri_clk_regs[] __initconst = { 9947dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 9957dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 9967dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 9977dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 9987dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 9997dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 10007dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 10017dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 10027dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 10037dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 10047dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 10057dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 10067dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 10077dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 10087dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 10097dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 10107dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 10117dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 10127dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 10137dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 10147dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 10157dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 10167dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 10177dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 10187dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 10197dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 10207dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 10217dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 10227dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 10237dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 10247dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 10257dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 10267dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 10277dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 10287dd05578SSam Protsenko }; 10297dd05578SSam Protsenko 10307dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_PERI */ 10317dd05578SSam Protsenko PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; 10327dd05578SSam Protsenko PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" }; 10337dd05578SSam Protsenko PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" }; 10347dd05578SSam Protsenko PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" }; 10357dd05578SSam Protsenko 10367dd05578SSam Protsenko static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 10377dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 10387dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 10397dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", 10407dd05578SSam Protsenko mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), 10417dd05578SSam Protsenko MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", 10427dd05578SSam Protsenko mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), 10437dd05578SSam Protsenko MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, 10447dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), 10457dd05578SSam Protsenko }; 10467dd05578SSam Protsenko 10477dd05578SSam Protsenko static const struct samsung_div_clock peri_div_clks[] __initconst = { 10487dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0", 10497dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5), 10507dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1", 10517dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), 10527dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", 10537dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), 10547dd05578SSam Protsenko DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", 10557dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), 10567dd05578SSam Protsenko }; 10577dd05578SSam Protsenko 10587dd05578SSam Protsenko static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 10597dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user", 10607dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0), 10617dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user", 10627dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0), 10637dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user", 10647dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0), 10657dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0", 10667dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0), 10677dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", 10687dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), 10697dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1", 10707dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0), 10717dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", 10727dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), 10737dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2", 10747dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0), 10757dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", 10767dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), 10777dd05578SSam Protsenko GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", 10787dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), 10797dd05578SSam Protsenko GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", 10807dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), 10817dd05578SSam Protsenko GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", 10827dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), 10837dd05578SSam Protsenko GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", 10847dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), 10857dd05578SSam Protsenko GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", 10867dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), 10877dd05578SSam Protsenko GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", 10887dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), 10897dd05578SSam Protsenko GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", 10907dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), 10917dd05578SSam Protsenko GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", 10927dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), 10937dd05578SSam Protsenko GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", 10947dd05578SSam Protsenko "mout_peri_bus_user", 10957dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), 10967dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", 10977dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), 10987dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", 10997dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), 11007dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", 11017dd05578SSam Protsenko "mout_peri_bus_user", 11027dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), 11037dd05578SSam Protsenko GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", 11047dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), 11057dd05578SSam Protsenko GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", 11067dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), 11077dd05578SSam Protsenko GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", 11087dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0), 11097dd05578SSam Protsenko GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", 11107dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0), 11116904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 11127dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk", 11137dd05578SSam Protsenko "mout_peri_bus_user", 11146904d7e5SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 11157dd05578SSam Protsenko }; 11167dd05578SSam Protsenko 11177dd05578SSam Protsenko static const struct samsung_cmu_info peri_cmu_info __initconst = { 11187dd05578SSam Protsenko .mux_clks = peri_mux_clks, 11197dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 11207dd05578SSam Protsenko .div_clks = peri_div_clks, 11217dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(peri_div_clks), 11227dd05578SSam Protsenko .gate_clks = peri_gate_clks, 11237dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 11247dd05578SSam Protsenko .nr_clk_ids = PERI_NR_CLK, 11257dd05578SSam Protsenko .clk_regs = peri_clk_regs, 11267dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 11277dd05578SSam Protsenko .clk_name = "dout_peri_bus", 11287dd05578SSam Protsenko }; 11297dd05578SSam Protsenko 1130bcda841fSSam Protsenko static void __init exynos850_cmu_peri_init(struct device_node *np) 1131bcda841fSSam Protsenko { 1132cfe238e4SDavid Virag exynos_arm64_register_cmu(NULL, np, &peri_cmu_info); 1133bcda841fSSam Protsenko } 1134bcda841fSSam Protsenko 1135bcda841fSSam Protsenko /* Register CMU_PERI early, as it's needed for MCT timer */ 1136bcda841fSSam Protsenko CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", 1137bcda841fSSam Protsenko exynos850_cmu_peri_init); 1138bcda841fSSam Protsenko 11397dd05578SSam Protsenko /* ---- CMU_CORE ------------------------------------------------------------ */ 11407dd05578SSam Protsenko 11417dd05578SSam Protsenko /* Register Offset definitions for CMU_CORE (0x12000000) */ 11427dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 11437dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610 11447dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 11457dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630 11467dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 11477dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 11487dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 11497dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 1150bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 11517dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 11527dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec 11537dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 11547dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c 1155bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 11567dd05578SSam Protsenko 11577dd05578SSam Protsenko static const unsigned long core_clk_regs[] __initconst = { 11587dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 11597dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 11607dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 11617dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 11627dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 11637dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 11647dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 11657dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 1166bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 11677dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 11687dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 11697dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 11707dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 1171bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 11727dd05578SSam Protsenko }; 11737dd05578SSam Protsenko 11747dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_CORE */ 11757dd05578SSam Protsenko PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; 11767dd05578SSam Protsenko PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; 11777dd05578SSam Protsenko PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" }; 11787dd05578SSam Protsenko PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" }; 11797dd05578SSam Protsenko PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; 11807dd05578SSam Protsenko 11817dd05578SSam Protsenko static const struct samsung_mux_clock core_mux_clks[] __initconst = { 11827dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 11837dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 11847dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, 11857dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), 11867dd05578SSam Protsenko MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", 11877dd05578SSam Protsenko mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 11887dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 11897dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p, 11907dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1), 11917dd05578SSam Protsenko MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, 11927dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), 11937dd05578SSam Protsenko }; 11947dd05578SSam Protsenko 11957dd05578SSam Protsenko static const struct samsung_div_clock core_div_clks[] __initconst = { 11967dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 11977dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 11987dd05578SSam Protsenko }; 11997dd05578SSam Protsenko 12007dd05578SSam Protsenko static const struct samsung_gate_clock core_gate_clks[] __initconst = { 12016904d7e5SSam Protsenko /* CCI (interconnect) clock must be always running */ 12027dd05578SSam Protsenko GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", 12036904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0), 12046904d7e5SSam Protsenko /* GIC (interrupt controller) clock must be always running */ 12057dd05578SSam Protsenko GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic", 12066904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0), 12077dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", 12087dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), 12097dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 12107dd05578SSam Protsenko "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 12117dd05578SSam Protsenko 21, CLK_SET_RATE_PARENT, 0), 12127dd05578SSam Protsenko GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", 12137dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), 12147dd05578SSam Protsenko GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", 12157dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), 1216bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 1217bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp", 1218bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1219bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk", 1220bc471d1fSSam Protsenko "dout_core_busp", 1221bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0), 12227dd05578SSam Protsenko }; 12237dd05578SSam Protsenko 12247dd05578SSam Protsenko static const struct samsung_cmu_info core_cmu_info __initconst = { 12257dd05578SSam Protsenko .mux_clks = core_mux_clks, 12267dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 12277dd05578SSam Protsenko .div_clks = core_div_clks, 12287dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(core_div_clks), 12297dd05578SSam Protsenko .gate_clks = core_gate_clks, 12307dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 12317dd05578SSam Protsenko .nr_clk_ids = CORE_NR_CLK, 12327dd05578SSam Protsenko .clk_regs = core_clk_regs, 12337dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 12347dd05578SSam Protsenko .clk_name = "dout_core_bus", 12357dd05578SSam Protsenko }; 12367dd05578SSam Protsenko 12377dd05578SSam Protsenko /* ---- CMU_DPU ------------------------------------------------------------- */ 12387dd05578SSam Protsenko 12397dd05578SSam Protsenko /* Register Offset definitions for CMU_DPU (0x13000000) */ 12407dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600 12417dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 12427dd05578SSam Protsenko #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004 12437dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010 12447dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014 12457dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018 12467dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028 12477dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c 12487dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038 12497dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c 12507dd05578SSam Protsenko 12517dd05578SSam Protsenko static const unsigned long dpu_clk_regs[] __initconst = { 12527dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 12537dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 12547dd05578SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 12557dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 12567dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 12577dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 12587dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 12597dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 12607dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 12617dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 12627dd05578SSam Protsenko }; 12637dd05578SSam Protsenko 1264dbaa27ccSSam Protsenko /* List of parent clocks for Muxes in CMU_DPU */ 12657dd05578SSam Protsenko PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" }; 12667dd05578SSam Protsenko 12677dd05578SSam Protsenko static const struct samsung_mux_clock dpu_mux_clks[] __initconst = { 12687dd05578SSam Protsenko MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p, 12697dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1), 12707dd05578SSam Protsenko }; 12717dd05578SSam Protsenko 12727dd05578SSam Protsenko static const struct samsung_div_clock dpu_div_clks[] __initconst = { 12737dd05578SSam Protsenko DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user", 12747dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), 12757dd05578SSam Protsenko }; 12767dd05578SSam Protsenko 12777dd05578SSam Protsenko static const struct samsung_gate_clock dpu_gate_clks[] __initconst = { 12786904d7e5SSam Protsenko /* TODO: Should be enabled in DSIM driver */ 12797dd05578SSam Protsenko GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk", 12806904d7e5SSam Protsenko "dout_dpu_busp", 12816904d7e5SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0), 12827dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user", 12837dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0), 12847dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user", 12857dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0), 12867dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user", 12877dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0), 12887dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user", 12897dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0), 12907dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp", 12917dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0), 12927dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user", 12937dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0), 12947dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp", 12957dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0), 12967dd05578SSam Protsenko }; 12977dd05578SSam Protsenko 12987dd05578SSam Protsenko static const struct samsung_cmu_info dpu_cmu_info __initconst = { 12997dd05578SSam Protsenko .mux_clks = dpu_mux_clks, 13007dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks), 13017dd05578SSam Protsenko .div_clks = dpu_div_clks, 13027dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(dpu_div_clks), 13037dd05578SSam Protsenko .gate_clks = dpu_gate_clks, 13047dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), 13057dd05578SSam Protsenko .nr_clk_ids = DPU_NR_CLK, 13067dd05578SSam Protsenko .clk_regs = dpu_clk_regs, 13077dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), 13087dd05578SSam Protsenko .clk_name = "dout_dpu", 13097dd05578SSam Protsenko }; 13107dd05578SSam Protsenko 13117dd05578SSam Protsenko /* ---- platform_driver ----------------------------------------------------- */ 13127dd05578SSam Protsenko 13137dd05578SSam Protsenko static int __init exynos850_cmu_probe(struct platform_device *pdev) 13147dd05578SSam Protsenko { 13157dd05578SSam Protsenko const struct samsung_cmu_info *info; 13167dd05578SSam Protsenko struct device *dev = &pdev->dev; 13177dd05578SSam Protsenko 13187dd05578SSam Protsenko info = of_device_get_match_data(dev); 1319cfe238e4SDavid Virag exynos_arm64_register_cmu(dev, dev->of_node, info); 13207dd05578SSam Protsenko 13217dd05578SSam Protsenko return 0; 13227dd05578SSam Protsenko } 13237dd05578SSam Protsenko 13247dd05578SSam Protsenko static const struct of_device_id exynos850_cmu_of_match[] = { 13257dd05578SSam Protsenko { 1326579839a9SSam Protsenko .compatible = "samsung,exynos850-cmu-apm", 1327579839a9SSam Protsenko .data = &apm_cmu_info, 1328579839a9SSam Protsenko }, { 1329*b73fd95dSSam Protsenko .compatible = "samsung,exynos850-cmu-aud", 1330*b73fd95dSSam Protsenko .data = &aud_cmu_info, 1331*b73fd95dSSam Protsenko }, { 133262782ba8SSam Protsenko .compatible = "samsung,exynos850-cmu-cmgp", 133362782ba8SSam Protsenko .data = &cmgp_cmu_info, 133462782ba8SSam Protsenko }, { 13357dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-hsi", 13367dd05578SSam Protsenko .data = &hsi_cmu_info, 13377dd05578SSam Protsenko }, { 13387dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-core", 13397dd05578SSam Protsenko .data = &core_cmu_info, 13407dd05578SSam Protsenko }, { 13417dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-dpu", 13427dd05578SSam Protsenko .data = &dpu_cmu_info, 13437dd05578SSam Protsenko }, { 13447dd05578SSam Protsenko }, 13457dd05578SSam Protsenko }; 13467dd05578SSam Protsenko 13477dd05578SSam Protsenko static struct platform_driver exynos850_cmu_driver __refdata = { 13487dd05578SSam Protsenko .driver = { 13497dd05578SSam Protsenko .name = "exynos850-cmu", 13507dd05578SSam Protsenko .of_match_table = exynos850_cmu_of_match, 13517dd05578SSam Protsenko .suppress_bind_attrs = true, 13527dd05578SSam Protsenko }, 13537dd05578SSam Protsenko .probe = exynos850_cmu_probe, 13547dd05578SSam Protsenko }; 13557dd05578SSam Protsenko 13567dd05578SSam Protsenko static int __init exynos850_cmu_init(void) 13577dd05578SSam Protsenko { 13587dd05578SSam Protsenko return platform_driver_register(&exynos850_cmu_driver); 13597dd05578SSam Protsenko } 13607dd05578SSam Protsenko core_initcall(exynos850_cmu_init); 1361