17dd05578SSam Protsenko // SPDX-License-Identifier: GPL-2.0-only 27dd05578SSam Protsenko /* 37dd05578SSam Protsenko * Copyright (C) 2021 Linaro Ltd. 47dd05578SSam Protsenko * Author: Sam Protsenko <semen.protsenko@linaro.org> 57dd05578SSam Protsenko * 67dd05578SSam Protsenko * Common Clock Framework support for Exynos850 SoC. 77dd05578SSam Protsenko */ 87dd05578SSam Protsenko 97dd05578SSam Protsenko #include <linux/clk.h> 107dd05578SSam Protsenko #include <linux/clk-provider.h> 117dd05578SSam Protsenko #include <linux/of.h> 127dd05578SSam Protsenko #include <linux/of_device.h> 137dd05578SSam Protsenko #include <linux/platform_device.h> 147dd05578SSam Protsenko 157dd05578SSam Protsenko #include <dt-bindings/clock/exynos850.h> 167dd05578SSam Protsenko 177dd05578SSam Protsenko #include "clk.h" 18cfe238e4SDavid Virag #include "clk-exynos-arm64.h" 19bcda841fSSam Protsenko 207dd05578SSam Protsenko /* ---- CMU_TOP ------------------------------------------------------------- */ 217dd05578SSam Protsenko 227dd05578SSam Protsenko /* Register Offset definitions for CMU_TOP (0x120e0000) */ 237dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_MMC 0x0000 247dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED0 0x0004 257dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED1 0x0008 267dd05578SSam Protsenko #define PLL_CON0_PLL_MMC 0x0100 277dd05578SSam Protsenko #define PLL_CON3_PLL_MMC 0x010c 287dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED0 0x0140 297dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED0 0x014c 307dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED1 0x0180 317dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED1 0x018c 32579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000 33b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004 347dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 357dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 367dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c 377dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 387dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 39e145c765SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038 407dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c 417dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 427dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 43bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048 44bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c 45bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050 46bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054 477f36d3b6SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058 487f36d3b6SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c 497f36d3b6SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060 507f36d3b6SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064 517dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 527dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 537dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 54579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c 55b73fd95dSSam Protsenko #define CLK_CON_DIV_CLKCMU_AUD 0x1810 567dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 577dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 587dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 597dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c 607dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_DPU 0x1840 61e145c765SSam Protsenko #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844 627dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 637dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c 647dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 65bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854 66bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858 67bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c 68bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860 697f36d3b6SSam Protsenko #define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864 707f36d3b6SSam Protsenko #define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868 717f36d3b6SSam Protsenko #define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c 727f36d3b6SSam Protsenko #define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870 737dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c 747dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 757dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 767dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c 777dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 787dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 797dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 807dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c 817dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 82579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008 83b73fd95dSSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c 847dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 857dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 867dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 877dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 887dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c 89e145c765SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040 907dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 917dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 927dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c 93bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050 94bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054 95bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058 96bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c 977f36d3b6SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060 987f36d3b6SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064 997f36d3b6SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068 1007f36d3b6SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c 1017dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 1027dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 1037dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 1047dd05578SSam Protsenko 1057dd05578SSam Protsenko static const unsigned long top_clk_regs[] __initconst = { 1067dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, 1077dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, 1087dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, 1097dd05578SSam Protsenko PLL_CON0_PLL_MMC, 1107dd05578SSam Protsenko PLL_CON3_PLL_MMC, 1117dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 1127dd05578SSam Protsenko PLL_CON3_PLL_SHARED0, 1137dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 1147dd05578SSam Protsenko PLL_CON3_PLL_SHARED1, 115579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 116b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLKCMU_AUD, 1177dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 1187dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 1197dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 1207dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 1217dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 122e145c765SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 1237dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 1247dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 1257dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 126bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 127bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 128bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 129bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 1307f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 1317f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 1327f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 1337f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 1347dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 1357dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 1367dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 137579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_APM_BUS, 138b73fd95dSSam Protsenko CLK_CON_DIV_CLKCMU_AUD, 1397dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 1407dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 1417dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 1427dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 1437dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 144e145c765SSam Protsenko CLK_CON_DIV_CLKCMU_G3D_SWITCH, 1457dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 1467dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 1477dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 148bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_BUS, 149bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_GDC, 150bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_ITP, 151bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_VRA, 1527f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 1537f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 1547f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 1557f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 1567dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 1577dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 1587dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 1597dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 1607dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 1617dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 1627dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 1637dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 1647dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 165579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 166b73fd95dSSam Protsenko CLK_CON_GAT_GATE_CLKCMU_AUD, 1677dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 1687dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 1697dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 1707dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 1717dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 172e145c765SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 1737dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 1747dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 1757dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 176bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 177bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 178bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 179bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 1807f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 1817f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 1827f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 1837f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 1847dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 1857dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 1867dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 1877dd05578SSam Protsenko }; 1887dd05578SSam Protsenko 1897dd05578SSam Protsenko /* 1907dd05578SSam Protsenko * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set 1917dd05578SSam Protsenko * for those PLLs by default, so set_rate operation would fail. 1927dd05578SSam Protsenko */ 1937dd05578SSam Protsenko static const struct samsung_pll_clock top_pll_clks[] __initconst = { 1947dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 1957dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 1967dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 1977dd05578SSam Protsenko NULL), 1987dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 1997dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 2007dd05578SSam Protsenko NULL), 2017dd05578SSam Protsenko PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 2027dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 2037dd05578SSam Protsenko }; 2047dd05578SSam Protsenko 2057dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP */ 2067dd05578SSam Protsenko PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 2077dd05578SSam Protsenko PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 2087dd05578SSam Protsenko PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 209579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */ 210579839a9SSam Protsenko PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" }; 211b73fd95dSSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */ 212b73fd95dSSam Protsenko PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2", 213b73fd95dSSam Protsenko "dout_shared1_div2", "dout_shared0_div3" }; 2147dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 2157dd05578SSam Protsenko PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", 2167dd05578SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 2177dd05578SSam Protsenko PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 2187dd05578SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 2197dd05578SSam Protsenko PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", 2207dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 2217dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 2227dd05578SSam Protsenko "oscclk", "oscclk" }; 2237dd05578SSam Protsenko PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", 2247dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 225e145c765SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */ 226e145c765SSam Protsenko PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", 227e145c765SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 2287dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ 2297dd05578SSam Protsenko PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 2307dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", 2317dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 2327dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 2337dd05578SSam Protsenko "oscclk", "oscclk" }; 2347dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4", 2357dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 236bf3a4c51SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */ 237bf3a4c51SSam Protsenko PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", 238bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 239bf3a4c51SSam Protsenko PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2", 240bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 241bf3a4c51SSam Protsenko PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2", 242bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 243bf3a4c51SSam Protsenko PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2", 244bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 2457f36d3b6SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */ 2467f36d3b6SSam Protsenko PNAME(mout_mfcmscl_mfc_p) = { "dout_shared1_div2", "dout_shared0_div3", 2477f36d3b6SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 2487f36d3b6SSam Protsenko PNAME(mout_mfcmscl_m2m_p) = { "dout_shared1_div2", "dout_shared0_div3", 2497f36d3b6SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 2507f36d3b6SSam Protsenko PNAME(mout_mfcmscl_mcsc_p) = { "dout_shared1_div2", "dout_shared0_div3", 2517f36d3b6SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 2527f36d3b6SSam Protsenko PNAME(mout_mfcmscl_jpeg_p) = { "dout_shared0_div3", "dout_shared1_div3", 2537f36d3b6SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 2547dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 2557dd05578SSam Protsenko PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 2567dd05578SSam Protsenko PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4", 2577dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2587dd05578SSam Protsenko PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4", 2597dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2607dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ 2617dd05578SSam Protsenko PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3", 2627dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 2637dd05578SSam Protsenko 2647dd05578SSam Protsenko static const struct samsung_mux_clock top_mux_clks[] __initconst = { 2657dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 2667dd05578SSam Protsenko MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 2677dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 4, 1), 2687dd05578SSam Protsenko MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 2697dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 4, 1), 2707dd05578SSam Protsenko MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 2717dd05578SSam Protsenko PLL_CON0_PLL_MMC, 4, 1), 2727dd05578SSam Protsenko 273579839a9SSam Protsenko /* APM */ 274579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", 275579839a9SSam Protsenko mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), 276579839a9SSam Protsenko 277b73fd95dSSam Protsenko /* AUD */ 278b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p, 279b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2), 280b73fd95dSSam Protsenko 2817dd05578SSam Protsenko /* CORE */ 2827dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 2837dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 2847dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 2857dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 2867dd05578SSam Protsenko MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, 2877dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), 2887dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, 2897dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), 2907dd05578SSam Protsenko 2917dd05578SSam Protsenko /* DPU */ 2927dd05578SSam Protsenko MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, 2937dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), 2947dd05578SSam Protsenko 295e145c765SSam Protsenko /* G3D */ 296e145c765SSam Protsenko MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p, 297e145c765SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2), 298e145c765SSam Protsenko 2997dd05578SSam Protsenko /* HSI */ 3007dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, 3017dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), 3027dd05578SSam Protsenko MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, 3037dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), 3047dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, 3057dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), 3067dd05578SSam Protsenko 307bf3a4c51SSam Protsenko /* IS */ 308bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p, 309bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2), 310bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p, 311bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2), 312bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p, 313bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2), 314bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p, 315bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2), 316bf3a4c51SSam Protsenko 3177f36d3b6SSam Protsenko /* MFCMSCL */ 3187f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p, 3197f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2), 3207f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p, 3217f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2), 3227f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p, 3237f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2), 3247f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p, 3257f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2), 3267f36d3b6SSam Protsenko 3277dd05578SSam Protsenko /* PERI */ 3287dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 3297dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 3307dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, 3317dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), 3327dd05578SSam Protsenko MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, 3337dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), 3347dd05578SSam Protsenko }; 3357dd05578SSam Protsenko 3367dd05578SSam Protsenko static const struct samsung_div_clock top_div_clks[] __initconst = { 3377dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 3387dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 3397dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 3407dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 3417dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 3427dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 3437dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 3447dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 3457dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 3467dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 3477dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 3487dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 3497dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 3507dd05578SSam Protsenko 351579839a9SSam Protsenko /* APM */ 352579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", 353579839a9SSam Protsenko "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), 354579839a9SSam Protsenko 355b73fd95dSSam Protsenko /* AUD */ 356b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud", 357b73fd95dSSam Protsenko CLK_CON_DIV_CLKCMU_AUD, 0, 4), 358b73fd95dSSam Protsenko 3597dd05578SSam Protsenko /* CORE */ 3607dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 3617dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 3627dd05578SSam Protsenko DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 3637dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), 3647dd05578SSam Protsenko DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", 3657dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), 3667dd05578SSam Protsenko DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", 3677dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), 3687dd05578SSam Protsenko 3697dd05578SSam Protsenko /* DPU */ 3707dd05578SSam Protsenko DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", 3717dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 0, 4), 3727dd05578SSam Protsenko 373e145c765SSam Protsenko /* G3D */ 374e145c765SSam Protsenko DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch", 375e145c765SSam Protsenko CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), 376e145c765SSam Protsenko 3777dd05578SSam Protsenko /* HSI */ 3787dd05578SSam Protsenko DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", 3797dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), 3807dd05578SSam Protsenko DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", 3817dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), 3827dd05578SSam Protsenko DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", 3837dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), 3847dd05578SSam Protsenko 385bf3a4c51SSam Protsenko /* IS */ 386bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus", 387bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4), 388bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp", 389bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4), 390bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra", 391bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4), 392bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc", 393bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4), 394bf3a4c51SSam Protsenko 3957f36d3b6SSam Protsenko /* MFCMSCL */ 3967f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc", 3977f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4), 3987f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m", 3997f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4), 4007f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc", 4017f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4), 4027f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg", 4037f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4), 4047f36d3b6SSam Protsenko 4057dd05578SSam Protsenko /* PERI */ 4067dd05578SSam Protsenko DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 4077dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 4087dd05578SSam Protsenko DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", 4097dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), 4107dd05578SSam Protsenko DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", 4117dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), 4127dd05578SSam Protsenko }; 4137dd05578SSam Protsenko 4147dd05578SSam Protsenko static const struct samsung_gate_clock top_gate_clks[] __initconst = { 4157dd05578SSam Protsenko /* CORE */ 4167dd05578SSam Protsenko GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 4177dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 4187dd05578SSam Protsenko GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 4197dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 4207dd05578SSam Protsenko GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", 4217dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), 4227dd05578SSam Protsenko GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", 4237dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), 4247dd05578SSam Protsenko 425579839a9SSam Protsenko /* APM */ 426579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", 427579839a9SSam Protsenko "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0), 428579839a9SSam Protsenko 429b73fd95dSSam Protsenko /* AUD */ 430b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud", 431b73fd95dSSam Protsenko CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0), 432b73fd95dSSam Protsenko 4337dd05578SSam Protsenko /* DPU */ 4347dd05578SSam Protsenko GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", 4357dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), 4367dd05578SSam Protsenko 437e145c765SSam Protsenko /* G3D */ 438e145c765SSam Protsenko GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch", 439e145c765SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0), 440e145c765SSam Protsenko 4417dd05578SSam Protsenko /* HSI */ 4427dd05578SSam Protsenko GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", 4437dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), 4447dd05578SSam Protsenko GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", 4457dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), 4467dd05578SSam Protsenko GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", 4477dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), 4487dd05578SSam Protsenko 449bf3a4c51SSam Protsenko /* IS */ 450bf3a4c51SSam Protsenko /* TODO: These clocks have to be always enabled to access CMU_IS regs */ 451bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus", 452bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0), 453bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp", 454bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0), 455bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra", 456bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0), 457bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc", 458bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0), 459bf3a4c51SSam Protsenko 4607f36d3b6SSam Protsenko /* MFCMSCL */ 4617f36d3b6SSam Protsenko /* TODO: These have to be always enabled to access CMU_MFCMSCL regs */ 4627f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc", 4637f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0), 4647f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m", 4657f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0), 4667f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc", 4677f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0), 4687f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg", 4697f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0), 4707f36d3b6SSam Protsenko 4717dd05578SSam Protsenko /* PERI */ 4727dd05578SSam Protsenko GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 4737dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 4747dd05578SSam Protsenko GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", 4757dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), 4767dd05578SSam Protsenko GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", 4777dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), 4787dd05578SSam Protsenko }; 4797dd05578SSam Protsenko 4807dd05578SSam Protsenko static const struct samsung_cmu_info top_cmu_info __initconst = { 4817dd05578SSam Protsenko .pll_clks = top_pll_clks, 4827dd05578SSam Protsenko .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 4837dd05578SSam Protsenko .mux_clks = top_mux_clks, 4847dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 4857dd05578SSam Protsenko .div_clks = top_div_clks, 4867dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(top_div_clks), 4877dd05578SSam Protsenko .gate_clks = top_gate_clks, 4887dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 4897dd05578SSam Protsenko .nr_clk_ids = TOP_NR_CLK, 4907dd05578SSam Protsenko .clk_regs = top_clk_regs, 4917dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 4927dd05578SSam Protsenko }; 4937dd05578SSam Protsenko 4947dd05578SSam Protsenko static void __init exynos850_cmu_top_init(struct device_node *np) 4957dd05578SSam Protsenko { 496cfe238e4SDavid Virag exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 4977dd05578SSam Protsenko } 4987dd05578SSam Protsenko 499bcda841fSSam Protsenko /* Register CMU_TOP early, as it's a dependency for other early domains */ 5007dd05578SSam Protsenko CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", 5017dd05578SSam Protsenko exynos850_cmu_top_init); 5027dd05578SSam Protsenko 503579839a9SSam Protsenko /* ---- CMU_APM ------------------------------------------------------------- */ 504579839a9SSam Protsenko 505579839a9SSam Protsenko /* Register Offset definitions for CMU_APM (0x11800000) */ 506579839a9SSam Protsenko #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600 507579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610 508579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620 509579839a9SSam Protsenko #define PLL_CON0_MUX_DLL_USER 0x0630 510579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000 511579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004 512579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008 513579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800 514579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804 515579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808 516579839a9SSam Protsenko #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 517579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014 518bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018 519bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020 520579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024 521579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028 522579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034 523579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038 524579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc 525bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0 526579839a9SSam Protsenko 527579839a9SSam Protsenko static const unsigned long apm_clk_regs[] __initconst = { 528579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 529579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 530579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 531579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 532579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 533579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 534579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 535579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 536579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 537579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 538579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 539579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 540bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 541bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 542579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 543579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 544579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 545579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 546579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 547bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 548579839a9SSam Protsenko }; 549579839a9SSam Protsenko 550579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_APM */ 551579839a9SSam Protsenko PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" }; 552579839a9SSam Protsenko PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" }; 553579839a9SSam Protsenko PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" }; 554579839a9SSam Protsenko PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" }; 555579839a9SSam Protsenko PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" }; 556579839a9SSam Protsenko PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user", 557579839a9SSam Protsenko "mout_dll_user", "oscclk_rco_apm" }; 558579839a9SSam Protsenko PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" }; 559579839a9SSam Protsenko 560579839a9SSam Protsenko static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 561579839a9SSam Protsenko FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000), 562579839a9SSam Protsenko FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000), 563579839a9SSam Protsenko FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000), 564579839a9SSam Protsenko FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000), 565579839a9SSam Protsenko }; 566579839a9SSam Protsenko 567579839a9SSam Protsenko static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 568579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p, 569579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1), 570579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user", 571579839a9SSam Protsenko mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1), 572579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p, 573579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1), 574579839a9SSam Protsenko MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p, 575579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 4, 1), 576579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus", 577579839a9SSam Protsenko mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1), 578579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p, 579579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2), 580579839a9SSam Protsenko MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p, 581579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1), 582579839a9SSam Protsenko }; 583579839a9SSam Protsenko 584579839a9SSam Protsenko static const struct samsung_div_clock apm_div_clks[] __initconst = { 585579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus", 586579839a9SSam Protsenko "gout_clkcmu_chub_bus", 587579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3), 588579839a9SSam Protsenko DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus", 589579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3), 590579839a9SSam Protsenko DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus", 591579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3), 592579839a9SSam Protsenko }; 593579839a9SSam Protsenko 594579839a9SSam Protsenko static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 595579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus", 596579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0), 597579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus", 598579839a9SSam Protsenko "mout_clkcmu_chub_bus", 599579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0), 600579839a9SSam Protsenko GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus", 601579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0), 602579839a9SSam Protsenko GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus", 603579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0), 604579839a9SSam Protsenko GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus", 605579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0), 606579839a9SSam Protsenko GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c", 607579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0), 608579839a9SSam Protsenko GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus", 609579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0), 610bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 611bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus", 612bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, 613bc471d1fSSam Protsenko 0), 614bc471d1fSSam Protsenko GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", 615bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0), 616bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", 617bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), 618579839a9SSam Protsenko }; 619579839a9SSam Protsenko 620579839a9SSam Protsenko static const struct samsung_cmu_info apm_cmu_info __initconst = { 621579839a9SSam Protsenko .mux_clks = apm_mux_clks, 622579839a9SSam Protsenko .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 623579839a9SSam Protsenko .div_clks = apm_div_clks, 624579839a9SSam Protsenko .nr_div_clks = ARRAY_SIZE(apm_div_clks), 625579839a9SSam Protsenko .gate_clks = apm_gate_clks, 626579839a9SSam Protsenko .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 627579839a9SSam Protsenko .fixed_clks = apm_fixed_clks, 628579839a9SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 629579839a9SSam Protsenko .nr_clk_ids = APM_NR_CLK, 630579839a9SSam Protsenko .clk_regs = apm_clk_regs, 631579839a9SSam Protsenko .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 632579839a9SSam Protsenko .clk_name = "dout_clkcmu_apm_bus", 633579839a9SSam Protsenko }; 634579839a9SSam Protsenko 635b73fd95dSSam Protsenko /* ---- CMU_AUD ------------------------------------------------------------- */ 636b73fd95dSSam Protsenko 637b73fd95dSSam Protsenko #define PLL_LOCKTIME_PLL_AUD 0x0000 638b73fd95dSSam Protsenko #define PLL_CON0_PLL_AUD 0x0100 639b73fd95dSSam Protsenko #define PLL_CON3_PLL_AUD 0x010c 640b73fd95dSSam Protsenko #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600 641b73fd95dSSam Protsenko #define PLL_CON0_MUX_TICK_USB_USER 0x0610 642b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000 643b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004 644b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008 645b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c 646b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010 647b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014 648b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018 649b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c 650b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020 651b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024 652b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800 653b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804 654b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808 655b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c 656b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810 657b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814 658b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818 659b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c 660b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820 661b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824 662b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828 663b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c 664b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830 665b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834 666b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838 667b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c 668b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840 669b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000 670b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004 671b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008 672b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c 673b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010 674b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 675b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 676b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c 677*9a8ab39fSSam Protsenko #define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020 678b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 679b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c 680b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 681b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054 682b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058 683b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c 684b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070 685b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074 686b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088 687b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c 688b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4 689b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8 690b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc 691b73fd95dSSam Protsenko 692b73fd95dSSam Protsenko static const unsigned long aud_clk_regs[] __initconst = { 693b73fd95dSSam Protsenko PLL_LOCKTIME_PLL_AUD, 694b73fd95dSSam Protsenko PLL_CON0_PLL_AUD, 695b73fd95dSSam Protsenko PLL_CON3_PLL_AUD, 696b73fd95dSSam Protsenko PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 697b73fd95dSSam Protsenko PLL_CON0_MUX_TICK_USB_USER, 698b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU, 699b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 700b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_FM, 701b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 702b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 703b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 704b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 705b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 706b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 707b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 708b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_MCLK, 709b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 710b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSD, 711b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSP, 712b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CNT, 713b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU, 714b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 715b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 716b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM, 717b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 718b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 719b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 720b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 721b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 722b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 723b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 724b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 725b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 726b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 727b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 728b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 729b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 730b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 731b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 732b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 733*9a8ab39fSSam Protsenko CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 734b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 735b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 736b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 737b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 738b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 739b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 740b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 741b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 742b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 743b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 744b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 745b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 746b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 747b73fd95dSSam Protsenko }; 748b73fd95dSSam Protsenko 749b73fd95dSSam Protsenko /* List of parent clocks for Muxes in CMU_AUD */ 750b73fd95dSSam Protsenko PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" }; 751b73fd95dSSam Protsenko PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" }; 752b73fd95dSSam Protsenko PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" }; 753b73fd95dSSam Protsenko PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" }; 754b73fd95dSSam Protsenko PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" }; 755b73fd95dSSam Protsenko PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" }; 756b73fd95dSSam Protsenko PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" }; 757b73fd95dSSam Protsenko PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" }; 758b73fd95dSSam Protsenko PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" }; 759b73fd95dSSam Protsenko PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" }; 760b73fd95dSSam Protsenko PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" }; 761b73fd95dSSam Protsenko PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" }; 762b73fd95dSSam Protsenko PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" }; 763b73fd95dSSam Protsenko 764b73fd95dSSam Protsenko /* 765b73fd95dSSam Protsenko * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set 766b73fd95dSSam Protsenko * for that PLL by default, so set_rate operation would fail. 767b73fd95dSSam Protsenko */ 768b73fd95dSSam Protsenko static const struct samsung_pll_clock aud_pll_clks[] __initconst = { 769b73fd95dSSam Protsenko PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 770b73fd95dSSam Protsenko PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL), 771b73fd95dSSam Protsenko }; 772b73fd95dSSam Protsenko 773b73fd95dSSam Protsenko static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { 774b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000), 775b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000), 776b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000), 777b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000), 778b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000), 779b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000), 780b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000), 781b73fd95dSSam Protsenko FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000), 782b73fd95dSSam Protsenko }; 783b73fd95dSSam Protsenko 784b73fd95dSSam Protsenko static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 785b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, 786b73fd95dSSam Protsenko PLL_CON0_PLL_AUD, 4, 1), 787b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p, 788b73fd95dSSam Protsenko PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1), 789b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user", 790b73fd95dSSam Protsenko mout_aud_tick_usb_user_p, 791b73fd95dSSam Protsenko PLL_CON0_MUX_TICK_USB_USER, 4, 1), 792b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p, 793b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1), 794b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p, 795b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1), 796b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p, 797b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1), 798b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p, 799b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1), 800b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p, 801b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1), 802b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p, 803b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1), 804b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p, 805b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1), 806b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p, 807b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1), 808b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p, 809b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1), 810b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p, 811b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1), 812b73fd95dSSam Protsenko }; 813b73fd95dSSam Protsenko 814b73fd95dSSam Protsenko static const struct samsung_div_clock aud_div_clks[] __initconst = { 815b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll", 816b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4), 817b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll", 818b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4), 819b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll", 820b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4), 821b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll", 822b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9), 823b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch", 824b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3), 825b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg", 826b73fd95dSSam Protsenko "mout_aud_cpu_hch", 827b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3), 828b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif", 829b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2), 830b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif", 831b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10), 832b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif", 833b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10), 834b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif", 835b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10), 836b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif", 837b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10), 838b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif", 839b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10), 840b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif", 841b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10), 842b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif", 843b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10), 844b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif", 845b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10), 846b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user", 847b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1), 848b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm", 849b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10), 850b73fd95dSSam Protsenko }; 851b73fd95dSSam Protsenko 852b73fd95dSSam Protsenko static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 853*9a8ab39fSSam Protsenko GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk", 854*9a8ab39fSSam Protsenko "dout_aud_busd", 855*9a8ab39fSSam Protsenko CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0), 856b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch", 857b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), 858b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk", 859b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0), 860b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg", 861b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0), 862b73fd95dSSam Protsenko /* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */ 863b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd", 864b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0), 865b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd", 866b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0), 867b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd", 868b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0), 869b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd", 870b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0), 871b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd", 872b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0), 873b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd", 874b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0), 875b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd", 876b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0), 877b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp", 878b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0), 879b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk", 880b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0), 881b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt", 882b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0), 883b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0", 884b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0), 885b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1", 886b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0), 887b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2", 888b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0), 889b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3", 890b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0), 891b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4", 892b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0), 893b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5", 894b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0), 895b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6", 896b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0), 897b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm", 898b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0), 899b73fd95dSSam Protsenko }; 900b73fd95dSSam Protsenko 901b73fd95dSSam Protsenko static const struct samsung_cmu_info aud_cmu_info __initconst = { 902b73fd95dSSam Protsenko .pll_clks = aud_pll_clks, 903b73fd95dSSam Protsenko .nr_pll_clks = ARRAY_SIZE(aud_pll_clks), 904b73fd95dSSam Protsenko .mux_clks = aud_mux_clks, 905b73fd95dSSam Protsenko .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 906b73fd95dSSam Protsenko .div_clks = aud_div_clks, 907b73fd95dSSam Protsenko .nr_div_clks = ARRAY_SIZE(aud_div_clks), 908b73fd95dSSam Protsenko .gate_clks = aud_gate_clks, 909b73fd95dSSam Protsenko .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 910b73fd95dSSam Protsenko .fixed_clks = aud_fixed_clks, 911b73fd95dSSam Protsenko .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), 912b73fd95dSSam Protsenko .nr_clk_ids = AUD_NR_CLK, 913b73fd95dSSam Protsenko .clk_regs = aud_clk_regs, 914b73fd95dSSam Protsenko .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 915b73fd95dSSam Protsenko .clk_name = "dout_aud", 916b73fd95dSSam Protsenko }; 917b73fd95dSSam Protsenko 91862782ba8SSam Protsenko /* ---- CMU_CMGP ------------------------------------------------------------ */ 91962782ba8SSam Protsenko 92062782ba8SSam Protsenko /* Register Offset definitions for CMU_CMGP (0x11c00000) */ 92162782ba8SSam Protsenko #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000 92262782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004 92362782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008 92462782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800 92562782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804 92662782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808 92762782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c 92862782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 92962782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018 930bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040 93162782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044 93262782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048 93362782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c 93462782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050 93562782ba8SSam Protsenko 93662782ba8SSam Protsenko static const unsigned long cmgp_clk_regs[] __initconst = { 93762782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 93862782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 93962782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 94062782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 94162782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 94262782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 94362782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 94462782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 94562782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 946bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 94762782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 94862782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 94962782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 95062782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 95162782ba8SSam Protsenko }; 95262782ba8SSam Protsenko 95362782ba8SSam Protsenko /* List of parent clocks for Muxes in CMU_CMGP */ 95462782ba8SSam Protsenko PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 95562782ba8SSam Protsenko PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 95662782ba8SSam Protsenko PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" }; 95762782ba8SSam Protsenko 95862782ba8SSam Protsenko static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = { 95962782ba8SSam Protsenko FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000), 96062782ba8SSam Protsenko }; 96162782ba8SSam Protsenko 96262782ba8SSam Protsenko static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = { 96362782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p, 96462782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 0, 1), 96562782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, 96662782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1), 96762782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, 96862782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1), 96962782ba8SSam Protsenko }; 97062782ba8SSam Protsenko 97162782ba8SSam Protsenko static const struct samsung_div_clock cmgp_div_clks[] __initconst = { 97262782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus", 97362782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), 97462782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", 97562782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5), 97662782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", 97762782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5), 97862782ba8SSam Protsenko }; 97962782ba8SSam Protsenko 98062782ba8SSam Protsenko static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { 98162782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk", 98262782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 98362782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0), 98462782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk", 98562782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 98662782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0), 9876904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 98862782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk", 98962782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 9906904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0), 99162782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0", 99262782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0), 99362782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk", 99462782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 99562782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0), 99662782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1", 99762782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0), 99862782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", 99962782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 100062782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), 1001bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk", 1002bc471d1fSSam Protsenko "gout_clkcmu_cmgp_bus", 1003bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0), 100462782ba8SSam Protsenko }; 100562782ba8SSam Protsenko 100662782ba8SSam Protsenko static const struct samsung_cmu_info cmgp_cmu_info __initconst = { 100762782ba8SSam Protsenko .mux_clks = cmgp_mux_clks, 100862782ba8SSam Protsenko .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks), 100962782ba8SSam Protsenko .div_clks = cmgp_div_clks, 101062782ba8SSam Protsenko .nr_div_clks = ARRAY_SIZE(cmgp_div_clks), 101162782ba8SSam Protsenko .gate_clks = cmgp_gate_clks, 101262782ba8SSam Protsenko .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks), 101362782ba8SSam Protsenko .fixed_clks = cmgp_fixed_clks, 101462782ba8SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks), 101562782ba8SSam Protsenko .nr_clk_ids = CMGP_NR_CLK, 101662782ba8SSam Protsenko .clk_regs = cmgp_clk_regs, 101762782ba8SSam Protsenko .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), 101862782ba8SSam Protsenko .clk_name = "gout_clkcmu_cmgp_bus", 101962782ba8SSam Protsenko }; 102062782ba8SSam Protsenko 1021e145c765SSam Protsenko /* ---- CMU_G3D ------------------------------------------------------------- */ 1022e145c765SSam Protsenko 1023e145c765SSam Protsenko /* Register Offset definitions for CMU_G3D (0x11400000) */ 1024e145c765SSam Protsenko #define PLL_LOCKTIME_PLL_G3D 0x0000 1025e145c765SSam Protsenko #define PLL_CON0_PLL_G3D 0x0100 1026e145c765SSam Protsenko #define PLL_CON3_PLL_G3D 0x010c 1027e145c765SSam Protsenko #define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600 1028e145c765SSam Protsenko #define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000 1029e145c765SSam Protsenko #define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804 1030e145c765SSam Protsenko #define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000 1031e145c765SSam Protsenko #define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004 1032e145c765SSam Protsenko #define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c 1033e145c765SSam Protsenko #define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010 1034e145c765SSam Protsenko #define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024 1035e145c765SSam Protsenko #define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028 1036e145c765SSam Protsenko #define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c 1037e145c765SSam Protsenko 1038e145c765SSam Protsenko static const unsigned long g3d_clk_regs[] __initconst = { 1039e145c765SSam Protsenko PLL_LOCKTIME_PLL_G3D, 1040e145c765SSam Protsenko PLL_CON0_PLL_G3D, 1041e145c765SSam Protsenko PLL_CON3_PLL_G3D, 1042e145c765SSam Protsenko PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 1043e145c765SSam Protsenko CLK_CON_MUX_MUX_CLK_G3D_BUSD, 1044e145c765SSam Protsenko CLK_CON_DIV_DIV_CLK_G3D_BUSP, 1045e145c765SSam Protsenko CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 1046e145c765SSam Protsenko CLK_CON_GAT_CLK_G3D_GPU_CLK, 1047e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 1048e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 1049e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 1050e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 1051e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 1052e145c765SSam Protsenko }; 1053e145c765SSam Protsenko 1054e145c765SSam Protsenko /* List of parent clocks for Muxes in CMU_G3D */ 1055e145c765SSam Protsenko PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" }; 1056e145c765SSam Protsenko PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" }; 1057e145c765SSam Protsenko PNAME(mout_g3d_busd_p) = { "mout_g3d_pll", "mout_g3d_switch_user" }; 1058e145c765SSam Protsenko 1059e145c765SSam Protsenko /* 1060e145c765SSam Protsenko * Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set 1061e145c765SSam Protsenko * for that PLL by default, so set_rate operation would fail. 1062e145c765SSam Protsenko */ 1063e145c765SSam Protsenko static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { 1064e145c765SSam Protsenko PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", 1065e145c765SSam Protsenko PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL), 1066e145c765SSam Protsenko }; 1067e145c765SSam Protsenko 1068e145c765SSam Protsenko static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { 1069e145c765SSam Protsenko MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, 1070e145c765SSam Protsenko PLL_CON0_PLL_G3D, 4, 1), 1071e145c765SSam Protsenko MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user", 1072e145c765SSam Protsenko mout_g3d_switch_user_p, 1073e145c765SSam Protsenko PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1), 1074e145c765SSam Protsenko MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p, 1075e145c765SSam Protsenko CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1), 1076e145c765SSam Protsenko }; 1077e145c765SSam Protsenko 1078e145c765SSam Protsenko static const struct samsung_div_clock g3d_div_clks[] __initconst = { 1079e145c765SSam Protsenko DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd", 1080e145c765SSam Protsenko CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3), 1081e145c765SSam Protsenko }; 1082e145c765SSam Protsenko 1083e145c765SSam Protsenko static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { 1084e145c765SSam Protsenko GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk", 1085e145c765SSam Protsenko "dout_g3d_busp", 1086e145c765SSam Protsenko CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1087e145c765SSam Protsenko GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd", 1088e145c765SSam Protsenko CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0), 1089e145c765SSam Protsenko GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp", 1090e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0), 1091e145c765SSam Protsenko GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk", 1092e145c765SSam Protsenko "mout_g3d_busd", 1093e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0), 1094e145c765SSam Protsenko GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd", 1095e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0), 1096e145c765SSam Protsenko GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp", 1097e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0), 1098e145c765SSam Protsenko GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp", 1099e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0), 1100e145c765SSam Protsenko }; 1101e145c765SSam Protsenko 1102e145c765SSam Protsenko static const struct samsung_cmu_info g3d_cmu_info __initconst = { 1103e145c765SSam Protsenko .pll_clks = g3d_pll_clks, 1104e145c765SSam Protsenko .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), 1105e145c765SSam Protsenko .mux_clks = g3d_mux_clks, 1106e145c765SSam Protsenko .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), 1107e145c765SSam Protsenko .div_clks = g3d_div_clks, 1108e145c765SSam Protsenko .nr_div_clks = ARRAY_SIZE(g3d_div_clks), 1109e145c765SSam Protsenko .gate_clks = g3d_gate_clks, 1110e145c765SSam Protsenko .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), 1111e145c765SSam Protsenko .nr_clk_ids = G3D_NR_CLK, 1112e145c765SSam Protsenko .clk_regs = g3d_clk_regs, 1113e145c765SSam Protsenko .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), 1114e145c765SSam Protsenko .clk_name = "dout_g3d_switch", 1115e145c765SSam Protsenko }; 1116e145c765SSam Protsenko 11177dd05578SSam Protsenko /* ---- CMU_HSI ------------------------------------------------------------- */ 11187dd05578SSam Protsenko 11197dd05578SSam Protsenko /* Register Offset definitions for CMU_HSI (0x13400000) */ 11207dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 11217dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 11227dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 11237dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 1124*9a8ab39fSSam Protsenko #define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000 11257dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 11267dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c 11277dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 11287dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 11297dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 11307dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 1131*9a8ab39fSSam Protsenko #define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c 1132*9a8ab39fSSam Protsenko #define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030 11337dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 11347dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c 11357dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 11367dd05578SSam Protsenko 11377dd05578SSam Protsenko static const unsigned long hsi_clk_regs[] __initconst = { 11387dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 11397dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 11407dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 11417dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 1142*9a8ab39fSSam Protsenko CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 11437dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 11447dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 11457dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 11467dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 11477dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 11487dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 1149*9a8ab39fSSam Protsenko CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 1150*9a8ab39fSSam Protsenko CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 11517dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 11527dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 11537dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 11547dd05578SSam Protsenko }; 11557dd05578SSam Protsenko 1156dbaa27ccSSam Protsenko /* List of parent clocks for Muxes in CMU_HSI */ 11577dd05578SSam Protsenko PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" }; 11587dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" }; 11597dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" }; 11607dd05578SSam Protsenko PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" }; 11617dd05578SSam Protsenko 11627dd05578SSam Protsenko static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { 11637dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, 11647dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), 11657dd05578SSam Protsenko MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", 11667dd05578SSam Protsenko mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 11677dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 11687dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", 11697dd05578SSam Protsenko mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 11707dd05578SSam Protsenko 4, 1), 11717dd05578SSam Protsenko MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p, 11727dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1), 11737dd05578SSam Protsenko }; 11747dd05578SSam Protsenko 11757dd05578SSam Protsenko static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { 1176*9a8ab39fSSam Protsenko /* TODO: Should be enabled in corresponding driver */ 1177*9a8ab39fSSam Protsenko GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk", 1178*9a8ab39fSSam Protsenko "mout_hsi_bus_user", 1179*9a8ab39fSSam Protsenko CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 11807dd05578SSam Protsenko GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", 11817dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), 11827dd05578SSam Protsenko GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", 11837dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), 11847dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk", 11857dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), 11866904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 11877dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user", 11886904d7e5SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 11897dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", 11907dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), 11917dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 11927dd05578SSam Protsenko "mout_hsi_mmc_card_user", 11937dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), 1194*9a8ab39fSSam Protsenko GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user", 1195*9a8ab39fSSam Protsenko CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0), 1196*9a8ab39fSSam Protsenko GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user", 1197*9a8ab39fSSam Protsenko CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0), 11987dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", 11997dd05578SSam Protsenko "mout_hsi_bus_user", 12007dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), 12017dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", 12027dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), 12037dd05578SSam Protsenko GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", 12047dd05578SSam Protsenko "mout_hsi_bus_user", 12057dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), 12067dd05578SSam Protsenko }; 12077dd05578SSam Protsenko 12087dd05578SSam Protsenko static const struct samsung_cmu_info hsi_cmu_info __initconst = { 12097dd05578SSam Protsenko .mux_clks = hsi_mux_clks, 12107dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), 12117dd05578SSam Protsenko .gate_clks = hsi_gate_clks, 12127dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), 12137dd05578SSam Protsenko .nr_clk_ids = HSI_NR_CLK, 12147dd05578SSam Protsenko .clk_regs = hsi_clk_regs, 12157dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), 12167dd05578SSam Protsenko .clk_name = "dout_hsi_bus", 12177dd05578SSam Protsenko }; 12187dd05578SSam Protsenko 1219bf3a4c51SSam Protsenko /* ---- CMU_IS -------------------------------------------------------------- */ 1220bf3a4c51SSam Protsenko 1221bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600 1222bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610 1223bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620 1224bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630 1225bf3a4c51SSam Protsenko #define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800 1226bf3a4c51SSam Protsenko #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000 1227bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040 1228bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044 1229bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048 1230bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c 1231bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050 1232bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054 1233bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058 1234bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c 1235bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060 1236bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064 1237bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074 1238bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078 1239bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c 1240bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080 1241bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098 1242bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c 1243bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0 1244bf3a4c51SSam Protsenko 1245bf3a4c51SSam Protsenko static const unsigned long is_clk_regs[] __initconst = { 1246bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 1247bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 1248bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 1249bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 1250bf3a4c51SSam Protsenko CLK_CON_DIV_DIV_CLK_IS_BUSP, 1251bf3a4c51SSam Protsenko CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 1252bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 1253bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 1254bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 1255bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 1256bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 1257bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_GDC, 1258bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_IPP, 1259bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_ITP, 1260bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_MCSC, 1261bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_VRA, 1262bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 1263bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 1264bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 1265bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 1266bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 1267bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 1268bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 1269bf3a4c51SSam Protsenko }; 1270bf3a4c51SSam Protsenko 1271bf3a4c51SSam Protsenko /* List of parent clocks for Muxes in CMU_IS */ 1272bf3a4c51SSam Protsenko PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" }; 1273bf3a4c51SSam Protsenko PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" }; 1274bf3a4c51SSam Protsenko PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" }; 1275bf3a4c51SSam Protsenko PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" }; 1276bf3a4c51SSam Protsenko 1277bf3a4c51SSam Protsenko static const struct samsung_mux_clock is_mux_clks[] __initconst = { 1278bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p, 1279bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1), 1280bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p, 1281bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1), 1282bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p, 1283bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1), 1284bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p, 1285bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1), 1286bf3a4c51SSam Protsenko }; 1287bf3a4c51SSam Protsenko 1288bf3a4c51SSam Protsenko static const struct samsung_div_clock is_div_clks[] __initconst = { 1289bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user", 1290bf3a4c51SSam Protsenko CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2), 1291bf3a4c51SSam Protsenko }; 1292bf3a4c51SSam Protsenko 1293bf3a4c51SSam Protsenko static const struct samsung_gate_clock is_gate_clks[] __initconst = { 1294bf3a4c51SSam Protsenko /* TODO: Should be enabled in IS driver */ 1295bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp", 1296bf3a4c51SSam Protsenko CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1297bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user", 1298bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0), 1299bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user", 1300bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0), 1301bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user", 1302bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0), 1303bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp", 1304bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0), 1305bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk", 1306bf3a4c51SSam Protsenko "mout_is_bus_user", 1307bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0), 1308bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user", 1309bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0), 1310bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user", 1311bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0), 1312bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user", 1313bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0), 1314bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user", 1315bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0), 1316bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user", 1317bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0), 1318bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk", 1319bf3a4c51SSam Protsenko "mout_is_bus_user", 1320bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0), 1321bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp", 1322bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0), 1323bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk", 1324bf3a4c51SSam Protsenko "mout_is_itp_user", 1325bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0), 1326bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp", 1327bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0), 1328bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk", 1329bf3a4c51SSam Protsenko "mout_is_bus_user", 1330bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0), 1331bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk", 1332bf3a4c51SSam Protsenko "mout_is_itp_user", 1333bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0), 1334bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp", 1335bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0), 1336bf3a4c51SSam Protsenko }; 1337bf3a4c51SSam Protsenko 1338bf3a4c51SSam Protsenko static const struct samsung_cmu_info is_cmu_info __initconst = { 1339bf3a4c51SSam Protsenko .mux_clks = is_mux_clks, 1340bf3a4c51SSam Protsenko .nr_mux_clks = ARRAY_SIZE(is_mux_clks), 1341bf3a4c51SSam Protsenko .div_clks = is_div_clks, 1342bf3a4c51SSam Protsenko .nr_div_clks = ARRAY_SIZE(is_div_clks), 1343bf3a4c51SSam Protsenko .gate_clks = is_gate_clks, 1344bf3a4c51SSam Protsenko .nr_gate_clks = ARRAY_SIZE(is_gate_clks), 1345bf3a4c51SSam Protsenko .nr_clk_ids = IS_NR_CLK, 1346bf3a4c51SSam Protsenko .clk_regs = is_clk_regs, 1347bf3a4c51SSam Protsenko .nr_clk_regs = ARRAY_SIZE(is_clk_regs), 1348bf3a4c51SSam Protsenko .clk_name = "dout_is_bus", 1349bf3a4c51SSam Protsenko }; 1350bf3a4c51SSam Protsenko 13517f36d3b6SSam Protsenko /* ---- CMU_MFCMSCL --------------------------------------------------------- */ 13527f36d3b6SSam Protsenko 13537f36d3b6SSam Protsenko #define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600 13547f36d3b6SSam Protsenko #define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610 13557f36d3b6SSam Protsenko #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620 13567f36d3b6SSam Protsenko #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630 13577f36d3b6SSam Protsenko #define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800 13587f36d3b6SSam Protsenko #define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000 13597f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038 13607f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c 13617f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048 13627f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c 13637f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050 13647f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054 13657f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058 13667f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074 13677f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078 13687f36d3b6SSam Protsenko 13697f36d3b6SSam Protsenko static const unsigned long mfcmscl_clk_regs[] __initconst = { 13707f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 13717f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 13727f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 13737f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 13747f36d3b6SSam Protsenko CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 13757f36d3b6SSam Protsenko CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK, 13767f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK, 13777f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK, 13787f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK, 13797f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK, 13807f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK, 13817f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK, 13827f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK, 13837f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1, 13847f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK, 13857f36d3b6SSam Protsenko }; 13867f36d3b6SSam Protsenko 13877f36d3b6SSam Protsenko /* List of parent clocks for Muxes in CMU_MFCMSCL */ 13887f36d3b6SSam Protsenko PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" }; 13897f36d3b6SSam Protsenko PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" }; 13907f36d3b6SSam Protsenko PNAME(mout_mfcmscl_mcsc_user_p) = { "oscclk", "dout_mfcmscl_mcsc" }; 13917f36d3b6SSam Protsenko PNAME(mout_mfcmscl_jpeg_user_p) = { "oscclk", "dout_mfcmscl_jpeg" }; 13927f36d3b6SSam Protsenko 13937f36d3b6SSam Protsenko static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = { 13947f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user", 13957f36d3b6SSam Protsenko mout_mfcmscl_mfc_user_p, 13967f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1), 13977f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user", 13987f36d3b6SSam Protsenko mout_mfcmscl_m2m_user_p, 13997f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1), 14007f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user", 14017f36d3b6SSam Protsenko mout_mfcmscl_mcsc_user_p, 14027f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1), 14037f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user", 14047f36d3b6SSam Protsenko mout_mfcmscl_jpeg_user_p, 14057f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1), 14067f36d3b6SSam Protsenko }; 14077f36d3b6SSam Protsenko 14087f36d3b6SSam Protsenko static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = { 14097f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user", 14107f36d3b6SSam Protsenko CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3), 14117f36d3b6SSam Protsenko }; 14127f36d3b6SSam Protsenko 14137f36d3b6SSam Protsenko static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = { 14147f36d3b6SSam Protsenko /* TODO: Should be enabled in MFC driver */ 14157f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk", 14167f36d3b6SSam Protsenko "dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK, 14177f36d3b6SSam Protsenko 21, CLK_IGNORE_UNUSED, 0), 14187f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk", 14197f36d3b6SSam Protsenko "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK, 14207f36d3b6SSam Protsenko 21, 0, 0), 14217f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk", 14227f36d3b6SSam Protsenko "mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK, 14237f36d3b6SSam Protsenko 21, 0, 0), 14247f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk", 14257f36d3b6SSam Protsenko "mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK, 14267f36d3b6SSam Protsenko 21, 0, 0), 14277f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk", 14287f36d3b6SSam Protsenko "mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK, 14297f36d3b6SSam Protsenko 21, 0, 0), 14307f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk", 14317f36d3b6SSam Protsenko "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK, 14327f36d3b6SSam Protsenko 21, 0, 0), 14337f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk", 14347f36d3b6SSam Protsenko "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK, 14357f36d3b6SSam Protsenko 21, 0, 0), 14367f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk", 14377f36d3b6SSam Protsenko "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK, 14387f36d3b6SSam Protsenko 21, 0, 0), 14397f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk", 14407f36d3b6SSam Protsenko "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1, 14417f36d3b6SSam Protsenko 21, 0, 0), 14427f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk", 14437f36d3b6SSam Protsenko "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK, 14447f36d3b6SSam Protsenko 21, 0, 0), 14457f36d3b6SSam Protsenko }; 14467f36d3b6SSam Protsenko 14477f36d3b6SSam Protsenko static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = { 14487f36d3b6SSam Protsenko .mux_clks = mfcmscl_mux_clks, 14497f36d3b6SSam Protsenko .nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks), 14507f36d3b6SSam Protsenko .div_clks = mfcmscl_div_clks, 14517f36d3b6SSam Protsenko .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks), 14527f36d3b6SSam Protsenko .gate_clks = mfcmscl_gate_clks, 14537f36d3b6SSam Protsenko .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks), 14547f36d3b6SSam Protsenko .nr_clk_ids = MFCMSCL_NR_CLK, 14557f36d3b6SSam Protsenko .clk_regs = mfcmscl_clk_regs, 14567f36d3b6SSam Protsenko .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs), 14577f36d3b6SSam Protsenko .clk_name = "dout_mfcmscl_mfc", 14587f36d3b6SSam Protsenko }; 14597f36d3b6SSam Protsenko 14607dd05578SSam Protsenko /* ---- CMU_PERI ------------------------------------------------------------ */ 14617dd05578SSam Protsenko 14627dd05578SSam Protsenko /* Register Offset definitions for CMU_PERI (0x10030000) */ 14637dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 14647dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610 14657dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620 14667dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 14677dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800 14687dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804 14697dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808 14707dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c 14717dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c 14727dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010 14737dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014 14747dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020 14757dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024 14767dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 14777dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c 14787dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030 14797dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034 14807dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038 14817dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c 14827dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040 14837dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044 14847dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048 14857dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c 14867dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050 14877dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054 14887dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c 14897dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064 14907dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c 14917dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0 14927dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4 14937dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 14947dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac 14957dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0 14967dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4 14977dd05578SSam Protsenko 14987dd05578SSam Protsenko static const unsigned long peri_clk_regs[] __initconst = { 14997dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 15007dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 15017dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 15027dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 15037dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 15047dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 15057dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 15067dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 15077dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 15087dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 15097dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 15107dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 15117dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 15127dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 15137dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 15147dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 15157dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 15167dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 15177dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 15187dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 15197dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 15207dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 15217dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 15227dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 15237dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 15247dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 15257dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 15267dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 15277dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 15287dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 15297dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 15307dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 15317dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 15327dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 15337dd05578SSam Protsenko }; 15347dd05578SSam Protsenko 15357dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_PERI */ 15367dd05578SSam Protsenko PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; 15377dd05578SSam Protsenko PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" }; 15387dd05578SSam Protsenko PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" }; 15397dd05578SSam Protsenko PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" }; 15407dd05578SSam Protsenko 15417dd05578SSam Protsenko static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 15427dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 15437dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 15447dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", 15457dd05578SSam Protsenko mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), 15467dd05578SSam Protsenko MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", 15477dd05578SSam Protsenko mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), 15487dd05578SSam Protsenko MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, 15497dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), 15507dd05578SSam Protsenko }; 15517dd05578SSam Protsenko 15527dd05578SSam Protsenko static const struct samsung_div_clock peri_div_clks[] __initconst = { 15537dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0", 15547dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5), 15557dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1", 15567dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), 15577dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", 15587dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), 15597dd05578SSam Protsenko DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", 15607dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), 15617dd05578SSam Protsenko }; 15627dd05578SSam Protsenko 15637dd05578SSam Protsenko static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 15647dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user", 15657dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0), 15667dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user", 15677dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0), 15687dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user", 15697dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0), 15707dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0", 15717dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0), 15727dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", 15737dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), 15747dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1", 15757dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0), 15767dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", 15777dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), 15787dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2", 15797dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0), 15807dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", 15817dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), 15827dd05578SSam Protsenko GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", 15837dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), 15847dd05578SSam Protsenko GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", 15857dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), 15867dd05578SSam Protsenko GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", 15877dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), 15887dd05578SSam Protsenko GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", 15897dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), 15907dd05578SSam Protsenko GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", 15917dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), 15927dd05578SSam Protsenko GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", 15937dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), 15947dd05578SSam Protsenko GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", 15957dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), 15967dd05578SSam Protsenko GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", 15977dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), 15987dd05578SSam Protsenko GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", 15997dd05578SSam Protsenko "mout_peri_bus_user", 16007dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), 16017dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", 16027dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), 16037dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", 16047dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), 16057dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", 16067dd05578SSam Protsenko "mout_peri_bus_user", 16077dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), 16087dd05578SSam Protsenko GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", 16097dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), 16107dd05578SSam Protsenko GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", 16117dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), 16127dd05578SSam Protsenko GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", 16137dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0), 16147dd05578SSam Protsenko GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", 16157dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0), 16166904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 16177dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk", 16187dd05578SSam Protsenko "mout_peri_bus_user", 16196904d7e5SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 16207dd05578SSam Protsenko }; 16217dd05578SSam Protsenko 16227dd05578SSam Protsenko static const struct samsung_cmu_info peri_cmu_info __initconst = { 16237dd05578SSam Protsenko .mux_clks = peri_mux_clks, 16247dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 16257dd05578SSam Protsenko .div_clks = peri_div_clks, 16267dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(peri_div_clks), 16277dd05578SSam Protsenko .gate_clks = peri_gate_clks, 16287dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 16297dd05578SSam Protsenko .nr_clk_ids = PERI_NR_CLK, 16307dd05578SSam Protsenko .clk_regs = peri_clk_regs, 16317dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 16327dd05578SSam Protsenko .clk_name = "dout_peri_bus", 16337dd05578SSam Protsenko }; 16347dd05578SSam Protsenko 1635bcda841fSSam Protsenko static void __init exynos850_cmu_peri_init(struct device_node *np) 1636bcda841fSSam Protsenko { 1637cfe238e4SDavid Virag exynos_arm64_register_cmu(NULL, np, &peri_cmu_info); 1638bcda841fSSam Protsenko } 1639bcda841fSSam Protsenko 1640bcda841fSSam Protsenko /* Register CMU_PERI early, as it's needed for MCT timer */ 1641bcda841fSSam Protsenko CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", 1642bcda841fSSam Protsenko exynos850_cmu_peri_init); 1643bcda841fSSam Protsenko 16447dd05578SSam Protsenko /* ---- CMU_CORE ------------------------------------------------------------ */ 16457dd05578SSam Protsenko 16467dd05578SSam Protsenko /* Register Offset definitions for CMU_CORE (0x12000000) */ 16477dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 16487dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610 16497dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 16507dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630 16517dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 16527dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 16537dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 16547dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 1655bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 16567dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 16577dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec 16587dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 16597dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c 1660bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 16617dd05578SSam Protsenko 16627dd05578SSam Protsenko static const unsigned long core_clk_regs[] __initconst = { 16637dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 16647dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 16657dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 16667dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 16677dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 16687dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 16697dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 16707dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 1671bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 16727dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 16737dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 16747dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 16757dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 1676bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 16777dd05578SSam Protsenko }; 16787dd05578SSam Protsenko 16797dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_CORE */ 16807dd05578SSam Protsenko PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; 16817dd05578SSam Protsenko PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; 16827dd05578SSam Protsenko PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" }; 16837dd05578SSam Protsenko PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" }; 16847dd05578SSam Protsenko PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; 16857dd05578SSam Protsenko 16867dd05578SSam Protsenko static const struct samsung_mux_clock core_mux_clks[] __initconst = { 16877dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 16887dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 16897dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, 16907dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), 16917dd05578SSam Protsenko MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", 16927dd05578SSam Protsenko mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 16937dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 16947dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p, 16957dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1), 16967dd05578SSam Protsenko MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, 16977dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), 16987dd05578SSam Protsenko }; 16997dd05578SSam Protsenko 17007dd05578SSam Protsenko static const struct samsung_div_clock core_div_clks[] __initconst = { 17017dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 17027dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 17037dd05578SSam Protsenko }; 17047dd05578SSam Protsenko 17057dd05578SSam Protsenko static const struct samsung_gate_clock core_gate_clks[] __initconst = { 17066904d7e5SSam Protsenko /* CCI (interconnect) clock must be always running */ 17077dd05578SSam Protsenko GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", 17086904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0), 17096904d7e5SSam Protsenko /* GIC (interrupt controller) clock must be always running */ 17107dd05578SSam Protsenko GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic", 17116904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0), 17127dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", 17137dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), 17147dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 17157dd05578SSam Protsenko "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 17167dd05578SSam Protsenko 21, CLK_SET_RATE_PARENT, 0), 17177dd05578SSam Protsenko GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", 17187dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), 17197dd05578SSam Protsenko GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", 17207dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), 1721bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 1722bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp", 1723bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1724bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk", 1725bc471d1fSSam Protsenko "dout_core_busp", 1726bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0), 17277dd05578SSam Protsenko }; 17287dd05578SSam Protsenko 17297dd05578SSam Protsenko static const struct samsung_cmu_info core_cmu_info __initconst = { 17307dd05578SSam Protsenko .mux_clks = core_mux_clks, 17317dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 17327dd05578SSam Protsenko .div_clks = core_div_clks, 17337dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(core_div_clks), 17347dd05578SSam Protsenko .gate_clks = core_gate_clks, 17357dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 17367dd05578SSam Protsenko .nr_clk_ids = CORE_NR_CLK, 17377dd05578SSam Protsenko .clk_regs = core_clk_regs, 17387dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 17397dd05578SSam Protsenko .clk_name = "dout_core_bus", 17407dd05578SSam Protsenko }; 17417dd05578SSam Protsenko 17427dd05578SSam Protsenko /* ---- CMU_DPU ------------------------------------------------------------- */ 17437dd05578SSam Protsenko 17447dd05578SSam Protsenko /* Register Offset definitions for CMU_DPU (0x13000000) */ 17457dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600 17467dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 17477dd05578SSam Protsenko #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004 17487dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010 17497dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014 17507dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018 17517dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028 17527dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c 17537dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038 17547dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c 17557dd05578SSam Protsenko 17567dd05578SSam Protsenko static const unsigned long dpu_clk_regs[] __initconst = { 17577dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 17587dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 17597dd05578SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 17607dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 17617dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 17627dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 17637dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 17647dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 17657dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 17667dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 17677dd05578SSam Protsenko }; 17687dd05578SSam Protsenko 1769dbaa27ccSSam Protsenko /* List of parent clocks for Muxes in CMU_DPU */ 17707dd05578SSam Protsenko PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" }; 17717dd05578SSam Protsenko 17727dd05578SSam Protsenko static const struct samsung_mux_clock dpu_mux_clks[] __initconst = { 17737dd05578SSam Protsenko MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p, 17747dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1), 17757dd05578SSam Protsenko }; 17767dd05578SSam Protsenko 17777dd05578SSam Protsenko static const struct samsung_div_clock dpu_div_clks[] __initconst = { 17787dd05578SSam Protsenko DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user", 17797dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), 17807dd05578SSam Protsenko }; 17817dd05578SSam Protsenko 17827dd05578SSam Protsenko static const struct samsung_gate_clock dpu_gate_clks[] __initconst = { 17836904d7e5SSam Protsenko /* TODO: Should be enabled in DSIM driver */ 17847dd05578SSam Protsenko GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk", 17856904d7e5SSam Protsenko "dout_dpu_busp", 17866904d7e5SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0), 17877dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user", 17887dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0), 17897dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user", 17907dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0), 17917dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user", 17927dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0), 17937dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user", 17947dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0), 17957dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp", 17967dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0), 17977dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user", 17987dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0), 17997dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp", 18007dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0), 18017dd05578SSam Protsenko }; 18027dd05578SSam Protsenko 18037dd05578SSam Protsenko static const struct samsung_cmu_info dpu_cmu_info __initconst = { 18047dd05578SSam Protsenko .mux_clks = dpu_mux_clks, 18057dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks), 18067dd05578SSam Protsenko .div_clks = dpu_div_clks, 18077dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(dpu_div_clks), 18087dd05578SSam Protsenko .gate_clks = dpu_gate_clks, 18097dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), 18107dd05578SSam Protsenko .nr_clk_ids = DPU_NR_CLK, 18117dd05578SSam Protsenko .clk_regs = dpu_clk_regs, 18127dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), 18137dd05578SSam Protsenko .clk_name = "dout_dpu", 18147dd05578SSam Protsenko }; 18157dd05578SSam Protsenko 18167dd05578SSam Protsenko /* ---- platform_driver ----------------------------------------------------- */ 18177dd05578SSam Protsenko 18187dd05578SSam Protsenko static int __init exynos850_cmu_probe(struct platform_device *pdev) 18197dd05578SSam Protsenko { 18207dd05578SSam Protsenko const struct samsung_cmu_info *info; 18217dd05578SSam Protsenko struct device *dev = &pdev->dev; 18227dd05578SSam Protsenko 18237dd05578SSam Protsenko info = of_device_get_match_data(dev); 1824cfe238e4SDavid Virag exynos_arm64_register_cmu(dev, dev->of_node, info); 18257dd05578SSam Protsenko 18267dd05578SSam Protsenko return 0; 18277dd05578SSam Protsenko } 18287dd05578SSam Protsenko 18297dd05578SSam Protsenko static const struct of_device_id exynos850_cmu_of_match[] = { 18307dd05578SSam Protsenko { 1831579839a9SSam Protsenko .compatible = "samsung,exynos850-cmu-apm", 1832579839a9SSam Protsenko .data = &apm_cmu_info, 1833579839a9SSam Protsenko }, { 1834b73fd95dSSam Protsenko .compatible = "samsung,exynos850-cmu-aud", 1835b73fd95dSSam Protsenko .data = &aud_cmu_info, 1836b73fd95dSSam Protsenko }, { 183762782ba8SSam Protsenko .compatible = "samsung,exynos850-cmu-cmgp", 183862782ba8SSam Protsenko .data = &cmgp_cmu_info, 183962782ba8SSam Protsenko }, { 1840e145c765SSam Protsenko .compatible = "samsung,exynos850-cmu-g3d", 1841e145c765SSam Protsenko .data = &g3d_cmu_info, 1842e145c765SSam Protsenko }, { 18437dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-hsi", 18447dd05578SSam Protsenko .data = &hsi_cmu_info, 18457dd05578SSam Protsenko }, { 1846bf3a4c51SSam Protsenko .compatible = "samsung,exynos850-cmu-is", 1847bf3a4c51SSam Protsenko .data = &is_cmu_info, 1848bf3a4c51SSam Protsenko }, { 18497f36d3b6SSam Protsenko .compatible = "samsung,exynos850-cmu-mfcmscl", 18507f36d3b6SSam Protsenko .data = &mfcmscl_cmu_info, 18517f36d3b6SSam Protsenko }, { 18527dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-core", 18537dd05578SSam Protsenko .data = &core_cmu_info, 18547dd05578SSam Protsenko }, { 18557dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-dpu", 18567dd05578SSam Protsenko .data = &dpu_cmu_info, 18577dd05578SSam Protsenko }, { 18587dd05578SSam Protsenko }, 18597dd05578SSam Protsenko }; 18607dd05578SSam Protsenko 18617dd05578SSam Protsenko static struct platform_driver exynos850_cmu_driver __refdata = { 18627dd05578SSam Protsenko .driver = { 18637dd05578SSam Protsenko .name = "exynos850-cmu", 18647dd05578SSam Protsenko .of_match_table = exynos850_cmu_of_match, 18657dd05578SSam Protsenko .suppress_bind_attrs = true, 18667dd05578SSam Protsenko }, 18677dd05578SSam Protsenko .probe = exynos850_cmu_probe, 18687dd05578SSam Protsenko }; 18697dd05578SSam Protsenko 18707dd05578SSam Protsenko static int __init exynos850_cmu_init(void) 18717dd05578SSam Protsenko { 18727dd05578SSam Protsenko return platform_driver_register(&exynos850_cmu_driver); 18737dd05578SSam Protsenko } 18747dd05578SSam Protsenko core_initcall(exynos850_cmu_init); 1875