17dd05578SSam Protsenko // SPDX-License-Identifier: GPL-2.0-only 27dd05578SSam Protsenko /* 37dd05578SSam Protsenko * Copyright (C) 2021 Linaro Ltd. 47dd05578SSam Protsenko * Author: Sam Protsenko <semen.protsenko@linaro.org> 57dd05578SSam Protsenko * 67dd05578SSam Protsenko * Common Clock Framework support for Exynos850 SoC. 77dd05578SSam Protsenko */ 87dd05578SSam Protsenko 97dd05578SSam Protsenko #include <linux/clk.h> 107dd05578SSam Protsenko #include <linux/clk-provider.h> 117dd05578SSam Protsenko #include <linux/of.h> 127dd05578SSam Protsenko #include <linux/of_device.h> 137dd05578SSam Protsenko #include <linux/platform_device.h> 147dd05578SSam Protsenko 157dd05578SSam Protsenko #include <dt-bindings/clock/exynos850.h> 167dd05578SSam Protsenko 177dd05578SSam Protsenko #include "clk.h" 18cfe238e4SDavid Virag #include "clk-exynos-arm64.h" 19bcda841fSSam Protsenko 207dd05578SSam Protsenko /* ---- CMU_TOP ------------------------------------------------------------- */ 217dd05578SSam Protsenko 227dd05578SSam Protsenko /* Register Offset definitions for CMU_TOP (0x120e0000) */ 237dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_MMC 0x0000 247dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED0 0x0004 257dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED1 0x0008 267dd05578SSam Protsenko #define PLL_CON0_PLL_MMC 0x0100 277dd05578SSam Protsenko #define PLL_CON3_PLL_MMC 0x010c 287dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED0 0x0140 297dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED0 0x014c 307dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED1 0x0180 317dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED1 0x018c 32579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000 33b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004 347dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 357dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 367dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c 377dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 387dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 397dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c 407dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 417dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 42bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048 43bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c 44bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050 45bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054 46*7f36d3b6SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058 47*7f36d3b6SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c 48*7f36d3b6SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060 49*7f36d3b6SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064 507dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 517dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 527dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 53579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c 54b73fd95dSSam Protsenko #define CLK_CON_DIV_CLKCMU_AUD 0x1810 557dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 567dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 577dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 587dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c 597dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_DPU 0x1840 607dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 617dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c 627dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 63bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854 64bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858 65bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c 66bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860 67*7f36d3b6SSam Protsenko #define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864 68*7f36d3b6SSam Protsenko #define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868 69*7f36d3b6SSam Protsenko #define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c 70*7f36d3b6SSam Protsenko #define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870 717dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c 727dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 737dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 747dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c 757dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 767dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 777dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 787dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c 797dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 80579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008 81b73fd95dSSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c 827dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 837dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 847dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 857dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 867dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c 877dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 887dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 897dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c 90bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050 91bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054 92bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058 93bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c 94*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060 95*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064 96*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068 97*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c 987dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 997dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 1007dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 1017dd05578SSam Protsenko 1027dd05578SSam Protsenko static const unsigned long top_clk_regs[] __initconst = { 1037dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, 1047dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, 1057dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, 1067dd05578SSam Protsenko PLL_CON0_PLL_MMC, 1077dd05578SSam Protsenko PLL_CON3_PLL_MMC, 1087dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 1097dd05578SSam Protsenko PLL_CON3_PLL_SHARED0, 1107dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 1117dd05578SSam Protsenko PLL_CON3_PLL_SHARED1, 112579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 113b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLKCMU_AUD, 1147dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 1157dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 1167dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 1177dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 1187dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 1197dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 1207dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 1217dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 122bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 123bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 124bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 125bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 126*7f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 127*7f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 128*7f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 129*7f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 1307dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 1317dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 1327dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 133579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_APM_BUS, 134b73fd95dSSam Protsenko CLK_CON_DIV_CLKCMU_AUD, 1357dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 1367dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 1377dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 1387dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 1397dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 1407dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 1417dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 1427dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 143bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_BUS, 144bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_GDC, 145bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_ITP, 146bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_VRA, 147*7f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 148*7f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 149*7f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 150*7f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 1517dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 1527dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 1537dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 1547dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 1557dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 1567dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 1577dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 1587dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 1597dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 160579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 161b73fd95dSSam Protsenko CLK_CON_GAT_GATE_CLKCMU_AUD, 1627dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 1637dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 1647dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 1657dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 1667dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 1677dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 1687dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 1697dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 170bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 171bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 172bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 173bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 174*7f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 175*7f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 176*7f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 177*7f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 1787dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 1797dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 1807dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 1817dd05578SSam Protsenko }; 1827dd05578SSam Protsenko 1837dd05578SSam Protsenko /* 1847dd05578SSam Protsenko * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set 1857dd05578SSam Protsenko * for those PLLs by default, so set_rate operation would fail. 1867dd05578SSam Protsenko */ 1877dd05578SSam Protsenko static const struct samsung_pll_clock top_pll_clks[] __initconst = { 1887dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 1897dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 1907dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 1917dd05578SSam Protsenko NULL), 1927dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 1937dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 1947dd05578SSam Protsenko NULL), 1957dd05578SSam Protsenko PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 1967dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 1977dd05578SSam Protsenko }; 1987dd05578SSam Protsenko 1997dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP */ 2007dd05578SSam Protsenko PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 2017dd05578SSam Protsenko PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 2027dd05578SSam Protsenko PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 203579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */ 204579839a9SSam Protsenko PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" }; 205b73fd95dSSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */ 206b73fd95dSSam Protsenko PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2", 207b73fd95dSSam Protsenko "dout_shared1_div2", "dout_shared0_div3" }; 2087dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 2097dd05578SSam Protsenko PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", 2107dd05578SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 2117dd05578SSam Protsenko PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 2127dd05578SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 2137dd05578SSam Protsenko PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", 2147dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 2157dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 2167dd05578SSam Protsenko "oscclk", "oscclk" }; 2177dd05578SSam Protsenko PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", 2187dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 2197dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ 2207dd05578SSam Protsenko PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 2217dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", 2227dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 2237dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 2247dd05578SSam Protsenko "oscclk", "oscclk" }; 2257dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4", 2267dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 227bf3a4c51SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */ 228bf3a4c51SSam Protsenko PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", 229bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 230bf3a4c51SSam Protsenko PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2", 231bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 232bf3a4c51SSam Protsenko PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2", 233bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 234bf3a4c51SSam Protsenko PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2", 235bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 236*7f36d3b6SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */ 237*7f36d3b6SSam Protsenko PNAME(mout_mfcmscl_mfc_p) = { "dout_shared1_div2", "dout_shared0_div3", 238*7f36d3b6SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 239*7f36d3b6SSam Protsenko PNAME(mout_mfcmscl_m2m_p) = { "dout_shared1_div2", "dout_shared0_div3", 240*7f36d3b6SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 241*7f36d3b6SSam Protsenko PNAME(mout_mfcmscl_mcsc_p) = { "dout_shared1_div2", "dout_shared0_div3", 242*7f36d3b6SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 243*7f36d3b6SSam Protsenko PNAME(mout_mfcmscl_jpeg_p) = { "dout_shared0_div3", "dout_shared1_div3", 244*7f36d3b6SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 2457dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 2467dd05578SSam Protsenko PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 2477dd05578SSam Protsenko PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4", 2487dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2497dd05578SSam Protsenko PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4", 2507dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2517dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ 2527dd05578SSam Protsenko PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3", 2537dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 2547dd05578SSam Protsenko 2557dd05578SSam Protsenko static const struct samsung_mux_clock top_mux_clks[] __initconst = { 2567dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 2577dd05578SSam Protsenko MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 2587dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 4, 1), 2597dd05578SSam Protsenko MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 2607dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 4, 1), 2617dd05578SSam Protsenko MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 2627dd05578SSam Protsenko PLL_CON0_PLL_MMC, 4, 1), 2637dd05578SSam Protsenko 264579839a9SSam Protsenko /* APM */ 265579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", 266579839a9SSam Protsenko mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), 267579839a9SSam Protsenko 268b73fd95dSSam Protsenko /* AUD */ 269b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p, 270b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2), 271b73fd95dSSam Protsenko 2727dd05578SSam Protsenko /* CORE */ 2737dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 2747dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 2757dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 2767dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 2777dd05578SSam Protsenko MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, 2787dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), 2797dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, 2807dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), 2817dd05578SSam Protsenko 2827dd05578SSam Protsenko /* DPU */ 2837dd05578SSam Protsenko MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, 2847dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), 2857dd05578SSam Protsenko 2867dd05578SSam Protsenko /* HSI */ 2877dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, 2887dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), 2897dd05578SSam Protsenko MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, 2907dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), 2917dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, 2927dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), 2937dd05578SSam Protsenko 294bf3a4c51SSam Protsenko /* IS */ 295bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p, 296bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2), 297bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p, 298bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2), 299bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p, 300bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2), 301bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p, 302bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2), 303bf3a4c51SSam Protsenko 304*7f36d3b6SSam Protsenko /* MFCMSCL */ 305*7f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p, 306*7f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2), 307*7f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p, 308*7f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2), 309*7f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p, 310*7f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2), 311*7f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p, 312*7f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2), 313*7f36d3b6SSam Protsenko 3147dd05578SSam Protsenko /* PERI */ 3157dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 3167dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 3177dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, 3187dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), 3197dd05578SSam Protsenko MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, 3207dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), 3217dd05578SSam Protsenko }; 3227dd05578SSam Protsenko 3237dd05578SSam Protsenko static const struct samsung_div_clock top_div_clks[] __initconst = { 3247dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 3257dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 3267dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 3277dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 3287dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 3297dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 3307dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 3317dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 3327dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 3337dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 3347dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 3357dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 3367dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 3377dd05578SSam Protsenko 338579839a9SSam Protsenko /* APM */ 339579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", 340579839a9SSam Protsenko "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), 341579839a9SSam Protsenko 342b73fd95dSSam Protsenko /* AUD */ 343b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud", 344b73fd95dSSam Protsenko CLK_CON_DIV_CLKCMU_AUD, 0, 4), 345b73fd95dSSam Protsenko 3467dd05578SSam Protsenko /* CORE */ 3477dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 3487dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 3497dd05578SSam Protsenko DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 3507dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), 3517dd05578SSam Protsenko DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", 3527dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), 3537dd05578SSam Protsenko DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", 3547dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), 3557dd05578SSam Protsenko 3567dd05578SSam Protsenko /* DPU */ 3577dd05578SSam Protsenko DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", 3587dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 0, 4), 3597dd05578SSam Protsenko 3607dd05578SSam Protsenko /* HSI */ 3617dd05578SSam Protsenko DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", 3627dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), 3637dd05578SSam Protsenko DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", 3647dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), 3657dd05578SSam Protsenko DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", 3667dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), 3677dd05578SSam Protsenko 368bf3a4c51SSam Protsenko /* IS */ 369bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus", 370bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4), 371bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp", 372bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4), 373bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra", 374bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4), 375bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc", 376bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4), 377bf3a4c51SSam Protsenko 378*7f36d3b6SSam Protsenko /* MFCMSCL */ 379*7f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc", 380*7f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4), 381*7f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m", 382*7f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4), 383*7f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc", 384*7f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4), 385*7f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg", 386*7f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4), 387*7f36d3b6SSam Protsenko 3887dd05578SSam Protsenko /* PERI */ 3897dd05578SSam Protsenko DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 3907dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 3917dd05578SSam Protsenko DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", 3927dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), 3937dd05578SSam Protsenko DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", 3947dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), 3957dd05578SSam Protsenko }; 3967dd05578SSam Protsenko 3977dd05578SSam Protsenko static const struct samsung_gate_clock top_gate_clks[] __initconst = { 3987dd05578SSam Protsenko /* CORE */ 3997dd05578SSam Protsenko GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 4007dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 4017dd05578SSam Protsenko GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 4027dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 4037dd05578SSam Protsenko GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", 4047dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), 4057dd05578SSam Protsenko GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", 4067dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), 4077dd05578SSam Protsenko 408579839a9SSam Protsenko /* APM */ 409579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", 410579839a9SSam Protsenko "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0), 411579839a9SSam Protsenko 412b73fd95dSSam Protsenko /* AUD */ 413b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud", 414b73fd95dSSam Protsenko CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0), 415b73fd95dSSam Protsenko 4167dd05578SSam Protsenko /* DPU */ 4177dd05578SSam Protsenko GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", 4187dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), 4197dd05578SSam Protsenko 4207dd05578SSam Protsenko /* HSI */ 4217dd05578SSam Protsenko GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", 4227dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), 4237dd05578SSam Protsenko GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", 4247dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), 4257dd05578SSam Protsenko GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", 4267dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), 4277dd05578SSam Protsenko 428bf3a4c51SSam Protsenko /* IS */ 429bf3a4c51SSam Protsenko /* TODO: These clocks have to be always enabled to access CMU_IS regs */ 430bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus", 431bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0), 432bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp", 433bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0), 434bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra", 435bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0), 436bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc", 437bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0), 438bf3a4c51SSam Protsenko 439*7f36d3b6SSam Protsenko /* MFCMSCL */ 440*7f36d3b6SSam Protsenko /* TODO: These have to be always enabled to access CMU_MFCMSCL regs */ 441*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc", 442*7f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0), 443*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m", 444*7f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0), 445*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc", 446*7f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0), 447*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg", 448*7f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0), 449*7f36d3b6SSam Protsenko 4507dd05578SSam Protsenko /* PERI */ 4517dd05578SSam Protsenko GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 4527dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 4537dd05578SSam Protsenko GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", 4547dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), 4557dd05578SSam Protsenko GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", 4567dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), 4577dd05578SSam Protsenko }; 4587dd05578SSam Protsenko 4597dd05578SSam Protsenko static const struct samsung_cmu_info top_cmu_info __initconst = { 4607dd05578SSam Protsenko .pll_clks = top_pll_clks, 4617dd05578SSam Protsenko .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 4627dd05578SSam Protsenko .mux_clks = top_mux_clks, 4637dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 4647dd05578SSam Protsenko .div_clks = top_div_clks, 4657dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(top_div_clks), 4667dd05578SSam Protsenko .gate_clks = top_gate_clks, 4677dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 4687dd05578SSam Protsenko .nr_clk_ids = TOP_NR_CLK, 4697dd05578SSam Protsenko .clk_regs = top_clk_regs, 4707dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 4717dd05578SSam Protsenko }; 4727dd05578SSam Protsenko 4737dd05578SSam Protsenko static void __init exynos850_cmu_top_init(struct device_node *np) 4747dd05578SSam Protsenko { 475cfe238e4SDavid Virag exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 4767dd05578SSam Protsenko } 4777dd05578SSam Protsenko 478bcda841fSSam Protsenko /* Register CMU_TOP early, as it's a dependency for other early domains */ 4797dd05578SSam Protsenko CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", 4807dd05578SSam Protsenko exynos850_cmu_top_init); 4817dd05578SSam Protsenko 482579839a9SSam Protsenko /* ---- CMU_APM ------------------------------------------------------------- */ 483579839a9SSam Protsenko 484579839a9SSam Protsenko /* Register Offset definitions for CMU_APM (0x11800000) */ 485579839a9SSam Protsenko #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600 486579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610 487579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620 488579839a9SSam Protsenko #define PLL_CON0_MUX_DLL_USER 0x0630 489579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000 490579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004 491579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008 492579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800 493579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804 494579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808 495579839a9SSam Protsenko #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 496579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014 497bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018 498bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020 499579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024 500579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028 501579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034 502579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038 503579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc 504bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0 505579839a9SSam Protsenko 506579839a9SSam Protsenko static const unsigned long apm_clk_regs[] __initconst = { 507579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 508579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 509579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 510579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 511579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 512579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 513579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 514579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 515579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 516579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 517579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 518579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 519bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 520bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 521579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 522579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 523579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 524579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 525579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 526bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 527579839a9SSam Protsenko }; 528579839a9SSam Protsenko 529579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_APM */ 530579839a9SSam Protsenko PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" }; 531579839a9SSam Protsenko PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" }; 532579839a9SSam Protsenko PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" }; 533579839a9SSam Protsenko PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" }; 534579839a9SSam Protsenko PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" }; 535579839a9SSam Protsenko PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user", 536579839a9SSam Protsenko "mout_dll_user", "oscclk_rco_apm" }; 537579839a9SSam Protsenko PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" }; 538579839a9SSam Protsenko 539579839a9SSam Protsenko static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 540579839a9SSam Protsenko FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000), 541579839a9SSam Protsenko FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000), 542579839a9SSam Protsenko FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000), 543579839a9SSam Protsenko FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000), 544579839a9SSam Protsenko }; 545579839a9SSam Protsenko 546579839a9SSam Protsenko static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 547579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p, 548579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1), 549579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user", 550579839a9SSam Protsenko mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1), 551579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p, 552579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1), 553579839a9SSam Protsenko MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p, 554579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 4, 1), 555579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus", 556579839a9SSam Protsenko mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1), 557579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p, 558579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2), 559579839a9SSam Protsenko MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p, 560579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1), 561579839a9SSam Protsenko }; 562579839a9SSam Protsenko 563579839a9SSam Protsenko static const struct samsung_div_clock apm_div_clks[] __initconst = { 564579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus", 565579839a9SSam Protsenko "gout_clkcmu_chub_bus", 566579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3), 567579839a9SSam Protsenko DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus", 568579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3), 569579839a9SSam Protsenko DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus", 570579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3), 571579839a9SSam Protsenko }; 572579839a9SSam Protsenko 573579839a9SSam Protsenko static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 574579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus", 575579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0), 576579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus", 577579839a9SSam Protsenko "mout_clkcmu_chub_bus", 578579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0), 579579839a9SSam Protsenko GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus", 580579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0), 581579839a9SSam Protsenko GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus", 582579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0), 583579839a9SSam Protsenko GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus", 584579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0), 585579839a9SSam Protsenko GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c", 586579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0), 587579839a9SSam Protsenko GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus", 588579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0), 589bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 590bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus", 591bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, 592bc471d1fSSam Protsenko 0), 593bc471d1fSSam Protsenko GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", 594bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0), 595bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", 596bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), 597579839a9SSam Protsenko }; 598579839a9SSam Protsenko 599579839a9SSam Protsenko static const struct samsung_cmu_info apm_cmu_info __initconst = { 600579839a9SSam Protsenko .mux_clks = apm_mux_clks, 601579839a9SSam Protsenko .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 602579839a9SSam Protsenko .div_clks = apm_div_clks, 603579839a9SSam Protsenko .nr_div_clks = ARRAY_SIZE(apm_div_clks), 604579839a9SSam Protsenko .gate_clks = apm_gate_clks, 605579839a9SSam Protsenko .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 606579839a9SSam Protsenko .fixed_clks = apm_fixed_clks, 607579839a9SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 608579839a9SSam Protsenko .nr_clk_ids = APM_NR_CLK, 609579839a9SSam Protsenko .clk_regs = apm_clk_regs, 610579839a9SSam Protsenko .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 611579839a9SSam Protsenko .clk_name = "dout_clkcmu_apm_bus", 612579839a9SSam Protsenko }; 613579839a9SSam Protsenko 614b73fd95dSSam Protsenko /* ---- CMU_AUD ------------------------------------------------------------- */ 615b73fd95dSSam Protsenko 616b73fd95dSSam Protsenko #define PLL_LOCKTIME_PLL_AUD 0x0000 617b73fd95dSSam Protsenko #define PLL_CON0_PLL_AUD 0x0100 618b73fd95dSSam Protsenko #define PLL_CON3_PLL_AUD 0x010c 619b73fd95dSSam Protsenko #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600 620b73fd95dSSam Protsenko #define PLL_CON0_MUX_TICK_USB_USER 0x0610 621b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000 622b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004 623b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008 624b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c 625b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010 626b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014 627b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018 628b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c 629b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020 630b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024 631b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800 632b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804 633b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808 634b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c 635b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810 636b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814 637b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818 638b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c 639b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820 640b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824 641b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828 642b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c 643b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830 644b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834 645b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838 646b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c 647b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840 648b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000 649b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004 650b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008 651b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c 652b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010 653b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 654b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 655b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c 656b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 657b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c 658b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 659b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054 660b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058 661b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c 662b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070 663b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074 664b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088 665b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c 666b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4 667b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8 668b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc 669b73fd95dSSam Protsenko 670b73fd95dSSam Protsenko static const unsigned long aud_clk_regs[] __initconst = { 671b73fd95dSSam Protsenko PLL_LOCKTIME_PLL_AUD, 672b73fd95dSSam Protsenko PLL_CON0_PLL_AUD, 673b73fd95dSSam Protsenko PLL_CON3_PLL_AUD, 674b73fd95dSSam Protsenko PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 675b73fd95dSSam Protsenko PLL_CON0_MUX_TICK_USB_USER, 676b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU, 677b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 678b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_FM, 679b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 680b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 681b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 682b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 683b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 684b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 685b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 686b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_MCLK, 687b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 688b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSD, 689b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSP, 690b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CNT, 691b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU, 692b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 693b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 694b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM, 695b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 696b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 697b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 698b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 699b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 700b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 701b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 702b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 703b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 704b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 705b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 706b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 707b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 708b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 709b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 710b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 711b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 712b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 713b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 714b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 715b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 716b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 717b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 718b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 719b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 720b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 721b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 722b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 723b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 724b73fd95dSSam Protsenko }; 725b73fd95dSSam Protsenko 726b73fd95dSSam Protsenko /* List of parent clocks for Muxes in CMU_AUD */ 727b73fd95dSSam Protsenko PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" }; 728b73fd95dSSam Protsenko PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" }; 729b73fd95dSSam Protsenko PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" }; 730b73fd95dSSam Protsenko PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" }; 731b73fd95dSSam Protsenko PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" }; 732b73fd95dSSam Protsenko PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" }; 733b73fd95dSSam Protsenko PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" }; 734b73fd95dSSam Protsenko PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" }; 735b73fd95dSSam Protsenko PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" }; 736b73fd95dSSam Protsenko PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" }; 737b73fd95dSSam Protsenko PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" }; 738b73fd95dSSam Protsenko PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" }; 739b73fd95dSSam Protsenko PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" }; 740b73fd95dSSam Protsenko 741b73fd95dSSam Protsenko /* 742b73fd95dSSam Protsenko * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set 743b73fd95dSSam Protsenko * for that PLL by default, so set_rate operation would fail. 744b73fd95dSSam Protsenko */ 745b73fd95dSSam Protsenko static const struct samsung_pll_clock aud_pll_clks[] __initconst = { 746b73fd95dSSam Protsenko PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 747b73fd95dSSam Protsenko PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL), 748b73fd95dSSam Protsenko }; 749b73fd95dSSam Protsenko 750b73fd95dSSam Protsenko static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { 751b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000), 752b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000), 753b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000), 754b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000), 755b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000), 756b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000), 757b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000), 758b73fd95dSSam Protsenko FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000), 759b73fd95dSSam Protsenko }; 760b73fd95dSSam Protsenko 761b73fd95dSSam Protsenko static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 762b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, 763b73fd95dSSam Protsenko PLL_CON0_PLL_AUD, 4, 1), 764b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p, 765b73fd95dSSam Protsenko PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1), 766b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user", 767b73fd95dSSam Protsenko mout_aud_tick_usb_user_p, 768b73fd95dSSam Protsenko PLL_CON0_MUX_TICK_USB_USER, 4, 1), 769b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p, 770b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1), 771b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p, 772b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1), 773b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p, 774b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1), 775b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p, 776b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1), 777b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p, 778b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1), 779b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p, 780b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1), 781b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p, 782b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1), 783b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p, 784b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1), 785b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p, 786b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1), 787b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p, 788b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1), 789b73fd95dSSam Protsenko }; 790b73fd95dSSam Protsenko 791b73fd95dSSam Protsenko static const struct samsung_div_clock aud_div_clks[] __initconst = { 792b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll", 793b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4), 794b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll", 795b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4), 796b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll", 797b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4), 798b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll", 799b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9), 800b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch", 801b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3), 802b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg", 803b73fd95dSSam Protsenko "mout_aud_cpu_hch", 804b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3), 805b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif", 806b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2), 807b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif", 808b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10), 809b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif", 810b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10), 811b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif", 812b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10), 813b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif", 814b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10), 815b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif", 816b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10), 817b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif", 818b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10), 819b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif", 820b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10), 821b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif", 822b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10), 823b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user", 824b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1), 825b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm", 826b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10), 827b73fd95dSSam Protsenko }; 828b73fd95dSSam Protsenko 829b73fd95dSSam Protsenko static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 830b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch", 831b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), 832b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk", 833b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0), 834b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg", 835b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0), 836b73fd95dSSam Protsenko /* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */ 837b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd", 838b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0), 839b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd", 840b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0), 841b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd", 842b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0), 843b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd", 844b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0), 845b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd", 846b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0), 847b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd", 848b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0), 849b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd", 850b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0), 851b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp", 852b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0), 853b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk", 854b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0), 855b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt", 856b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0), 857b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0", 858b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0), 859b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1", 860b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0), 861b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2", 862b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0), 863b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3", 864b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0), 865b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4", 866b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0), 867b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5", 868b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0), 869b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6", 870b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0), 871b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm", 872b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0), 873b73fd95dSSam Protsenko }; 874b73fd95dSSam Protsenko 875b73fd95dSSam Protsenko static const struct samsung_cmu_info aud_cmu_info __initconst = { 876b73fd95dSSam Protsenko .pll_clks = aud_pll_clks, 877b73fd95dSSam Protsenko .nr_pll_clks = ARRAY_SIZE(aud_pll_clks), 878b73fd95dSSam Protsenko .mux_clks = aud_mux_clks, 879b73fd95dSSam Protsenko .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 880b73fd95dSSam Protsenko .div_clks = aud_div_clks, 881b73fd95dSSam Protsenko .nr_div_clks = ARRAY_SIZE(aud_div_clks), 882b73fd95dSSam Protsenko .gate_clks = aud_gate_clks, 883b73fd95dSSam Protsenko .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 884b73fd95dSSam Protsenko .fixed_clks = aud_fixed_clks, 885b73fd95dSSam Protsenko .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), 886b73fd95dSSam Protsenko .nr_clk_ids = AUD_NR_CLK, 887b73fd95dSSam Protsenko .clk_regs = aud_clk_regs, 888b73fd95dSSam Protsenko .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 889b73fd95dSSam Protsenko .clk_name = "dout_aud", 890b73fd95dSSam Protsenko }; 891b73fd95dSSam Protsenko 89262782ba8SSam Protsenko /* ---- CMU_CMGP ------------------------------------------------------------ */ 89362782ba8SSam Protsenko 89462782ba8SSam Protsenko /* Register Offset definitions for CMU_CMGP (0x11c00000) */ 89562782ba8SSam Protsenko #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000 89662782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004 89762782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008 89862782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800 89962782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804 90062782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808 90162782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c 90262782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 90362782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018 904bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040 90562782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044 90662782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048 90762782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c 90862782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050 90962782ba8SSam Protsenko 91062782ba8SSam Protsenko static const unsigned long cmgp_clk_regs[] __initconst = { 91162782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 91262782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 91362782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 91462782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 91562782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 91662782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 91762782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 91862782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 91962782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 920bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 92162782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 92262782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 92362782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 92462782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 92562782ba8SSam Protsenko }; 92662782ba8SSam Protsenko 92762782ba8SSam Protsenko /* List of parent clocks for Muxes in CMU_CMGP */ 92862782ba8SSam Protsenko PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 92962782ba8SSam Protsenko PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 93062782ba8SSam Protsenko PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" }; 93162782ba8SSam Protsenko 93262782ba8SSam Protsenko static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = { 93362782ba8SSam Protsenko FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000), 93462782ba8SSam Protsenko }; 93562782ba8SSam Protsenko 93662782ba8SSam Protsenko static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = { 93762782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p, 93862782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 0, 1), 93962782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, 94062782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1), 94162782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, 94262782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1), 94362782ba8SSam Protsenko }; 94462782ba8SSam Protsenko 94562782ba8SSam Protsenko static const struct samsung_div_clock cmgp_div_clks[] __initconst = { 94662782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus", 94762782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), 94862782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", 94962782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5), 95062782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", 95162782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5), 95262782ba8SSam Protsenko }; 95362782ba8SSam Protsenko 95462782ba8SSam Protsenko static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { 95562782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk", 95662782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 95762782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0), 95862782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk", 95962782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 96062782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0), 9616904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 96262782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk", 96362782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 9646904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0), 96562782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0", 96662782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0), 96762782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk", 96862782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 96962782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0), 97062782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1", 97162782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0), 97262782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", 97362782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 97462782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), 975bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk", 976bc471d1fSSam Protsenko "gout_clkcmu_cmgp_bus", 977bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0), 97862782ba8SSam Protsenko }; 97962782ba8SSam Protsenko 98062782ba8SSam Protsenko static const struct samsung_cmu_info cmgp_cmu_info __initconst = { 98162782ba8SSam Protsenko .mux_clks = cmgp_mux_clks, 98262782ba8SSam Protsenko .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks), 98362782ba8SSam Protsenko .div_clks = cmgp_div_clks, 98462782ba8SSam Protsenko .nr_div_clks = ARRAY_SIZE(cmgp_div_clks), 98562782ba8SSam Protsenko .gate_clks = cmgp_gate_clks, 98662782ba8SSam Protsenko .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks), 98762782ba8SSam Protsenko .fixed_clks = cmgp_fixed_clks, 98862782ba8SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks), 98962782ba8SSam Protsenko .nr_clk_ids = CMGP_NR_CLK, 99062782ba8SSam Protsenko .clk_regs = cmgp_clk_regs, 99162782ba8SSam Protsenko .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), 99262782ba8SSam Protsenko .clk_name = "gout_clkcmu_cmgp_bus", 99362782ba8SSam Protsenko }; 99462782ba8SSam Protsenko 9957dd05578SSam Protsenko /* ---- CMU_HSI ------------------------------------------------------------- */ 9967dd05578SSam Protsenko 9977dd05578SSam Protsenko /* Register Offset definitions for CMU_HSI (0x13400000) */ 9987dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 9997dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 10007dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 10017dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 10027dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 10037dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c 10047dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 10057dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 10067dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 10077dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 10087dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 10097dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c 10107dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 10117dd05578SSam Protsenko 10127dd05578SSam Protsenko static const unsigned long hsi_clk_regs[] __initconst = { 10137dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 10147dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 10157dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 10167dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 10177dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 10187dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 10197dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 10207dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 10217dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 10227dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 10237dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 10247dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 10257dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 10267dd05578SSam Protsenko }; 10277dd05578SSam Protsenko 1028dbaa27ccSSam Protsenko /* List of parent clocks for Muxes in CMU_HSI */ 10297dd05578SSam Protsenko PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" }; 10307dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" }; 10317dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" }; 10327dd05578SSam Protsenko PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" }; 10337dd05578SSam Protsenko 10347dd05578SSam Protsenko static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { 10357dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, 10367dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), 10377dd05578SSam Protsenko MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", 10387dd05578SSam Protsenko mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 10397dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 10407dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", 10417dd05578SSam Protsenko mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 10427dd05578SSam Protsenko 4, 1), 10437dd05578SSam Protsenko MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p, 10447dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1), 10457dd05578SSam Protsenko }; 10467dd05578SSam Protsenko 10477dd05578SSam Protsenko static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { 10487dd05578SSam Protsenko GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", 10497dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), 10507dd05578SSam Protsenko GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", 10517dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), 10527dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk", 10537dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), 10546904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 10557dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user", 10566904d7e5SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 10577dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", 10587dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), 10597dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 10607dd05578SSam Protsenko "mout_hsi_mmc_card_user", 10617dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), 10627dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", 10637dd05578SSam Protsenko "mout_hsi_bus_user", 10647dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), 10657dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", 10667dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), 10677dd05578SSam Protsenko GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", 10687dd05578SSam Protsenko "mout_hsi_bus_user", 10697dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), 10707dd05578SSam Protsenko }; 10717dd05578SSam Protsenko 10727dd05578SSam Protsenko static const struct samsung_cmu_info hsi_cmu_info __initconst = { 10737dd05578SSam Protsenko .mux_clks = hsi_mux_clks, 10747dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), 10757dd05578SSam Protsenko .gate_clks = hsi_gate_clks, 10767dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), 10777dd05578SSam Protsenko .nr_clk_ids = HSI_NR_CLK, 10787dd05578SSam Protsenko .clk_regs = hsi_clk_regs, 10797dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), 10807dd05578SSam Protsenko .clk_name = "dout_hsi_bus", 10817dd05578SSam Protsenko }; 10827dd05578SSam Protsenko 1083bf3a4c51SSam Protsenko /* ---- CMU_IS -------------------------------------------------------------- */ 1084bf3a4c51SSam Protsenko 1085bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600 1086bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610 1087bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620 1088bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630 1089bf3a4c51SSam Protsenko #define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800 1090bf3a4c51SSam Protsenko #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000 1091bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040 1092bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044 1093bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048 1094bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c 1095bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050 1096bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054 1097bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058 1098bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c 1099bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060 1100bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064 1101bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074 1102bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078 1103bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c 1104bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080 1105bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098 1106bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c 1107bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0 1108bf3a4c51SSam Protsenko 1109bf3a4c51SSam Protsenko static const unsigned long is_clk_regs[] __initconst = { 1110bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 1111bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 1112bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 1113bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 1114bf3a4c51SSam Protsenko CLK_CON_DIV_DIV_CLK_IS_BUSP, 1115bf3a4c51SSam Protsenko CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 1116bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 1117bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 1118bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 1119bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 1120bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 1121bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_GDC, 1122bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_IPP, 1123bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_ITP, 1124bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_MCSC, 1125bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_VRA, 1126bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 1127bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 1128bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 1129bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 1130bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 1131bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 1132bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 1133bf3a4c51SSam Protsenko }; 1134bf3a4c51SSam Protsenko 1135bf3a4c51SSam Protsenko /* List of parent clocks for Muxes in CMU_IS */ 1136bf3a4c51SSam Protsenko PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" }; 1137bf3a4c51SSam Protsenko PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" }; 1138bf3a4c51SSam Protsenko PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" }; 1139bf3a4c51SSam Protsenko PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" }; 1140bf3a4c51SSam Protsenko 1141bf3a4c51SSam Protsenko static const struct samsung_mux_clock is_mux_clks[] __initconst = { 1142bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p, 1143bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1), 1144bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p, 1145bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1), 1146bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p, 1147bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1), 1148bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p, 1149bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1), 1150bf3a4c51SSam Protsenko }; 1151bf3a4c51SSam Protsenko 1152bf3a4c51SSam Protsenko static const struct samsung_div_clock is_div_clks[] __initconst = { 1153bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user", 1154bf3a4c51SSam Protsenko CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2), 1155bf3a4c51SSam Protsenko }; 1156bf3a4c51SSam Protsenko 1157bf3a4c51SSam Protsenko static const struct samsung_gate_clock is_gate_clks[] __initconst = { 1158bf3a4c51SSam Protsenko /* TODO: Should be enabled in IS driver */ 1159bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp", 1160bf3a4c51SSam Protsenko CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1161bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user", 1162bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0), 1163bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user", 1164bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0), 1165bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user", 1166bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0), 1167bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp", 1168bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0), 1169bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk", 1170bf3a4c51SSam Protsenko "mout_is_bus_user", 1171bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0), 1172bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user", 1173bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0), 1174bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user", 1175bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0), 1176bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user", 1177bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0), 1178bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user", 1179bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0), 1180bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user", 1181bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0), 1182bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk", 1183bf3a4c51SSam Protsenko "mout_is_bus_user", 1184bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0), 1185bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp", 1186bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0), 1187bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk", 1188bf3a4c51SSam Protsenko "mout_is_itp_user", 1189bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0), 1190bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp", 1191bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0), 1192bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk", 1193bf3a4c51SSam Protsenko "mout_is_bus_user", 1194bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0), 1195bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk", 1196bf3a4c51SSam Protsenko "mout_is_itp_user", 1197bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0), 1198bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp", 1199bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0), 1200bf3a4c51SSam Protsenko }; 1201bf3a4c51SSam Protsenko 1202bf3a4c51SSam Protsenko static const struct samsung_cmu_info is_cmu_info __initconst = { 1203bf3a4c51SSam Protsenko .mux_clks = is_mux_clks, 1204bf3a4c51SSam Protsenko .nr_mux_clks = ARRAY_SIZE(is_mux_clks), 1205bf3a4c51SSam Protsenko .div_clks = is_div_clks, 1206bf3a4c51SSam Protsenko .nr_div_clks = ARRAY_SIZE(is_div_clks), 1207bf3a4c51SSam Protsenko .gate_clks = is_gate_clks, 1208bf3a4c51SSam Protsenko .nr_gate_clks = ARRAY_SIZE(is_gate_clks), 1209bf3a4c51SSam Protsenko .nr_clk_ids = IS_NR_CLK, 1210bf3a4c51SSam Protsenko .clk_regs = is_clk_regs, 1211bf3a4c51SSam Protsenko .nr_clk_regs = ARRAY_SIZE(is_clk_regs), 1212bf3a4c51SSam Protsenko .clk_name = "dout_is_bus", 1213bf3a4c51SSam Protsenko }; 1214bf3a4c51SSam Protsenko 1215*7f36d3b6SSam Protsenko /* ---- CMU_MFCMSCL --------------------------------------------------------- */ 1216*7f36d3b6SSam Protsenko 1217*7f36d3b6SSam Protsenko #define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600 1218*7f36d3b6SSam Protsenko #define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610 1219*7f36d3b6SSam Protsenko #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620 1220*7f36d3b6SSam Protsenko #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630 1221*7f36d3b6SSam Protsenko #define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800 1222*7f36d3b6SSam Protsenko #define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000 1223*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038 1224*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c 1225*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048 1226*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c 1227*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050 1228*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054 1229*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058 1230*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074 1231*7f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078 1232*7f36d3b6SSam Protsenko 1233*7f36d3b6SSam Protsenko static const unsigned long mfcmscl_clk_regs[] __initconst = { 1234*7f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 1235*7f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 1236*7f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 1237*7f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 1238*7f36d3b6SSam Protsenko CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 1239*7f36d3b6SSam Protsenko CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK, 1240*7f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK, 1241*7f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK, 1242*7f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK, 1243*7f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK, 1244*7f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK, 1245*7f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK, 1246*7f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK, 1247*7f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1, 1248*7f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK, 1249*7f36d3b6SSam Protsenko }; 1250*7f36d3b6SSam Protsenko 1251*7f36d3b6SSam Protsenko /* List of parent clocks for Muxes in CMU_MFCMSCL */ 1252*7f36d3b6SSam Protsenko PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" }; 1253*7f36d3b6SSam Protsenko PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" }; 1254*7f36d3b6SSam Protsenko PNAME(mout_mfcmscl_mcsc_user_p) = { "oscclk", "dout_mfcmscl_mcsc" }; 1255*7f36d3b6SSam Protsenko PNAME(mout_mfcmscl_jpeg_user_p) = { "oscclk", "dout_mfcmscl_jpeg" }; 1256*7f36d3b6SSam Protsenko 1257*7f36d3b6SSam Protsenko static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = { 1258*7f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user", 1259*7f36d3b6SSam Protsenko mout_mfcmscl_mfc_user_p, 1260*7f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1), 1261*7f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user", 1262*7f36d3b6SSam Protsenko mout_mfcmscl_m2m_user_p, 1263*7f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1), 1264*7f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user", 1265*7f36d3b6SSam Protsenko mout_mfcmscl_mcsc_user_p, 1266*7f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1), 1267*7f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user", 1268*7f36d3b6SSam Protsenko mout_mfcmscl_jpeg_user_p, 1269*7f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1), 1270*7f36d3b6SSam Protsenko }; 1271*7f36d3b6SSam Protsenko 1272*7f36d3b6SSam Protsenko static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = { 1273*7f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user", 1274*7f36d3b6SSam Protsenko CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3), 1275*7f36d3b6SSam Protsenko }; 1276*7f36d3b6SSam Protsenko 1277*7f36d3b6SSam Protsenko static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = { 1278*7f36d3b6SSam Protsenko /* TODO: Should be enabled in MFC driver */ 1279*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk", 1280*7f36d3b6SSam Protsenko "dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK, 1281*7f36d3b6SSam Protsenko 21, CLK_IGNORE_UNUSED, 0), 1282*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk", 1283*7f36d3b6SSam Protsenko "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK, 1284*7f36d3b6SSam Protsenko 21, 0, 0), 1285*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk", 1286*7f36d3b6SSam Protsenko "mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK, 1287*7f36d3b6SSam Protsenko 21, 0, 0), 1288*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk", 1289*7f36d3b6SSam Protsenko "mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK, 1290*7f36d3b6SSam Protsenko 21, 0, 0), 1291*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk", 1292*7f36d3b6SSam Protsenko "mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK, 1293*7f36d3b6SSam Protsenko 21, 0, 0), 1294*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk", 1295*7f36d3b6SSam Protsenko "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK, 1296*7f36d3b6SSam Protsenko 21, 0, 0), 1297*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk", 1298*7f36d3b6SSam Protsenko "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK, 1299*7f36d3b6SSam Protsenko 21, 0, 0), 1300*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk", 1301*7f36d3b6SSam Protsenko "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK, 1302*7f36d3b6SSam Protsenko 21, 0, 0), 1303*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk", 1304*7f36d3b6SSam Protsenko "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1, 1305*7f36d3b6SSam Protsenko 21, 0, 0), 1306*7f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk", 1307*7f36d3b6SSam Protsenko "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK, 1308*7f36d3b6SSam Protsenko 21, 0, 0), 1309*7f36d3b6SSam Protsenko }; 1310*7f36d3b6SSam Protsenko 1311*7f36d3b6SSam Protsenko static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = { 1312*7f36d3b6SSam Protsenko .mux_clks = mfcmscl_mux_clks, 1313*7f36d3b6SSam Protsenko .nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks), 1314*7f36d3b6SSam Protsenko .div_clks = mfcmscl_div_clks, 1315*7f36d3b6SSam Protsenko .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks), 1316*7f36d3b6SSam Protsenko .gate_clks = mfcmscl_gate_clks, 1317*7f36d3b6SSam Protsenko .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks), 1318*7f36d3b6SSam Protsenko .nr_clk_ids = MFCMSCL_NR_CLK, 1319*7f36d3b6SSam Protsenko .clk_regs = mfcmscl_clk_regs, 1320*7f36d3b6SSam Protsenko .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs), 1321*7f36d3b6SSam Protsenko .clk_name = "dout_mfcmscl_mfc", 1322*7f36d3b6SSam Protsenko }; 1323*7f36d3b6SSam Protsenko 13247dd05578SSam Protsenko /* ---- CMU_PERI ------------------------------------------------------------ */ 13257dd05578SSam Protsenko 13267dd05578SSam Protsenko /* Register Offset definitions for CMU_PERI (0x10030000) */ 13277dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 13287dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610 13297dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620 13307dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 13317dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800 13327dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804 13337dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808 13347dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c 13357dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c 13367dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010 13377dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014 13387dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020 13397dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024 13407dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 13417dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c 13427dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030 13437dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034 13447dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038 13457dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c 13467dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040 13477dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044 13487dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048 13497dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c 13507dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050 13517dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054 13527dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c 13537dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064 13547dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c 13557dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0 13567dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4 13577dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 13587dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac 13597dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0 13607dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4 13617dd05578SSam Protsenko 13627dd05578SSam Protsenko static const unsigned long peri_clk_regs[] __initconst = { 13637dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 13647dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 13657dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 13667dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 13677dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 13687dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 13697dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 13707dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 13717dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 13727dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 13737dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 13747dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 13757dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 13767dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 13777dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 13787dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 13797dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 13807dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 13817dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 13827dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 13837dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 13847dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 13857dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 13867dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 13877dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 13887dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 13897dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 13907dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 13917dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 13927dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 13937dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 13947dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 13957dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 13967dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 13977dd05578SSam Protsenko }; 13987dd05578SSam Protsenko 13997dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_PERI */ 14007dd05578SSam Protsenko PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; 14017dd05578SSam Protsenko PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" }; 14027dd05578SSam Protsenko PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" }; 14037dd05578SSam Protsenko PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" }; 14047dd05578SSam Protsenko 14057dd05578SSam Protsenko static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 14067dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 14077dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 14087dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", 14097dd05578SSam Protsenko mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), 14107dd05578SSam Protsenko MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", 14117dd05578SSam Protsenko mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), 14127dd05578SSam Protsenko MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, 14137dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), 14147dd05578SSam Protsenko }; 14157dd05578SSam Protsenko 14167dd05578SSam Protsenko static const struct samsung_div_clock peri_div_clks[] __initconst = { 14177dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0", 14187dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5), 14197dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1", 14207dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), 14217dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", 14227dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), 14237dd05578SSam Protsenko DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", 14247dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), 14257dd05578SSam Protsenko }; 14267dd05578SSam Protsenko 14277dd05578SSam Protsenko static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 14287dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user", 14297dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0), 14307dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user", 14317dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0), 14327dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user", 14337dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0), 14347dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0", 14357dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0), 14367dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", 14377dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), 14387dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1", 14397dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0), 14407dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", 14417dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), 14427dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2", 14437dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0), 14447dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", 14457dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), 14467dd05578SSam Protsenko GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", 14477dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), 14487dd05578SSam Protsenko GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", 14497dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), 14507dd05578SSam Protsenko GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", 14517dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), 14527dd05578SSam Protsenko GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", 14537dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), 14547dd05578SSam Protsenko GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", 14557dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), 14567dd05578SSam Protsenko GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", 14577dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), 14587dd05578SSam Protsenko GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", 14597dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), 14607dd05578SSam Protsenko GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", 14617dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), 14627dd05578SSam Protsenko GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", 14637dd05578SSam Protsenko "mout_peri_bus_user", 14647dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), 14657dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", 14667dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), 14677dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", 14687dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), 14697dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", 14707dd05578SSam Protsenko "mout_peri_bus_user", 14717dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), 14727dd05578SSam Protsenko GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", 14737dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), 14747dd05578SSam Protsenko GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", 14757dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), 14767dd05578SSam Protsenko GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", 14777dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0), 14787dd05578SSam Protsenko GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", 14797dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0), 14806904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 14817dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk", 14827dd05578SSam Protsenko "mout_peri_bus_user", 14836904d7e5SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 14847dd05578SSam Protsenko }; 14857dd05578SSam Protsenko 14867dd05578SSam Protsenko static const struct samsung_cmu_info peri_cmu_info __initconst = { 14877dd05578SSam Protsenko .mux_clks = peri_mux_clks, 14887dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 14897dd05578SSam Protsenko .div_clks = peri_div_clks, 14907dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(peri_div_clks), 14917dd05578SSam Protsenko .gate_clks = peri_gate_clks, 14927dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 14937dd05578SSam Protsenko .nr_clk_ids = PERI_NR_CLK, 14947dd05578SSam Protsenko .clk_regs = peri_clk_regs, 14957dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 14967dd05578SSam Protsenko .clk_name = "dout_peri_bus", 14977dd05578SSam Protsenko }; 14987dd05578SSam Protsenko 1499bcda841fSSam Protsenko static void __init exynos850_cmu_peri_init(struct device_node *np) 1500bcda841fSSam Protsenko { 1501cfe238e4SDavid Virag exynos_arm64_register_cmu(NULL, np, &peri_cmu_info); 1502bcda841fSSam Protsenko } 1503bcda841fSSam Protsenko 1504bcda841fSSam Protsenko /* Register CMU_PERI early, as it's needed for MCT timer */ 1505bcda841fSSam Protsenko CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", 1506bcda841fSSam Protsenko exynos850_cmu_peri_init); 1507bcda841fSSam Protsenko 15087dd05578SSam Protsenko /* ---- CMU_CORE ------------------------------------------------------------ */ 15097dd05578SSam Protsenko 15107dd05578SSam Protsenko /* Register Offset definitions for CMU_CORE (0x12000000) */ 15117dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 15127dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610 15137dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 15147dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630 15157dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 15167dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 15177dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 15187dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 1519bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 15207dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 15217dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec 15227dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 15237dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c 1524bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 15257dd05578SSam Protsenko 15267dd05578SSam Protsenko static const unsigned long core_clk_regs[] __initconst = { 15277dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 15287dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 15297dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 15307dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 15317dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 15327dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 15337dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 15347dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 1535bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 15367dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 15377dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 15387dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 15397dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 1540bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 15417dd05578SSam Protsenko }; 15427dd05578SSam Protsenko 15437dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_CORE */ 15447dd05578SSam Protsenko PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; 15457dd05578SSam Protsenko PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; 15467dd05578SSam Protsenko PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" }; 15477dd05578SSam Protsenko PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" }; 15487dd05578SSam Protsenko PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; 15497dd05578SSam Protsenko 15507dd05578SSam Protsenko static const struct samsung_mux_clock core_mux_clks[] __initconst = { 15517dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 15527dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 15537dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, 15547dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), 15557dd05578SSam Protsenko MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", 15567dd05578SSam Protsenko mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 15577dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 15587dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p, 15597dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1), 15607dd05578SSam Protsenko MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, 15617dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), 15627dd05578SSam Protsenko }; 15637dd05578SSam Protsenko 15647dd05578SSam Protsenko static const struct samsung_div_clock core_div_clks[] __initconst = { 15657dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 15667dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 15677dd05578SSam Protsenko }; 15687dd05578SSam Protsenko 15697dd05578SSam Protsenko static const struct samsung_gate_clock core_gate_clks[] __initconst = { 15706904d7e5SSam Protsenko /* CCI (interconnect) clock must be always running */ 15717dd05578SSam Protsenko GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", 15726904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0), 15736904d7e5SSam Protsenko /* GIC (interrupt controller) clock must be always running */ 15747dd05578SSam Protsenko GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic", 15756904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0), 15767dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", 15777dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), 15787dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 15797dd05578SSam Protsenko "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 15807dd05578SSam Protsenko 21, CLK_SET_RATE_PARENT, 0), 15817dd05578SSam Protsenko GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", 15827dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), 15837dd05578SSam Protsenko GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", 15847dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), 1585bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 1586bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp", 1587bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1588bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk", 1589bc471d1fSSam Protsenko "dout_core_busp", 1590bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0), 15917dd05578SSam Protsenko }; 15927dd05578SSam Protsenko 15937dd05578SSam Protsenko static const struct samsung_cmu_info core_cmu_info __initconst = { 15947dd05578SSam Protsenko .mux_clks = core_mux_clks, 15957dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 15967dd05578SSam Protsenko .div_clks = core_div_clks, 15977dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(core_div_clks), 15987dd05578SSam Protsenko .gate_clks = core_gate_clks, 15997dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 16007dd05578SSam Protsenko .nr_clk_ids = CORE_NR_CLK, 16017dd05578SSam Protsenko .clk_regs = core_clk_regs, 16027dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 16037dd05578SSam Protsenko .clk_name = "dout_core_bus", 16047dd05578SSam Protsenko }; 16057dd05578SSam Protsenko 16067dd05578SSam Protsenko /* ---- CMU_DPU ------------------------------------------------------------- */ 16077dd05578SSam Protsenko 16087dd05578SSam Protsenko /* Register Offset definitions for CMU_DPU (0x13000000) */ 16097dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600 16107dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 16117dd05578SSam Protsenko #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004 16127dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010 16137dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014 16147dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018 16157dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028 16167dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c 16177dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038 16187dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c 16197dd05578SSam Protsenko 16207dd05578SSam Protsenko static const unsigned long dpu_clk_regs[] __initconst = { 16217dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 16227dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 16237dd05578SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 16247dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 16257dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 16267dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 16277dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 16287dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 16297dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 16307dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 16317dd05578SSam Protsenko }; 16327dd05578SSam Protsenko 1633dbaa27ccSSam Protsenko /* List of parent clocks for Muxes in CMU_DPU */ 16347dd05578SSam Protsenko PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" }; 16357dd05578SSam Protsenko 16367dd05578SSam Protsenko static const struct samsung_mux_clock dpu_mux_clks[] __initconst = { 16377dd05578SSam Protsenko MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p, 16387dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1), 16397dd05578SSam Protsenko }; 16407dd05578SSam Protsenko 16417dd05578SSam Protsenko static const struct samsung_div_clock dpu_div_clks[] __initconst = { 16427dd05578SSam Protsenko DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user", 16437dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), 16447dd05578SSam Protsenko }; 16457dd05578SSam Protsenko 16467dd05578SSam Protsenko static const struct samsung_gate_clock dpu_gate_clks[] __initconst = { 16476904d7e5SSam Protsenko /* TODO: Should be enabled in DSIM driver */ 16487dd05578SSam Protsenko GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk", 16496904d7e5SSam Protsenko "dout_dpu_busp", 16506904d7e5SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0), 16517dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user", 16527dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0), 16537dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user", 16547dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0), 16557dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user", 16567dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0), 16577dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user", 16587dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0), 16597dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp", 16607dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0), 16617dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user", 16627dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0), 16637dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp", 16647dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0), 16657dd05578SSam Protsenko }; 16667dd05578SSam Protsenko 16677dd05578SSam Protsenko static const struct samsung_cmu_info dpu_cmu_info __initconst = { 16687dd05578SSam Protsenko .mux_clks = dpu_mux_clks, 16697dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks), 16707dd05578SSam Protsenko .div_clks = dpu_div_clks, 16717dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(dpu_div_clks), 16727dd05578SSam Protsenko .gate_clks = dpu_gate_clks, 16737dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), 16747dd05578SSam Protsenko .nr_clk_ids = DPU_NR_CLK, 16757dd05578SSam Protsenko .clk_regs = dpu_clk_regs, 16767dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), 16777dd05578SSam Protsenko .clk_name = "dout_dpu", 16787dd05578SSam Protsenko }; 16797dd05578SSam Protsenko 16807dd05578SSam Protsenko /* ---- platform_driver ----------------------------------------------------- */ 16817dd05578SSam Protsenko 16827dd05578SSam Protsenko static int __init exynos850_cmu_probe(struct platform_device *pdev) 16837dd05578SSam Protsenko { 16847dd05578SSam Protsenko const struct samsung_cmu_info *info; 16857dd05578SSam Protsenko struct device *dev = &pdev->dev; 16867dd05578SSam Protsenko 16877dd05578SSam Protsenko info = of_device_get_match_data(dev); 1688cfe238e4SDavid Virag exynos_arm64_register_cmu(dev, dev->of_node, info); 16897dd05578SSam Protsenko 16907dd05578SSam Protsenko return 0; 16917dd05578SSam Protsenko } 16927dd05578SSam Protsenko 16937dd05578SSam Protsenko static const struct of_device_id exynos850_cmu_of_match[] = { 16947dd05578SSam Protsenko { 1695579839a9SSam Protsenko .compatible = "samsung,exynos850-cmu-apm", 1696579839a9SSam Protsenko .data = &apm_cmu_info, 1697579839a9SSam Protsenko }, { 1698b73fd95dSSam Protsenko .compatible = "samsung,exynos850-cmu-aud", 1699b73fd95dSSam Protsenko .data = &aud_cmu_info, 1700b73fd95dSSam Protsenko }, { 170162782ba8SSam Protsenko .compatible = "samsung,exynos850-cmu-cmgp", 170262782ba8SSam Protsenko .data = &cmgp_cmu_info, 170362782ba8SSam Protsenko }, { 17047dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-hsi", 17057dd05578SSam Protsenko .data = &hsi_cmu_info, 17067dd05578SSam Protsenko }, { 1707bf3a4c51SSam Protsenko .compatible = "samsung,exynos850-cmu-is", 1708bf3a4c51SSam Protsenko .data = &is_cmu_info, 1709bf3a4c51SSam Protsenko }, { 1710*7f36d3b6SSam Protsenko .compatible = "samsung,exynos850-cmu-mfcmscl", 1711*7f36d3b6SSam Protsenko .data = &mfcmscl_cmu_info, 1712*7f36d3b6SSam Protsenko }, { 17137dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-core", 17147dd05578SSam Protsenko .data = &core_cmu_info, 17157dd05578SSam Protsenko }, { 17167dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-dpu", 17177dd05578SSam Protsenko .data = &dpu_cmu_info, 17187dd05578SSam Protsenko }, { 17197dd05578SSam Protsenko }, 17207dd05578SSam Protsenko }; 17217dd05578SSam Protsenko 17227dd05578SSam Protsenko static struct platform_driver exynos850_cmu_driver __refdata = { 17237dd05578SSam Protsenko .driver = { 17247dd05578SSam Protsenko .name = "exynos850-cmu", 17257dd05578SSam Protsenko .of_match_table = exynos850_cmu_of_match, 17267dd05578SSam Protsenko .suppress_bind_attrs = true, 17277dd05578SSam Protsenko }, 17287dd05578SSam Protsenko .probe = exynos850_cmu_probe, 17297dd05578SSam Protsenko }; 17307dd05578SSam Protsenko 17317dd05578SSam Protsenko static int __init exynos850_cmu_init(void) 17327dd05578SSam Protsenko { 17337dd05578SSam Protsenko return platform_driver_register(&exynos850_cmu_driver); 17347dd05578SSam Protsenko } 17357dd05578SSam Protsenko core_initcall(exynos850_cmu_init); 1736