1*7dd05578SSam Protsenko // SPDX-License-Identifier: GPL-2.0-only 2*7dd05578SSam Protsenko /* 3*7dd05578SSam Protsenko * Copyright (C) 2021 Linaro Ltd. 4*7dd05578SSam Protsenko * Author: Sam Protsenko <semen.protsenko@linaro.org> 5*7dd05578SSam Protsenko * 6*7dd05578SSam Protsenko * Common Clock Framework support for Exynos850 SoC. 7*7dd05578SSam Protsenko */ 8*7dd05578SSam Protsenko 9*7dd05578SSam Protsenko #include <linux/clk.h> 10*7dd05578SSam Protsenko #include <linux/clk-provider.h> 11*7dd05578SSam Protsenko #include <linux/of.h> 12*7dd05578SSam Protsenko #include <linux/of_address.h> 13*7dd05578SSam Protsenko #include <linux/of_device.h> 14*7dd05578SSam Protsenko #include <linux/platform_device.h> 15*7dd05578SSam Protsenko 16*7dd05578SSam Protsenko #include <dt-bindings/clock/exynos850.h> 17*7dd05578SSam Protsenko 18*7dd05578SSam Protsenko #include "clk.h" 19*7dd05578SSam Protsenko 20*7dd05578SSam Protsenko /* Gate register bits */ 21*7dd05578SSam Protsenko #define GATE_MANUAL BIT(20) 22*7dd05578SSam Protsenko #define GATE_ENABLE_HWACG BIT(28) 23*7dd05578SSam Protsenko 24*7dd05578SSam Protsenko /* Gate register offsets range */ 25*7dd05578SSam Protsenko #define GATE_OFF_START 0x2000 26*7dd05578SSam Protsenko #define GATE_OFF_END 0x2fff 27*7dd05578SSam Protsenko 28*7dd05578SSam Protsenko /** 29*7dd05578SSam Protsenko * exynos850_init_clocks - Set clocks initial configuration 30*7dd05578SSam Protsenko * @np: CMU device tree node with "reg" property (CMU addr) 31*7dd05578SSam Protsenko * @reg_offs: Register offsets array for clocks to init 32*7dd05578SSam Protsenko * @reg_offs_len: Number of register offsets in reg_offs array 33*7dd05578SSam Protsenko * 34*7dd05578SSam Protsenko * Set manual control mode for all gate clocks. 35*7dd05578SSam Protsenko */ 36*7dd05578SSam Protsenko static void __init exynos850_init_clocks(struct device_node *np, 37*7dd05578SSam Protsenko const unsigned long *reg_offs, size_t reg_offs_len) 38*7dd05578SSam Protsenko { 39*7dd05578SSam Protsenko void __iomem *reg_base; 40*7dd05578SSam Protsenko size_t i; 41*7dd05578SSam Protsenko 42*7dd05578SSam Protsenko reg_base = of_iomap(np, 0); 43*7dd05578SSam Protsenko if (!reg_base) 44*7dd05578SSam Protsenko panic("%s: failed to map registers\n", __func__); 45*7dd05578SSam Protsenko 46*7dd05578SSam Protsenko for (i = 0; i < reg_offs_len; ++i) { 47*7dd05578SSam Protsenko void __iomem *reg = reg_base + reg_offs[i]; 48*7dd05578SSam Protsenko u32 val; 49*7dd05578SSam Protsenko 50*7dd05578SSam Protsenko /* Modify only gate clock registers */ 51*7dd05578SSam Protsenko if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END) 52*7dd05578SSam Protsenko continue; 53*7dd05578SSam Protsenko 54*7dd05578SSam Protsenko val = readl(reg); 55*7dd05578SSam Protsenko val |= GATE_MANUAL; 56*7dd05578SSam Protsenko val &= ~GATE_ENABLE_HWACG; 57*7dd05578SSam Protsenko writel(val, reg); 58*7dd05578SSam Protsenko } 59*7dd05578SSam Protsenko 60*7dd05578SSam Protsenko iounmap(reg_base); 61*7dd05578SSam Protsenko } 62*7dd05578SSam Protsenko 63*7dd05578SSam Protsenko /* ---- CMU_TOP ------------------------------------------------------------- */ 64*7dd05578SSam Protsenko 65*7dd05578SSam Protsenko /* Register Offset definitions for CMU_TOP (0x120e0000) */ 66*7dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_MMC 0x0000 67*7dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED0 0x0004 68*7dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED1 0x0008 69*7dd05578SSam Protsenko #define PLL_CON0_PLL_MMC 0x0100 70*7dd05578SSam Protsenko #define PLL_CON3_PLL_MMC 0x010c 71*7dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED0 0x0140 72*7dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED0 0x014c 73*7dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED1 0x0180 74*7dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED1 0x018c 75*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 76*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 77*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c 78*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 79*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 80*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c 81*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 82*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 83*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 84*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 85*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 86*7dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 87*7dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 88*7dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 89*7dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c 90*7dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_DPU 0x1840 91*7dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 92*7dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c 93*7dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 94*7dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c 95*7dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 96*7dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 97*7dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c 98*7dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 99*7dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 100*7dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 101*7dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c 102*7dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 103*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 104*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 105*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 106*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 107*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c 108*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 109*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 110*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c 111*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 112*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 113*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 114*7dd05578SSam Protsenko 115*7dd05578SSam Protsenko static const unsigned long top_clk_regs[] __initconst = { 116*7dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, 117*7dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, 118*7dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, 119*7dd05578SSam Protsenko PLL_CON0_PLL_MMC, 120*7dd05578SSam Protsenko PLL_CON3_PLL_MMC, 121*7dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 122*7dd05578SSam Protsenko PLL_CON3_PLL_SHARED0, 123*7dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 124*7dd05578SSam Protsenko PLL_CON3_PLL_SHARED1, 125*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 126*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 127*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 128*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 129*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 130*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 131*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 132*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 133*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 134*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 135*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 136*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 137*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 138*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 139*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 140*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 141*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 142*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 143*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 144*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 145*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 146*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 147*7dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 148*7dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 149*7dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 150*7dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 151*7dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 152*7dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 153*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 154*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 155*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 156*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 157*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 158*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 159*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 160*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 161*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 162*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 163*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 164*7dd05578SSam Protsenko }; 165*7dd05578SSam Protsenko 166*7dd05578SSam Protsenko /* 167*7dd05578SSam Protsenko * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set 168*7dd05578SSam Protsenko * for those PLLs by default, so set_rate operation would fail. 169*7dd05578SSam Protsenko */ 170*7dd05578SSam Protsenko static const struct samsung_pll_clock top_pll_clks[] __initconst = { 171*7dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 172*7dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 173*7dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 174*7dd05578SSam Protsenko NULL), 175*7dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 176*7dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 177*7dd05578SSam Protsenko NULL), 178*7dd05578SSam Protsenko PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 179*7dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 180*7dd05578SSam Protsenko }; 181*7dd05578SSam Protsenko 182*7dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP */ 183*7dd05578SSam Protsenko PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 184*7dd05578SSam Protsenko PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 185*7dd05578SSam Protsenko PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 186*7dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 187*7dd05578SSam Protsenko PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", 188*7dd05578SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 189*7dd05578SSam Protsenko PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 190*7dd05578SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 191*7dd05578SSam Protsenko PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", 192*7dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 193*7dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 194*7dd05578SSam Protsenko "oscclk", "oscclk" }; 195*7dd05578SSam Protsenko PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", 196*7dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 197*7dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ 198*7dd05578SSam Protsenko PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 199*7dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", 200*7dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 201*7dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 202*7dd05578SSam Protsenko "oscclk", "oscclk" }; 203*7dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4", 204*7dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 205*7dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 206*7dd05578SSam Protsenko PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 207*7dd05578SSam Protsenko PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4", 208*7dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 209*7dd05578SSam Protsenko PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4", 210*7dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 211*7dd05578SSam Protsenko 212*7dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ 213*7dd05578SSam Protsenko PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3", 214*7dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 215*7dd05578SSam Protsenko 216*7dd05578SSam Protsenko static const struct samsung_mux_clock top_mux_clks[] __initconst = { 217*7dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 218*7dd05578SSam Protsenko MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 219*7dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 4, 1), 220*7dd05578SSam Protsenko MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 221*7dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 4, 1), 222*7dd05578SSam Protsenko MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 223*7dd05578SSam Protsenko PLL_CON0_PLL_MMC, 4, 1), 224*7dd05578SSam Protsenko 225*7dd05578SSam Protsenko /* CORE */ 226*7dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 227*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 228*7dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 229*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 230*7dd05578SSam Protsenko MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, 231*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), 232*7dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, 233*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), 234*7dd05578SSam Protsenko 235*7dd05578SSam Protsenko /* DPU */ 236*7dd05578SSam Protsenko MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, 237*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), 238*7dd05578SSam Protsenko 239*7dd05578SSam Protsenko /* HSI */ 240*7dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, 241*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), 242*7dd05578SSam Protsenko MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, 243*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), 244*7dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, 245*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), 246*7dd05578SSam Protsenko 247*7dd05578SSam Protsenko /* PERI */ 248*7dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 249*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 250*7dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, 251*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), 252*7dd05578SSam Protsenko MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, 253*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), 254*7dd05578SSam Protsenko }; 255*7dd05578SSam Protsenko 256*7dd05578SSam Protsenko static const struct samsung_div_clock top_div_clks[] __initconst = { 257*7dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 258*7dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 259*7dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 260*7dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 261*7dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 262*7dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 263*7dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 264*7dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 265*7dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 266*7dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 267*7dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 268*7dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 269*7dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 270*7dd05578SSam Protsenko 271*7dd05578SSam Protsenko /* CORE */ 272*7dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 273*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 274*7dd05578SSam Protsenko DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 275*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), 276*7dd05578SSam Protsenko DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", 277*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), 278*7dd05578SSam Protsenko DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", 279*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), 280*7dd05578SSam Protsenko 281*7dd05578SSam Protsenko /* DPU */ 282*7dd05578SSam Protsenko DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", 283*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 0, 4), 284*7dd05578SSam Protsenko 285*7dd05578SSam Protsenko /* HSI */ 286*7dd05578SSam Protsenko DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", 287*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), 288*7dd05578SSam Protsenko DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", 289*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), 290*7dd05578SSam Protsenko DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", 291*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), 292*7dd05578SSam Protsenko 293*7dd05578SSam Protsenko /* PERI */ 294*7dd05578SSam Protsenko DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 295*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 296*7dd05578SSam Protsenko DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", 297*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), 298*7dd05578SSam Protsenko DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", 299*7dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), 300*7dd05578SSam Protsenko }; 301*7dd05578SSam Protsenko 302*7dd05578SSam Protsenko static const struct samsung_gate_clock top_gate_clks[] __initconst = { 303*7dd05578SSam Protsenko /* CORE */ 304*7dd05578SSam Protsenko GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 305*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 306*7dd05578SSam Protsenko GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 307*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 308*7dd05578SSam Protsenko GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", 309*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), 310*7dd05578SSam Protsenko GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", 311*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), 312*7dd05578SSam Protsenko 313*7dd05578SSam Protsenko /* DPU */ 314*7dd05578SSam Protsenko GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", 315*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), 316*7dd05578SSam Protsenko 317*7dd05578SSam Protsenko /* HSI */ 318*7dd05578SSam Protsenko GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", 319*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), 320*7dd05578SSam Protsenko GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", 321*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), 322*7dd05578SSam Protsenko GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", 323*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), 324*7dd05578SSam Protsenko 325*7dd05578SSam Protsenko /* PERI */ 326*7dd05578SSam Protsenko GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 327*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 328*7dd05578SSam Protsenko GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", 329*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), 330*7dd05578SSam Protsenko GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", 331*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), 332*7dd05578SSam Protsenko }; 333*7dd05578SSam Protsenko 334*7dd05578SSam Protsenko static const struct samsung_cmu_info top_cmu_info __initconst = { 335*7dd05578SSam Protsenko .pll_clks = top_pll_clks, 336*7dd05578SSam Protsenko .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 337*7dd05578SSam Protsenko .mux_clks = top_mux_clks, 338*7dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 339*7dd05578SSam Protsenko .div_clks = top_div_clks, 340*7dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(top_div_clks), 341*7dd05578SSam Protsenko .gate_clks = top_gate_clks, 342*7dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 343*7dd05578SSam Protsenko .nr_clk_ids = TOP_NR_CLK, 344*7dd05578SSam Protsenko .clk_regs = top_clk_regs, 345*7dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 346*7dd05578SSam Protsenko }; 347*7dd05578SSam Protsenko 348*7dd05578SSam Protsenko static void __init exynos850_cmu_top_init(struct device_node *np) 349*7dd05578SSam Protsenko { 350*7dd05578SSam Protsenko exynos850_init_clocks(np, top_clk_regs, ARRAY_SIZE(top_clk_regs)); 351*7dd05578SSam Protsenko samsung_cmu_register_one(np, &top_cmu_info); 352*7dd05578SSam Protsenko } 353*7dd05578SSam Protsenko 354*7dd05578SSam Protsenko CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", 355*7dd05578SSam Protsenko exynos850_cmu_top_init); 356*7dd05578SSam Protsenko 357*7dd05578SSam Protsenko /* ---- CMU_HSI ------------------------------------------------------------- */ 358*7dd05578SSam Protsenko 359*7dd05578SSam Protsenko /* Register Offset definitions for CMU_HSI (0x13400000) */ 360*7dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 361*7dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 362*7dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 363*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 364*7dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 365*7dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c 366*7dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 367*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 368*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 369*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 370*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 371*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c 372*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 373*7dd05578SSam Protsenko 374*7dd05578SSam Protsenko static const unsigned long hsi_clk_regs[] __initconst = { 375*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 376*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 377*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 378*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 379*7dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 380*7dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 381*7dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 382*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 383*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 384*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 385*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 386*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 387*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 388*7dd05578SSam Protsenko }; 389*7dd05578SSam Protsenko 390*7dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_PERI */ 391*7dd05578SSam Protsenko PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" }; 392*7dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" }; 393*7dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" }; 394*7dd05578SSam Protsenko PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" }; 395*7dd05578SSam Protsenko 396*7dd05578SSam Protsenko static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { 397*7dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, 398*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), 399*7dd05578SSam Protsenko MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", 400*7dd05578SSam Protsenko mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 401*7dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 402*7dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", 403*7dd05578SSam Protsenko mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 404*7dd05578SSam Protsenko 4, 1), 405*7dd05578SSam Protsenko MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p, 406*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1), 407*7dd05578SSam Protsenko }; 408*7dd05578SSam Protsenko 409*7dd05578SSam Protsenko static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { 410*7dd05578SSam Protsenko GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", 411*7dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), 412*7dd05578SSam Protsenko GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", 413*7dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), 414*7dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk", 415*7dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), 416*7dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user", 417*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, 0, 0), 418*7dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", 419*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), 420*7dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 421*7dd05578SSam Protsenko "mout_hsi_mmc_card_user", 422*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), 423*7dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", 424*7dd05578SSam Protsenko "mout_hsi_bus_user", 425*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), 426*7dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", 427*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), 428*7dd05578SSam Protsenko GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", 429*7dd05578SSam Protsenko "mout_hsi_bus_user", 430*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), 431*7dd05578SSam Protsenko }; 432*7dd05578SSam Protsenko 433*7dd05578SSam Protsenko static const struct samsung_cmu_info hsi_cmu_info __initconst = { 434*7dd05578SSam Protsenko .mux_clks = hsi_mux_clks, 435*7dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), 436*7dd05578SSam Protsenko .gate_clks = hsi_gate_clks, 437*7dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), 438*7dd05578SSam Protsenko .nr_clk_ids = HSI_NR_CLK, 439*7dd05578SSam Protsenko .clk_regs = hsi_clk_regs, 440*7dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), 441*7dd05578SSam Protsenko .clk_name = "dout_hsi_bus", 442*7dd05578SSam Protsenko }; 443*7dd05578SSam Protsenko 444*7dd05578SSam Protsenko /* ---- CMU_PERI ------------------------------------------------------------ */ 445*7dd05578SSam Protsenko 446*7dd05578SSam Protsenko /* Register Offset definitions for CMU_PERI (0x10030000) */ 447*7dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 448*7dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610 449*7dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620 450*7dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 451*7dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800 452*7dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804 453*7dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808 454*7dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c 455*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c 456*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010 457*7dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014 458*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020 459*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024 460*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 461*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c 462*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030 463*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034 464*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038 465*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c 466*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040 467*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044 468*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048 469*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c 470*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050 471*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054 472*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c 473*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064 474*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c 475*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0 476*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4 477*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 478*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac 479*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0 480*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4 481*7dd05578SSam Protsenko 482*7dd05578SSam Protsenko static const unsigned long peri_clk_regs[] __initconst = { 483*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 484*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 485*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 486*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 487*7dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 488*7dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 489*7dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 490*7dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 491*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 492*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 493*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 494*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 495*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 496*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 497*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 498*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 499*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 500*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 501*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 502*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 503*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 504*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 505*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 506*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 507*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 508*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 509*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 510*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 511*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 512*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 513*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 514*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 515*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 516*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 517*7dd05578SSam Protsenko }; 518*7dd05578SSam Protsenko 519*7dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_PERI */ 520*7dd05578SSam Protsenko PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; 521*7dd05578SSam Protsenko PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" }; 522*7dd05578SSam Protsenko PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" }; 523*7dd05578SSam Protsenko PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" }; 524*7dd05578SSam Protsenko 525*7dd05578SSam Protsenko static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 526*7dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 527*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 528*7dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", 529*7dd05578SSam Protsenko mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), 530*7dd05578SSam Protsenko MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", 531*7dd05578SSam Protsenko mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), 532*7dd05578SSam Protsenko MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, 533*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), 534*7dd05578SSam Protsenko }; 535*7dd05578SSam Protsenko 536*7dd05578SSam Protsenko static const struct samsung_div_clock peri_div_clks[] __initconst = { 537*7dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0", 538*7dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5), 539*7dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1", 540*7dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), 541*7dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", 542*7dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), 543*7dd05578SSam Protsenko DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", 544*7dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), 545*7dd05578SSam Protsenko }; 546*7dd05578SSam Protsenko 547*7dd05578SSam Protsenko static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 548*7dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user", 549*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0), 550*7dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user", 551*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0), 552*7dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user", 553*7dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0), 554*7dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0", 555*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0), 556*7dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", 557*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), 558*7dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1", 559*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0), 560*7dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", 561*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), 562*7dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2", 563*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0), 564*7dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", 565*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), 566*7dd05578SSam Protsenko GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", 567*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), 568*7dd05578SSam Protsenko GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", 569*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), 570*7dd05578SSam Protsenko GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", 571*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), 572*7dd05578SSam Protsenko GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", 573*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), 574*7dd05578SSam Protsenko GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", 575*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), 576*7dd05578SSam Protsenko GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", 577*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), 578*7dd05578SSam Protsenko GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", 579*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), 580*7dd05578SSam Protsenko GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", 581*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), 582*7dd05578SSam Protsenko GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", 583*7dd05578SSam Protsenko "mout_peri_bus_user", 584*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), 585*7dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", 586*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), 587*7dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", 588*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), 589*7dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", 590*7dd05578SSam Protsenko "mout_peri_bus_user", 591*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), 592*7dd05578SSam Protsenko GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", 593*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), 594*7dd05578SSam Protsenko GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", 595*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), 596*7dd05578SSam Protsenko GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", 597*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0), 598*7dd05578SSam Protsenko GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", 599*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0), 600*7dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk", 601*7dd05578SSam Protsenko "mout_peri_bus_user", 602*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, 0, 0), 603*7dd05578SSam Protsenko }; 604*7dd05578SSam Protsenko 605*7dd05578SSam Protsenko static const struct samsung_cmu_info peri_cmu_info __initconst = { 606*7dd05578SSam Protsenko .mux_clks = peri_mux_clks, 607*7dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 608*7dd05578SSam Protsenko .div_clks = peri_div_clks, 609*7dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(peri_div_clks), 610*7dd05578SSam Protsenko .gate_clks = peri_gate_clks, 611*7dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 612*7dd05578SSam Protsenko .nr_clk_ids = PERI_NR_CLK, 613*7dd05578SSam Protsenko .clk_regs = peri_clk_regs, 614*7dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 615*7dd05578SSam Protsenko .clk_name = "dout_peri_bus", 616*7dd05578SSam Protsenko }; 617*7dd05578SSam Protsenko 618*7dd05578SSam Protsenko /* ---- CMU_CORE ------------------------------------------------------------ */ 619*7dd05578SSam Protsenko 620*7dd05578SSam Protsenko /* Register Offset definitions for CMU_CORE (0x12000000) */ 621*7dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 622*7dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610 623*7dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 624*7dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630 625*7dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 626*7dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 627*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 628*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 629*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 630*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec 631*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 632*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c 633*7dd05578SSam Protsenko 634*7dd05578SSam Protsenko static const unsigned long core_clk_regs[] __initconst = { 635*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 636*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 637*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 638*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 639*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 640*7dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 641*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 642*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 643*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 644*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 645*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 646*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 647*7dd05578SSam Protsenko }; 648*7dd05578SSam Protsenko 649*7dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_CORE */ 650*7dd05578SSam Protsenko PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; 651*7dd05578SSam Protsenko PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; 652*7dd05578SSam Protsenko PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" }; 653*7dd05578SSam Protsenko PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" }; 654*7dd05578SSam Protsenko PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; 655*7dd05578SSam Protsenko 656*7dd05578SSam Protsenko static const struct samsung_mux_clock core_mux_clks[] __initconst = { 657*7dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 658*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 659*7dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, 660*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), 661*7dd05578SSam Protsenko MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", 662*7dd05578SSam Protsenko mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 663*7dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 664*7dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p, 665*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1), 666*7dd05578SSam Protsenko MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, 667*7dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), 668*7dd05578SSam Protsenko }; 669*7dd05578SSam Protsenko 670*7dd05578SSam Protsenko static const struct samsung_div_clock core_div_clks[] __initconst = { 671*7dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 672*7dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 673*7dd05578SSam Protsenko }; 674*7dd05578SSam Protsenko 675*7dd05578SSam Protsenko static const struct samsung_gate_clock core_gate_clks[] __initconst = { 676*7dd05578SSam Protsenko GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", 677*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, 0, 0), 678*7dd05578SSam Protsenko GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic", 679*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, 0, 0), 680*7dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", 681*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), 682*7dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 683*7dd05578SSam Protsenko "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 684*7dd05578SSam Protsenko 21, CLK_SET_RATE_PARENT, 0), 685*7dd05578SSam Protsenko GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", 686*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), 687*7dd05578SSam Protsenko GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", 688*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), 689*7dd05578SSam Protsenko }; 690*7dd05578SSam Protsenko 691*7dd05578SSam Protsenko static const struct samsung_cmu_info core_cmu_info __initconst = { 692*7dd05578SSam Protsenko .mux_clks = core_mux_clks, 693*7dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 694*7dd05578SSam Protsenko .div_clks = core_div_clks, 695*7dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(core_div_clks), 696*7dd05578SSam Protsenko .gate_clks = core_gate_clks, 697*7dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 698*7dd05578SSam Protsenko .nr_clk_ids = CORE_NR_CLK, 699*7dd05578SSam Protsenko .clk_regs = core_clk_regs, 700*7dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 701*7dd05578SSam Protsenko .clk_name = "dout_core_bus", 702*7dd05578SSam Protsenko }; 703*7dd05578SSam Protsenko 704*7dd05578SSam Protsenko /* ---- CMU_DPU ------------------------------------------------------------- */ 705*7dd05578SSam Protsenko 706*7dd05578SSam Protsenko /* Register Offset definitions for CMU_DPU (0x13000000) */ 707*7dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600 708*7dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 709*7dd05578SSam Protsenko #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004 710*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010 711*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014 712*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018 713*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028 714*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c 715*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038 716*7dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c 717*7dd05578SSam Protsenko 718*7dd05578SSam Protsenko static const unsigned long dpu_clk_regs[] __initconst = { 719*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 720*7dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 721*7dd05578SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 722*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 723*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 724*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 725*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 726*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 727*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 728*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 729*7dd05578SSam Protsenko }; 730*7dd05578SSam Protsenko 731*7dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_CORE */ 732*7dd05578SSam Protsenko PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" }; 733*7dd05578SSam Protsenko 734*7dd05578SSam Protsenko static const struct samsung_mux_clock dpu_mux_clks[] __initconst = { 735*7dd05578SSam Protsenko MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p, 736*7dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1), 737*7dd05578SSam Protsenko }; 738*7dd05578SSam Protsenko 739*7dd05578SSam Protsenko static const struct samsung_div_clock dpu_div_clks[] __initconst = { 740*7dd05578SSam Protsenko DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user", 741*7dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), 742*7dd05578SSam Protsenko }; 743*7dd05578SSam Protsenko 744*7dd05578SSam Protsenko static const struct samsung_gate_clock dpu_gate_clks[] __initconst = { 745*7dd05578SSam Protsenko GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk", 746*7dd05578SSam Protsenko "dout_dpu_busp", CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, 0, 0), 747*7dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user", 748*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0), 749*7dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user", 750*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0), 751*7dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user", 752*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0), 753*7dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user", 754*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0), 755*7dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp", 756*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0), 757*7dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user", 758*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0), 759*7dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp", 760*7dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0), 761*7dd05578SSam Protsenko }; 762*7dd05578SSam Protsenko 763*7dd05578SSam Protsenko static const struct samsung_cmu_info dpu_cmu_info __initconst = { 764*7dd05578SSam Protsenko .mux_clks = dpu_mux_clks, 765*7dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks), 766*7dd05578SSam Protsenko .div_clks = dpu_div_clks, 767*7dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(dpu_div_clks), 768*7dd05578SSam Protsenko .gate_clks = dpu_gate_clks, 769*7dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), 770*7dd05578SSam Protsenko .nr_clk_ids = DPU_NR_CLK, 771*7dd05578SSam Protsenko .clk_regs = dpu_clk_regs, 772*7dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), 773*7dd05578SSam Protsenko .clk_name = "dout_dpu", 774*7dd05578SSam Protsenko }; 775*7dd05578SSam Protsenko 776*7dd05578SSam Protsenko /* ---- platform_driver ----------------------------------------------------- */ 777*7dd05578SSam Protsenko 778*7dd05578SSam Protsenko static int __init exynos850_cmu_probe(struct platform_device *pdev) 779*7dd05578SSam Protsenko { 780*7dd05578SSam Protsenko const struct samsung_cmu_info *info; 781*7dd05578SSam Protsenko struct device *dev = &pdev->dev; 782*7dd05578SSam Protsenko struct device_node *np = dev->of_node; 783*7dd05578SSam Protsenko 784*7dd05578SSam Protsenko info = of_device_get_match_data(dev); 785*7dd05578SSam Protsenko exynos850_init_clocks(np, info->clk_regs, info->nr_clk_regs); 786*7dd05578SSam Protsenko samsung_cmu_register_one(np, info); 787*7dd05578SSam Protsenko 788*7dd05578SSam Protsenko /* Keep bus clock running, so it's possible to access CMU registers */ 789*7dd05578SSam Protsenko if (info->clk_name) { 790*7dd05578SSam Protsenko struct clk *bus_clk; 791*7dd05578SSam Protsenko 792*7dd05578SSam Protsenko bus_clk = clk_get(dev, info->clk_name); 793*7dd05578SSam Protsenko if (IS_ERR(bus_clk)) { 794*7dd05578SSam Protsenko pr_err("%s: could not find bus clock %s; err = %ld\n", 795*7dd05578SSam Protsenko __func__, info->clk_name, PTR_ERR(bus_clk)); 796*7dd05578SSam Protsenko } else { 797*7dd05578SSam Protsenko clk_prepare_enable(bus_clk); 798*7dd05578SSam Protsenko } 799*7dd05578SSam Protsenko } 800*7dd05578SSam Protsenko 801*7dd05578SSam Protsenko return 0; 802*7dd05578SSam Protsenko } 803*7dd05578SSam Protsenko 804*7dd05578SSam Protsenko /* CMUs which belong to Power Domains and need runtime PM to be implemented */ 805*7dd05578SSam Protsenko static const struct of_device_id exynos850_cmu_of_match[] = { 806*7dd05578SSam Protsenko { 807*7dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-hsi", 808*7dd05578SSam Protsenko .data = &hsi_cmu_info, 809*7dd05578SSam Protsenko }, { 810*7dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-peri", 811*7dd05578SSam Protsenko .data = &peri_cmu_info, 812*7dd05578SSam Protsenko }, { 813*7dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-core", 814*7dd05578SSam Protsenko .data = &core_cmu_info, 815*7dd05578SSam Protsenko }, { 816*7dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-dpu", 817*7dd05578SSam Protsenko .data = &dpu_cmu_info, 818*7dd05578SSam Protsenko }, { 819*7dd05578SSam Protsenko }, 820*7dd05578SSam Protsenko }; 821*7dd05578SSam Protsenko 822*7dd05578SSam Protsenko static struct platform_driver exynos850_cmu_driver __refdata = { 823*7dd05578SSam Protsenko .driver = { 824*7dd05578SSam Protsenko .name = "exynos850-cmu", 825*7dd05578SSam Protsenko .of_match_table = exynos850_cmu_of_match, 826*7dd05578SSam Protsenko .suppress_bind_attrs = true, 827*7dd05578SSam Protsenko }, 828*7dd05578SSam Protsenko .probe = exynos850_cmu_probe, 829*7dd05578SSam Protsenko }; 830*7dd05578SSam Protsenko 831*7dd05578SSam Protsenko static int __init exynos850_cmu_init(void) 832*7dd05578SSam Protsenko { 833*7dd05578SSam Protsenko return platform_driver_register(&exynos850_cmu_driver); 834*7dd05578SSam Protsenko } 835*7dd05578SSam Protsenko core_initcall(exynos850_cmu_init); 836