17dd05578SSam Protsenko // SPDX-License-Identifier: GPL-2.0-only 27dd05578SSam Protsenko /* 37dd05578SSam Protsenko * Copyright (C) 2021 Linaro Ltd. 47dd05578SSam Protsenko * Author: Sam Protsenko <semen.protsenko@linaro.org> 57dd05578SSam Protsenko * 67dd05578SSam Protsenko * Common Clock Framework support for Exynos850 SoC. 77dd05578SSam Protsenko */ 87dd05578SSam Protsenko 97dd05578SSam Protsenko #include <linux/clk.h> 107dd05578SSam Protsenko #include <linux/clk-provider.h> 117dd05578SSam Protsenko #include <linux/of.h> 127dd05578SSam Protsenko #include <linux/of_address.h> 137dd05578SSam Protsenko #include <linux/of_device.h> 147dd05578SSam Protsenko #include <linux/platform_device.h> 157dd05578SSam Protsenko 167dd05578SSam Protsenko #include <dt-bindings/clock/exynos850.h> 177dd05578SSam Protsenko 187dd05578SSam Protsenko #include "clk.h" 197dd05578SSam Protsenko 207dd05578SSam Protsenko /* Gate register bits */ 217dd05578SSam Protsenko #define GATE_MANUAL BIT(20) 227dd05578SSam Protsenko #define GATE_ENABLE_HWACG BIT(28) 237dd05578SSam Protsenko 247dd05578SSam Protsenko /* Gate register offsets range */ 257dd05578SSam Protsenko #define GATE_OFF_START 0x2000 267dd05578SSam Protsenko #define GATE_OFF_END 0x2fff 277dd05578SSam Protsenko 287dd05578SSam Protsenko /** 297dd05578SSam Protsenko * exynos850_init_clocks - Set clocks initial configuration 307dd05578SSam Protsenko * @np: CMU device tree node with "reg" property (CMU addr) 317dd05578SSam Protsenko * @reg_offs: Register offsets array for clocks to init 327dd05578SSam Protsenko * @reg_offs_len: Number of register offsets in reg_offs array 337dd05578SSam Protsenko * 347dd05578SSam Protsenko * Set manual control mode for all gate clocks. 357dd05578SSam Protsenko */ 367dd05578SSam Protsenko static void __init exynos850_init_clocks(struct device_node *np, 377dd05578SSam Protsenko const unsigned long *reg_offs, size_t reg_offs_len) 387dd05578SSam Protsenko { 397dd05578SSam Protsenko void __iomem *reg_base; 407dd05578SSam Protsenko size_t i; 417dd05578SSam Protsenko 427dd05578SSam Protsenko reg_base = of_iomap(np, 0); 437dd05578SSam Protsenko if (!reg_base) 447dd05578SSam Protsenko panic("%s: failed to map registers\n", __func__); 457dd05578SSam Protsenko 467dd05578SSam Protsenko for (i = 0; i < reg_offs_len; ++i) { 477dd05578SSam Protsenko void __iomem *reg = reg_base + reg_offs[i]; 487dd05578SSam Protsenko u32 val; 497dd05578SSam Protsenko 507dd05578SSam Protsenko /* Modify only gate clock registers */ 517dd05578SSam Protsenko if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END) 527dd05578SSam Protsenko continue; 537dd05578SSam Protsenko 547dd05578SSam Protsenko val = readl(reg); 557dd05578SSam Protsenko val |= GATE_MANUAL; 567dd05578SSam Protsenko val &= ~GATE_ENABLE_HWACG; 577dd05578SSam Protsenko writel(val, reg); 587dd05578SSam Protsenko } 597dd05578SSam Protsenko 607dd05578SSam Protsenko iounmap(reg_base); 617dd05578SSam Protsenko } 627dd05578SSam Protsenko 637dd05578SSam Protsenko /* ---- CMU_TOP ------------------------------------------------------------- */ 647dd05578SSam Protsenko 657dd05578SSam Protsenko /* Register Offset definitions for CMU_TOP (0x120e0000) */ 667dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_MMC 0x0000 677dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED0 0x0004 687dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED1 0x0008 697dd05578SSam Protsenko #define PLL_CON0_PLL_MMC 0x0100 707dd05578SSam Protsenko #define PLL_CON3_PLL_MMC 0x010c 717dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED0 0x0140 727dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED0 0x014c 737dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED1 0x0180 747dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED1 0x018c 75*579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000 767dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 777dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 787dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c 797dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 807dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 817dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c 827dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 837dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 847dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 857dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 867dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 87*579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c 887dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 897dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 907dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 917dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c 927dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_DPU 0x1840 937dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 947dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c 957dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 967dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c 977dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 987dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 997dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c 1007dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 1017dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 1027dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 1037dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c 1047dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 105*579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008 1067dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 1077dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 1087dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 1097dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 1107dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c 1117dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 1127dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 1137dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c 1147dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 1157dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 1167dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 1177dd05578SSam Protsenko 1187dd05578SSam Protsenko static const unsigned long top_clk_regs[] __initconst = { 1197dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, 1207dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, 1217dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, 1227dd05578SSam Protsenko PLL_CON0_PLL_MMC, 1237dd05578SSam Protsenko PLL_CON3_PLL_MMC, 1247dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 1257dd05578SSam Protsenko PLL_CON3_PLL_SHARED0, 1267dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 1277dd05578SSam Protsenko PLL_CON3_PLL_SHARED1, 128*579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 1297dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 1307dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 1317dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 1327dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 1337dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 1347dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 1357dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 1367dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 1377dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 1387dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 1397dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 140*579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_APM_BUS, 1417dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 1427dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 1437dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 1447dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 1457dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 1467dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 1477dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 1487dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 1497dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 1507dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 1517dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 1527dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 1537dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 1547dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 1557dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 1567dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 1577dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 158*579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 1597dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 1607dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 1617dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 1627dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 1637dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 1647dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 1657dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 1667dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 1677dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 1687dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 1697dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 1707dd05578SSam Protsenko }; 1717dd05578SSam Protsenko 1727dd05578SSam Protsenko /* 1737dd05578SSam Protsenko * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set 1747dd05578SSam Protsenko * for those PLLs by default, so set_rate operation would fail. 1757dd05578SSam Protsenko */ 1767dd05578SSam Protsenko static const struct samsung_pll_clock top_pll_clks[] __initconst = { 1777dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 1787dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 1797dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 1807dd05578SSam Protsenko NULL), 1817dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 1827dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 1837dd05578SSam Protsenko NULL), 1847dd05578SSam Protsenko PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 1857dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 1867dd05578SSam Protsenko }; 1877dd05578SSam Protsenko 1887dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP */ 1897dd05578SSam Protsenko PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 1907dd05578SSam Protsenko PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 1917dd05578SSam Protsenko PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 192*579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */ 193*579839a9SSam Protsenko PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" }; 1947dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 1957dd05578SSam Protsenko PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", 1967dd05578SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 1977dd05578SSam Protsenko PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 1987dd05578SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 1997dd05578SSam Protsenko PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", 2007dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 2017dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 2027dd05578SSam Protsenko "oscclk", "oscclk" }; 2037dd05578SSam Protsenko PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", 2047dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 2057dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ 2067dd05578SSam Protsenko PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 2077dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", 2087dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 2097dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 2107dd05578SSam Protsenko "oscclk", "oscclk" }; 2117dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4", 2127dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2137dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 2147dd05578SSam Protsenko PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 2157dd05578SSam Protsenko PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4", 2167dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2177dd05578SSam Protsenko PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4", 2187dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2197dd05578SSam Protsenko 2207dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ 2217dd05578SSam Protsenko PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3", 2227dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 2237dd05578SSam Protsenko 2247dd05578SSam Protsenko static const struct samsung_mux_clock top_mux_clks[] __initconst = { 2257dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 2267dd05578SSam Protsenko MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 2277dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 4, 1), 2287dd05578SSam Protsenko MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 2297dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 4, 1), 2307dd05578SSam Protsenko MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 2317dd05578SSam Protsenko PLL_CON0_PLL_MMC, 4, 1), 2327dd05578SSam Protsenko 233*579839a9SSam Protsenko /* APM */ 234*579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", 235*579839a9SSam Protsenko mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), 236*579839a9SSam Protsenko 2377dd05578SSam Protsenko /* CORE */ 2387dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 2397dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 2407dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 2417dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 2427dd05578SSam Protsenko MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, 2437dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), 2447dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, 2457dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), 2467dd05578SSam Protsenko 2477dd05578SSam Protsenko /* DPU */ 2487dd05578SSam Protsenko MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, 2497dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), 2507dd05578SSam Protsenko 2517dd05578SSam Protsenko /* HSI */ 2527dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, 2537dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), 2547dd05578SSam Protsenko MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, 2557dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), 2567dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, 2577dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), 2587dd05578SSam Protsenko 2597dd05578SSam Protsenko /* PERI */ 2607dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 2617dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 2627dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, 2637dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), 2647dd05578SSam Protsenko MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, 2657dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), 2667dd05578SSam Protsenko }; 2677dd05578SSam Protsenko 2687dd05578SSam Protsenko static const struct samsung_div_clock top_div_clks[] __initconst = { 2697dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 2707dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 2717dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 2727dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 2737dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 2747dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 2757dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 2767dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 2777dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 2787dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 2797dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 2807dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 2817dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 2827dd05578SSam Protsenko 283*579839a9SSam Protsenko /* APM */ 284*579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", 285*579839a9SSam Protsenko "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), 286*579839a9SSam Protsenko 2877dd05578SSam Protsenko /* CORE */ 2887dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 2897dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 2907dd05578SSam Protsenko DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 2917dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), 2927dd05578SSam Protsenko DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", 2937dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), 2947dd05578SSam Protsenko DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", 2957dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), 2967dd05578SSam Protsenko 2977dd05578SSam Protsenko /* DPU */ 2987dd05578SSam Protsenko DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", 2997dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 0, 4), 3007dd05578SSam Protsenko 3017dd05578SSam Protsenko /* HSI */ 3027dd05578SSam Protsenko DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", 3037dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), 3047dd05578SSam Protsenko DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", 3057dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), 3067dd05578SSam Protsenko DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", 3077dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), 3087dd05578SSam Protsenko 3097dd05578SSam Protsenko /* PERI */ 3107dd05578SSam Protsenko DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 3117dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 3127dd05578SSam Protsenko DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", 3137dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), 3147dd05578SSam Protsenko DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", 3157dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), 3167dd05578SSam Protsenko }; 3177dd05578SSam Protsenko 3187dd05578SSam Protsenko static const struct samsung_gate_clock top_gate_clks[] __initconst = { 3197dd05578SSam Protsenko /* CORE */ 3207dd05578SSam Protsenko GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 3217dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 3227dd05578SSam Protsenko GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 3237dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 3247dd05578SSam Protsenko GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", 3257dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), 3267dd05578SSam Protsenko GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", 3277dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), 3287dd05578SSam Protsenko 329*579839a9SSam Protsenko /* APM */ 330*579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", 331*579839a9SSam Protsenko "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0), 332*579839a9SSam Protsenko 3337dd05578SSam Protsenko /* DPU */ 3347dd05578SSam Protsenko GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", 3357dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), 3367dd05578SSam Protsenko 3377dd05578SSam Protsenko /* HSI */ 3387dd05578SSam Protsenko GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", 3397dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), 3407dd05578SSam Protsenko GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", 3417dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), 3427dd05578SSam Protsenko GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", 3437dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), 3447dd05578SSam Protsenko 3457dd05578SSam Protsenko /* PERI */ 3467dd05578SSam Protsenko GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 3477dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 3487dd05578SSam Protsenko GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", 3497dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), 3507dd05578SSam Protsenko GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", 3517dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), 3527dd05578SSam Protsenko }; 3537dd05578SSam Protsenko 3547dd05578SSam Protsenko static const struct samsung_cmu_info top_cmu_info __initconst = { 3557dd05578SSam Protsenko .pll_clks = top_pll_clks, 3567dd05578SSam Protsenko .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 3577dd05578SSam Protsenko .mux_clks = top_mux_clks, 3587dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 3597dd05578SSam Protsenko .div_clks = top_div_clks, 3607dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(top_div_clks), 3617dd05578SSam Protsenko .gate_clks = top_gate_clks, 3627dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 3637dd05578SSam Protsenko .nr_clk_ids = TOP_NR_CLK, 3647dd05578SSam Protsenko .clk_regs = top_clk_regs, 3657dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 3667dd05578SSam Protsenko }; 3677dd05578SSam Protsenko 3687dd05578SSam Protsenko static void __init exynos850_cmu_top_init(struct device_node *np) 3697dd05578SSam Protsenko { 3707dd05578SSam Protsenko exynos850_init_clocks(np, top_clk_regs, ARRAY_SIZE(top_clk_regs)); 3717dd05578SSam Protsenko samsung_cmu_register_one(np, &top_cmu_info); 3727dd05578SSam Protsenko } 3737dd05578SSam Protsenko 3747dd05578SSam Protsenko CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", 3757dd05578SSam Protsenko exynos850_cmu_top_init); 3767dd05578SSam Protsenko 377*579839a9SSam Protsenko /* ---- CMU_APM ------------------------------------------------------------- */ 378*579839a9SSam Protsenko 379*579839a9SSam Protsenko /* Register Offset definitions for CMU_APM (0x11800000) */ 380*579839a9SSam Protsenko #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600 381*579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610 382*579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620 383*579839a9SSam Protsenko #define PLL_CON0_MUX_DLL_USER 0x0630 384*579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000 385*579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004 386*579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008 387*579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800 388*579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804 389*579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808 390*579839a9SSam Protsenko #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 391*579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014 392*579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024 393*579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028 394*579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034 395*579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038 396*579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc 397*579839a9SSam Protsenko 398*579839a9SSam Protsenko static const unsigned long apm_clk_regs[] __initconst = { 399*579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 400*579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 401*579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 402*579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 403*579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 404*579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 405*579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 406*579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 407*579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 408*579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 409*579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 410*579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 411*579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 412*579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 413*579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 414*579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 415*579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 416*579839a9SSam Protsenko }; 417*579839a9SSam Protsenko 418*579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_APM */ 419*579839a9SSam Protsenko PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" }; 420*579839a9SSam Protsenko PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" }; 421*579839a9SSam Protsenko PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" }; 422*579839a9SSam Protsenko PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" }; 423*579839a9SSam Protsenko PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" }; 424*579839a9SSam Protsenko PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user", 425*579839a9SSam Protsenko "mout_dll_user", "oscclk_rco_apm" }; 426*579839a9SSam Protsenko PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" }; 427*579839a9SSam Protsenko 428*579839a9SSam Protsenko static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 429*579839a9SSam Protsenko FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000), 430*579839a9SSam Protsenko FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000), 431*579839a9SSam Protsenko FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000), 432*579839a9SSam Protsenko FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000), 433*579839a9SSam Protsenko }; 434*579839a9SSam Protsenko 435*579839a9SSam Protsenko static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 436*579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p, 437*579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1), 438*579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user", 439*579839a9SSam Protsenko mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1), 440*579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p, 441*579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1), 442*579839a9SSam Protsenko MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p, 443*579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 4, 1), 444*579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus", 445*579839a9SSam Protsenko mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1), 446*579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p, 447*579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2), 448*579839a9SSam Protsenko MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p, 449*579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1), 450*579839a9SSam Protsenko }; 451*579839a9SSam Protsenko 452*579839a9SSam Protsenko static const struct samsung_div_clock apm_div_clks[] __initconst = { 453*579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus", 454*579839a9SSam Protsenko "gout_clkcmu_chub_bus", 455*579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3), 456*579839a9SSam Protsenko DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus", 457*579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3), 458*579839a9SSam Protsenko DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus", 459*579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3), 460*579839a9SSam Protsenko }; 461*579839a9SSam Protsenko 462*579839a9SSam Protsenko static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 463*579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus", 464*579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0), 465*579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus", 466*579839a9SSam Protsenko "mout_clkcmu_chub_bus", 467*579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0), 468*579839a9SSam Protsenko GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus", 469*579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0), 470*579839a9SSam Protsenko GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus", 471*579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0), 472*579839a9SSam Protsenko GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus", 473*579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0), 474*579839a9SSam Protsenko GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c", 475*579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0), 476*579839a9SSam Protsenko GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus", 477*579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0), 478*579839a9SSam Protsenko }; 479*579839a9SSam Protsenko 480*579839a9SSam Protsenko static const struct samsung_cmu_info apm_cmu_info __initconst = { 481*579839a9SSam Protsenko .mux_clks = apm_mux_clks, 482*579839a9SSam Protsenko .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 483*579839a9SSam Protsenko .div_clks = apm_div_clks, 484*579839a9SSam Protsenko .nr_div_clks = ARRAY_SIZE(apm_div_clks), 485*579839a9SSam Protsenko .gate_clks = apm_gate_clks, 486*579839a9SSam Protsenko .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 487*579839a9SSam Protsenko .fixed_clks = apm_fixed_clks, 488*579839a9SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 489*579839a9SSam Protsenko .nr_clk_ids = APM_NR_CLK, 490*579839a9SSam Protsenko .clk_regs = apm_clk_regs, 491*579839a9SSam Protsenko .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 492*579839a9SSam Protsenko .clk_name = "dout_clkcmu_apm_bus", 493*579839a9SSam Protsenko }; 494*579839a9SSam Protsenko 4957dd05578SSam Protsenko /* ---- CMU_HSI ------------------------------------------------------------- */ 4967dd05578SSam Protsenko 4977dd05578SSam Protsenko /* Register Offset definitions for CMU_HSI (0x13400000) */ 4987dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 4997dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 5007dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 5017dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 5027dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 5037dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c 5047dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 5057dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 5067dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 5077dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 5087dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 5097dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c 5107dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 5117dd05578SSam Protsenko 5127dd05578SSam Protsenko static const unsigned long hsi_clk_regs[] __initconst = { 5137dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 5147dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 5157dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 5167dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 5177dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 5187dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 5197dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 5207dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 5217dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 5227dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 5237dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 5247dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 5257dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 5267dd05578SSam Protsenko }; 5277dd05578SSam Protsenko 5287dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_PERI */ 5297dd05578SSam Protsenko PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" }; 5307dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" }; 5317dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" }; 5327dd05578SSam Protsenko PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" }; 5337dd05578SSam Protsenko 5347dd05578SSam Protsenko static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { 5357dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, 5367dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), 5377dd05578SSam Protsenko MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", 5387dd05578SSam Protsenko mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 5397dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 5407dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", 5417dd05578SSam Protsenko mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 5427dd05578SSam Protsenko 4, 1), 5437dd05578SSam Protsenko MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p, 5447dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1), 5457dd05578SSam Protsenko }; 5467dd05578SSam Protsenko 5477dd05578SSam Protsenko static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { 5487dd05578SSam Protsenko GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", 5497dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), 5507dd05578SSam Protsenko GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", 5517dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), 5527dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk", 5537dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), 5547dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user", 5557dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, 0, 0), 5567dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", 5577dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), 5587dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 5597dd05578SSam Protsenko "mout_hsi_mmc_card_user", 5607dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), 5617dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", 5627dd05578SSam Protsenko "mout_hsi_bus_user", 5637dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), 5647dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", 5657dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), 5667dd05578SSam Protsenko GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", 5677dd05578SSam Protsenko "mout_hsi_bus_user", 5687dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), 5697dd05578SSam Protsenko }; 5707dd05578SSam Protsenko 5717dd05578SSam Protsenko static const struct samsung_cmu_info hsi_cmu_info __initconst = { 5727dd05578SSam Protsenko .mux_clks = hsi_mux_clks, 5737dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), 5747dd05578SSam Protsenko .gate_clks = hsi_gate_clks, 5757dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), 5767dd05578SSam Protsenko .nr_clk_ids = HSI_NR_CLK, 5777dd05578SSam Protsenko .clk_regs = hsi_clk_regs, 5787dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), 5797dd05578SSam Protsenko .clk_name = "dout_hsi_bus", 5807dd05578SSam Protsenko }; 5817dd05578SSam Protsenko 5827dd05578SSam Protsenko /* ---- CMU_PERI ------------------------------------------------------------ */ 5837dd05578SSam Protsenko 5847dd05578SSam Protsenko /* Register Offset definitions for CMU_PERI (0x10030000) */ 5857dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 5867dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610 5877dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620 5887dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 5897dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800 5907dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804 5917dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808 5927dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c 5937dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c 5947dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010 5957dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014 5967dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020 5977dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024 5987dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 5997dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c 6007dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030 6017dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034 6027dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038 6037dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c 6047dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040 6057dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044 6067dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048 6077dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c 6087dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050 6097dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054 6107dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c 6117dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064 6127dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c 6137dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0 6147dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4 6157dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 6167dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac 6177dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0 6187dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4 6197dd05578SSam Protsenko 6207dd05578SSam Protsenko static const unsigned long peri_clk_regs[] __initconst = { 6217dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 6227dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 6237dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 6247dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 6257dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 6267dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 6277dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 6287dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 6297dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 6307dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 6317dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 6327dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 6337dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 6347dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 6357dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 6367dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 6377dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 6387dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 6397dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 6407dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 6417dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 6427dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 6437dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 6447dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 6457dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 6467dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 6477dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 6487dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 6497dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 6507dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 6517dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 6527dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 6537dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 6547dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 6557dd05578SSam Protsenko }; 6567dd05578SSam Protsenko 6577dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_PERI */ 6587dd05578SSam Protsenko PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; 6597dd05578SSam Protsenko PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" }; 6607dd05578SSam Protsenko PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" }; 6617dd05578SSam Protsenko PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" }; 6627dd05578SSam Protsenko 6637dd05578SSam Protsenko static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 6647dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 6657dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 6667dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", 6677dd05578SSam Protsenko mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), 6687dd05578SSam Protsenko MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", 6697dd05578SSam Protsenko mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), 6707dd05578SSam Protsenko MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, 6717dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), 6727dd05578SSam Protsenko }; 6737dd05578SSam Protsenko 6747dd05578SSam Protsenko static const struct samsung_div_clock peri_div_clks[] __initconst = { 6757dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0", 6767dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5), 6777dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1", 6787dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), 6797dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", 6807dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), 6817dd05578SSam Protsenko DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", 6827dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), 6837dd05578SSam Protsenko }; 6847dd05578SSam Protsenko 6857dd05578SSam Protsenko static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 6867dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user", 6877dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0), 6887dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user", 6897dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0), 6907dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user", 6917dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0), 6927dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0", 6937dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0), 6947dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", 6957dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), 6967dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1", 6977dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0), 6987dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", 6997dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), 7007dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2", 7017dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0), 7027dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", 7037dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), 7047dd05578SSam Protsenko GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", 7057dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), 7067dd05578SSam Protsenko GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", 7077dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), 7087dd05578SSam Protsenko GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", 7097dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), 7107dd05578SSam Protsenko GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", 7117dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), 7127dd05578SSam Protsenko GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", 7137dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), 7147dd05578SSam Protsenko GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", 7157dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), 7167dd05578SSam Protsenko GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", 7177dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), 7187dd05578SSam Protsenko GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", 7197dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), 7207dd05578SSam Protsenko GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", 7217dd05578SSam Protsenko "mout_peri_bus_user", 7227dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), 7237dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", 7247dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), 7257dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", 7267dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), 7277dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", 7287dd05578SSam Protsenko "mout_peri_bus_user", 7297dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), 7307dd05578SSam Protsenko GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", 7317dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), 7327dd05578SSam Protsenko GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", 7337dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), 7347dd05578SSam Protsenko GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", 7357dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0), 7367dd05578SSam Protsenko GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", 7377dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0), 7387dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk", 7397dd05578SSam Protsenko "mout_peri_bus_user", 7407dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, 0, 0), 7417dd05578SSam Protsenko }; 7427dd05578SSam Protsenko 7437dd05578SSam Protsenko static const struct samsung_cmu_info peri_cmu_info __initconst = { 7447dd05578SSam Protsenko .mux_clks = peri_mux_clks, 7457dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 7467dd05578SSam Protsenko .div_clks = peri_div_clks, 7477dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(peri_div_clks), 7487dd05578SSam Protsenko .gate_clks = peri_gate_clks, 7497dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 7507dd05578SSam Protsenko .nr_clk_ids = PERI_NR_CLK, 7517dd05578SSam Protsenko .clk_regs = peri_clk_regs, 7527dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 7537dd05578SSam Protsenko .clk_name = "dout_peri_bus", 7547dd05578SSam Protsenko }; 7557dd05578SSam Protsenko 7567dd05578SSam Protsenko /* ---- CMU_CORE ------------------------------------------------------------ */ 7577dd05578SSam Protsenko 7587dd05578SSam Protsenko /* Register Offset definitions for CMU_CORE (0x12000000) */ 7597dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 7607dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610 7617dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 7627dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630 7637dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 7647dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 7657dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 7667dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 7677dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 7687dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec 7697dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 7707dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c 7717dd05578SSam Protsenko 7727dd05578SSam Protsenko static const unsigned long core_clk_regs[] __initconst = { 7737dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 7747dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 7757dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 7767dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 7777dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 7787dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 7797dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 7807dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 7817dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 7827dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 7837dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 7847dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 7857dd05578SSam Protsenko }; 7867dd05578SSam Protsenko 7877dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_CORE */ 7887dd05578SSam Protsenko PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; 7897dd05578SSam Protsenko PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; 7907dd05578SSam Protsenko PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" }; 7917dd05578SSam Protsenko PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" }; 7927dd05578SSam Protsenko PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; 7937dd05578SSam Protsenko 7947dd05578SSam Protsenko static const struct samsung_mux_clock core_mux_clks[] __initconst = { 7957dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 7967dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 7977dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, 7987dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), 7997dd05578SSam Protsenko MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", 8007dd05578SSam Protsenko mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 8017dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 8027dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p, 8037dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1), 8047dd05578SSam Protsenko MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, 8057dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), 8067dd05578SSam Protsenko }; 8077dd05578SSam Protsenko 8087dd05578SSam Protsenko static const struct samsung_div_clock core_div_clks[] __initconst = { 8097dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 8107dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 8117dd05578SSam Protsenko }; 8127dd05578SSam Protsenko 8137dd05578SSam Protsenko static const struct samsung_gate_clock core_gate_clks[] __initconst = { 8147dd05578SSam Protsenko GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", 8157dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, 0, 0), 8167dd05578SSam Protsenko GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic", 8177dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, 0, 0), 8187dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", 8197dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), 8207dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 8217dd05578SSam Protsenko "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 8227dd05578SSam Protsenko 21, CLK_SET_RATE_PARENT, 0), 8237dd05578SSam Protsenko GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", 8247dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), 8257dd05578SSam Protsenko GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", 8267dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), 8277dd05578SSam Protsenko }; 8287dd05578SSam Protsenko 8297dd05578SSam Protsenko static const struct samsung_cmu_info core_cmu_info __initconst = { 8307dd05578SSam Protsenko .mux_clks = core_mux_clks, 8317dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 8327dd05578SSam Protsenko .div_clks = core_div_clks, 8337dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(core_div_clks), 8347dd05578SSam Protsenko .gate_clks = core_gate_clks, 8357dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 8367dd05578SSam Protsenko .nr_clk_ids = CORE_NR_CLK, 8377dd05578SSam Protsenko .clk_regs = core_clk_regs, 8387dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 8397dd05578SSam Protsenko .clk_name = "dout_core_bus", 8407dd05578SSam Protsenko }; 8417dd05578SSam Protsenko 8427dd05578SSam Protsenko /* ---- CMU_DPU ------------------------------------------------------------- */ 8437dd05578SSam Protsenko 8447dd05578SSam Protsenko /* Register Offset definitions for CMU_DPU (0x13000000) */ 8457dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600 8467dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 8477dd05578SSam Protsenko #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004 8487dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010 8497dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014 8507dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018 8517dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028 8527dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c 8537dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038 8547dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c 8557dd05578SSam Protsenko 8567dd05578SSam Protsenko static const unsigned long dpu_clk_regs[] __initconst = { 8577dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 8587dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 8597dd05578SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 8607dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 8617dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 8627dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 8637dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 8647dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 8657dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 8667dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 8677dd05578SSam Protsenko }; 8687dd05578SSam Protsenko 8697dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_CORE */ 8707dd05578SSam Protsenko PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" }; 8717dd05578SSam Protsenko 8727dd05578SSam Protsenko static const struct samsung_mux_clock dpu_mux_clks[] __initconst = { 8737dd05578SSam Protsenko MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p, 8747dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1), 8757dd05578SSam Protsenko }; 8767dd05578SSam Protsenko 8777dd05578SSam Protsenko static const struct samsung_div_clock dpu_div_clks[] __initconst = { 8787dd05578SSam Protsenko DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user", 8797dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), 8807dd05578SSam Protsenko }; 8817dd05578SSam Protsenko 8827dd05578SSam Protsenko static const struct samsung_gate_clock dpu_gate_clks[] __initconst = { 8837dd05578SSam Protsenko GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk", 8847dd05578SSam Protsenko "dout_dpu_busp", CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, 0, 0), 8857dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user", 8867dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0), 8877dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user", 8887dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0), 8897dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user", 8907dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0), 8917dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user", 8927dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0), 8937dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp", 8947dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0), 8957dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user", 8967dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0), 8977dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp", 8987dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0), 8997dd05578SSam Protsenko }; 9007dd05578SSam Protsenko 9017dd05578SSam Protsenko static const struct samsung_cmu_info dpu_cmu_info __initconst = { 9027dd05578SSam Protsenko .mux_clks = dpu_mux_clks, 9037dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks), 9047dd05578SSam Protsenko .div_clks = dpu_div_clks, 9057dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(dpu_div_clks), 9067dd05578SSam Protsenko .gate_clks = dpu_gate_clks, 9077dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), 9087dd05578SSam Protsenko .nr_clk_ids = DPU_NR_CLK, 9097dd05578SSam Protsenko .clk_regs = dpu_clk_regs, 9107dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), 9117dd05578SSam Protsenko .clk_name = "dout_dpu", 9127dd05578SSam Protsenko }; 9137dd05578SSam Protsenko 9147dd05578SSam Protsenko /* ---- platform_driver ----------------------------------------------------- */ 9157dd05578SSam Protsenko 9167dd05578SSam Protsenko static int __init exynos850_cmu_probe(struct platform_device *pdev) 9177dd05578SSam Protsenko { 9187dd05578SSam Protsenko const struct samsung_cmu_info *info; 9197dd05578SSam Protsenko struct device *dev = &pdev->dev; 9207dd05578SSam Protsenko struct device_node *np = dev->of_node; 9217dd05578SSam Protsenko 9227dd05578SSam Protsenko info = of_device_get_match_data(dev); 9237dd05578SSam Protsenko exynos850_init_clocks(np, info->clk_regs, info->nr_clk_regs); 9247dd05578SSam Protsenko samsung_cmu_register_one(np, info); 9257dd05578SSam Protsenko 9267dd05578SSam Protsenko /* Keep bus clock running, so it's possible to access CMU registers */ 9277dd05578SSam Protsenko if (info->clk_name) { 9287dd05578SSam Protsenko struct clk *bus_clk; 9297dd05578SSam Protsenko 9307dd05578SSam Protsenko bus_clk = clk_get(dev, info->clk_name); 9317dd05578SSam Protsenko if (IS_ERR(bus_clk)) { 9327dd05578SSam Protsenko pr_err("%s: could not find bus clock %s; err = %ld\n", 9337dd05578SSam Protsenko __func__, info->clk_name, PTR_ERR(bus_clk)); 9347dd05578SSam Protsenko } else { 9357dd05578SSam Protsenko clk_prepare_enable(bus_clk); 9367dd05578SSam Protsenko } 9377dd05578SSam Protsenko } 9387dd05578SSam Protsenko 9397dd05578SSam Protsenko return 0; 9407dd05578SSam Protsenko } 9417dd05578SSam Protsenko 9427dd05578SSam Protsenko static const struct of_device_id exynos850_cmu_of_match[] = { 9437dd05578SSam Protsenko { 944*579839a9SSam Protsenko .compatible = "samsung,exynos850-cmu-apm", 945*579839a9SSam Protsenko .data = &apm_cmu_info, 946*579839a9SSam Protsenko }, { 9477dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-hsi", 9487dd05578SSam Protsenko .data = &hsi_cmu_info, 9497dd05578SSam Protsenko }, { 9507dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-peri", 9517dd05578SSam Protsenko .data = &peri_cmu_info, 9527dd05578SSam Protsenko }, { 9537dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-core", 9547dd05578SSam Protsenko .data = &core_cmu_info, 9557dd05578SSam Protsenko }, { 9567dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-dpu", 9577dd05578SSam Protsenko .data = &dpu_cmu_info, 9587dd05578SSam Protsenko }, { 9597dd05578SSam Protsenko }, 9607dd05578SSam Protsenko }; 9617dd05578SSam Protsenko 9627dd05578SSam Protsenko static struct platform_driver exynos850_cmu_driver __refdata = { 9637dd05578SSam Protsenko .driver = { 9647dd05578SSam Protsenko .name = "exynos850-cmu", 9657dd05578SSam Protsenko .of_match_table = exynos850_cmu_of_match, 9667dd05578SSam Protsenko .suppress_bind_attrs = true, 9677dd05578SSam Protsenko }, 9687dd05578SSam Protsenko .probe = exynos850_cmu_probe, 9697dd05578SSam Protsenko }; 9707dd05578SSam Protsenko 9717dd05578SSam Protsenko static int __init exynos850_cmu_init(void) 9727dd05578SSam Protsenko { 9737dd05578SSam Protsenko return platform_driver_register(&exynos850_cmu_driver); 9747dd05578SSam Protsenko } 9757dd05578SSam Protsenko core_initcall(exynos850_cmu_init); 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