17dd05578SSam Protsenko // SPDX-License-Identifier: GPL-2.0-only 27dd05578SSam Protsenko /* 37dd05578SSam Protsenko * Copyright (C) 2021 Linaro Ltd. 47dd05578SSam Protsenko * Author: Sam Protsenko <semen.protsenko@linaro.org> 57dd05578SSam Protsenko * 67dd05578SSam Protsenko * Common Clock Framework support for Exynos850 SoC. 77dd05578SSam Protsenko */ 87dd05578SSam Protsenko 97dd05578SSam Protsenko #include <linux/clk.h> 107dd05578SSam Protsenko #include <linux/clk-provider.h> 117dd05578SSam Protsenko #include <linux/of.h> 127dd05578SSam Protsenko #include <linux/of_device.h> 137dd05578SSam Protsenko #include <linux/platform_device.h> 147dd05578SSam Protsenko 157dd05578SSam Protsenko #include <dt-bindings/clock/exynos850.h> 167dd05578SSam Protsenko 177dd05578SSam Protsenko #include "clk.h" 18cfe238e4SDavid Virag #include "clk-exynos-arm64.h" 19bcda841fSSam Protsenko 20*56d62cd4SKrzysztof Kozlowski /* NOTE: Must be equal to the last clock ID increased by one */ 21*56d62cd4SKrzysztof Kozlowski #define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1) 22*56d62cd4SKrzysztof Kozlowski #define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1) 23*56d62cd4SKrzysztof Kozlowski #define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1) 24*56d62cd4SKrzysztof Kozlowski #define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1) 25*56d62cd4SKrzysztof Kozlowski #define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1) 26*56d62cd4SKrzysztof Kozlowski #define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1) 27*56d62cd4SKrzysztof Kozlowski #define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1) 28*56d62cd4SKrzysztof Kozlowski #define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1) 29*56d62cd4SKrzysztof Kozlowski #define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1) 30*56d62cd4SKrzysztof Kozlowski #define CLKS_NR_CORE (CLK_GOUT_SYSREG_CORE_PCLK + 1) 31*56d62cd4SKrzysztof Kozlowski #define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1) 32*56d62cd4SKrzysztof Kozlowski 337dd05578SSam Protsenko /* ---- CMU_TOP ------------------------------------------------------------- */ 347dd05578SSam Protsenko 357dd05578SSam Protsenko /* Register Offset definitions for CMU_TOP (0x120e0000) */ 367dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_MMC 0x0000 377dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED0 0x0004 387dd05578SSam Protsenko #define PLL_LOCKTIME_PLL_SHARED1 0x0008 397dd05578SSam Protsenko #define PLL_CON0_PLL_MMC 0x0100 407dd05578SSam Protsenko #define PLL_CON3_PLL_MMC 0x010c 417dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED0 0x0140 427dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED0 0x014c 437dd05578SSam Protsenko #define PLL_CON0_PLL_SHARED1 0x0180 447dd05578SSam Protsenko #define PLL_CON3_PLL_SHARED1 0x018c 45579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000 46b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004 477dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 487dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 497dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c 507dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 517dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 52e145c765SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038 537dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c 547dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 557dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 56bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048 57bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c 58bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050 59bf3a4c51SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054 607f36d3b6SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058 617f36d3b6SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c 627f36d3b6SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060 637f36d3b6SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064 647dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 657dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 667dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 67579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c 68b73fd95dSSam Protsenko #define CLK_CON_DIV_CLKCMU_AUD 0x1810 697dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 707dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 717dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 727dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c 737dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_DPU 0x1840 74e145c765SSam Protsenko #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844 757dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 767dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c 777dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 78bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854 79bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858 80bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c 81bf3a4c51SSam Protsenko #define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860 827f36d3b6SSam Protsenko #define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864 837f36d3b6SSam Protsenko #define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868 847f36d3b6SSam Protsenko #define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c 857f36d3b6SSam Protsenko #define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870 867dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c 877dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 887dd05578SSam Protsenko #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 897dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c 907dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 917dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 927dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 937dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c 947dd05578SSam Protsenko #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 95579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008 96b73fd95dSSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c 977dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 987dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 997dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 1007dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 1017dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c 102e145c765SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040 1037dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 1047dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 1057dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c 106bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050 107bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054 108bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058 109bf3a4c51SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c 1107f36d3b6SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060 1117f36d3b6SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064 1127f36d3b6SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068 1137f36d3b6SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c 1147dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 1157dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 1167dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 1177dd05578SSam Protsenko 1187dd05578SSam Protsenko static const unsigned long top_clk_regs[] __initconst = { 1197dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, 1207dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, 1217dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, 1227dd05578SSam Protsenko PLL_CON0_PLL_MMC, 1237dd05578SSam Protsenko PLL_CON3_PLL_MMC, 1247dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 1257dd05578SSam Protsenko PLL_CON3_PLL_SHARED0, 1267dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 1277dd05578SSam Protsenko PLL_CON3_PLL_SHARED1, 128579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 129b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLKCMU_AUD, 1307dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 1317dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 1327dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 1337dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 1347dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 135e145c765SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 1367dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 1377dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 1387dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 139bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 140bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 141bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 142bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 1437f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 1447f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 1457f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 1467f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 1477dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 1487dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 1497dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 150579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_APM_BUS, 151b73fd95dSSam Protsenko CLK_CON_DIV_CLKCMU_AUD, 1527dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 1537dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 1547dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 1557dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 1567dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 157e145c765SSam Protsenko CLK_CON_DIV_CLKCMU_G3D_SWITCH, 1587dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 1597dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 1607dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 161bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_BUS, 162bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_GDC, 163bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_ITP, 164bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_VRA, 1657f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 1667f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 1677f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 1687f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 1697dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 1707dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 1717dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 1727dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 1737dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 1747dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 1757dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 1767dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 1777dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 178579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 179b73fd95dSSam Protsenko CLK_CON_GAT_GATE_CLKCMU_AUD, 1807dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 1817dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 1827dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 1837dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 1847dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 185e145c765SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 1867dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 1877dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 1887dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 189bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 190bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 191bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 192bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 1937f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 1947f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 1957f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 1967f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 1977dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 1987dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 1997dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 2007dd05578SSam Protsenko }; 2017dd05578SSam Protsenko 2027dd05578SSam Protsenko /* 2037dd05578SSam Protsenko * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set 2047dd05578SSam Protsenko * for those PLLs by default, so set_rate operation would fail. 2057dd05578SSam Protsenko */ 2067dd05578SSam Protsenko static const struct samsung_pll_clock top_pll_clks[] __initconst = { 2077dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 2087dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 2097dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 2107dd05578SSam Protsenko NULL), 2117dd05578SSam Protsenko PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 2127dd05578SSam Protsenko PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 2137dd05578SSam Protsenko NULL), 2147dd05578SSam Protsenko PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 2157dd05578SSam Protsenko PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 2167dd05578SSam Protsenko }; 2177dd05578SSam Protsenko 2187dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP */ 2197dd05578SSam Protsenko PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 2207dd05578SSam Protsenko PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 2217dd05578SSam Protsenko PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 222579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */ 223579839a9SSam Protsenko PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" }; 224b73fd95dSSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */ 225b73fd95dSSam Protsenko PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2", 226b73fd95dSSam Protsenko "dout_shared1_div2", "dout_shared0_div3" }; 2277dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 2287dd05578SSam Protsenko PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", 2297dd05578SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 2307dd05578SSam Protsenko PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 2317dd05578SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 2327dd05578SSam Protsenko PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", 2337dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 2347dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 2357dd05578SSam Protsenko "oscclk", "oscclk" }; 2367dd05578SSam Protsenko PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", 2377dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 238e145c765SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */ 239e145c765SSam Protsenko PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", 240e145c765SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 2417dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ 2427dd05578SSam Protsenko PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 2437dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", 2447dd05578SSam Protsenko "dout_shared1_div2", "dout_shared0_div3", 2457dd05578SSam Protsenko "dout_shared1_div3", "mout_mmc_pll", 2467dd05578SSam Protsenko "oscclk", "oscclk" }; 2477dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4", 2487dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 249bf3a4c51SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */ 250bf3a4c51SSam Protsenko PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", 251bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 252bf3a4c51SSam Protsenko PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2", 253bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 254bf3a4c51SSam Protsenko PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2", 255bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 256bf3a4c51SSam Protsenko PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2", 257bf3a4c51SSam Protsenko "dout_shared0_div3", "dout_shared1_div3" }; 2587f36d3b6SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */ 2597f36d3b6SSam Protsenko PNAME(mout_mfcmscl_mfc_p) = { "dout_shared1_div2", "dout_shared0_div3", 2607f36d3b6SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 2617f36d3b6SSam Protsenko PNAME(mout_mfcmscl_m2m_p) = { "dout_shared1_div2", "dout_shared0_div3", 2627f36d3b6SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 2637f36d3b6SSam Protsenko PNAME(mout_mfcmscl_mcsc_p) = { "dout_shared1_div2", "dout_shared0_div3", 2647f36d3b6SSam Protsenko "dout_shared1_div3", "dout_shared0_div4" }; 2657f36d3b6SSam Protsenko PNAME(mout_mfcmscl_jpeg_p) = { "dout_shared0_div3", "dout_shared1_div3", 2667f36d3b6SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 2677dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 2687dd05578SSam Protsenko PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 2697dd05578SSam Protsenko PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4", 2707dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2717dd05578SSam Protsenko PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4", 2727dd05578SSam Protsenko "dout_shared1_div4", "oscclk" }; 2737dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ 2747dd05578SSam Protsenko PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3", 2757dd05578SSam Protsenko "dout_shared0_div4", "dout_shared1_div4" }; 2767dd05578SSam Protsenko 2777dd05578SSam Protsenko static const struct samsung_mux_clock top_mux_clks[] __initconst = { 2787dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 2797dd05578SSam Protsenko MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 2807dd05578SSam Protsenko PLL_CON0_PLL_SHARED0, 4, 1), 2817dd05578SSam Protsenko MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 2827dd05578SSam Protsenko PLL_CON0_PLL_SHARED1, 4, 1), 2837dd05578SSam Protsenko MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 2847dd05578SSam Protsenko PLL_CON0_PLL_MMC, 4, 1), 2857dd05578SSam Protsenko 286579839a9SSam Protsenko /* APM */ 287579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", 288579839a9SSam Protsenko mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), 289579839a9SSam Protsenko 290b73fd95dSSam Protsenko /* AUD */ 291b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p, 292b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2), 293b73fd95dSSam Protsenko 2947dd05578SSam Protsenko /* CORE */ 2957dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 2967dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 2977dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 2987dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 2997dd05578SSam Protsenko MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, 3007dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), 3017dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, 3027dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), 3037dd05578SSam Protsenko 3047dd05578SSam Protsenko /* DPU */ 3057dd05578SSam Protsenko MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, 3067dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), 3077dd05578SSam Protsenko 308e145c765SSam Protsenko /* G3D */ 309e145c765SSam Protsenko MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p, 310e145c765SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2), 311e145c765SSam Protsenko 3127dd05578SSam Protsenko /* HSI */ 3137dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, 3147dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), 3157dd05578SSam Protsenko MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, 3167dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), 3177dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, 3187dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), 3197dd05578SSam Protsenko 320bf3a4c51SSam Protsenko /* IS */ 321bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p, 322bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2), 323bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p, 324bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2), 325bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p, 326bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2), 327bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p, 328bf3a4c51SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2), 329bf3a4c51SSam Protsenko 3307f36d3b6SSam Protsenko /* MFCMSCL */ 3317f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p, 3327f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2), 3337f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p, 3347f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2), 3357f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p, 3367f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2), 3377f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p, 3387f36d3b6SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2), 3397f36d3b6SSam Protsenko 3407dd05578SSam Protsenko /* PERI */ 3417dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 3427dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 3437dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, 3447dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), 3457dd05578SSam Protsenko MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, 3467dd05578SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), 3477dd05578SSam Protsenko }; 3487dd05578SSam Protsenko 3497dd05578SSam Protsenko static const struct samsung_div_clock top_div_clks[] __initconst = { 3507dd05578SSam Protsenko /* CMU_TOP_PURECLKCOMP */ 3517dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", 3527dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 3537dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", 3547dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 3557dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", 3567dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 3577dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", 3587dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 3597dd05578SSam Protsenko DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 3607dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 3617dd05578SSam Protsenko DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 3627dd05578SSam Protsenko CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 3637dd05578SSam Protsenko 364579839a9SSam Protsenko /* APM */ 365579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", 366579839a9SSam Protsenko "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), 367579839a9SSam Protsenko 368b73fd95dSSam Protsenko /* AUD */ 369b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud", 370b73fd95dSSam Protsenko CLK_CON_DIV_CLKCMU_AUD, 0, 4), 371b73fd95dSSam Protsenko 3727dd05578SSam Protsenko /* CORE */ 3737dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 3747dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 3757dd05578SSam Protsenko DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 3767dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), 3777dd05578SSam Protsenko DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", 3787dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), 3797dd05578SSam Protsenko DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", 3807dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), 3817dd05578SSam Protsenko 3827dd05578SSam Protsenko /* DPU */ 3837dd05578SSam Protsenko DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", 3847dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_DPU, 0, 4), 3857dd05578SSam Protsenko 386e145c765SSam Protsenko /* G3D */ 387e145c765SSam Protsenko DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch", 388e145c765SSam Protsenko CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), 389e145c765SSam Protsenko 3907dd05578SSam Protsenko /* HSI */ 3917dd05578SSam Protsenko DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", 3927dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), 3937dd05578SSam Protsenko DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", 3947dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), 3957dd05578SSam Protsenko DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", 3967dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), 3977dd05578SSam Protsenko 398bf3a4c51SSam Protsenko /* IS */ 399bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus", 400bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4), 401bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp", 402bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4), 403bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra", 404bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4), 405bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc", 406bf3a4c51SSam Protsenko CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4), 407bf3a4c51SSam Protsenko 4087f36d3b6SSam Protsenko /* MFCMSCL */ 4097f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc", 4107f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4), 4117f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m", 4127f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4), 4137f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc", 4147f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4), 4157f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg", 4167f36d3b6SSam Protsenko CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4), 4177f36d3b6SSam Protsenko 4187dd05578SSam Protsenko /* PERI */ 4197dd05578SSam Protsenko DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 4207dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 4217dd05578SSam Protsenko DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", 4227dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), 4237dd05578SSam Protsenko DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", 4247dd05578SSam Protsenko CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), 4257dd05578SSam Protsenko }; 4267dd05578SSam Protsenko 4277dd05578SSam Protsenko static const struct samsung_gate_clock top_gate_clks[] __initconst = { 4287dd05578SSam Protsenko /* CORE */ 4297dd05578SSam Protsenko GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 4307dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 4317dd05578SSam Protsenko GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 4327dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 4337dd05578SSam Protsenko GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", 4347dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), 4357dd05578SSam Protsenko GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", 4367dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), 4377dd05578SSam Protsenko 438579839a9SSam Protsenko /* APM */ 439579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", 440579839a9SSam Protsenko "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0), 441579839a9SSam Protsenko 442b73fd95dSSam Protsenko /* AUD */ 443b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud", 444b73fd95dSSam Protsenko CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0), 445b73fd95dSSam Protsenko 4467dd05578SSam Protsenko /* DPU */ 4477dd05578SSam Protsenko GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", 4487dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), 4497dd05578SSam Protsenko 450e145c765SSam Protsenko /* G3D */ 451e145c765SSam Protsenko GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch", 452e145c765SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0), 453e145c765SSam Protsenko 4547dd05578SSam Protsenko /* HSI */ 4557dd05578SSam Protsenko GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", 4567dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), 4577dd05578SSam Protsenko GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", 4587dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), 4597dd05578SSam Protsenko GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", 4607dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), 4617dd05578SSam Protsenko 462bf3a4c51SSam Protsenko /* IS */ 463bf3a4c51SSam Protsenko /* TODO: These clocks have to be always enabled to access CMU_IS regs */ 464bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus", 465bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0), 466bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp", 467bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0), 468bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra", 469bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0), 470bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc", 471bf3a4c51SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0), 472bf3a4c51SSam Protsenko 4737f36d3b6SSam Protsenko /* MFCMSCL */ 4747f36d3b6SSam Protsenko /* TODO: These have to be always enabled to access CMU_MFCMSCL regs */ 4757f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc", 4767f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0), 4777f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m", 4787f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0), 4797f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc", 4807f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0), 4817f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg", 4827f36d3b6SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0), 4837f36d3b6SSam Protsenko 4847dd05578SSam Protsenko /* PERI */ 4857dd05578SSam Protsenko GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 4867dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 4877dd05578SSam Protsenko GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", 4887dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), 4897dd05578SSam Protsenko GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", 4907dd05578SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), 4917dd05578SSam Protsenko }; 4927dd05578SSam Protsenko 4937dd05578SSam Protsenko static const struct samsung_cmu_info top_cmu_info __initconst = { 4947dd05578SSam Protsenko .pll_clks = top_pll_clks, 4957dd05578SSam Protsenko .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 4967dd05578SSam Protsenko .mux_clks = top_mux_clks, 4977dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 4987dd05578SSam Protsenko .div_clks = top_div_clks, 4997dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(top_div_clks), 5007dd05578SSam Protsenko .gate_clks = top_gate_clks, 5017dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 502*56d62cd4SKrzysztof Kozlowski .nr_clk_ids = CLKS_NR_TOP, 5037dd05578SSam Protsenko .clk_regs = top_clk_regs, 5047dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 5057dd05578SSam Protsenko }; 5067dd05578SSam Protsenko 5077dd05578SSam Protsenko static void __init exynos850_cmu_top_init(struct device_node *np) 5087dd05578SSam Protsenko { 509cfe238e4SDavid Virag exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 5107dd05578SSam Protsenko } 5117dd05578SSam Protsenko 512bcda841fSSam Protsenko /* Register CMU_TOP early, as it's a dependency for other early domains */ 5137dd05578SSam Protsenko CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", 5147dd05578SSam Protsenko exynos850_cmu_top_init); 5157dd05578SSam Protsenko 516579839a9SSam Protsenko /* ---- CMU_APM ------------------------------------------------------------- */ 517579839a9SSam Protsenko 518579839a9SSam Protsenko /* Register Offset definitions for CMU_APM (0x11800000) */ 519579839a9SSam Protsenko #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600 520579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610 521579839a9SSam Protsenko #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620 522579839a9SSam Protsenko #define PLL_CON0_MUX_DLL_USER 0x0630 523579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000 524579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004 525579839a9SSam Protsenko #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008 526579839a9SSam Protsenko #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800 527579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804 528579839a9SSam Protsenko #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808 529579839a9SSam Protsenko #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 530579839a9SSam Protsenko #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014 531bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018 532bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020 533579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024 534579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028 535579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034 536579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038 537579839a9SSam Protsenko #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc 538bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0 539579839a9SSam Protsenko 540579839a9SSam Protsenko static const unsigned long apm_clk_regs[] __initconst = { 541579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 542579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 543579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 544579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 545579839a9SSam Protsenko CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 546579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 547579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 548579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 549579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 550579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 551579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 552579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 553bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 554bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 555579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 556579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 557579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 558579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 559579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 560bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 561579839a9SSam Protsenko }; 562579839a9SSam Protsenko 563579839a9SSam Protsenko /* List of parent clocks for Muxes in CMU_APM */ 564579839a9SSam Protsenko PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" }; 565579839a9SSam Protsenko PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" }; 566579839a9SSam Protsenko PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" }; 567579839a9SSam Protsenko PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" }; 568579839a9SSam Protsenko PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" }; 569579839a9SSam Protsenko PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user", 570579839a9SSam Protsenko "mout_dll_user", "oscclk_rco_apm" }; 571579839a9SSam Protsenko PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" }; 572579839a9SSam Protsenko 573579839a9SSam Protsenko static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 574579839a9SSam Protsenko FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000), 575579839a9SSam Protsenko FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000), 576579839a9SSam Protsenko FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000), 577579839a9SSam Protsenko FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000), 578579839a9SSam Protsenko }; 579579839a9SSam Protsenko 580579839a9SSam Protsenko static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 581579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p, 582579839a9SSam Protsenko PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1), 583579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user", 584579839a9SSam Protsenko mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1), 585579839a9SSam Protsenko MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p, 586579839a9SSam Protsenko PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1), 587579839a9SSam Protsenko MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p, 588579839a9SSam Protsenko PLL_CON0_MUX_DLL_USER, 4, 1), 589579839a9SSam Protsenko MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus", 590579839a9SSam Protsenko mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1), 591579839a9SSam Protsenko MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p, 592579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2), 593579839a9SSam Protsenko MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p, 594579839a9SSam Protsenko CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1), 595579839a9SSam Protsenko }; 596579839a9SSam Protsenko 597579839a9SSam Protsenko static const struct samsung_div_clock apm_div_clks[] __initconst = { 598579839a9SSam Protsenko DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus", 599579839a9SSam Protsenko "gout_clkcmu_chub_bus", 600579839a9SSam Protsenko CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3), 601579839a9SSam Protsenko DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus", 602579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3), 603579839a9SSam Protsenko DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus", 604579839a9SSam Protsenko CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3), 605579839a9SSam Protsenko }; 606579839a9SSam Protsenko 607579839a9SSam Protsenko static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 608579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus", 609579839a9SSam Protsenko CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0), 610579839a9SSam Protsenko GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus", 611579839a9SSam Protsenko "mout_clkcmu_chub_bus", 612579839a9SSam Protsenko CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0), 613579839a9SSam Protsenko GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus", 614579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0), 615579839a9SSam Protsenko GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus", 616579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0), 617579839a9SSam Protsenko GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus", 618579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0), 619579839a9SSam Protsenko GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c", 620579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0), 621579839a9SSam Protsenko GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus", 622579839a9SSam Protsenko CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0), 623bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 624bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus", 625bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, 626bc471d1fSSam Protsenko 0), 627bc471d1fSSam Protsenko GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", 628babb3e6aSSam Protsenko CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0), 629bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", 630bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), 631579839a9SSam Protsenko }; 632579839a9SSam Protsenko 633579839a9SSam Protsenko static const struct samsung_cmu_info apm_cmu_info __initconst = { 634579839a9SSam Protsenko .mux_clks = apm_mux_clks, 635579839a9SSam Protsenko .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 636579839a9SSam Protsenko .div_clks = apm_div_clks, 637579839a9SSam Protsenko .nr_div_clks = ARRAY_SIZE(apm_div_clks), 638579839a9SSam Protsenko .gate_clks = apm_gate_clks, 639579839a9SSam Protsenko .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 640579839a9SSam Protsenko .fixed_clks = apm_fixed_clks, 641579839a9SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 642*56d62cd4SKrzysztof Kozlowski .nr_clk_ids = CLKS_NR_APM, 643579839a9SSam Protsenko .clk_regs = apm_clk_regs, 644579839a9SSam Protsenko .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 645579839a9SSam Protsenko .clk_name = "dout_clkcmu_apm_bus", 646579839a9SSam Protsenko }; 647579839a9SSam Protsenko 648b73fd95dSSam Protsenko /* ---- CMU_AUD ------------------------------------------------------------- */ 649b73fd95dSSam Protsenko 650b73fd95dSSam Protsenko #define PLL_LOCKTIME_PLL_AUD 0x0000 651b73fd95dSSam Protsenko #define PLL_CON0_PLL_AUD 0x0100 652b73fd95dSSam Protsenko #define PLL_CON3_PLL_AUD 0x010c 653b73fd95dSSam Protsenko #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600 654b73fd95dSSam Protsenko #define PLL_CON0_MUX_TICK_USB_USER 0x0610 655b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000 656b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004 657b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008 658b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c 659b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010 660b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014 661b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018 662b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c 663b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020 664b73fd95dSSam Protsenko #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024 665b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800 666b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804 667b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808 668b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c 669b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810 670b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814 671b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818 672b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c 673b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820 674b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824 675b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828 676b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c 677b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830 678b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834 679b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838 680b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c 681b73fd95dSSam Protsenko #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840 682b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000 683b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004 684b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008 685b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c 686b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010 687b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 688b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 689b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c 6909a8ab39fSSam Protsenko #define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020 691b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 692b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c 693b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 694b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054 695b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058 696b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c 697b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070 698b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074 699b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088 700b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c 701b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4 702b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8 703b73fd95dSSam Protsenko #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc 704b73fd95dSSam Protsenko 705b73fd95dSSam Protsenko static const unsigned long aud_clk_regs[] __initconst = { 706b73fd95dSSam Protsenko PLL_LOCKTIME_PLL_AUD, 707b73fd95dSSam Protsenko PLL_CON0_PLL_AUD, 708b73fd95dSSam Protsenko PLL_CON3_PLL_AUD, 709b73fd95dSSam Protsenko PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 710b73fd95dSSam Protsenko PLL_CON0_MUX_TICK_USB_USER, 711b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU, 712b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 713b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_FM, 714b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 715b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 716b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 717b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 718b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 719b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 720b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 721b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_MCLK, 722b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 723b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSD, 724b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSP, 725b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CNT, 726b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU, 727b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 728b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 729b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM, 730b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 731b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 732b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 733b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 734b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 735b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 736b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 737b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 738b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 739b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 740b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 741b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 742b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 743b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 744b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 745b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 7469a8ab39fSSam Protsenko CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 747b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 748b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 749b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 750b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 751b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 752b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 753b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 754b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 755b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 756b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 757b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 758b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 759b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 760b73fd95dSSam Protsenko }; 761b73fd95dSSam Protsenko 762b73fd95dSSam Protsenko /* List of parent clocks for Muxes in CMU_AUD */ 763b73fd95dSSam Protsenko PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" }; 764b73fd95dSSam Protsenko PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" }; 765b73fd95dSSam Protsenko PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" }; 766b73fd95dSSam Protsenko PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" }; 767b73fd95dSSam Protsenko PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" }; 768b73fd95dSSam Protsenko PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" }; 769b73fd95dSSam Protsenko PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" }; 770b73fd95dSSam Protsenko PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" }; 771b73fd95dSSam Protsenko PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" }; 772b73fd95dSSam Protsenko PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" }; 773b73fd95dSSam Protsenko PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" }; 774b73fd95dSSam Protsenko PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" }; 775b73fd95dSSam Protsenko PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" }; 776b73fd95dSSam Protsenko 777b73fd95dSSam Protsenko /* 778b73fd95dSSam Protsenko * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set 779b73fd95dSSam Protsenko * for that PLL by default, so set_rate operation would fail. 780b73fd95dSSam Protsenko */ 781b73fd95dSSam Protsenko static const struct samsung_pll_clock aud_pll_clks[] __initconst = { 782b73fd95dSSam Protsenko PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 783b73fd95dSSam Protsenko PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL), 784b73fd95dSSam Protsenko }; 785b73fd95dSSam Protsenko 786b73fd95dSSam Protsenko static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { 787b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000), 788b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000), 789b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000), 790b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000), 791b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000), 792b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000), 793b73fd95dSSam Protsenko FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000), 794b73fd95dSSam Protsenko FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000), 795b73fd95dSSam Protsenko }; 796b73fd95dSSam Protsenko 797b73fd95dSSam Protsenko static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 798b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, 799b73fd95dSSam Protsenko PLL_CON0_PLL_AUD, 4, 1), 800b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p, 801b73fd95dSSam Protsenko PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1), 802b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user", 803b73fd95dSSam Protsenko mout_aud_tick_usb_user_p, 804b73fd95dSSam Protsenko PLL_CON0_MUX_TICK_USB_USER, 4, 1), 805b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p, 806b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1), 807b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p, 808b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1), 809b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p, 810b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1), 811b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p, 812b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1), 813b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p, 814b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1), 815b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p, 816b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1), 817b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p, 818b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1), 819b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p, 820b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1), 821b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p, 822b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1), 823b73fd95dSSam Protsenko MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p, 824b73fd95dSSam Protsenko CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1), 825b73fd95dSSam Protsenko }; 826b73fd95dSSam Protsenko 827b73fd95dSSam Protsenko static const struct samsung_div_clock aud_div_clks[] __initconst = { 828b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll", 829b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4), 830b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll", 831b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4), 832b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll", 833b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4), 834b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll", 835b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9), 836b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch", 837b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3), 838b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg", 839b73fd95dSSam Protsenko "mout_aud_cpu_hch", 840b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3), 841b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif", 842b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2), 843b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif", 844b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10), 845b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif", 846b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10), 847b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif", 848b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10), 849b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif", 850b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10), 851b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif", 852b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10), 853b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif", 854b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10), 855b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif", 856b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10), 857b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif", 858b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10), 859b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user", 860b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1), 861b73fd95dSSam Protsenko DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm", 862b73fd95dSSam Protsenko CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10), 863b73fd95dSSam Protsenko }; 864b73fd95dSSam Protsenko 865b73fd95dSSam Protsenko static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 8669a8ab39fSSam Protsenko GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk", 8679a8ab39fSSam Protsenko "dout_aud_busd", 8689a8ab39fSSam Protsenko CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0), 869b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch", 870b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), 871b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk", 872b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0), 873b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg", 874b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0), 875b73fd95dSSam Protsenko /* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */ 876b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd", 877b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0), 878b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd", 879b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0), 880b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd", 881b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0), 882b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd", 883b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0), 884b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd", 885b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0), 886b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd", 887b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0), 888b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd", 889b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0), 890b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp", 891b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0), 892b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk", 893b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0), 894b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt", 895b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0), 896b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0", 897b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0), 898b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1", 899b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0), 900b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2", 901b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0), 902b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3", 903b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0), 904b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4", 905b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0), 906b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5", 907b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0), 908b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6", 909b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0), 910b73fd95dSSam Protsenko GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm", 911b73fd95dSSam Protsenko CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0), 912b73fd95dSSam Protsenko }; 913b73fd95dSSam Protsenko 914b73fd95dSSam Protsenko static const struct samsung_cmu_info aud_cmu_info __initconst = { 915b73fd95dSSam Protsenko .pll_clks = aud_pll_clks, 916b73fd95dSSam Protsenko .nr_pll_clks = ARRAY_SIZE(aud_pll_clks), 917b73fd95dSSam Protsenko .mux_clks = aud_mux_clks, 918b73fd95dSSam Protsenko .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 919b73fd95dSSam Protsenko .div_clks = aud_div_clks, 920b73fd95dSSam Protsenko .nr_div_clks = ARRAY_SIZE(aud_div_clks), 921b73fd95dSSam Protsenko .gate_clks = aud_gate_clks, 922b73fd95dSSam Protsenko .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 923b73fd95dSSam Protsenko .fixed_clks = aud_fixed_clks, 924b73fd95dSSam Protsenko .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), 925*56d62cd4SKrzysztof Kozlowski .nr_clk_ids = CLKS_NR_AUD, 926b73fd95dSSam Protsenko .clk_regs = aud_clk_regs, 927b73fd95dSSam Protsenko .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 928b73fd95dSSam Protsenko .clk_name = "dout_aud", 929b73fd95dSSam Protsenko }; 930b73fd95dSSam Protsenko 93162782ba8SSam Protsenko /* ---- CMU_CMGP ------------------------------------------------------------ */ 93262782ba8SSam Protsenko 93362782ba8SSam Protsenko /* Register Offset definitions for CMU_CMGP (0x11c00000) */ 93462782ba8SSam Protsenko #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000 93562782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004 93662782ba8SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008 93762782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800 93862782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804 93962782ba8SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808 94062782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c 94162782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 94262782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018 943bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040 94462782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044 94562782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048 94662782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c 94762782ba8SSam Protsenko #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050 94862782ba8SSam Protsenko 94962782ba8SSam Protsenko static const unsigned long cmgp_clk_regs[] __initconst = { 95062782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 95162782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 95262782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 95362782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 95462782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 95562782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 95662782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 95762782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 95862782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 959bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 96062782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 96162782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 96262782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 96362782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 96462782ba8SSam Protsenko }; 96562782ba8SSam Protsenko 96662782ba8SSam Protsenko /* List of parent clocks for Muxes in CMU_CMGP */ 96762782ba8SSam Protsenko PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 96862782ba8SSam Protsenko PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; 96962782ba8SSam Protsenko PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" }; 97062782ba8SSam Protsenko 97162782ba8SSam Protsenko static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = { 97262782ba8SSam Protsenko FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000), 97362782ba8SSam Protsenko }; 97462782ba8SSam Protsenko 97562782ba8SSam Protsenko static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = { 97662782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p, 97762782ba8SSam Protsenko CLK_CON_MUX_CLK_CMGP_ADC, 0, 1), 97862782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, 97962782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1), 98062782ba8SSam Protsenko MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, 98162782ba8SSam Protsenko CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1), 98262782ba8SSam Protsenko }; 98362782ba8SSam Protsenko 98462782ba8SSam Protsenko static const struct samsung_div_clock cmgp_div_clks[] __initconst = { 98562782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus", 98662782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), 98762782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", 98862782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5), 98962782ba8SSam Protsenko DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", 99062782ba8SSam Protsenko CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5), 99162782ba8SSam Protsenko }; 99262782ba8SSam Protsenko 99362782ba8SSam Protsenko static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { 99462782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk", 99562782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 99662782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0), 99762782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk", 99862782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 99962782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0), 10006904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 100162782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk", 100262782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 10036904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0), 100462782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0", 100562782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0), 100662782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk", 100762782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 100862782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0), 100962782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1", 101062782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0), 101162782ba8SSam Protsenko GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", 101262782ba8SSam Protsenko "gout_clkcmu_cmgp_bus", 101362782ba8SSam Protsenko CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), 1014bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk", 1015bc471d1fSSam Protsenko "gout_clkcmu_cmgp_bus", 1016bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0), 101762782ba8SSam Protsenko }; 101862782ba8SSam Protsenko 101962782ba8SSam Protsenko static const struct samsung_cmu_info cmgp_cmu_info __initconst = { 102062782ba8SSam Protsenko .mux_clks = cmgp_mux_clks, 102162782ba8SSam Protsenko .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks), 102262782ba8SSam Protsenko .div_clks = cmgp_div_clks, 102362782ba8SSam Protsenko .nr_div_clks = ARRAY_SIZE(cmgp_div_clks), 102462782ba8SSam Protsenko .gate_clks = cmgp_gate_clks, 102562782ba8SSam Protsenko .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks), 102662782ba8SSam Protsenko .fixed_clks = cmgp_fixed_clks, 102762782ba8SSam Protsenko .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks), 1028*56d62cd4SKrzysztof Kozlowski .nr_clk_ids = CLKS_NR_CMGP, 102962782ba8SSam Protsenko .clk_regs = cmgp_clk_regs, 103062782ba8SSam Protsenko .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), 103162782ba8SSam Protsenko .clk_name = "gout_clkcmu_cmgp_bus", 103262782ba8SSam Protsenko }; 103362782ba8SSam Protsenko 1034e145c765SSam Protsenko /* ---- CMU_G3D ------------------------------------------------------------- */ 1035e145c765SSam Protsenko 1036e145c765SSam Protsenko /* Register Offset definitions for CMU_G3D (0x11400000) */ 1037e145c765SSam Protsenko #define PLL_LOCKTIME_PLL_G3D 0x0000 1038e145c765SSam Protsenko #define PLL_CON0_PLL_G3D 0x0100 1039e145c765SSam Protsenko #define PLL_CON3_PLL_G3D 0x010c 1040e145c765SSam Protsenko #define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600 1041e145c765SSam Protsenko #define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000 1042e145c765SSam Protsenko #define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804 1043e145c765SSam Protsenko #define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000 1044e145c765SSam Protsenko #define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004 1045e145c765SSam Protsenko #define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c 1046e145c765SSam Protsenko #define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010 1047e145c765SSam Protsenko #define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024 1048e145c765SSam Protsenko #define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028 1049e145c765SSam Protsenko #define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c 1050e145c765SSam Protsenko 1051e145c765SSam Protsenko static const unsigned long g3d_clk_regs[] __initconst = { 1052e145c765SSam Protsenko PLL_LOCKTIME_PLL_G3D, 1053e145c765SSam Protsenko PLL_CON0_PLL_G3D, 1054e145c765SSam Protsenko PLL_CON3_PLL_G3D, 1055e145c765SSam Protsenko PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 1056e145c765SSam Protsenko CLK_CON_MUX_MUX_CLK_G3D_BUSD, 1057e145c765SSam Protsenko CLK_CON_DIV_DIV_CLK_G3D_BUSP, 1058e145c765SSam Protsenko CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 1059e145c765SSam Protsenko CLK_CON_GAT_CLK_G3D_GPU_CLK, 1060e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 1061e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 1062e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 1063e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 1064e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 1065e145c765SSam Protsenko }; 1066e145c765SSam Protsenko 1067e145c765SSam Protsenko /* List of parent clocks for Muxes in CMU_G3D */ 1068e145c765SSam Protsenko PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" }; 1069e145c765SSam Protsenko PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" }; 1070e145c765SSam Protsenko PNAME(mout_g3d_busd_p) = { "mout_g3d_pll", "mout_g3d_switch_user" }; 1071e145c765SSam Protsenko 1072e145c765SSam Protsenko /* 1073e145c765SSam Protsenko * Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set 1074e145c765SSam Protsenko * for that PLL by default, so set_rate operation would fail. 1075e145c765SSam Protsenko */ 1076e145c765SSam Protsenko static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { 1077e145c765SSam Protsenko PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", 1078e145c765SSam Protsenko PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL), 1079e145c765SSam Protsenko }; 1080e145c765SSam Protsenko 1081e145c765SSam Protsenko static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { 1082e145c765SSam Protsenko MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, 1083e145c765SSam Protsenko PLL_CON0_PLL_G3D, 4, 1), 1084e145c765SSam Protsenko MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user", 1085e145c765SSam Protsenko mout_g3d_switch_user_p, 1086e145c765SSam Protsenko PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1), 1087e145c765SSam Protsenko MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p, 1088e145c765SSam Protsenko CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1), 1089e145c765SSam Protsenko }; 1090e145c765SSam Protsenko 1091e145c765SSam Protsenko static const struct samsung_div_clock g3d_div_clks[] __initconst = { 1092e145c765SSam Protsenko DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd", 1093e145c765SSam Protsenko CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3), 1094e145c765SSam Protsenko }; 1095e145c765SSam Protsenko 1096e145c765SSam Protsenko static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { 1097e145c765SSam Protsenko GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk", 1098e145c765SSam Protsenko "dout_g3d_busp", 1099e145c765SSam Protsenko CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1100e145c765SSam Protsenko GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd", 1101e145c765SSam Protsenko CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0), 1102e145c765SSam Protsenko GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp", 1103e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0), 1104e145c765SSam Protsenko GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk", 1105e145c765SSam Protsenko "mout_g3d_busd", 1106e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0), 1107e145c765SSam Protsenko GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd", 1108e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0), 1109e145c765SSam Protsenko GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp", 1110e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0), 1111e145c765SSam Protsenko GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp", 1112e145c765SSam Protsenko CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0), 1113e145c765SSam Protsenko }; 1114e145c765SSam Protsenko 1115e145c765SSam Protsenko static const struct samsung_cmu_info g3d_cmu_info __initconst = { 1116e145c765SSam Protsenko .pll_clks = g3d_pll_clks, 1117e145c765SSam Protsenko .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), 1118e145c765SSam Protsenko .mux_clks = g3d_mux_clks, 1119e145c765SSam Protsenko .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), 1120e145c765SSam Protsenko .div_clks = g3d_div_clks, 1121e145c765SSam Protsenko .nr_div_clks = ARRAY_SIZE(g3d_div_clks), 1122e145c765SSam Protsenko .gate_clks = g3d_gate_clks, 1123e145c765SSam Protsenko .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), 1124*56d62cd4SKrzysztof Kozlowski .nr_clk_ids = CLKS_NR_G3D, 1125e145c765SSam Protsenko .clk_regs = g3d_clk_regs, 1126e145c765SSam Protsenko .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), 1127e145c765SSam Protsenko .clk_name = "dout_g3d_switch", 1128e145c765SSam Protsenko }; 1129e145c765SSam Protsenko 11307dd05578SSam Protsenko /* ---- CMU_HSI ------------------------------------------------------------- */ 11317dd05578SSam Protsenko 11327dd05578SSam Protsenko /* Register Offset definitions for CMU_HSI (0x13400000) */ 11337dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 11347dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 11357dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 11367dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 11379a8ab39fSSam Protsenko #define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000 11387dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 11397dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c 11407dd05578SSam Protsenko #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 11417dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 11427dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 11437dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 11449a8ab39fSSam Protsenko #define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c 11459a8ab39fSSam Protsenko #define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030 11467dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 11477dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c 11487dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 11497dd05578SSam Protsenko 11507dd05578SSam Protsenko static const unsigned long hsi_clk_regs[] __initconst = { 11517dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 11527dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 11537dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 11547dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 11559a8ab39fSSam Protsenko CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 11567dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 11577dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 11587dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 11597dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 11607dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 11617dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 11629a8ab39fSSam Protsenko CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 11639a8ab39fSSam Protsenko CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 11647dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 11657dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 11667dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 11677dd05578SSam Protsenko }; 11687dd05578SSam Protsenko 1169dbaa27ccSSam Protsenko /* List of parent clocks for Muxes in CMU_HSI */ 11707dd05578SSam Protsenko PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" }; 11717dd05578SSam Protsenko PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" }; 11727dd05578SSam Protsenko PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" }; 11737dd05578SSam Protsenko PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" }; 11747dd05578SSam Protsenko 11757dd05578SSam Protsenko static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { 11767dd05578SSam Protsenko MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, 11777dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), 11787dd05578SSam Protsenko MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", 11797dd05578SSam Protsenko mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 11807dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 11817dd05578SSam Protsenko MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", 11827dd05578SSam Protsenko mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 11837dd05578SSam Protsenko 4, 1), 11847dd05578SSam Protsenko MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p, 11857dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1), 11867dd05578SSam Protsenko }; 11877dd05578SSam Protsenko 11887dd05578SSam Protsenko static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { 11899a8ab39fSSam Protsenko /* TODO: Should be enabled in corresponding driver */ 11909a8ab39fSSam Protsenko GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk", 11919a8ab39fSSam Protsenko "mout_hsi_bus_user", 11929a8ab39fSSam Protsenko CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 11937dd05578SSam Protsenko GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", 11947dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), 11957dd05578SSam Protsenko GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", 11967dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), 11977dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk", 11987dd05578SSam Protsenko CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), 11996904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 12007dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user", 12016904d7e5SSam Protsenko CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 12027dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", 12037dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), 12047dd05578SSam Protsenko GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 12057dd05578SSam Protsenko "mout_hsi_mmc_card_user", 12067dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), 12079a8ab39fSSam Protsenko GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user", 12089a8ab39fSSam Protsenko CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0), 12099a8ab39fSSam Protsenko GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user", 12109a8ab39fSSam Protsenko CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0), 12117dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", 12127dd05578SSam Protsenko "mout_hsi_bus_user", 12137dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), 12147dd05578SSam Protsenko GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", 12157dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), 12167dd05578SSam Protsenko GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", 12177dd05578SSam Protsenko "mout_hsi_bus_user", 12187dd05578SSam Protsenko CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), 12197dd05578SSam Protsenko }; 12207dd05578SSam Protsenko 12217dd05578SSam Protsenko static const struct samsung_cmu_info hsi_cmu_info __initconst = { 12227dd05578SSam Protsenko .mux_clks = hsi_mux_clks, 12237dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), 12247dd05578SSam Protsenko .gate_clks = hsi_gate_clks, 12257dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), 1226*56d62cd4SKrzysztof Kozlowski .nr_clk_ids = CLKS_NR_HSI, 12277dd05578SSam Protsenko .clk_regs = hsi_clk_regs, 12287dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), 12297dd05578SSam Protsenko .clk_name = "dout_hsi_bus", 12307dd05578SSam Protsenko }; 12317dd05578SSam Protsenko 1232bf3a4c51SSam Protsenko /* ---- CMU_IS -------------------------------------------------------------- */ 1233bf3a4c51SSam Protsenko 1234bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600 1235bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610 1236bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620 1237bf3a4c51SSam Protsenko #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630 1238bf3a4c51SSam Protsenko #define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800 1239bf3a4c51SSam Protsenko #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000 1240bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040 1241bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044 1242bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048 1243bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c 1244bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050 1245bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054 1246bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058 1247bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c 1248bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060 1249bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064 1250bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074 1251bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078 1252bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c 1253bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080 1254bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098 1255bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c 1256bf3a4c51SSam Protsenko #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0 1257bf3a4c51SSam Protsenko 1258bf3a4c51SSam Protsenko static const unsigned long is_clk_regs[] __initconst = { 1259bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 1260bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 1261bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 1262bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 1263bf3a4c51SSam Protsenko CLK_CON_DIV_DIV_CLK_IS_BUSP, 1264bf3a4c51SSam Protsenko CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 1265bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 1266bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 1267bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 1268bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 1269bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 1270bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_GDC, 1271bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_IPP, 1272bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_ITP, 1273bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_MCSC, 1274bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_VRA, 1275bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 1276bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 1277bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 1278bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 1279bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 1280bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 1281bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 1282bf3a4c51SSam Protsenko }; 1283bf3a4c51SSam Protsenko 1284bf3a4c51SSam Protsenko /* List of parent clocks for Muxes in CMU_IS */ 1285bf3a4c51SSam Protsenko PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" }; 1286bf3a4c51SSam Protsenko PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" }; 1287bf3a4c51SSam Protsenko PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" }; 1288bf3a4c51SSam Protsenko PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" }; 1289bf3a4c51SSam Protsenko 1290bf3a4c51SSam Protsenko static const struct samsung_mux_clock is_mux_clks[] __initconst = { 1291bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p, 1292bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1), 1293bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p, 1294bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1), 1295bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p, 1296bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1), 1297bf3a4c51SSam Protsenko MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p, 1298bf3a4c51SSam Protsenko PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1), 1299bf3a4c51SSam Protsenko }; 1300bf3a4c51SSam Protsenko 1301bf3a4c51SSam Protsenko static const struct samsung_div_clock is_div_clks[] __initconst = { 1302bf3a4c51SSam Protsenko DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user", 1303bf3a4c51SSam Protsenko CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2), 1304bf3a4c51SSam Protsenko }; 1305bf3a4c51SSam Protsenko 1306bf3a4c51SSam Protsenko static const struct samsung_gate_clock is_gate_clks[] __initconst = { 1307bf3a4c51SSam Protsenko /* TODO: Should be enabled in IS driver */ 1308bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp", 1309bf3a4c51SSam Protsenko CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1310bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user", 1311bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0), 1312bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user", 1313bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0), 1314bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user", 1315bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0), 1316bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp", 1317bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0), 1318bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk", 1319bf3a4c51SSam Protsenko "mout_is_bus_user", 1320bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0), 1321bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user", 1322bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0), 1323bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user", 1324bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0), 1325bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user", 1326bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0), 1327bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user", 1328bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0), 1329bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user", 1330bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0), 1331bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk", 1332bf3a4c51SSam Protsenko "mout_is_bus_user", 1333bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0), 1334bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp", 1335bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0), 1336bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk", 1337bf3a4c51SSam Protsenko "mout_is_itp_user", 1338bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0), 1339bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp", 1340bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0), 1341bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk", 1342bf3a4c51SSam Protsenko "mout_is_bus_user", 1343bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0), 1344bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk", 1345bf3a4c51SSam Protsenko "mout_is_itp_user", 1346bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0), 1347bf3a4c51SSam Protsenko GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp", 1348bf3a4c51SSam Protsenko CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0), 1349bf3a4c51SSam Protsenko }; 1350bf3a4c51SSam Protsenko 1351bf3a4c51SSam Protsenko static const struct samsung_cmu_info is_cmu_info __initconst = { 1352bf3a4c51SSam Protsenko .mux_clks = is_mux_clks, 1353bf3a4c51SSam Protsenko .nr_mux_clks = ARRAY_SIZE(is_mux_clks), 1354bf3a4c51SSam Protsenko .div_clks = is_div_clks, 1355bf3a4c51SSam Protsenko .nr_div_clks = ARRAY_SIZE(is_div_clks), 1356bf3a4c51SSam Protsenko .gate_clks = is_gate_clks, 1357bf3a4c51SSam Protsenko .nr_gate_clks = ARRAY_SIZE(is_gate_clks), 1358*56d62cd4SKrzysztof Kozlowski .nr_clk_ids = CLKS_NR_IS, 1359bf3a4c51SSam Protsenko .clk_regs = is_clk_regs, 1360bf3a4c51SSam Protsenko .nr_clk_regs = ARRAY_SIZE(is_clk_regs), 1361bf3a4c51SSam Protsenko .clk_name = "dout_is_bus", 1362bf3a4c51SSam Protsenko }; 1363bf3a4c51SSam Protsenko 13647f36d3b6SSam Protsenko /* ---- CMU_MFCMSCL --------------------------------------------------------- */ 13657f36d3b6SSam Protsenko 13667f36d3b6SSam Protsenko #define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600 13677f36d3b6SSam Protsenko #define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610 13687f36d3b6SSam Protsenko #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620 13697f36d3b6SSam Protsenko #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630 13707f36d3b6SSam Protsenko #define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800 13717f36d3b6SSam Protsenko #define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000 13727f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038 13737f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c 13747f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048 13757f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c 13767f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050 13777f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054 13787f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058 13797f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074 13807f36d3b6SSam Protsenko #define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078 13817f36d3b6SSam Protsenko 13827f36d3b6SSam Protsenko static const unsigned long mfcmscl_clk_regs[] __initconst = { 13837f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 13847f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 13857f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 13867f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 13877f36d3b6SSam Protsenko CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 13887f36d3b6SSam Protsenko CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK, 13897f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK, 13907f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK, 13917f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK, 13927f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK, 13937f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK, 13947f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK, 13957f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK, 13967f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1, 13977f36d3b6SSam Protsenko CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK, 13987f36d3b6SSam Protsenko }; 13997f36d3b6SSam Protsenko 14007f36d3b6SSam Protsenko /* List of parent clocks for Muxes in CMU_MFCMSCL */ 14017f36d3b6SSam Protsenko PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" }; 14027f36d3b6SSam Protsenko PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" }; 14037f36d3b6SSam Protsenko PNAME(mout_mfcmscl_mcsc_user_p) = { "oscclk", "dout_mfcmscl_mcsc" }; 14047f36d3b6SSam Protsenko PNAME(mout_mfcmscl_jpeg_user_p) = { "oscclk", "dout_mfcmscl_jpeg" }; 14057f36d3b6SSam Protsenko 14067f36d3b6SSam Protsenko static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = { 14077f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user", 14087f36d3b6SSam Protsenko mout_mfcmscl_mfc_user_p, 14097f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1), 14107f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user", 14117f36d3b6SSam Protsenko mout_mfcmscl_m2m_user_p, 14127f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1), 14137f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user", 14147f36d3b6SSam Protsenko mout_mfcmscl_mcsc_user_p, 14157f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1), 14167f36d3b6SSam Protsenko MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user", 14177f36d3b6SSam Protsenko mout_mfcmscl_jpeg_user_p, 14187f36d3b6SSam Protsenko PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1), 14197f36d3b6SSam Protsenko }; 14207f36d3b6SSam Protsenko 14217f36d3b6SSam Protsenko static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = { 14227f36d3b6SSam Protsenko DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user", 14237f36d3b6SSam Protsenko CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3), 14247f36d3b6SSam Protsenko }; 14257f36d3b6SSam Protsenko 14267f36d3b6SSam Protsenko static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = { 14277f36d3b6SSam Protsenko /* TODO: Should be enabled in MFC driver */ 14287f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk", 14297f36d3b6SSam Protsenko "dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK, 14307f36d3b6SSam Protsenko 21, CLK_IGNORE_UNUSED, 0), 14317f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk", 14327f36d3b6SSam Protsenko "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK, 14337f36d3b6SSam Protsenko 21, 0, 0), 14347f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk", 14357f36d3b6SSam Protsenko "mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK, 14367f36d3b6SSam Protsenko 21, 0, 0), 14377f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk", 14387f36d3b6SSam Protsenko "mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK, 14397f36d3b6SSam Protsenko 21, 0, 0), 14407f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk", 14417f36d3b6SSam Protsenko "mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK, 14427f36d3b6SSam Protsenko 21, 0, 0), 14437f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk", 14447f36d3b6SSam Protsenko "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK, 14457f36d3b6SSam Protsenko 21, 0, 0), 14467f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk", 14477f36d3b6SSam Protsenko "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK, 14487f36d3b6SSam Protsenko 21, 0, 0), 14497f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk", 14507f36d3b6SSam Protsenko "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK, 14517f36d3b6SSam Protsenko 21, 0, 0), 14527f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk", 14537f36d3b6SSam Protsenko "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1, 14547f36d3b6SSam Protsenko 21, 0, 0), 14557f36d3b6SSam Protsenko GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk", 14567f36d3b6SSam Protsenko "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK, 14577f36d3b6SSam Protsenko 21, 0, 0), 14587f36d3b6SSam Protsenko }; 14597f36d3b6SSam Protsenko 14607f36d3b6SSam Protsenko static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = { 14617f36d3b6SSam Protsenko .mux_clks = mfcmscl_mux_clks, 14627f36d3b6SSam Protsenko .nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks), 14637f36d3b6SSam Protsenko .div_clks = mfcmscl_div_clks, 14647f36d3b6SSam Protsenko .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks), 14657f36d3b6SSam Protsenko .gate_clks = mfcmscl_gate_clks, 14667f36d3b6SSam Protsenko .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks), 1467*56d62cd4SKrzysztof Kozlowski .nr_clk_ids = CLKS_NR_MFCMSCL, 14687f36d3b6SSam Protsenko .clk_regs = mfcmscl_clk_regs, 14697f36d3b6SSam Protsenko .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs), 14707f36d3b6SSam Protsenko .clk_name = "dout_mfcmscl_mfc", 14717f36d3b6SSam Protsenko }; 14727f36d3b6SSam Protsenko 14737dd05578SSam Protsenko /* ---- CMU_PERI ------------------------------------------------------------ */ 14747dd05578SSam Protsenko 14757dd05578SSam Protsenko /* Register Offset definitions for CMU_PERI (0x10030000) */ 14767dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 14777dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610 14787dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620 14797dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 14807dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800 14817dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804 14827dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808 14837dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c 14847dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c 14857dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010 14867dd05578SSam Protsenko #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014 14877dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020 14887dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024 14897dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 14907dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c 14917dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030 14927dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034 14937dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038 14947dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c 14957dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040 14967dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044 14977dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048 14987dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c 14997dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050 15007dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054 15017dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c 15027dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064 15037dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c 15047dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0 15057dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4 15067dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 15077dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac 15087dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0 15097dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4 15107dd05578SSam Protsenko 15117dd05578SSam Protsenko static const unsigned long peri_clk_regs[] __initconst = { 15127dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 15137dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 15147dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 15157dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 15167dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 15177dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 15187dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 15197dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 15207dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 15217dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 15227dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 15237dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 15247dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 15257dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 15267dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 15277dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 15287dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 15297dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 15307dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 15317dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 15327dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 15337dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 15347dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 15357dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 15367dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 15377dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 15387dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 15397dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 15407dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 15417dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 15427dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 15437dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 15447dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 15457dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 15467dd05578SSam Protsenko }; 15477dd05578SSam Protsenko 15487dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_PERI */ 15497dd05578SSam Protsenko PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; 15507dd05578SSam Protsenko PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" }; 15517dd05578SSam Protsenko PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" }; 15527dd05578SSam Protsenko PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" }; 15537dd05578SSam Protsenko 15547dd05578SSam Protsenko static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 15557dd05578SSam Protsenko MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 15567dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 15577dd05578SSam Protsenko MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", 15587dd05578SSam Protsenko mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), 15597dd05578SSam Protsenko MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", 15607dd05578SSam Protsenko mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), 15617dd05578SSam Protsenko MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, 15627dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), 15637dd05578SSam Protsenko }; 15647dd05578SSam Protsenko 15657dd05578SSam Protsenko static const struct samsung_div_clock peri_div_clks[] __initconst = { 15667dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0", 15677dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5), 15687dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1", 15697dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), 15707dd05578SSam Protsenko DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", 15717dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), 15727dd05578SSam Protsenko DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", 15737dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), 15747dd05578SSam Protsenko }; 15757dd05578SSam Protsenko 15767dd05578SSam Protsenko static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 15777dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user", 15787dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0), 15797dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user", 15807dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0), 15817dd05578SSam Protsenko GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user", 15827dd05578SSam Protsenko CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0), 15837dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0", 15847dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0), 15857dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", 15867dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), 15877dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1", 15887dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0), 15897dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", 15907dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), 15917dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2", 15927dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0), 15937dd05578SSam Protsenko GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", 15947dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), 15957dd05578SSam Protsenko GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", 15967dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), 15977dd05578SSam Protsenko GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", 15987dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), 15997dd05578SSam Protsenko GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", 16007dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), 16017dd05578SSam Protsenko GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", 16027dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), 16037dd05578SSam Protsenko GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", 16047dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), 16057dd05578SSam Protsenko GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", 16067dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), 16077dd05578SSam Protsenko GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", 16087dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), 16097dd05578SSam Protsenko GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", 16107dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), 16117dd05578SSam Protsenko GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", 16127dd05578SSam Protsenko "mout_peri_bus_user", 16137dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), 16147dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", 16157dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), 16167dd05578SSam Protsenko GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", 16177dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), 16187dd05578SSam Protsenko GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", 16197dd05578SSam Protsenko "mout_peri_bus_user", 16207dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), 16217dd05578SSam Protsenko GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", 16227dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), 16237dd05578SSam Protsenko GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", 16247dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), 16257dd05578SSam Protsenko GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", 16267dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0), 16277dd05578SSam Protsenko GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", 16287dd05578SSam Protsenko CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0), 16296904d7e5SSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 16307dd05578SSam Protsenko GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk", 16317dd05578SSam Protsenko "mout_peri_bus_user", 16326904d7e5SSam Protsenko CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0), 16337dd05578SSam Protsenko }; 16347dd05578SSam Protsenko 16357dd05578SSam Protsenko static const struct samsung_cmu_info peri_cmu_info __initconst = { 16367dd05578SSam Protsenko .mux_clks = peri_mux_clks, 16377dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 16387dd05578SSam Protsenko .div_clks = peri_div_clks, 16397dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(peri_div_clks), 16407dd05578SSam Protsenko .gate_clks = peri_gate_clks, 16417dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 1642*56d62cd4SKrzysztof Kozlowski .nr_clk_ids = CLKS_NR_PERI, 16437dd05578SSam Protsenko .clk_regs = peri_clk_regs, 16447dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 16457dd05578SSam Protsenko .clk_name = "dout_peri_bus", 16467dd05578SSam Protsenko }; 16477dd05578SSam Protsenko 1648bcda841fSSam Protsenko static void __init exynos850_cmu_peri_init(struct device_node *np) 1649bcda841fSSam Protsenko { 1650cfe238e4SDavid Virag exynos_arm64_register_cmu(NULL, np, &peri_cmu_info); 1651bcda841fSSam Protsenko } 1652bcda841fSSam Protsenko 1653bcda841fSSam Protsenko /* Register CMU_PERI early, as it's needed for MCT timer */ 1654bcda841fSSam Protsenko CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", 1655bcda841fSSam Protsenko exynos850_cmu_peri_init); 1656bcda841fSSam Protsenko 16577dd05578SSam Protsenko /* ---- CMU_CORE ------------------------------------------------------------ */ 16587dd05578SSam Protsenko 16597dd05578SSam Protsenko /* Register Offset definitions for CMU_CORE (0x12000000) */ 16607dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 16617dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610 16627dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 16637dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630 16647dd05578SSam Protsenko #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 16657dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 16667dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 16677dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 1668bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 16697dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 16707dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec 16717dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 16727dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c 1673bc471d1fSSam Protsenko #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 16747dd05578SSam Protsenko 16757dd05578SSam Protsenko static const unsigned long core_clk_regs[] __initconst = { 16767dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 16777dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 16787dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 16797dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 16807dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 16817dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 16827dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 16837dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 1684bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 16857dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 16867dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 16877dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 16887dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 1689bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 16907dd05578SSam Protsenko }; 16917dd05578SSam Protsenko 16927dd05578SSam Protsenko /* List of parent clocks for Muxes in CMU_CORE */ 16937dd05578SSam Protsenko PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; 16947dd05578SSam Protsenko PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; 16957dd05578SSam Protsenko PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" }; 16967dd05578SSam Protsenko PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" }; 16977dd05578SSam Protsenko PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; 16987dd05578SSam Protsenko 16997dd05578SSam Protsenko static const struct samsung_mux_clock core_mux_clks[] __initconst = { 17007dd05578SSam Protsenko MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 17017dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 17027dd05578SSam Protsenko MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, 17037dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), 17047dd05578SSam Protsenko MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", 17057dd05578SSam Protsenko mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 17067dd05578SSam Protsenko 4, 1, CLK_SET_RATE_PARENT, 0), 17077dd05578SSam Protsenko MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p, 17087dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1), 17097dd05578SSam Protsenko MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, 17107dd05578SSam Protsenko CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), 17117dd05578SSam Protsenko }; 17127dd05578SSam Protsenko 17137dd05578SSam Protsenko static const struct samsung_div_clock core_div_clks[] __initconst = { 17147dd05578SSam Protsenko DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 17157dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 17167dd05578SSam Protsenko }; 17177dd05578SSam Protsenko 17187dd05578SSam Protsenko static const struct samsung_gate_clock core_gate_clks[] __initconst = { 17196904d7e5SSam Protsenko /* CCI (interconnect) clock must be always running */ 17207dd05578SSam Protsenko GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", 17216904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0), 17226904d7e5SSam Protsenko /* GIC (interrupt controller) clock must be always running */ 17237dd05578SSam Protsenko GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic", 17246904d7e5SSam Protsenko CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0), 17257dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", 17267dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), 17277dd05578SSam Protsenko GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 17287dd05578SSam Protsenko "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 17297dd05578SSam Protsenko 21, CLK_SET_RATE_PARENT, 0), 17307dd05578SSam Protsenko GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", 17317dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), 17327dd05578SSam Protsenko GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", 17337dd05578SSam Protsenko CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), 1734bc471d1fSSam Protsenko /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 1735bc471d1fSSam Protsenko GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp", 1736bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1737bc471d1fSSam Protsenko GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk", 1738bc471d1fSSam Protsenko "dout_core_busp", 1739bc471d1fSSam Protsenko CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0), 17407dd05578SSam Protsenko }; 17417dd05578SSam Protsenko 17427dd05578SSam Protsenko static const struct samsung_cmu_info core_cmu_info __initconst = { 17437dd05578SSam Protsenko .mux_clks = core_mux_clks, 17447dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 17457dd05578SSam Protsenko .div_clks = core_div_clks, 17467dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(core_div_clks), 17477dd05578SSam Protsenko .gate_clks = core_gate_clks, 17487dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 1749*56d62cd4SKrzysztof Kozlowski .nr_clk_ids = CLKS_NR_CORE, 17507dd05578SSam Protsenko .clk_regs = core_clk_regs, 17517dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 17527dd05578SSam Protsenko .clk_name = "dout_core_bus", 17537dd05578SSam Protsenko }; 17547dd05578SSam Protsenko 17557dd05578SSam Protsenko /* ---- CMU_DPU ------------------------------------------------------------- */ 17567dd05578SSam Protsenko 17577dd05578SSam Protsenko /* Register Offset definitions for CMU_DPU (0x13000000) */ 17587dd05578SSam Protsenko #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600 17597dd05578SSam Protsenko #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 17607dd05578SSam Protsenko #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004 17617dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010 17627dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014 17637dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018 17647dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028 17657dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c 17667dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038 17677dd05578SSam Protsenko #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c 17687dd05578SSam Protsenko 17697dd05578SSam Protsenko static const unsigned long dpu_clk_regs[] __initconst = { 17707dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 17717dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 17727dd05578SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 17737dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 17747dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 17757dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 17767dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 17777dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 17787dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 17797dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 17807dd05578SSam Protsenko }; 17817dd05578SSam Protsenko 1782dbaa27ccSSam Protsenko /* List of parent clocks for Muxes in CMU_DPU */ 17837dd05578SSam Protsenko PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" }; 17847dd05578SSam Protsenko 17857dd05578SSam Protsenko static const struct samsung_mux_clock dpu_mux_clks[] __initconst = { 17867dd05578SSam Protsenko MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p, 17877dd05578SSam Protsenko PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1), 17887dd05578SSam Protsenko }; 17897dd05578SSam Protsenko 17907dd05578SSam Protsenko static const struct samsung_div_clock dpu_div_clks[] __initconst = { 17917dd05578SSam Protsenko DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user", 17927dd05578SSam Protsenko CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), 17937dd05578SSam Protsenko }; 17947dd05578SSam Protsenko 17957dd05578SSam Protsenko static const struct samsung_gate_clock dpu_gate_clks[] __initconst = { 17966904d7e5SSam Protsenko /* TODO: Should be enabled in DSIM driver */ 17977dd05578SSam Protsenko GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk", 17986904d7e5SSam Protsenko "dout_dpu_busp", 17996904d7e5SSam Protsenko CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0), 18007dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user", 18017dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0), 18027dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user", 18037dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0), 18047dd05578SSam Protsenko GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user", 18057dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0), 18067dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user", 18077dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0), 18087dd05578SSam Protsenko GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp", 18097dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0), 18107dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user", 18117dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0), 18127dd05578SSam Protsenko GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp", 18137dd05578SSam Protsenko CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0), 18147dd05578SSam Protsenko }; 18157dd05578SSam Protsenko 18167dd05578SSam Protsenko static const struct samsung_cmu_info dpu_cmu_info __initconst = { 18177dd05578SSam Protsenko .mux_clks = dpu_mux_clks, 18187dd05578SSam Protsenko .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks), 18197dd05578SSam Protsenko .div_clks = dpu_div_clks, 18207dd05578SSam Protsenko .nr_div_clks = ARRAY_SIZE(dpu_div_clks), 18217dd05578SSam Protsenko .gate_clks = dpu_gate_clks, 18227dd05578SSam Protsenko .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), 1823*56d62cd4SKrzysztof Kozlowski .nr_clk_ids = CLKS_NR_DPU, 18247dd05578SSam Protsenko .clk_regs = dpu_clk_regs, 18257dd05578SSam Protsenko .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), 18267dd05578SSam Protsenko .clk_name = "dout_dpu", 18277dd05578SSam Protsenko }; 18287dd05578SSam Protsenko 18297dd05578SSam Protsenko /* ---- platform_driver ----------------------------------------------------- */ 18307dd05578SSam Protsenko 18317dd05578SSam Protsenko static int __init exynos850_cmu_probe(struct platform_device *pdev) 18327dd05578SSam Protsenko { 18337dd05578SSam Protsenko const struct samsung_cmu_info *info; 18347dd05578SSam Protsenko struct device *dev = &pdev->dev; 18357dd05578SSam Protsenko 18367dd05578SSam Protsenko info = of_device_get_match_data(dev); 1837cfe238e4SDavid Virag exynos_arm64_register_cmu(dev, dev->of_node, info); 18387dd05578SSam Protsenko 18397dd05578SSam Protsenko return 0; 18407dd05578SSam Protsenko } 18417dd05578SSam Protsenko 18427dd05578SSam Protsenko static const struct of_device_id exynos850_cmu_of_match[] = { 18437dd05578SSam Protsenko { 1844579839a9SSam Protsenko .compatible = "samsung,exynos850-cmu-apm", 1845579839a9SSam Protsenko .data = &apm_cmu_info, 1846579839a9SSam Protsenko }, { 1847b73fd95dSSam Protsenko .compatible = "samsung,exynos850-cmu-aud", 1848b73fd95dSSam Protsenko .data = &aud_cmu_info, 1849b73fd95dSSam Protsenko }, { 185062782ba8SSam Protsenko .compatible = "samsung,exynos850-cmu-cmgp", 185162782ba8SSam Protsenko .data = &cmgp_cmu_info, 185262782ba8SSam Protsenko }, { 1853e145c765SSam Protsenko .compatible = "samsung,exynos850-cmu-g3d", 1854e145c765SSam Protsenko .data = &g3d_cmu_info, 1855e145c765SSam Protsenko }, { 18567dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-hsi", 18577dd05578SSam Protsenko .data = &hsi_cmu_info, 18587dd05578SSam Protsenko }, { 1859bf3a4c51SSam Protsenko .compatible = "samsung,exynos850-cmu-is", 1860bf3a4c51SSam Protsenko .data = &is_cmu_info, 1861bf3a4c51SSam Protsenko }, { 18627f36d3b6SSam Protsenko .compatible = "samsung,exynos850-cmu-mfcmscl", 18637f36d3b6SSam Protsenko .data = &mfcmscl_cmu_info, 18647f36d3b6SSam Protsenko }, { 18657dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-core", 18667dd05578SSam Protsenko .data = &core_cmu_info, 18677dd05578SSam Protsenko }, { 18687dd05578SSam Protsenko .compatible = "samsung,exynos850-cmu-dpu", 18697dd05578SSam Protsenko .data = &dpu_cmu_info, 18707dd05578SSam Protsenko }, { 18717dd05578SSam Protsenko }, 18727dd05578SSam Protsenko }; 18737dd05578SSam Protsenko 18747dd05578SSam Protsenko static struct platform_driver exynos850_cmu_driver __refdata = { 18757dd05578SSam Protsenko .driver = { 18767dd05578SSam Protsenko .name = "exynos850-cmu", 18777dd05578SSam Protsenko .of_match_table = exynos850_cmu_of_match, 18787dd05578SSam Protsenko .suppress_bind_attrs = true, 18797dd05578SSam Protsenko }, 18807dd05578SSam Protsenko .probe = exynos850_cmu_probe, 18817dd05578SSam Protsenko }; 18827dd05578SSam Protsenko 18837dd05578SSam Protsenko static int __init exynos850_cmu_init(void) 18847dd05578SSam Protsenko { 18857dd05578SSam Protsenko return platform_driver_register(&exynos850_cmu_driver); 18867dd05578SSam Protsenko } 18877dd05578SSam Protsenko core_initcall(exynos850_cmu_init); 1888