1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
4  * Author: Dávid Virág <virag.david003@gmail.com>
5  *
6  * Common Clock Framework support for Exynos7885 SoC.
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 
15 #include <dt-bindings/clock/exynos7885.h>
16 
17 #include "clk.h"
18 #include "clk-exynos-arm64.h"
19 
20 /* ---- CMU_TOP ------------------------------------------------------------- */
21 
22 /* Register Offset definitions for CMU_TOP (0x12060000) */
23 #define PLL_LOCKTIME_PLL_SHARED0		0x0000
24 #define PLL_LOCKTIME_PLL_SHARED1		0x0004
25 #define PLL_CON0_PLL_SHARED0			0x0100
26 #define PLL_CON0_PLL_SHARED1			0x0120
27 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS		0x1014
28 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI		0x1018
29 #define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D		0x101c
30 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS		0x1028
31 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD	0x102c
32 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD	0x1030
33 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO	0x1034
34 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD	0x1038
35 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS		0x1058
36 #define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0	0x105c
37 #define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1	0x1060
38 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART0	0x1064
39 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART1	0x1068
40 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART2	0x106c
41 #define CLK_CON_MUX_MUX_CLKCMU_PERI_USI0	0x1070
42 #define CLK_CON_MUX_MUX_CLKCMU_PERI_USI1	0x1074
43 #define CLK_CON_MUX_MUX_CLKCMU_PERI_USI2	0x1078
44 #define CLK_CON_DIV_CLKCMU_CORE_BUS		0x181c
45 #define CLK_CON_DIV_CLKCMU_CORE_CCI		0x1820
46 #define CLK_CON_DIV_CLKCMU_CORE_G3D		0x1824
47 #define CLK_CON_DIV_CLKCMU_FSYS_BUS		0x1844
48 #define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD	0x1848
49 #define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD	0x184c
50 #define CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO	0x1850
51 #define CLK_CON_DIV_CLKCMU_FSYS_USB30DRD	0x1854
52 #define CLK_CON_DIV_CLKCMU_PERI_BUS		0x1874
53 #define CLK_CON_DIV_CLKCMU_PERI_SPI0		0x1878
54 #define CLK_CON_DIV_CLKCMU_PERI_SPI1		0x187c
55 #define CLK_CON_DIV_CLKCMU_PERI_UART0		0x1880
56 #define CLK_CON_DIV_CLKCMU_PERI_UART1		0x1884
57 #define CLK_CON_DIV_CLKCMU_PERI_UART2		0x1888
58 #define CLK_CON_DIV_CLKCMU_PERI_USI0		0x188c
59 #define CLK_CON_DIV_CLKCMU_PERI_USI1		0x1890
60 #define CLK_CON_DIV_CLKCMU_PERI_USI2		0x1894
61 #define CLK_CON_DIV_PLL_SHARED0_DIV2		0x189c
62 #define CLK_CON_DIV_PLL_SHARED0_DIV3		0x18a0
63 #define CLK_CON_DIV_PLL_SHARED0_DIV4		0x18a4
64 #define CLK_CON_DIV_PLL_SHARED0_DIV5		0x18a8
65 #define CLK_CON_DIV_PLL_SHARED1_DIV2		0x18ac
66 #define CLK_CON_DIV_PLL_SHARED1_DIV3		0x18b0
67 #define CLK_CON_DIV_PLL_SHARED1_DIV4		0x18b4
68 #define CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1	0x2004
69 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS	0x201c
70 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI	0x2020
71 #define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D	0x2024
72 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS	0x2044
73 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD	0x2048
74 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD	0x204c
75 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO	0x2050
76 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD	0x2054
77 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS	0x207c
78 #define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0	0x2080
79 #define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1	0x2084
80 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART0	0x2088
81 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART2	0x208c
82 #define CLK_CON_GAT_GATE_CLKCMU_PERI_USI0	0x2090
83 #define CLK_CON_GAT_GATE_CLKCMU_PERI_USI1	0x2094
84 #define CLK_CON_GAT_GATE_CLKCMU_PERI_USI2	0x2098
85 
86 static const unsigned long top_clk_regs[] __initconst = {
87 	PLL_LOCKTIME_PLL_SHARED0,
88 	PLL_LOCKTIME_PLL_SHARED1,
89 	PLL_CON0_PLL_SHARED0,
90 	PLL_CON0_PLL_SHARED1,
91 	CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
92 	CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
93 	CLK_CON_MUX_MUX_CLKCMU_CORE_G3D,
94 	CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS,
95 	CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD,
96 	CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD,
97 	CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO,
98 	CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD,
99 	CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
100 	CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0,
101 	CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1,
102 	CLK_CON_MUX_MUX_CLKCMU_PERI_UART0,
103 	CLK_CON_MUX_MUX_CLKCMU_PERI_UART1,
104 	CLK_CON_MUX_MUX_CLKCMU_PERI_UART2,
105 	CLK_CON_MUX_MUX_CLKCMU_PERI_USI0,
106 	CLK_CON_MUX_MUX_CLKCMU_PERI_USI1,
107 	CLK_CON_MUX_MUX_CLKCMU_PERI_USI2,
108 	CLK_CON_DIV_CLKCMU_CORE_BUS,
109 	CLK_CON_DIV_CLKCMU_CORE_CCI,
110 	CLK_CON_DIV_CLKCMU_CORE_G3D,
111 	CLK_CON_DIV_CLKCMU_FSYS_BUS,
112 	CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD,
113 	CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD,
114 	CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO,
115 	CLK_CON_DIV_CLKCMU_FSYS_USB30DRD,
116 	CLK_CON_DIV_CLKCMU_PERI_BUS,
117 	CLK_CON_DIV_CLKCMU_PERI_SPI0,
118 	CLK_CON_DIV_CLKCMU_PERI_SPI1,
119 	CLK_CON_DIV_CLKCMU_PERI_UART0,
120 	CLK_CON_DIV_CLKCMU_PERI_UART1,
121 	CLK_CON_DIV_CLKCMU_PERI_UART2,
122 	CLK_CON_DIV_CLKCMU_PERI_USI0,
123 	CLK_CON_DIV_CLKCMU_PERI_USI1,
124 	CLK_CON_DIV_CLKCMU_PERI_USI2,
125 	CLK_CON_DIV_PLL_SHARED0_DIV2,
126 	CLK_CON_DIV_PLL_SHARED0_DIV3,
127 	CLK_CON_DIV_PLL_SHARED0_DIV4,
128 	CLK_CON_DIV_PLL_SHARED0_DIV5,
129 	CLK_CON_DIV_PLL_SHARED1_DIV2,
130 	CLK_CON_DIV_PLL_SHARED1_DIV3,
131 	CLK_CON_DIV_PLL_SHARED1_DIV4,
132 	CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1,
133 	CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
134 	CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
135 	CLK_CON_GAT_GATE_CLKCMU_CORE_G3D,
136 	CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS,
137 	CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD,
138 	CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD,
139 	CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO,
140 	CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD,
141 	CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
142 	CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0,
143 	CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1,
144 	CLK_CON_GAT_GATE_CLKCMU_PERI_UART0,
145 	CLK_CON_GAT_GATE_CLKCMU_PERI_UART2,
146 	CLK_CON_GAT_GATE_CLKCMU_PERI_USI0,
147 	CLK_CON_GAT_GATE_CLKCMU_PERI_USI1,
148 	CLK_CON_GAT_GATE_CLKCMU_PERI_USI2,
149 };
150 
151 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
152 	PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
153 	    PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
154 	    NULL),
155 	PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
156 	    PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1,
157 	    NULL),
158 };
159 
160 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
161 PNAME(mout_core_bus_p)		= { "dout_shared0_div2", "dout_shared1_div2",
162 				    "dout_shared0_div3", "dout_shared0_div3" };
163 PNAME(mout_core_cci_p)		= { "dout_shared0_div2", "dout_shared1_div2",
164 				    "dout_shared0_div3", "dout_shared0_div3" };
165 PNAME(mout_core_g3d_p)		= { "dout_shared0_div2", "dout_shared1_div2",
166 				    "dout_shared0_div3", "dout_shared0_div3" };
167 
168 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
169 PNAME(mout_peri_bus_p)		= { "dout_shared0_div4", "dout_shared1_div4" };
170 PNAME(mout_peri_spi0_p)		= { "oscclk", "dout_shared0_div4" };
171 PNAME(mout_peri_spi1_p)		= { "oscclk", "dout_shared0_div4" };
172 PNAME(mout_peri_uart0_p)	= { "oscclk", "dout_shared0_div4" };
173 PNAME(mout_peri_uart1_p)	= { "oscclk", "dout_shared0_div4" };
174 PNAME(mout_peri_uart2_p)	= { "oscclk", "dout_shared0_div4" };
175 PNAME(mout_peri_usi0_p)		= { "oscclk", "dout_shared0_div4" };
176 PNAME(mout_peri_usi1_p)		= { "oscclk", "dout_shared0_div4" };
177 PNAME(mout_peri_usi2_p)		= { "oscclk", "dout_shared0_div4" };
178 
179 /* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */
180 PNAME(mout_fsys_bus_p)		= { "dout_shared0_div2", "dout_shared1_div2" };
181 PNAME(mout_fsys_mmc_card_p)	= { "dout_shared0_div2", "dout_shared1_div2" };
182 PNAME(mout_fsys_mmc_embd_p)	= { "dout_shared0_div2", "dout_shared1_div2" };
183 PNAME(mout_fsys_mmc_sdio_p)	= { "dout_shared0_div2", "dout_shared1_div2" };
184 PNAME(mout_fsys_usb30drd_p)	= { "dout_shared0_div4", "dout_shared1_div4" };
185 
186 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
187 	/* CORE */
188 	MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
189 	    CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
190 	MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
191 	    CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
192 	MUX(CLK_MOUT_CORE_G3D, "mout_core_g3d", mout_core_g3d_p,
193 	    CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2),
194 
195 	/* PERI */
196 	MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
197 	    CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
198 	MUX(CLK_MOUT_PERI_SPI0, "mout_peri_spi0", mout_peri_spi0_p,
199 	    CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, 0, 1),
200 	MUX(CLK_MOUT_PERI_SPI1, "mout_peri_spi1", mout_peri_spi1_p,
201 	    CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, 0, 1),
202 	MUX(CLK_MOUT_PERI_UART0, "mout_peri_uart0", mout_peri_uart0_p,
203 	    CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, 0, 1),
204 	MUX(CLK_MOUT_PERI_UART1, "mout_peri_uart1", mout_peri_uart1_p,
205 	    CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, 0, 1),
206 	MUX(CLK_MOUT_PERI_UART2, "mout_peri_uart2", mout_peri_uart2_p,
207 	    CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, 0, 1),
208 	MUX(CLK_MOUT_PERI_USI0, "mout_peri_usi0", mout_peri_usi0_p,
209 	    CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 0, 1),
210 	MUX(CLK_MOUT_PERI_USI1, "mout_peri_usi1", mout_peri_usi1_p,
211 	    CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1),
212 	MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p,
213 	    CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1),
214 
215 	/* FSYS */
216 	MUX(CLK_MOUT_FSYS_BUS, "mout_fsys_bus", mout_fsys_bus_p,
217 	    CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1),
218 	MUX(CLK_MOUT_FSYS_MMC_CARD, "mout_fsys_mmc_card", mout_fsys_mmc_card_p,
219 	    CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 1),
220 	MUX(CLK_MOUT_FSYS_MMC_EMBD, "mout_fsys_mmc_embd", mout_fsys_mmc_embd_p,
221 	    CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 1),
222 	MUX(CLK_MOUT_FSYS_MMC_SDIO, "mout_fsys_mmc_sdio", mout_fsys_mmc_sdio_p,
223 	    CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 0, 1),
224 	MUX(CLK_MOUT_FSYS_USB30DRD, "mout_fsys_usb30drd", mout_fsys_usb30drd_p,
225 	    CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, 0, 1),
226 };
227 
228 static const struct samsung_div_clock top_div_clks[] __initconst = {
229 	/* TOP */
230 	DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "fout_shared0_pll",
231 	    CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
232 	DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
233 	    CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
234 	DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
235 	    CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
236 	DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
237 	    CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
238 	DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "fout_shared1_pll",
239 	    CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
240 	DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
241 	    CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
242 	DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
243 	    CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
244 
245 	/* CORE */
246 	DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
247 	    CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 3),
248 	DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
249 	    CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 3),
250 	DIV(CLK_DOUT_CORE_G3D, "dout_core_g3d", "gout_core_g3d",
251 	    CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 3),
252 
253 	/* PERI */
254 	DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
255 	    CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
256 	DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "gout_peri_spi0",
257 	    CLK_CON_DIV_CLKCMU_PERI_SPI0, 0, 6),
258 	DIV(CLK_DOUT_PERI_SPI1, "dout_peri_spi1", "gout_peri_spi1",
259 	    CLK_CON_DIV_CLKCMU_PERI_SPI1, 0, 6),
260 	DIV(CLK_DOUT_PERI_UART0, "dout_peri_uart0", "gout_peri_uart0",
261 	    CLK_CON_DIV_CLKCMU_PERI_UART0, 0, 4),
262 	DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "gout_peri_uart1",
263 	    CLK_CON_DIV_CLKCMU_PERI_UART1, 0, 4),
264 	DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "gout_peri_uart2",
265 	    CLK_CON_DIV_CLKCMU_PERI_UART2, 0, 4),
266 	DIV(CLK_DOUT_PERI_USI0, "dout_peri_usi0", "gout_peri_usi0",
267 	    CLK_CON_DIV_CLKCMU_PERI_USI0, 0, 4),
268 	DIV(CLK_DOUT_PERI_USI1, "dout_peri_usi1", "gout_peri_usi1",
269 	    CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4),
270 	DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2",
271 	    CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4),
272 
273 	/* FSYS */
274 	DIV(CLK_DOUT_FSYS_BUS, "dout_fsys_bus", "gout_fsys_bus",
275 	    CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4),
276 	DIV(CLK_DOUT_FSYS_MMC_CARD, "dout_fsys_mmc_card", "gout_fsys_mmc_card",
277 	    CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9),
278 	DIV(CLK_DOUT_FSYS_MMC_EMBD, "dout_fsys_mmc_embd", "gout_fsys_mmc_embd",
279 	    CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9),
280 	DIV(CLK_DOUT_FSYS_MMC_SDIO, "dout_fsys_mmc_sdio", "gout_fsys_mmc_sdio",
281 	    CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 0, 9),
282 	DIV(CLK_DOUT_FSYS_USB30DRD, "dout_fsys_usb30drd", "gout_fsys_usb30drd",
283 	    CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, 0, 4),
284 };
285 
286 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
287 	/* CORE */
288 	GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
289 	     CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
290 	GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
291 	     CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
292 	GATE(CLK_GOUT_CORE_G3D, "gout_core_g3d", "mout_core_g3d",
293 	     CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, 0, 0),
294 
295 	/* PERI */
296 	GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
297 	     CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
298 	GATE(CLK_GOUT_PERI_SPI0, "gout_peri_spi0", "mout_peri_spi0",
299 	     CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, 21, 0, 0),
300 	GATE(CLK_GOUT_PERI_SPI1, "gout_peri_spi1", "mout_peri_spi1",
301 	     CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, 21, 0, 0),
302 	GATE(CLK_GOUT_PERI_UART0, "gout_peri_uart0", "mout_peri_uart0",
303 	     CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, 21, 0, 0),
304 	GATE(CLK_GOUT_PERI_UART1, "gout_peri_uart1", "mout_peri_uart1",
305 	     CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, 21, 0, 0),
306 	GATE(CLK_GOUT_PERI_UART2, "gout_peri_uart2", "mout_peri_uart2",
307 	     CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, 21, 0, 0),
308 	GATE(CLK_GOUT_PERI_USI0, "gout_peri_usi0", "mout_peri_usi0",
309 	     CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 21, 0, 0),
310 	GATE(CLK_GOUT_PERI_USI1, "gout_peri_usi1", "mout_peri_usi1",
311 	     CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0),
312 	GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2",
313 	     CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0),
314 
315 	/* FSYS */
316 	GATE(CLK_GOUT_FSYS_BUS, "gout_fsys_bus", "mout_fsys_bus",
317 	     CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0),
318 	GATE(CLK_GOUT_FSYS_MMC_CARD, "gout_fsys_mmc_card", "mout_fsys_mmc_card",
319 	     CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0),
320 	GATE(CLK_GOUT_FSYS_MMC_EMBD, "gout_fsys_mmc_embd", "mout_fsys_mmc_embd",
321 	     CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0),
322 	GATE(CLK_GOUT_FSYS_MMC_SDIO, "gout_fsys_mmc_sdio", "mout_fsys_mmc_sdio",
323 	     CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 21, 0, 0),
324 	GATE(CLK_GOUT_FSYS_USB30DRD, "gout_fsys_usb30drd", "mout_fsys_usb30drd",
325 	     CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, 21, 0, 0),
326 };
327 
328 static const struct samsung_cmu_info top_cmu_info __initconst = {
329 	.pll_clks		= top_pll_clks,
330 	.nr_pll_clks		= ARRAY_SIZE(top_pll_clks),
331 	.mux_clks		= top_mux_clks,
332 	.nr_mux_clks		= ARRAY_SIZE(top_mux_clks),
333 	.div_clks		= top_div_clks,
334 	.nr_div_clks		= ARRAY_SIZE(top_div_clks),
335 	.gate_clks		= top_gate_clks,
336 	.nr_gate_clks		= ARRAY_SIZE(top_gate_clks),
337 	.nr_clk_ids		= TOP_NR_CLK,
338 	.clk_regs		= top_clk_regs,
339 	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
340 };
341 
342 static void __init exynos7885_cmu_top_init(struct device_node *np)
343 {
344 	exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
345 }
346 
347 /* Register CMU_TOP early, as it's a dependency for other early domains */
348 CLK_OF_DECLARE(exynos7885_cmu_top, "samsung,exynos7885-cmu-top",
349 	       exynos7885_cmu_top_init);
350 
351 /* ---- CMU_PERI ------------------------------------------------------------ */
352 
353 /* Register Offset definitions for CMU_PERI (0x10010000) */
354 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER	0x0100
355 #define PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER	0x0120
356 #define PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER	0x0140
357 #define PLL_CON0_MUX_CLKCMU_PERI_UART0_USER	0x0160
358 #define PLL_CON0_MUX_CLKCMU_PERI_UART1_USER	0x0180
359 #define PLL_CON0_MUX_CLKCMU_PERI_UART2_USER	0x01a0
360 #define PLL_CON0_MUX_CLKCMU_PERI_USI0_USER	0x01c0
361 #define PLL_CON0_MUX_CLKCMU_PERI_USI1_USER	0x01e0
362 #define PLL_CON0_MUX_CLKCMU_PERI_USI2_USER	0x0200
363 #define CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK	0x2024
364 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK	0x2028
365 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK	0x202c
366 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK	0x2030
367 #define CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK	0x2034
368 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK	0x2038
369 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK	0x203c
370 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK	0x2040
371 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK	0x2044
372 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK	0x2048
373 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK	0x204c
374 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK	0x2050
375 #define CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK	0x2054
376 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK	0x2058
377 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK	0x205c
378 #define CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK	0x2060
379 #define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK	0x2064
380 #define CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK	0x2068
381 #define CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK	0x206c
382 #define CLK_CON_GAT_GOUT_PERI_UART_0_PCLK	0x2070
383 #define CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK	0x2074
384 #define CLK_CON_GAT_GOUT_PERI_UART_1_PCLK	0x2078
385 #define CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK	0x207c
386 #define CLK_CON_GAT_GOUT_PERI_UART_2_PCLK	0x2080
387 #define CLK_CON_GAT_GOUT_PERI_USI0_PCLK		0x2084
388 #define CLK_CON_GAT_GOUT_PERI_USI0_SCLK		0x2088
389 #define CLK_CON_GAT_GOUT_PERI_USI1_PCLK		0x208c
390 #define CLK_CON_GAT_GOUT_PERI_USI1_SCLK		0x2090
391 #define CLK_CON_GAT_GOUT_PERI_USI2_PCLK		0x2094
392 #define CLK_CON_GAT_GOUT_PERI_USI2_SCLK		0x2098
393 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK		0x20a0
394 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK	0x20b0
395 #define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK	0x20b4
396 #define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK	0x20b8
397 
398 static const unsigned long peri_clk_regs[] __initconst = {
399 	PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
400 	PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER,
401 	PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER,
402 	PLL_CON0_MUX_CLKCMU_PERI_UART0_USER,
403 	PLL_CON0_MUX_CLKCMU_PERI_UART1_USER,
404 	PLL_CON0_MUX_CLKCMU_PERI_UART2_USER,
405 	PLL_CON0_MUX_CLKCMU_PERI_USI0_USER,
406 	PLL_CON0_MUX_CLKCMU_PERI_USI1_USER,
407 	PLL_CON0_MUX_CLKCMU_PERI_USI2_USER,
408 	CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK,
409 	CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
410 	CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
411 	CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
412 	CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK,
413 	CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
414 	CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
415 	CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
416 	CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
417 	CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
418 	CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
419 	CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
420 	CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK,
421 	CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
422 	CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
423 	CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK,
424 	CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK,
425 	CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK,
426 	CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK,
427 	CLK_CON_GAT_GOUT_PERI_UART_0_PCLK,
428 	CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK,
429 	CLK_CON_GAT_GOUT_PERI_UART_1_PCLK,
430 	CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK,
431 	CLK_CON_GAT_GOUT_PERI_UART_2_PCLK,
432 	CLK_CON_GAT_GOUT_PERI_USI0_PCLK,
433 	CLK_CON_GAT_GOUT_PERI_USI0_SCLK,
434 	CLK_CON_GAT_GOUT_PERI_USI1_PCLK,
435 	CLK_CON_GAT_GOUT_PERI_USI1_SCLK,
436 	CLK_CON_GAT_GOUT_PERI_USI2_PCLK,
437 	CLK_CON_GAT_GOUT_PERI_USI2_SCLK,
438 	CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
439 	CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
440 	CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK,
441 	CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK,
442 };
443 
444 /* List of parent clocks for Muxes in CMU_PERI */
445 PNAME(mout_peri_bus_user_p)	= { "oscclk", "dout_peri_bus" };
446 PNAME(mout_peri_spi0_user_p)	= { "oscclk", "dout_peri_spi0" };
447 PNAME(mout_peri_spi1_user_p)	= { "oscclk", "dout_peri_spi1" };
448 PNAME(mout_peri_uart0_user_p)	= { "oscclk", "dout_peri_uart0" };
449 PNAME(mout_peri_uart1_user_p)	= { "oscclk", "dout_peri_uart1" };
450 PNAME(mout_peri_uart2_user_p)	= { "oscclk", "dout_peri_uart2" };
451 PNAME(mout_peri_usi0_user_p)	= { "oscclk", "dout_peri_usi0" };
452 PNAME(mout_peri_usi1_user_p)	= { "oscclk", "dout_peri_usi1" };
453 PNAME(mout_peri_usi2_user_p)	= { "oscclk", "dout_peri_usi2" };
454 
455 static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
456 	MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
457 	    PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
458 	MUX(CLK_MOUT_PERI_SPI0_USER, "mout_peri_spi0_user", mout_peri_spi0_user_p,
459 	    PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, 4, 1),
460 	MUX(CLK_MOUT_PERI_SPI1_USER, "mout_peri_spi1_user", mout_peri_spi1_user_p,
461 	    PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, 4, 1),
462 	MUX(CLK_MOUT_PERI_UART0_USER, "mout_peri_uart0_user",
463 	    mout_peri_uart0_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, 4, 1),
464 	MUX(CLK_MOUT_PERI_UART1_USER, "mout_peri_uart1_user",
465 	    mout_peri_uart1_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, 4, 1),
466 	MUX(CLK_MOUT_PERI_UART2_USER, "mout_peri_uart2_user",
467 	    mout_peri_uart2_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, 4, 1),
468 	MUX(CLK_MOUT_PERI_USI0_USER, "mout_peri_usi0_user",
469 	    mout_peri_usi0_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, 4, 1),
470 	MUX(CLK_MOUT_PERI_USI1_USER, "mout_peri_usi1_user",
471 	    mout_peri_usi1_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, 4, 1),
472 	MUX(CLK_MOUT_PERI_USI2_USER, "mout_peri_usi2_user",
473 	    mout_peri_usi2_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, 4, 1),
474 };
475 
476 static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
477 	/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
478 	GATE(CLK_GOUT_GPIO_TOP_PCLK, "gout_gpio_top_pclk",
479 	     "mout_peri_bus_user",
480 	     CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, 21, CLK_IGNORE_UNUSED, 0),
481 	GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
482 	     CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
483 	GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
484 	     CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
485 	GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
486 	     CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
487 	GATE(CLK_GOUT_HSI2C3_PCLK, "gout_hsi2c3_pclk", "mout_peri_bus_user",
488 	     CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, 21, 0, 0),
489 	GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
490 	     CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
491 	GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
492 	     CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
493 	GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
494 	     CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
495 	GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
496 	     CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
497 	GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
498 	     CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
499 	GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
500 	     CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
501 	GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
502 	     CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
503 	GATE(CLK_GOUT_I2C7_PCLK, "gout_i2c7_pclk", "mout_peri_bus_user",
504 	     CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, 21, 0, 0),
505 	GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
506 	     "mout_peri_bus_user",
507 	     CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
508 	GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
509 	     CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
510 	GATE(CLK_GOUT_SPI0_EXT_CLK, "gout_spi0_ipclk", "mout_peri_spi0_user",
511 	     CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, 21, 0, 0),
512 	GATE(CLK_GOUT_SPI1_PCLK, "gout_spi1_pclk", "mout_peri_bus_user",
513 	     CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, 0, 0),
514 	GATE(CLK_GOUT_SPI1_EXT_CLK, "gout_spi1_ipclk", "mout_peri_spi1_user",
515 	     CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, 21, 0, 0),
516 	GATE(CLK_GOUT_UART0_EXT_UCLK, "gout_uart0_ext_uclk", "mout_peri_uart0_user",
517 	     CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, 21, 0, 0),
518 	GATE(CLK_GOUT_UART0_PCLK, "gout_uart0_pclk", "mout_peri_bus_user",
519 	     CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, 21, 0, 0),
520 	GATE(CLK_GOUT_UART1_EXT_UCLK, "gout_uart1_ext_uclk", "mout_peri_uart1_user",
521 	     CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, 21, 0, 0),
522 	GATE(CLK_GOUT_UART1_PCLK, "gout_uart1_pclk", "mout_peri_bus_user",
523 	     CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, 21, 0, 0),
524 	GATE(CLK_GOUT_UART2_EXT_UCLK, "gout_uart2_ext_uclk", "mout_peri_uart2_user",
525 	     CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, 21, 0, 0),
526 	GATE(CLK_GOUT_UART2_PCLK, "gout_uart2_pclk", "mout_peri_bus_user",
527 	     CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, 21, 0, 0),
528 	GATE(CLK_GOUT_USI0_PCLK, "gout_usi0_pclk", "mout_peri_bus_user",
529 	     CLK_CON_GAT_GOUT_PERI_USI0_PCLK, 21, 0, 0),
530 	GATE(CLK_GOUT_USI0_SCLK, "gout_usi0_sclk", "mout_peri_usi0_user",
531 	     CLK_CON_GAT_GOUT_PERI_USI0_SCLK, 21, 0, 0),
532 	GATE(CLK_GOUT_USI1_PCLK, "gout_usi1_pclk", "mout_peri_bus_user",
533 	     CLK_CON_GAT_GOUT_PERI_USI1_PCLK, 21, 0, 0),
534 	GATE(CLK_GOUT_USI1_SCLK, "gout_usi1_sclk", "mout_peri_usi1_user",
535 	     CLK_CON_GAT_GOUT_PERI_USI1_SCLK, 21, 0, 0),
536 	GATE(CLK_GOUT_USI2_PCLK, "gout_usi2_pclk", "mout_peri_bus_user",
537 	     CLK_CON_GAT_GOUT_PERI_USI2_PCLK, 21, 0, 0),
538 	GATE(CLK_GOUT_USI2_SCLK, "gout_usi2_sclk", "mout_peri_usi2_user",
539 	     CLK_CON_GAT_GOUT_PERI_USI2_SCLK, 21, 0, 0),
540 	GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
541 	     CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
542 	GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
543 	     "mout_peri_bus_user",
544 	     CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
545 	GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
546 	     CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, 21, 0, 0),
547 	GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
548 	     CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, 21, 0, 0),
549 };
550 
551 static const struct samsung_cmu_info peri_cmu_info __initconst = {
552 	.mux_clks		= peri_mux_clks,
553 	.nr_mux_clks		= ARRAY_SIZE(peri_mux_clks),
554 	.gate_clks		= peri_gate_clks,
555 	.nr_gate_clks		= ARRAY_SIZE(peri_gate_clks),
556 	.nr_clk_ids		= PERI_NR_CLK,
557 	.clk_regs		= peri_clk_regs,
558 	.nr_clk_regs		= ARRAY_SIZE(peri_clk_regs),
559 	.clk_name		= "dout_peri_bus",
560 };
561 
562 static void __init exynos7885_cmu_peri_init(struct device_node *np)
563 {
564 	exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
565 }
566 
567 /* Register CMU_PERI early, as it's needed for MCT timer */
568 CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri",
569 	       exynos7885_cmu_peri_init);
570 
571 /* ---- CMU_CORE ------------------------------------------------------------ */
572 
573 /* Register Offset definitions for CMU_CORE (0x12000000) */
574 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER		0x0100
575 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER		0x0120
576 #define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER		0x0140
577 #define CLK_CON_MUX_MUX_CLK_CORE_GIC			0x1000
578 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP			0x1800
579 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK		0x2054
580 #define CLK_CON_GAT_GOUT_CORE_GIC400_CLK		0x2058
581 #define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK		0x215c
582 #define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK		0x2160
583 #define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK		0x2164
584 #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE	0x2168
585 #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE	0x216c
586 #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK		0x2170
587 #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE	0x2174
588 
589 static const unsigned long core_clk_regs[] __initconst = {
590 	PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
591 	PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
592 	PLL_CON0_MUX_CLKCMU_CORE_G3D_USER,
593 	CLK_CON_MUX_MUX_CLK_CORE_GIC,
594 	CLK_CON_DIV_DIV_CLK_CORE_BUSP,
595 	CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
596 	CLK_CON_GAT_GOUT_CORE_GIC400_CLK,
597 	CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK,
598 	CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK,
599 	CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK,
600 	CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE,
601 	CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE,
602 	CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK,
603 	CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE,
604 };
605 
606 /* List of parent clocks for Muxes in CMU_CORE */
607 PNAME(mout_core_bus_user_p)		= { "oscclk", "dout_core_bus" };
608 PNAME(mout_core_cci_user_p)		= { "oscclk", "dout_core_cci" };
609 PNAME(mout_core_g3d_user_p)		= { "oscclk", "dout_core_g3d" };
610 PNAME(mout_core_gic_p)			= { "dout_core_busp", "oscclk" };
611 
612 static const struct samsung_mux_clock core_mux_clks[] __initconst = {
613 	MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
614 	    PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
615 	MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
616 	    PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
617 	MUX(CLK_MOUT_CORE_G3D_USER, "mout_core_g3d_user", mout_core_g3d_user_p,
618 	    PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 4, 1),
619 	MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
620 	    CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
621 };
622 
623 static const struct samsung_div_clock core_div_clks[] __initconst = {
624 	DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
625 	    CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
626 };
627 
628 static const struct samsung_gate_clock core_gate_clks[] __initconst = {
629 	/* CCI (interconnect) clock must be always running */
630 	GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
631 	     CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
632 	/* GIC (interrupt controller) clock must be always running */
633 	GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic",
634 	     CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0),
635 	/*
636 	 * TREX D and P Core (seems to be related to "bus traffic shaper")
637 	 * clocks must always be running
638 	 */
639 	GATE(CLK_GOUT_TREX_D_CORE_ACLK, "gout_trex_d_core_aclk", "mout_core_bus_user",
640 	     CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, 21, CLK_IS_CRITICAL, 0),
641 	GATE(CLK_GOUT_TREX_D_CORE_GCLK, "gout_trex_d_core_gclk", "mout_core_g3d_user",
642 	     CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, 21, CLK_IS_CRITICAL, 0),
643 	GATE(CLK_GOUT_TREX_D_CORE_PCLK, "gout_trex_d_core_pclk", "dout_core_busp",
644 	     CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),
645 	GATE(CLK_GOUT_TREX_P_CORE_ACLK_P_CORE, "gout_trex_p_core_aclk_p_core",
646 	     "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, 21,
647 	     CLK_IS_CRITICAL, 0),
648 	GATE(CLK_GOUT_TREX_P_CORE_CCLK_P_CORE, "gout_trex_p_core_cclk_p_core",
649 	     "mout_core_cci_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, 21,
650 	     CLK_IS_CRITICAL, 0),
651 	GATE(CLK_GOUT_TREX_P_CORE_PCLK, "gout_trex_p_core_pclk", "dout_core_busp",
652 	     CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),
653 	GATE(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE, "gout_trex_p_core_pclk_p_core",
654 	     "dout_core_busp", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, 21,
655 	     CLK_IS_CRITICAL, 0),
656 };
657 
658 static const struct samsung_cmu_info core_cmu_info __initconst = {
659 	.mux_clks		= core_mux_clks,
660 	.nr_mux_clks		= ARRAY_SIZE(core_mux_clks),
661 	.div_clks		= core_div_clks,
662 	.nr_div_clks		= ARRAY_SIZE(core_div_clks),
663 	.gate_clks		= core_gate_clks,
664 	.nr_gate_clks		= ARRAY_SIZE(core_gate_clks),
665 	.nr_clk_ids		= CORE_NR_CLK,
666 	.clk_regs		= core_clk_regs,
667 	.nr_clk_regs		= ARRAY_SIZE(core_clk_regs),
668 	.clk_name		= "dout_core_bus",
669 };
670 
671 /* ---- CMU_FSYS ------------------------------------------------------------ */
672 
673 /* Register Offset definitions for CMU_FSYS (0x13400000) */
674 #define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER	0x0100
675 #define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER	0x0120
676 #define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER	0x0140
677 #define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER	0x0160
678 #define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER	0x0180
679 #define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK	0x2030
680 #define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN	0x2034
681 #define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK	0x2038
682 #define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN	0x203c
683 #define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK	0x2040
684 #define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN	0x2044
685 
686 static const unsigned long fsys_clk_regs[] __initconst = {
687 	PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,
688 	PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
689 	PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
690 	PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
691 	PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
692 	CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK,
693 	CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
694 	CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK,
695 	CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
696 	CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK,
697 	CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
698 };
699 
700 /* List of parent clocks for Muxes in CMU_FSYS */
701 PNAME(mout_fsys_bus_user_p)		= { "oscclk", "dout_fsys_bus" };
702 PNAME(mout_fsys_mmc_card_user_p)	= { "oscclk", "dout_fsys_mmc_card" };
703 PNAME(mout_fsys_mmc_embd_user_p)	= { "oscclk", "dout_fsys_mmc_embd" };
704 PNAME(mout_fsys_mmc_sdio_user_p)	= { "oscclk", "dout_fsys_mmc_sdio" };
705 PNAME(mout_fsys_usb30drd_user_p)	= { "oscclk", "dout_fsys_usb30drd" };
706 
707 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
708 	MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p,
709 	    PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 4, 1),
710 	MUX_F(CLK_MOUT_FSYS_MMC_CARD_USER, "mout_fsys_mmc_card_user",
711 	      mout_fsys_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
712 	      4, 1, CLK_SET_RATE_PARENT, 0),
713 	MUX_F(CLK_MOUT_FSYS_MMC_EMBD_USER, "mout_fsys_mmc_embd_user",
714 	      mout_fsys_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
715 	      4, 1, CLK_SET_RATE_PARENT, 0),
716 	MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user",
717 	      mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
718 	      4, 1, CLK_SET_RATE_PARENT, 0),
719 	MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
720 	      mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
721 	      4, 1, CLK_SET_RATE_PARENT, 0),
722 };
723 
724 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
725 	GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user",
726 	     CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),
727 	GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
728 	     "mout_fsys_mmc_card_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
729 	     21, CLK_SET_RATE_PARENT, 0),
730 	GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "mout_fsys_bus_user",
731 	     CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, 21, 0, 0),
732 	GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
733 	     "mout_fsys_mmc_embd_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
734 	     21, CLK_SET_RATE_PARENT, 0),
735 	GATE(CLK_GOUT_MMC_SDIO_ACLK, "gout_mmc_sdio_aclk", "mout_fsys_bus_user",
736 	     CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, 21, 0, 0),
737 	GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin",
738 	     "mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
739 	     21, CLK_SET_RATE_PARENT, 0),
740 };
741 
742 static const struct samsung_cmu_info fsys_cmu_info __initconst = {
743 	.mux_clks		= fsys_mux_clks,
744 	.nr_mux_clks		= ARRAY_SIZE(fsys_mux_clks),
745 	.gate_clks		= fsys_gate_clks,
746 	.nr_gate_clks		= ARRAY_SIZE(fsys_gate_clks),
747 	.nr_clk_ids		= FSYS_NR_CLK,
748 	.clk_regs		= fsys_clk_regs,
749 	.nr_clk_regs		= ARRAY_SIZE(fsys_clk_regs),
750 	.clk_name		= "dout_fsys_bus",
751 };
752 
753 /* ---- platform_driver ----------------------------------------------------- */
754 
755 static int __init exynos7885_cmu_probe(struct platform_device *pdev)
756 {
757 	const struct samsung_cmu_info *info;
758 	struct device *dev = &pdev->dev;
759 
760 	info = of_device_get_match_data(dev);
761 	exynos_arm64_register_cmu(dev, dev->of_node, info);
762 
763 	return 0;
764 }
765 
766 static const struct of_device_id exynos7885_cmu_of_match[] = {
767 	{
768 		.compatible = "samsung,exynos7885-cmu-core",
769 		.data = &core_cmu_info,
770 	}, {
771 		.compatible = "samsung,exynos7885-cmu-fsys",
772 		.data = &fsys_cmu_info,
773 	}, {
774 	},
775 };
776 
777 static struct platform_driver exynos7885_cmu_driver __refdata = {
778 	.driver	= {
779 		.name = "exynos7885-cmu",
780 		.of_match_table = exynos7885_cmu_of_match,
781 		.suppress_bind_attrs = true,
782 	},
783 	.probe = exynos7885_cmu_probe,
784 };
785 
786 static int __init exynos7885_cmu_init(void)
787 {
788 	return platform_driver_register(&exynos7885_cmu_driver);
789 }
790 core_initcall(exynos7885_cmu_init);
791