1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com> 4 * Author: Dávid Virág <virag.david003@gmail.com> 5 * 6 * Common Clock Framework support for Exynos7885 SoC. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 15 #include <dt-bindings/clock/exynos7885.h> 16 17 #include "clk.h" 18 #include "clk-exynos-arm64.h" 19 20 /* NOTE: Must be equal to the last clock ID increased by one */ 21 #define CLKS_NR_TOP (CLK_GOUT_FSYS_USB30DRD + 1) 22 #define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1) 23 #define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1) 24 #define CLKS_NR_FSYS (CLK_GOUT_MMC_SDIO_SDCLKIN + 1) 25 26 /* ---- CMU_TOP ------------------------------------------------------------- */ 27 28 /* Register Offset definitions for CMU_TOP (0x12060000) */ 29 #define PLL_LOCKTIME_PLL_SHARED0 0x0000 30 #define PLL_LOCKTIME_PLL_SHARED1 0x0004 31 #define PLL_CON0_PLL_SHARED0 0x0100 32 #define PLL_CON0_PLL_SHARED1 0x0120 33 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 34 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 35 #define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c 36 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS 0x1028 37 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD 0x102c 38 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD 0x1030 39 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO 0x1034 40 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD 0x1038 41 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058 42 #define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c 43 #define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060 44 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART0 0x1064 45 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART1 0x1068 46 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART2 0x106c 47 #define CLK_CON_MUX_MUX_CLKCMU_PERI_USI0 0x1070 48 #define CLK_CON_MUX_MUX_CLKCMU_PERI_USI1 0x1074 49 #define CLK_CON_MUX_MUX_CLKCMU_PERI_USI2 0x1078 50 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c 51 #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820 52 #define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824 53 #define CLK_CON_DIV_CLKCMU_FSYS_BUS 0x1844 54 #define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD 0x1848 55 #define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD 0x184c 56 #define CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO 0x1850 57 #define CLK_CON_DIV_CLKCMU_FSYS_USB30DRD 0x1854 58 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874 59 #define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878 60 #define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c 61 #define CLK_CON_DIV_CLKCMU_PERI_UART0 0x1880 62 #define CLK_CON_DIV_CLKCMU_PERI_UART1 0x1884 63 #define CLK_CON_DIV_CLKCMU_PERI_UART2 0x1888 64 #define CLK_CON_DIV_CLKCMU_PERI_USI0 0x188c 65 #define CLK_CON_DIV_CLKCMU_PERI_USI1 0x1890 66 #define CLK_CON_DIV_CLKCMU_PERI_USI2 0x1894 67 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x189c 68 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18a0 69 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18a4 70 #define CLK_CON_DIV_PLL_SHARED0_DIV5 0x18a8 71 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18ac 72 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18b0 73 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18b4 74 #define CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1 0x2004 75 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c 76 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 77 #define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024 78 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS 0x2044 79 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD 0x2048 80 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD 0x204c 81 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO 0x2050 82 #define CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD 0x2054 83 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c 84 #define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080 85 #define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084 86 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART0 0x2088 87 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART2 0x208c 88 #define CLK_CON_GAT_GATE_CLKCMU_PERI_USI0 0x2090 89 #define CLK_CON_GAT_GATE_CLKCMU_PERI_USI1 0x2094 90 #define CLK_CON_GAT_GATE_CLKCMU_PERI_USI2 0x2098 91 92 static const unsigned long top_clk_regs[] __initconst = { 93 PLL_LOCKTIME_PLL_SHARED0, 94 PLL_LOCKTIME_PLL_SHARED1, 95 PLL_CON0_PLL_SHARED0, 96 PLL_CON0_PLL_SHARED1, 97 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 98 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 99 CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 100 CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 101 CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 102 CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 103 CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 104 CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, 105 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 106 CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, 107 CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, 108 CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, 109 CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, 110 CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, 111 CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 112 CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 113 CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 114 CLK_CON_DIV_CLKCMU_CORE_BUS, 115 CLK_CON_DIV_CLKCMU_CORE_CCI, 116 CLK_CON_DIV_CLKCMU_CORE_G3D, 117 CLK_CON_DIV_CLKCMU_FSYS_BUS, 118 CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 119 CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 120 CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 121 CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, 122 CLK_CON_DIV_CLKCMU_PERI_BUS, 123 CLK_CON_DIV_CLKCMU_PERI_SPI0, 124 CLK_CON_DIV_CLKCMU_PERI_SPI1, 125 CLK_CON_DIV_CLKCMU_PERI_UART0, 126 CLK_CON_DIV_CLKCMU_PERI_UART1, 127 CLK_CON_DIV_CLKCMU_PERI_UART2, 128 CLK_CON_DIV_CLKCMU_PERI_USI0, 129 CLK_CON_DIV_CLKCMU_PERI_USI1, 130 CLK_CON_DIV_CLKCMU_PERI_USI2, 131 CLK_CON_DIV_PLL_SHARED0_DIV2, 132 CLK_CON_DIV_PLL_SHARED0_DIV3, 133 CLK_CON_DIV_PLL_SHARED0_DIV4, 134 CLK_CON_DIV_PLL_SHARED0_DIV5, 135 CLK_CON_DIV_PLL_SHARED1_DIV2, 136 CLK_CON_DIV_PLL_SHARED1_DIV3, 137 CLK_CON_DIV_PLL_SHARED1_DIV4, 138 CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, 139 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 140 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 141 CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 142 CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 143 CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 144 CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 145 CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 146 CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, 147 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 148 CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, 149 CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, 150 CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, 151 CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, 152 CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 153 CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 154 CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 155 }; 156 157 static const struct samsung_pll_clock top_pll_clks[] __initconst = { 158 PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 159 PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, 160 NULL), 161 PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 162 PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, 163 NULL), 164 }; 165 166 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ 167 PNAME(mout_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", 168 "dout_shared0_div3", "dout_shared0_div3" }; 169 PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", 170 "dout_shared0_div3", "dout_shared0_div3" }; 171 PNAME(mout_core_g3d_p) = { "dout_shared0_div2", "dout_shared1_div2", 172 "dout_shared0_div3", "dout_shared0_div3" }; 173 174 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ 175 PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 176 PNAME(mout_peri_spi0_p) = { "oscclk", "dout_shared0_div4" }; 177 PNAME(mout_peri_spi1_p) = { "oscclk", "dout_shared0_div4" }; 178 PNAME(mout_peri_uart0_p) = { "oscclk", "dout_shared0_div4" }; 179 PNAME(mout_peri_uart1_p) = { "oscclk", "dout_shared0_div4" }; 180 PNAME(mout_peri_uart2_p) = { "oscclk", "dout_shared0_div4" }; 181 PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" }; 182 PNAME(mout_peri_usi1_p) = { "oscclk", "dout_shared0_div4" }; 183 PNAME(mout_peri_usi2_p) = { "oscclk", "dout_shared0_div4" }; 184 185 /* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */ 186 PNAME(mout_fsys_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 187 PNAME(mout_fsys_mmc_card_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 188 PNAME(mout_fsys_mmc_embd_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 189 PNAME(mout_fsys_mmc_sdio_p) = { "dout_shared0_div2", "dout_shared1_div2" }; 190 PNAME(mout_fsys_usb30drd_p) = { "dout_shared0_div4", "dout_shared1_div4" }; 191 192 static const struct samsung_mux_clock top_mux_clks[] __initconst = { 193 /* CORE */ 194 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, 195 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), 196 MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, 197 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), 198 MUX(CLK_MOUT_CORE_G3D, "mout_core_g3d", mout_core_g3d_p, 199 CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2), 200 201 /* PERI */ 202 MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, 203 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), 204 MUX(CLK_MOUT_PERI_SPI0, "mout_peri_spi0", mout_peri_spi0_p, 205 CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, 0, 1), 206 MUX(CLK_MOUT_PERI_SPI1, "mout_peri_spi1", mout_peri_spi1_p, 207 CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, 0, 1), 208 MUX(CLK_MOUT_PERI_UART0, "mout_peri_uart0", mout_peri_uart0_p, 209 CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, 0, 1), 210 MUX(CLK_MOUT_PERI_UART1, "mout_peri_uart1", mout_peri_uart1_p, 211 CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, 0, 1), 212 MUX(CLK_MOUT_PERI_UART2, "mout_peri_uart2", mout_peri_uart2_p, 213 CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, 0, 1), 214 MUX(CLK_MOUT_PERI_USI0, "mout_peri_usi0", mout_peri_usi0_p, 215 CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 0, 1), 216 MUX(CLK_MOUT_PERI_USI1, "mout_peri_usi1", mout_peri_usi1_p, 217 CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1), 218 MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p, 219 CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1), 220 221 /* FSYS */ 222 MUX(CLK_MOUT_FSYS_BUS, "mout_fsys_bus", mout_fsys_bus_p, 223 CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1), 224 MUX(CLK_MOUT_FSYS_MMC_CARD, "mout_fsys_mmc_card", mout_fsys_mmc_card_p, 225 CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 1), 226 MUX(CLK_MOUT_FSYS_MMC_EMBD, "mout_fsys_mmc_embd", mout_fsys_mmc_embd_p, 227 CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 1), 228 MUX(CLK_MOUT_FSYS_MMC_SDIO, "mout_fsys_mmc_sdio", mout_fsys_mmc_sdio_p, 229 CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 0, 1), 230 MUX(CLK_MOUT_FSYS_USB30DRD, "mout_fsys_usb30drd", mout_fsys_usb30drd_p, 231 CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, 0, 1), 232 }; 233 234 static const struct samsung_div_clock top_div_clks[] __initconst = { 235 /* TOP */ 236 DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "fout_shared0_pll", 237 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 238 DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll", 239 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 240 DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", 241 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 242 DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll", 243 CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3), 244 DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "fout_shared1_pll", 245 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 246 DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll", 247 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 248 DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", 249 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 250 251 /* CORE */ 252 DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", 253 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 3), 254 DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", 255 CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 3), 256 DIV(CLK_DOUT_CORE_G3D, "dout_core_g3d", "gout_core_g3d", 257 CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 3), 258 259 /* PERI */ 260 DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", 261 CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), 262 DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "gout_peri_spi0", 263 CLK_CON_DIV_CLKCMU_PERI_SPI0, 0, 6), 264 DIV(CLK_DOUT_PERI_SPI1, "dout_peri_spi1", "gout_peri_spi1", 265 CLK_CON_DIV_CLKCMU_PERI_SPI1, 0, 6), 266 DIV(CLK_DOUT_PERI_UART0, "dout_peri_uart0", "gout_peri_uart0", 267 CLK_CON_DIV_CLKCMU_PERI_UART0, 0, 4), 268 DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "gout_peri_uart1", 269 CLK_CON_DIV_CLKCMU_PERI_UART1, 0, 4), 270 DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "gout_peri_uart2", 271 CLK_CON_DIV_CLKCMU_PERI_UART2, 0, 4), 272 DIV(CLK_DOUT_PERI_USI0, "dout_peri_usi0", "gout_peri_usi0", 273 CLK_CON_DIV_CLKCMU_PERI_USI0, 0, 4), 274 DIV(CLK_DOUT_PERI_USI1, "dout_peri_usi1", "gout_peri_usi1", 275 CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4), 276 DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2", 277 CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4), 278 279 /* FSYS */ 280 DIV(CLK_DOUT_FSYS_BUS, "dout_fsys_bus", "gout_fsys_bus", 281 CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4), 282 DIV(CLK_DOUT_FSYS_MMC_CARD, "dout_fsys_mmc_card", "gout_fsys_mmc_card", 283 CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9), 284 DIV(CLK_DOUT_FSYS_MMC_EMBD, "dout_fsys_mmc_embd", "gout_fsys_mmc_embd", 285 CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9), 286 DIV(CLK_DOUT_FSYS_MMC_SDIO, "dout_fsys_mmc_sdio", "gout_fsys_mmc_sdio", 287 CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 0, 9), 288 DIV(CLK_DOUT_FSYS_USB30DRD, "dout_fsys_usb30drd", "gout_fsys_usb30drd", 289 CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, 0, 4), 290 }; 291 292 static const struct samsung_gate_clock top_gate_clks[] __initconst = { 293 /* CORE */ 294 GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", 295 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 296 GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", 297 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), 298 GATE(CLK_GOUT_CORE_G3D, "gout_core_g3d", "mout_core_g3d", 299 CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, 0, 0), 300 301 /* PERI */ 302 GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", 303 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), 304 GATE(CLK_GOUT_PERI_SPI0, "gout_peri_spi0", "mout_peri_spi0", 305 CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, 21, 0, 0), 306 GATE(CLK_GOUT_PERI_SPI1, "gout_peri_spi1", "mout_peri_spi1", 307 CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, 21, 0, 0), 308 GATE(CLK_GOUT_PERI_UART0, "gout_peri_uart0", "mout_peri_uart0", 309 CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, 21, 0, 0), 310 GATE(CLK_GOUT_PERI_UART1, "gout_peri_uart1", "mout_peri_uart1", 311 CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, 21, 0, 0), 312 GATE(CLK_GOUT_PERI_UART2, "gout_peri_uart2", "mout_peri_uart2", 313 CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, 21, 0, 0), 314 GATE(CLK_GOUT_PERI_USI0, "gout_peri_usi0", "mout_peri_usi0", 315 CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 21, 0, 0), 316 GATE(CLK_GOUT_PERI_USI1, "gout_peri_usi1", "mout_peri_usi1", 317 CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0), 318 GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2", 319 CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0), 320 321 /* FSYS */ 322 GATE(CLK_GOUT_FSYS_BUS, "gout_fsys_bus", "mout_fsys_bus", 323 CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0), 324 GATE(CLK_GOUT_FSYS_MMC_CARD, "gout_fsys_mmc_card", "mout_fsys_mmc_card", 325 CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0), 326 GATE(CLK_GOUT_FSYS_MMC_EMBD, "gout_fsys_mmc_embd", "mout_fsys_mmc_embd", 327 CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0), 328 GATE(CLK_GOUT_FSYS_MMC_SDIO, "gout_fsys_mmc_sdio", "mout_fsys_mmc_sdio", 329 CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 21, 0, 0), 330 GATE(CLK_GOUT_FSYS_USB30DRD, "gout_fsys_usb30drd", "mout_fsys_usb30drd", 331 CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, 21, 0, 0), 332 }; 333 334 static const struct samsung_cmu_info top_cmu_info __initconst = { 335 .pll_clks = top_pll_clks, 336 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 337 .mux_clks = top_mux_clks, 338 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 339 .div_clks = top_div_clks, 340 .nr_div_clks = ARRAY_SIZE(top_div_clks), 341 .gate_clks = top_gate_clks, 342 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 343 .nr_clk_ids = CLKS_NR_TOP, 344 .clk_regs = top_clk_regs, 345 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 346 }; 347 348 static void __init exynos7885_cmu_top_init(struct device_node *np) 349 { 350 exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 351 } 352 353 /* Register CMU_TOP early, as it's a dependency for other early domains */ 354 CLK_OF_DECLARE(exynos7885_cmu_top, "samsung,exynos7885-cmu-top", 355 exynos7885_cmu_top_init); 356 357 /* ---- CMU_PERI ------------------------------------------------------------ */ 358 359 /* Register Offset definitions for CMU_PERI (0x10010000) */ 360 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0100 361 #define PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER 0x0120 362 #define PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER 0x0140 363 #define PLL_CON0_MUX_CLKCMU_PERI_UART0_USER 0x0160 364 #define PLL_CON0_MUX_CLKCMU_PERI_UART1_USER 0x0180 365 #define PLL_CON0_MUX_CLKCMU_PERI_UART2_USER 0x01a0 366 #define PLL_CON0_MUX_CLKCMU_PERI_USI0_USER 0x01c0 367 #define PLL_CON0_MUX_CLKCMU_PERI_USI1_USER 0x01e0 368 #define PLL_CON0_MUX_CLKCMU_PERI_USI2_USER 0x0200 369 #define CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK 0x2024 370 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 371 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x202c 372 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2030 373 #define CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK 0x2034 374 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x2038 375 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x203c 376 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2040 377 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2044 378 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x2048 379 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x204c 380 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2050 381 #define CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK 0x2054 382 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2058 383 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x205c 384 #define CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK 0x2060 385 #define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK 0x2064 386 #define CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK 0x2068 387 #define CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK 0x206c 388 #define CLK_CON_GAT_GOUT_PERI_UART_0_PCLK 0x2070 389 #define CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK 0x2074 390 #define CLK_CON_GAT_GOUT_PERI_UART_1_PCLK 0x2078 391 #define CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK 0x207c 392 #define CLK_CON_GAT_GOUT_PERI_UART_2_PCLK 0x2080 393 #define CLK_CON_GAT_GOUT_PERI_USI0_PCLK 0x2084 394 #define CLK_CON_GAT_GOUT_PERI_USI0_SCLK 0x2088 395 #define CLK_CON_GAT_GOUT_PERI_USI1_PCLK 0x208c 396 #define CLK_CON_GAT_GOUT_PERI_USI1_SCLK 0x2090 397 #define CLK_CON_GAT_GOUT_PERI_USI2_PCLK 0x2094 398 #define CLK_CON_GAT_GOUT_PERI_USI2_SCLK 0x2098 399 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x20a0 400 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20b0 401 #define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK 0x20b4 402 #define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK 0x20b8 403 404 static const unsigned long peri_clk_regs[] __initconst = { 405 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 406 PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, 407 PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, 408 PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, 409 PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, 410 PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, 411 PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, 412 PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, 413 PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, 414 CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, 415 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 416 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 417 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 418 CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, 419 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 420 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 421 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 422 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 423 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 424 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 425 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 426 CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, 427 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 428 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 429 CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, 430 CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 431 CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, 432 CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, 433 CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, 434 CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, 435 CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, 436 CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, 437 CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, 438 CLK_CON_GAT_GOUT_PERI_USI0_PCLK, 439 CLK_CON_GAT_GOUT_PERI_USI0_SCLK, 440 CLK_CON_GAT_GOUT_PERI_USI1_PCLK, 441 CLK_CON_GAT_GOUT_PERI_USI1_SCLK, 442 CLK_CON_GAT_GOUT_PERI_USI2_PCLK, 443 CLK_CON_GAT_GOUT_PERI_USI2_SCLK, 444 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 445 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 446 CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, 447 CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, 448 }; 449 450 /* List of parent clocks for Muxes in CMU_PERI */ 451 PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; 452 PNAME(mout_peri_spi0_user_p) = { "oscclk", "dout_peri_spi0" }; 453 PNAME(mout_peri_spi1_user_p) = { "oscclk", "dout_peri_spi1" }; 454 PNAME(mout_peri_uart0_user_p) = { "oscclk", "dout_peri_uart0" }; 455 PNAME(mout_peri_uart1_user_p) = { "oscclk", "dout_peri_uart1" }; 456 PNAME(mout_peri_uart2_user_p) = { "oscclk", "dout_peri_uart2" }; 457 PNAME(mout_peri_usi0_user_p) = { "oscclk", "dout_peri_usi0" }; 458 PNAME(mout_peri_usi1_user_p) = { "oscclk", "dout_peri_usi1" }; 459 PNAME(mout_peri_usi2_user_p) = { "oscclk", "dout_peri_usi2" }; 460 461 static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 462 MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, 463 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), 464 MUX(CLK_MOUT_PERI_SPI0_USER, "mout_peri_spi0_user", mout_peri_spi0_user_p, 465 PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, 4, 1), 466 MUX(CLK_MOUT_PERI_SPI1_USER, "mout_peri_spi1_user", mout_peri_spi1_user_p, 467 PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, 4, 1), 468 MUX(CLK_MOUT_PERI_UART0_USER, "mout_peri_uart0_user", 469 mout_peri_uart0_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, 4, 1), 470 MUX(CLK_MOUT_PERI_UART1_USER, "mout_peri_uart1_user", 471 mout_peri_uart1_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, 4, 1), 472 MUX(CLK_MOUT_PERI_UART2_USER, "mout_peri_uart2_user", 473 mout_peri_uart2_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, 4, 1), 474 MUX(CLK_MOUT_PERI_USI0_USER, "mout_peri_usi0_user", 475 mout_peri_usi0_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, 4, 1), 476 MUX(CLK_MOUT_PERI_USI1_USER, "mout_peri_usi1_user", 477 mout_peri_usi1_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, 4, 1), 478 MUX(CLK_MOUT_PERI_USI2_USER, "mout_peri_usi2_user", 479 mout_peri_usi2_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, 4, 1), 480 }; 481 482 static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 483 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ 484 GATE(CLK_GOUT_GPIO_TOP_PCLK, "gout_gpio_top_pclk", 485 "mout_peri_bus_user", 486 CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, 21, CLK_IGNORE_UNUSED, 0), 487 GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", 488 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), 489 GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", 490 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), 491 GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", 492 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), 493 GATE(CLK_GOUT_HSI2C3_PCLK, "gout_hsi2c3_pclk", "mout_peri_bus_user", 494 CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, 21, 0, 0), 495 GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", 496 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), 497 GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", 498 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), 499 GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", 500 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), 501 GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", 502 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), 503 GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", 504 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), 505 GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", 506 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), 507 GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", 508 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), 509 GATE(CLK_GOUT_I2C7_PCLK, "gout_i2c7_pclk", "mout_peri_bus_user", 510 CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, 21, 0, 0), 511 GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", 512 "mout_peri_bus_user", 513 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), 514 GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", 515 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), 516 GATE(CLK_GOUT_SPI0_EXT_CLK, "gout_spi0_ipclk", "mout_peri_spi0_user", 517 CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, 21, 0, 0), 518 GATE(CLK_GOUT_SPI1_PCLK, "gout_spi1_pclk", "mout_peri_bus_user", 519 CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, 0, 0), 520 GATE(CLK_GOUT_SPI1_EXT_CLK, "gout_spi1_ipclk", "mout_peri_spi1_user", 521 CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, 21, 0, 0), 522 GATE(CLK_GOUT_UART0_EXT_UCLK, "gout_uart0_ext_uclk", "mout_peri_uart0_user", 523 CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, 21, 0, 0), 524 GATE(CLK_GOUT_UART0_PCLK, "gout_uart0_pclk", "mout_peri_bus_user", 525 CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, 21, 0, 0), 526 GATE(CLK_GOUT_UART1_EXT_UCLK, "gout_uart1_ext_uclk", "mout_peri_uart1_user", 527 CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, 21, 0, 0), 528 GATE(CLK_GOUT_UART1_PCLK, "gout_uart1_pclk", "mout_peri_bus_user", 529 CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, 21, 0, 0), 530 GATE(CLK_GOUT_UART2_EXT_UCLK, "gout_uart2_ext_uclk", "mout_peri_uart2_user", 531 CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, 21, 0, 0), 532 GATE(CLK_GOUT_UART2_PCLK, "gout_uart2_pclk", "mout_peri_bus_user", 533 CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, 21, 0, 0), 534 GATE(CLK_GOUT_USI0_PCLK, "gout_usi0_pclk", "mout_peri_bus_user", 535 CLK_CON_GAT_GOUT_PERI_USI0_PCLK, 21, 0, 0), 536 GATE(CLK_GOUT_USI0_SCLK, "gout_usi0_sclk", "mout_peri_usi0_user", 537 CLK_CON_GAT_GOUT_PERI_USI0_SCLK, 21, 0, 0), 538 GATE(CLK_GOUT_USI1_PCLK, "gout_usi1_pclk", "mout_peri_bus_user", 539 CLK_CON_GAT_GOUT_PERI_USI1_PCLK, 21, 0, 0), 540 GATE(CLK_GOUT_USI1_SCLK, "gout_usi1_sclk", "mout_peri_usi1_user", 541 CLK_CON_GAT_GOUT_PERI_USI1_SCLK, 21, 0, 0), 542 GATE(CLK_GOUT_USI2_PCLK, "gout_usi2_pclk", "mout_peri_bus_user", 543 CLK_CON_GAT_GOUT_PERI_USI2_PCLK, 21, 0, 0), 544 GATE(CLK_GOUT_USI2_SCLK, "gout_usi2_sclk", "mout_peri_usi2_user", 545 CLK_CON_GAT_GOUT_PERI_USI2_SCLK, 21, 0, 0), 546 GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", 547 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), 548 GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", 549 "mout_peri_bus_user", 550 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), 551 GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", 552 CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, 21, 0, 0), 553 GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", 554 CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, 21, 0, 0), 555 }; 556 557 static const struct samsung_cmu_info peri_cmu_info __initconst = { 558 .mux_clks = peri_mux_clks, 559 .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 560 .gate_clks = peri_gate_clks, 561 .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 562 .nr_clk_ids = CLKS_NR_PERI, 563 .clk_regs = peri_clk_regs, 564 .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 565 .clk_name = "dout_peri_bus", 566 }; 567 568 static void __init exynos7885_cmu_peri_init(struct device_node *np) 569 { 570 exynos_arm64_register_cmu(NULL, np, &peri_cmu_info); 571 } 572 573 /* Register CMU_PERI early, as it's needed for MCT timer */ 574 CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri", 575 exynos7885_cmu_peri_init); 576 577 /* ---- CMU_CORE ------------------------------------------------------------ */ 578 579 /* Register Offset definitions for CMU_CORE (0x12000000) */ 580 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100 581 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120 582 #define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140 583 #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 584 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 585 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054 586 #define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058 587 #define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK 0x215c 588 #define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK 0x2160 589 #define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK 0x2164 590 #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE 0x2168 591 #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE 0x216c 592 #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK 0x2170 593 #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE 0x2174 594 595 static const unsigned long core_clk_regs[] __initconst = { 596 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 597 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 598 PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 599 CLK_CON_MUX_MUX_CLK_CORE_GIC, 600 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 601 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 602 CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 603 CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, 604 CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, 605 CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, 606 CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, 607 CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, 608 CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, 609 CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, 610 }; 611 612 /* List of parent clocks for Muxes in CMU_CORE */ 613 PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; 614 PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; 615 PNAME(mout_core_g3d_user_p) = { "oscclk", "dout_core_g3d" }; 616 PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; 617 618 static const struct samsung_mux_clock core_mux_clks[] __initconst = { 619 MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, 620 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), 621 MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, 622 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), 623 MUX(CLK_MOUT_CORE_G3D_USER, "mout_core_g3d_user", mout_core_g3d_user_p, 624 PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 4, 1), 625 MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, 626 CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), 627 }; 628 629 static const struct samsung_div_clock core_div_clks[] __initconst = { 630 DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", 631 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), 632 }; 633 634 static const struct samsung_gate_clock core_gate_clks[] __initconst = { 635 /* CCI (interconnect) clock must be always running */ 636 GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", 637 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0), 638 /* GIC (interrupt controller) clock must be always running */ 639 GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic", 640 CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0), 641 /* 642 * TREX D and P Core (seems to be related to "bus traffic shaper") 643 * clocks must always be running 644 */ 645 GATE(CLK_GOUT_TREX_D_CORE_ACLK, "gout_trex_d_core_aclk", "mout_core_bus_user", 646 CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, 21, CLK_IS_CRITICAL, 0), 647 GATE(CLK_GOUT_TREX_D_CORE_GCLK, "gout_trex_d_core_gclk", "mout_core_g3d_user", 648 CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, 21, CLK_IS_CRITICAL, 0), 649 GATE(CLK_GOUT_TREX_D_CORE_PCLK, "gout_trex_d_core_pclk", "dout_core_busp", 650 CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, 21, CLK_IS_CRITICAL, 0), 651 GATE(CLK_GOUT_TREX_P_CORE_ACLK_P_CORE, "gout_trex_p_core_aclk_p_core", 652 "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, 21, 653 CLK_IS_CRITICAL, 0), 654 GATE(CLK_GOUT_TREX_P_CORE_CCLK_P_CORE, "gout_trex_p_core_cclk_p_core", 655 "mout_core_cci_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, 21, 656 CLK_IS_CRITICAL, 0), 657 GATE(CLK_GOUT_TREX_P_CORE_PCLK, "gout_trex_p_core_pclk", "dout_core_busp", 658 CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, 21, CLK_IS_CRITICAL, 0), 659 GATE(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE, "gout_trex_p_core_pclk_p_core", 660 "dout_core_busp", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, 21, 661 CLK_IS_CRITICAL, 0), 662 }; 663 664 static const struct samsung_cmu_info core_cmu_info __initconst = { 665 .mux_clks = core_mux_clks, 666 .nr_mux_clks = ARRAY_SIZE(core_mux_clks), 667 .div_clks = core_div_clks, 668 .nr_div_clks = ARRAY_SIZE(core_div_clks), 669 .gate_clks = core_gate_clks, 670 .nr_gate_clks = ARRAY_SIZE(core_gate_clks), 671 .nr_clk_ids = CLKS_NR_CORE, 672 .clk_regs = core_clk_regs, 673 .nr_clk_regs = ARRAY_SIZE(core_clk_regs), 674 .clk_name = "dout_core_bus", 675 }; 676 677 /* ---- CMU_FSYS ------------------------------------------------------------ */ 678 679 /* Register Offset definitions for CMU_FSYS (0x13400000) */ 680 #define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100 681 #define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120 682 #define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140 683 #define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160 684 #define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180 685 #define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030 686 #define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034 687 #define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038 688 #define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c 689 #define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040 690 #define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044 691 692 static const unsigned long fsys_clk_regs[] __initconst = { 693 PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 694 PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, 695 PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, 696 PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER, 697 PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER, 698 CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 699 CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN, 700 CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, 701 CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN, 702 CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, 703 CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN, 704 }; 705 706 /* List of parent clocks for Muxes in CMU_FSYS */ 707 PNAME(mout_fsys_bus_user_p) = { "oscclk", "dout_fsys_bus" }; 708 PNAME(mout_fsys_mmc_card_user_p) = { "oscclk", "dout_fsys_mmc_card" }; 709 PNAME(mout_fsys_mmc_embd_user_p) = { "oscclk", "dout_fsys_mmc_embd" }; 710 PNAME(mout_fsys_mmc_sdio_user_p) = { "oscclk", "dout_fsys_mmc_sdio" }; 711 PNAME(mout_fsys_usb30drd_user_p) = { "oscclk", "dout_fsys_usb30drd" }; 712 713 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { 714 MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p, 715 PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 4, 1), 716 MUX_F(CLK_MOUT_FSYS_MMC_CARD_USER, "mout_fsys_mmc_card_user", 717 mout_fsys_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, 718 4, 1, CLK_SET_RATE_PARENT, 0), 719 MUX_F(CLK_MOUT_FSYS_MMC_EMBD_USER, "mout_fsys_mmc_embd_user", 720 mout_fsys_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, 721 4, 1, CLK_SET_RATE_PARENT, 0), 722 MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user", 723 mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER, 724 4, 1, CLK_SET_RATE_PARENT, 0), 725 MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user", 726 mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER, 727 4, 1, CLK_SET_RATE_PARENT, 0), 728 }; 729 730 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { 731 GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user", 732 CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0), 733 GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", 734 "mout_fsys_mmc_card_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN, 735 21, CLK_SET_RATE_PARENT, 0), 736 GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "mout_fsys_bus_user", 737 CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, 21, 0, 0), 738 GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", 739 "mout_fsys_mmc_embd_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN, 740 21, CLK_SET_RATE_PARENT, 0), 741 GATE(CLK_GOUT_MMC_SDIO_ACLK, "gout_mmc_sdio_aclk", "mout_fsys_bus_user", 742 CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, 21, 0, 0), 743 GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin", 744 "mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN, 745 21, CLK_SET_RATE_PARENT, 0), 746 }; 747 748 static const struct samsung_cmu_info fsys_cmu_info __initconst = { 749 .mux_clks = fsys_mux_clks, 750 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), 751 .gate_clks = fsys_gate_clks, 752 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), 753 .nr_clk_ids = CLKS_NR_FSYS, 754 .clk_regs = fsys_clk_regs, 755 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), 756 .clk_name = "dout_fsys_bus", 757 }; 758 759 /* ---- platform_driver ----------------------------------------------------- */ 760 761 static int __init exynos7885_cmu_probe(struct platform_device *pdev) 762 { 763 const struct samsung_cmu_info *info; 764 struct device *dev = &pdev->dev; 765 766 info = of_device_get_match_data(dev); 767 exynos_arm64_register_cmu(dev, dev->of_node, info); 768 769 return 0; 770 } 771 772 static const struct of_device_id exynos7885_cmu_of_match[] = { 773 { 774 .compatible = "samsung,exynos7885-cmu-core", 775 .data = &core_cmu_info, 776 }, { 777 .compatible = "samsung,exynos7885-cmu-fsys", 778 .data = &fsys_cmu_info, 779 }, { 780 }, 781 }; 782 783 static struct platform_driver exynos7885_cmu_driver __refdata = { 784 .driver = { 785 .name = "exynos7885-cmu", 786 .of_match_table = exynos7885_cmu_of_match, 787 .suppress_bind_attrs = true, 788 }, 789 .probe = exynos7885_cmu_probe, 790 }; 791 792 static int __init exynos7885_cmu_init(void) 793 { 794 return platform_driver_register(&exynos7885_cmu_driver); 795 } 796 core_initcall(exynos7885_cmu_init); 797