1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Common Clock Framework support for Exynos5433 SoC. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 20 #include <dt-bindings/clock/exynos5433.h> 21 22 #include "clk.h" 23 #include "clk-cpu.h" 24 #include "clk-pll.h" 25 26 /* 27 * Register offset definitions for CMU_TOP 28 */ 29 #define ISP_PLL_LOCK 0x0000 30 #define AUD_PLL_LOCK 0x0004 31 #define ISP_PLL_CON0 0x0100 32 #define ISP_PLL_CON1 0x0104 33 #define ISP_PLL_FREQ_DET 0x0108 34 #define AUD_PLL_CON0 0x0110 35 #define AUD_PLL_CON1 0x0114 36 #define AUD_PLL_CON2 0x0118 37 #define AUD_PLL_FREQ_DET 0x011c 38 #define MUX_SEL_TOP0 0x0200 39 #define MUX_SEL_TOP1 0x0204 40 #define MUX_SEL_TOP2 0x0208 41 #define MUX_SEL_TOP3 0x020c 42 #define MUX_SEL_TOP4 0x0210 43 #define MUX_SEL_TOP_MSCL 0x0220 44 #define MUX_SEL_TOP_CAM1 0x0224 45 #define MUX_SEL_TOP_DISP 0x0228 46 #define MUX_SEL_TOP_FSYS0 0x0230 47 #define MUX_SEL_TOP_FSYS1 0x0234 48 #define MUX_SEL_TOP_PERIC0 0x0238 49 #define MUX_SEL_TOP_PERIC1 0x023c 50 #define MUX_ENABLE_TOP0 0x0300 51 #define MUX_ENABLE_TOP1 0x0304 52 #define MUX_ENABLE_TOP2 0x0308 53 #define MUX_ENABLE_TOP3 0x030c 54 #define MUX_ENABLE_TOP4 0x0310 55 #define MUX_ENABLE_TOP_MSCL 0x0320 56 #define MUX_ENABLE_TOP_CAM1 0x0324 57 #define MUX_ENABLE_TOP_DISP 0x0328 58 #define MUX_ENABLE_TOP_FSYS0 0x0330 59 #define MUX_ENABLE_TOP_FSYS1 0x0334 60 #define MUX_ENABLE_TOP_PERIC0 0x0338 61 #define MUX_ENABLE_TOP_PERIC1 0x033c 62 #define MUX_STAT_TOP0 0x0400 63 #define MUX_STAT_TOP1 0x0404 64 #define MUX_STAT_TOP2 0x0408 65 #define MUX_STAT_TOP3 0x040c 66 #define MUX_STAT_TOP4 0x0410 67 #define MUX_STAT_TOP_MSCL 0x0420 68 #define MUX_STAT_TOP_CAM1 0x0424 69 #define MUX_STAT_TOP_FSYS0 0x0430 70 #define MUX_STAT_TOP_FSYS1 0x0434 71 #define MUX_STAT_TOP_PERIC0 0x0438 72 #define MUX_STAT_TOP_PERIC1 0x043c 73 #define DIV_TOP0 0x0600 74 #define DIV_TOP1 0x0604 75 #define DIV_TOP2 0x0608 76 #define DIV_TOP3 0x060c 77 #define DIV_TOP4 0x0610 78 #define DIV_TOP_MSCL 0x0618 79 #define DIV_TOP_CAM10 0x061c 80 #define DIV_TOP_CAM11 0x0620 81 #define DIV_TOP_FSYS0 0x062c 82 #define DIV_TOP_FSYS1 0x0630 83 #define DIV_TOP_FSYS2 0x0634 84 #define DIV_TOP_PERIC0 0x0638 85 #define DIV_TOP_PERIC1 0x063c 86 #define DIV_TOP_PERIC2 0x0640 87 #define DIV_TOP_PERIC3 0x0644 88 #define DIV_TOP_PERIC4 0x0648 89 #define DIV_TOP_PLL_FREQ_DET 0x064c 90 #define DIV_STAT_TOP0 0x0700 91 #define DIV_STAT_TOP1 0x0704 92 #define DIV_STAT_TOP2 0x0708 93 #define DIV_STAT_TOP3 0x070c 94 #define DIV_STAT_TOP4 0x0710 95 #define DIV_STAT_TOP_MSCL 0x0718 96 #define DIV_STAT_TOP_CAM10 0x071c 97 #define DIV_STAT_TOP_CAM11 0x0720 98 #define DIV_STAT_TOP_FSYS0 0x072c 99 #define DIV_STAT_TOP_FSYS1 0x0730 100 #define DIV_STAT_TOP_FSYS2 0x0734 101 #define DIV_STAT_TOP_PERIC0 0x0738 102 #define DIV_STAT_TOP_PERIC1 0x073c 103 #define DIV_STAT_TOP_PERIC2 0x0740 104 #define DIV_STAT_TOP_PERIC3 0x0744 105 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c 106 #define ENABLE_ACLK_TOP 0x0800 107 #define ENABLE_SCLK_TOP 0x0a00 108 #define ENABLE_SCLK_TOP_MSCL 0x0a04 109 #define ENABLE_SCLK_TOP_CAM1 0x0a08 110 #define ENABLE_SCLK_TOP_DISP 0x0a0c 111 #define ENABLE_SCLK_TOP_FSYS 0x0a10 112 #define ENABLE_SCLK_TOP_PERIC 0x0a14 113 #define ENABLE_IP_TOP 0x0b00 114 #define ENABLE_CMU_TOP 0x0c00 115 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04 116 117 static const unsigned long top_clk_regs[] __initconst = { 118 ISP_PLL_LOCK, 119 AUD_PLL_LOCK, 120 ISP_PLL_CON0, 121 ISP_PLL_CON1, 122 ISP_PLL_FREQ_DET, 123 AUD_PLL_CON0, 124 AUD_PLL_CON1, 125 AUD_PLL_CON2, 126 AUD_PLL_FREQ_DET, 127 MUX_SEL_TOP0, 128 MUX_SEL_TOP1, 129 MUX_SEL_TOP2, 130 MUX_SEL_TOP3, 131 MUX_SEL_TOP4, 132 MUX_SEL_TOP_MSCL, 133 MUX_SEL_TOP_CAM1, 134 MUX_SEL_TOP_DISP, 135 MUX_SEL_TOP_FSYS0, 136 MUX_SEL_TOP_FSYS1, 137 MUX_SEL_TOP_PERIC0, 138 MUX_SEL_TOP_PERIC1, 139 MUX_ENABLE_TOP0, 140 MUX_ENABLE_TOP1, 141 MUX_ENABLE_TOP2, 142 MUX_ENABLE_TOP3, 143 MUX_ENABLE_TOP4, 144 MUX_ENABLE_TOP_MSCL, 145 MUX_ENABLE_TOP_CAM1, 146 MUX_ENABLE_TOP_DISP, 147 MUX_ENABLE_TOP_FSYS0, 148 MUX_ENABLE_TOP_FSYS1, 149 MUX_ENABLE_TOP_PERIC0, 150 MUX_ENABLE_TOP_PERIC1, 151 DIV_TOP0, 152 DIV_TOP1, 153 DIV_TOP2, 154 DIV_TOP3, 155 DIV_TOP4, 156 DIV_TOP_MSCL, 157 DIV_TOP_CAM10, 158 DIV_TOP_CAM11, 159 DIV_TOP_FSYS0, 160 DIV_TOP_FSYS1, 161 DIV_TOP_FSYS2, 162 DIV_TOP_PERIC0, 163 DIV_TOP_PERIC1, 164 DIV_TOP_PERIC2, 165 DIV_TOP_PERIC3, 166 DIV_TOP_PERIC4, 167 DIV_TOP_PLL_FREQ_DET, 168 ENABLE_ACLK_TOP, 169 ENABLE_SCLK_TOP, 170 ENABLE_SCLK_TOP_MSCL, 171 ENABLE_SCLK_TOP_CAM1, 172 ENABLE_SCLK_TOP_DISP, 173 ENABLE_SCLK_TOP_FSYS, 174 ENABLE_SCLK_TOP_PERIC, 175 ENABLE_IP_TOP, 176 ENABLE_CMU_TOP, 177 ENABLE_CMU_TOP_DIV_STAT, 178 }; 179 180 /* list of all parent clock list */ 181 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; 182 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; 183 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", }; 184 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", }; 185 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", }; 186 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", }; 187 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", }; 188 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", }; 189 190 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",}; 191 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",}; 192 PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a", 193 "mout_mfc_pll_user", }; 194 PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", }; 195 196 PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b", 197 "mout_mphy_pll_user", }; 198 PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a", 199 "mout_bus_pll_user", }; 200 PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", }; 201 202 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user", 203 "mout_mphy_pll_user", }; 204 PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a", 205 "mout_mphy_pll_user", }; 206 PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a", 207 "mout_mphy_pll_user", }; 208 209 PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",}; 210 PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", }; 211 212 PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",}; 213 PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",}; 214 PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", }; 215 PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",}; 216 PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", }; 217 218 PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1", 219 "oscclk", "ioclk_spdif_extclk", }; 220 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk", 221 "mout_aud_pll_user_t",}; 222 PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk", 223 "mout_aud_pll_user_t",}; 224 225 PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; 226 227 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = { 228 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), 229 }; 230 231 static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = { 232 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ 233 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000), 234 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000), 235 /* Xi2s1SDI input clock for SPDIF */ 236 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000), 237 /* XspiCLK[4:0] input clock for SPI */ 238 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000), 239 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000), 240 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000), 241 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000), 242 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000), 243 /* Xi2s1SCLK input clock for I2S1_BCLK */ 244 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000), 245 }; 246 247 static const struct samsung_mux_clock top_mux_clks[] __initconst = { 248 /* MUX_SEL_TOP0 */ 249 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, 250 4, 1), 251 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0, 252 0, 1), 253 254 /* MUX_SEL_TOP1 */ 255 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t", 256 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1), 257 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p, 258 MUX_SEL_TOP1, 8, 1), 259 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p, 260 MUX_SEL_TOP1, 4, 1), 261 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p, 262 MUX_SEL_TOP1, 0, 1), 263 264 /* MUX_SEL_TOP2 */ 265 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400", 266 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1), 267 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333", 268 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1), 269 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b", 270 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1), 271 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a", 272 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1), 273 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400", 274 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1), 275 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400", 276 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1), 277 278 /* MUX_SEL_TOP3 */ 279 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400", 280 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1), 281 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b", 282 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1), 283 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a", 284 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1), 285 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333", 286 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1), 287 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b", 288 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1), 289 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a", 290 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1), 291 292 /* MUX_SEL_TOP4 */ 293 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c", 294 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1), 295 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b", 296 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1), 297 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a", 298 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1), 299 300 /* MUX_SEL_TOP_MSCL */ 301 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p, 302 MUX_SEL_TOP_MSCL, 8, 1), 303 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p, 304 MUX_SEL_TOP_MSCL, 4, 1), 305 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p, 306 MUX_SEL_TOP_MSCL, 0, 1), 307 308 /* MUX_SEL_TOP_CAM1 */ 309 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2", 310 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1), 311 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1", 312 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1), 313 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0", 314 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1), 315 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart", 316 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1), 317 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1", 318 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1), 319 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0", 320 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1), 321 322 /* MUX_SEL_TOP_FSYS0 */ 323 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p, 324 MUX_SEL_TOP_FSYS0, 28, 1), 325 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p, 326 MUX_SEL_TOP_FSYS0, 24, 1), 327 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p, 328 MUX_SEL_TOP_FSYS0, 20, 1), 329 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p, 330 MUX_SEL_TOP_FSYS0, 16, 1), 331 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p, 332 MUX_SEL_TOP_FSYS0, 12, 1), 333 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p, 334 MUX_SEL_TOP_FSYS0, 8, 1), 335 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p, 336 MUX_SEL_TOP_FSYS0, 4, 1), 337 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p, 338 MUX_SEL_TOP_FSYS0, 0, 1), 339 340 /* MUX_SEL_TOP_FSYS1 */ 341 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p, 342 MUX_SEL_TOP_FSYS1, 12, 1), 343 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro", 344 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1), 345 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30", 346 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1), 347 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30", 348 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1), 349 350 /* MUX_SEL_TOP_PERIC0 */ 351 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p, 352 MUX_SEL_TOP_PERIC0, 28, 1), 353 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p, 354 MUX_SEL_TOP_PERIC0, 24, 1), 355 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p, 356 MUX_SEL_TOP_PERIC0, 20, 1), 357 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p, 358 MUX_SEL_TOP_PERIC0, 16, 1), 359 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p, 360 MUX_SEL_TOP_PERIC0, 12, 1), 361 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p, 362 MUX_SEL_TOP_PERIC0, 8, 1), 363 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p, 364 MUX_SEL_TOP_PERIC0, 4, 1), 365 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p, 366 MUX_SEL_TOP_PERIC0, 0, 1), 367 368 /* MUX_SEL_TOP_PERIC1 */ 369 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p, 370 MUX_SEL_TOP_PERIC1, 16, 1), 371 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p, 372 MUX_SEL_TOP_PERIC1, 12, 2), 373 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p, 374 MUX_SEL_TOP_PERIC1, 4, 2), 375 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p, 376 MUX_SEL_TOP_PERIC1, 0, 2), 377 378 /* MUX_SEL_TOP_DISP */ 379 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif", 380 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), 381 }; 382 383 static const struct samsung_div_clock top_div_clks[] __initconst = { 384 /* DIV_TOP0 */ 385 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333", 386 DIV_TOP0, 28, 3), 387 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user", 388 DIV_TOP0, 24, 3), 389 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b", 390 DIV_TOP0, 20, 3), 391 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user", 392 DIV_TOP0, 16, 3), 393 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user", 394 DIV_TOP0, 12, 3), 395 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll", 396 DIV_TOP0, 8, 3), 397 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400", 398 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4), 399 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400", 400 "mout_aclk_isp_400", DIV_TOP0, 0, 4), 401 402 /* DIV_TOP1 */ 403 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333", 404 DIV_TOP1, 28, 3), 405 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333", 406 DIV_TOP1, 24, 3), 407 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400", 408 DIV_TOP1, 20, 3), 409 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c", 410 DIV_TOP1, 12, 3), 411 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user", 412 DIV_TOP1, 8, 3), 413 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b", 414 DIV_TOP1, 0, 3), 415 416 /* DIV_TOP2 */ 417 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b", 418 DIV_TOP2, 4, 3), 419 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user", 420 DIV_TOP2, 0, 3), 421 422 /* DIV_TOP3 */ 423 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266", 424 "mout_bus_pll_user", DIV_TOP3, 24, 3), 425 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200", 426 "mout_bus_pll_user", DIV_TOP3, 20, 3), 427 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266", 428 "mout_bus_pll_user", DIV_TOP3, 16, 3), 429 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b", 430 "div_aclk_peric_66_a", DIV_TOP3, 12, 3), 431 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a", 432 "mout_bus_pll_user", DIV_TOP3, 8, 3), 433 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b", 434 "div_aclk_peris_66_a", DIV_TOP3, 4, 3), 435 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a", 436 "mout_bus_pll_user", DIV_TOP3, 0, 3), 437 438 /* DIV_TOP4 */ 439 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user", 440 DIV_TOP4, 8, 3), 441 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400", 442 DIV_TOP4, 4, 3), 443 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user", 444 DIV_TOP4, 0, 3), 445 446 /* DIV_TOP_MSCL */ 447 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c", 448 DIV_TOP_MSCL, 0, 4), 449 450 /* DIV_TOP_CAM10 */ 451 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart", 452 DIV_TOP_CAM10, 24, 5), 453 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b", 454 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8), 455 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a", 456 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4), 457 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b", 458 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8), 459 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a", 460 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4), 461 462 /* DIV_TOP_CAM11 */ 463 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b", 464 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4), 465 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a", 466 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4), 467 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b", 468 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4), 469 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a", 470 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4), 471 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b", 472 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4), 473 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a", 474 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4), 475 476 /* DIV_TOP_FSYS0 */ 477 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a", 478 DIV_TOP_FSYS0, 16, 8), 479 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b", 480 DIV_TOP_FSYS0, 12, 4), 481 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a", 482 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0), 483 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d", 484 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0), 485 486 /* DIV_TOP_FSYS1 */ 487 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a", 488 DIV_TOP_FSYS1, 4, 8), 489 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b", 490 DIV_TOP_FSYS1, 0, 4), 491 492 /* DIV_TOP_FSYS2 */ 493 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100", 494 DIV_TOP_FSYS2, 12, 3), 495 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30", 496 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4), 497 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro", 498 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4), 499 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30", 500 DIV_TOP_FSYS2, 0, 4), 501 502 /* DIV_TOP_PERIC0 */ 503 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a", 504 DIV_TOP_PERIC0, 16, 8), 505 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1", 506 DIV_TOP_PERIC0, 12, 4), 507 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a", 508 DIV_TOP_PERIC0, 4, 8), 509 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0", 510 DIV_TOP_PERIC0, 0, 4), 511 512 /* DIV_TOP_PERIC1 */ 513 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a", 514 DIV_TOP_PERIC1, 4, 8), 515 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2", 516 DIV_TOP_PERIC1, 0, 4), 517 518 /* DIV_TOP_PERIC2 */ 519 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2", 520 DIV_TOP_PERIC2, 8, 4), 521 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0", 522 DIV_TOP_PERIC2, 4, 4), 523 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1", 524 DIV_TOP_PERIC2, 0, 4), 525 526 /* DIV_TOP_PERIC3 */ 527 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1", 528 DIV_TOP_PERIC3, 16, 6), 529 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1", 530 DIV_TOP_PERIC3, 8, 8), 531 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1", 532 DIV_TOP_PERIC3, 4, 4), 533 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0", 534 DIV_TOP_PERIC3, 0, 4), 535 536 /* DIV_TOP_PERIC4 */ 537 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a", 538 DIV_TOP_PERIC4, 16, 8), 539 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4", 540 DIV_TOP_PERIC4, 12, 4), 541 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a", 542 DIV_TOP_PERIC4, 4, 8), 543 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3", 544 DIV_TOP_PERIC4, 0, 4), 545 }; 546 547 static const struct samsung_gate_clock top_gate_clks[] __initconst = { 548 /* ENABLE_ACLK_TOP */ 549 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", 550 ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0), 551 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266", 552 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP, 553 29, CLK_IGNORE_UNUSED, 0), 554 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400", 555 ENABLE_ACLK_TOP, 26, 556 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 557 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400", 558 ENABLE_ACLK_TOP, 25, 559 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 560 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266", 561 ENABLE_ACLK_TOP, 24, 562 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 563 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200", 564 ENABLE_ACLK_TOP, 23, 565 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 566 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b", 567 ENABLE_ACLK_TOP, 22, 568 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 569 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b", 570 ENABLE_ACLK_TOP, 21, 571 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 572 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400", 573 ENABLE_ACLK_TOP, 19, 574 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 575 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200", 576 ENABLE_ACLK_TOP, 18, 577 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 578 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111", 579 ENABLE_ACLK_TOP, 15, 580 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 581 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333", 582 ENABLE_ACLK_TOP, 14, 583 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 584 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333", 585 ENABLE_ACLK_TOP, 13, 586 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 587 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400", 588 ENABLE_ACLK_TOP, 12, 589 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 590 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552", 591 ENABLE_ACLK_TOP, 11, 592 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 593 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333", 594 ENABLE_ACLK_TOP, 10, 595 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 596 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400", 597 ENABLE_ACLK_TOP, 9, 598 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 599 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552", 600 ENABLE_ACLK_TOP, 8, 601 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 602 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400", 603 ENABLE_ACLK_TOP, 7, 604 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 605 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400", 606 ENABLE_ACLK_TOP, 6, 607 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 608 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400", 609 ENABLE_ACLK_TOP, 5, 610 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 611 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400", 612 ENABLE_ACLK_TOP, 3, 613 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 614 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266", 615 ENABLE_ACLK_TOP, 2, 616 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 617 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400", 618 ENABLE_ACLK_TOP, 0, 619 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 620 621 /* ENABLE_SCLK_TOP_MSCL */ 622 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg", 623 ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0), 624 625 /* ENABLE_SCLK_TOP_CAM1 */ 626 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b", 627 ENABLE_SCLK_TOP_CAM1, 7, 0, 0), 628 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b", 629 ENABLE_SCLK_TOP_CAM1, 6, 0, 0), 630 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b", 631 ENABLE_SCLK_TOP_CAM1, 5, 0, 0), 632 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk", 633 ENABLE_SCLK_TOP_CAM1, 4, 0, 0), 634 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart", 635 ENABLE_SCLK_TOP_CAM1, 2, 0, 0), 636 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b", 637 ENABLE_SCLK_TOP_CAM1, 1, 0, 0), 638 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b", 639 ENABLE_SCLK_TOP_CAM1, 0, 0, 0), 640 641 /* ENABLE_SCLK_TOP_DISP */ 642 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp", 643 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0, 644 CLK_IGNORE_UNUSED, 0), 645 646 /* ENABLE_SCLK_TOP_FSYS */ 647 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100", 648 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0), 649 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", 650 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), 651 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", 652 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0), 653 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b", 654 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0), 655 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys", 656 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS, 657 3, CLK_SET_RATE_PARENT, 0), 658 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys", 659 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS, 660 1, CLK_SET_RATE_PARENT, 0), 661 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys", 662 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS, 663 0, CLK_SET_RATE_PARENT, 0), 664 665 /* ENABLE_SCLK_TOP_PERIC */ 666 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b", 667 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0), 668 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b", 669 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0), 670 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif", 671 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0), 672 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1", 673 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0), 674 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1", 675 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0), 676 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2", 677 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT | 678 CLK_IGNORE_UNUSED, 0), 679 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1", 680 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT | 681 CLK_IGNORE_UNUSED, 0), 682 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0", 683 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT | 684 CLK_IGNORE_UNUSED, 0), 685 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b", 686 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0), 687 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b", 688 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0), 689 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b", 690 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0), 691 692 /* MUX_ENABLE_TOP_PERIC1 */ 693 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus", 694 MUX_ENABLE_TOP_PERIC1, 16, 0, 0), 695 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1", 696 MUX_ENABLE_TOP_PERIC1, 4, 0, 0), 697 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0", 698 MUX_ENABLE_TOP_PERIC1, 0, 0, 0), 699 }; 700 701 /* 702 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL 703 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL 704 */ 705 static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = { 706 PLL_35XX_RATE(2500000000U, 625, 6, 0), 707 PLL_35XX_RATE(2400000000U, 500, 5, 0), 708 PLL_35XX_RATE(2300000000U, 575, 6, 0), 709 PLL_35XX_RATE(2200000000U, 550, 6, 0), 710 PLL_35XX_RATE(2100000000U, 350, 4, 0), 711 PLL_35XX_RATE(2000000000U, 500, 6, 0), 712 PLL_35XX_RATE(1900000000U, 475, 6, 0), 713 PLL_35XX_RATE(1800000000U, 375, 5, 0), 714 PLL_35XX_RATE(1700000000U, 425, 6, 0), 715 PLL_35XX_RATE(1600000000U, 400, 6, 0), 716 PLL_35XX_RATE(1500000000U, 250, 4, 0), 717 PLL_35XX_RATE(1400000000U, 350, 6, 0), 718 PLL_35XX_RATE(1332000000U, 222, 4, 0), 719 PLL_35XX_RATE(1300000000U, 325, 6, 0), 720 PLL_35XX_RATE(1200000000U, 500, 5, 1), 721 PLL_35XX_RATE(1100000000U, 550, 6, 1), 722 PLL_35XX_RATE(1086000000U, 362, 4, 1), 723 PLL_35XX_RATE(1066000000U, 533, 6, 1), 724 PLL_35XX_RATE(1000000000U, 500, 6, 1), 725 PLL_35XX_RATE(933000000U, 311, 4, 1), 726 PLL_35XX_RATE(921000000U, 307, 4, 1), 727 PLL_35XX_RATE(900000000U, 375, 5, 1), 728 PLL_35XX_RATE(825000000U, 275, 4, 1), 729 PLL_35XX_RATE(800000000U, 400, 6, 1), 730 PLL_35XX_RATE(733000000U, 733, 12, 1), 731 PLL_35XX_RATE(700000000U, 175, 3, 1), 732 PLL_35XX_RATE(667000000U, 222, 4, 1), 733 PLL_35XX_RATE(633000000U, 211, 4, 1), 734 PLL_35XX_RATE(600000000U, 500, 5, 2), 735 PLL_35XX_RATE(552000000U, 460, 5, 2), 736 PLL_35XX_RATE(550000000U, 550, 6, 2), 737 PLL_35XX_RATE(543000000U, 362, 4, 2), 738 PLL_35XX_RATE(533000000U, 533, 6, 2), 739 PLL_35XX_RATE(500000000U, 500, 6, 2), 740 PLL_35XX_RATE(444000000U, 370, 5, 2), 741 PLL_35XX_RATE(420000000U, 350, 5, 2), 742 PLL_35XX_RATE(400000000U, 400, 6, 2), 743 PLL_35XX_RATE(350000000U, 350, 6, 2), 744 PLL_35XX_RATE(333000000U, 222, 4, 2), 745 PLL_35XX_RATE(300000000U, 500, 5, 3), 746 PLL_35XX_RATE(278000000U, 556, 6, 3), 747 PLL_35XX_RATE(266000000U, 532, 6, 3), 748 PLL_35XX_RATE(250000000U, 500, 6, 3), 749 PLL_35XX_RATE(200000000U, 400, 6, 3), 750 PLL_35XX_RATE(166000000U, 332, 6, 3), 751 PLL_35XX_RATE(160000000U, 320, 6, 3), 752 PLL_35XX_RATE(133000000U, 532, 6, 4), 753 PLL_35XX_RATE(100000000U, 400, 6, 4), 754 { /* sentinel */ } 755 }; 756 757 /* AUD_PLL */ 758 static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = { 759 PLL_36XX_RATE(400000000U, 200, 3, 2, 0), 760 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), 761 PLL_36XX_RATE(384000000U, 128, 2, 2, 0), 762 PLL_36XX_RATE(368640000U, 246, 4, 2, -15729), 763 PLL_36XX_RATE(361507200U, 181, 3, 2, -16148), 764 PLL_36XX_RATE(338688000U, 113, 2, 2, -6816), 765 PLL_36XX_RATE(294912000U, 98, 1, 3, 19923), 766 PLL_36XX_RATE(288000000U, 96, 1, 3, 0), 767 PLL_36XX_RATE(252000000U, 84, 1, 3, 0), 768 { /* sentinel */ } 769 }; 770 771 static const struct samsung_pll_clock top_pll_clks[] __initconst = { 772 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", 773 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates), 774 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 775 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates), 776 }; 777 778 static const struct samsung_cmu_info top_cmu_info __initconst = { 779 .pll_clks = top_pll_clks, 780 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 781 .mux_clks = top_mux_clks, 782 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 783 .div_clks = top_div_clks, 784 .nr_div_clks = ARRAY_SIZE(top_div_clks), 785 .gate_clks = top_gate_clks, 786 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 787 .fixed_clks = top_fixed_clks, 788 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks), 789 .fixed_factor_clks = top_fixed_factor_clks, 790 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), 791 .nr_clk_ids = TOP_NR_CLK, 792 .clk_regs = top_clk_regs, 793 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 794 }; 795 796 static void __init exynos5433_cmu_top_init(struct device_node *np) 797 { 798 samsung_cmu_register_one(np, &top_cmu_info); 799 } 800 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", 801 exynos5433_cmu_top_init); 802 803 /* 804 * Register offset definitions for CMU_CPIF 805 */ 806 #define MPHY_PLL_LOCK 0x0000 807 #define MPHY_PLL_CON0 0x0100 808 #define MPHY_PLL_CON1 0x0104 809 #define MPHY_PLL_FREQ_DET 0x010c 810 #define MUX_SEL_CPIF0 0x0200 811 #define DIV_CPIF 0x0600 812 #define ENABLE_SCLK_CPIF 0x0a00 813 814 static const unsigned long cpif_clk_regs[] __initconst = { 815 MPHY_PLL_LOCK, 816 MPHY_PLL_CON0, 817 MPHY_PLL_CON1, 818 MPHY_PLL_FREQ_DET, 819 MUX_SEL_CPIF0, 820 DIV_CPIF, 821 ENABLE_SCLK_CPIF, 822 }; 823 824 /* list of all parent clock list */ 825 PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; 826 827 static const struct samsung_pll_clock cpif_pll_clks[] __initconst = { 828 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", 829 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates), 830 }; 831 832 static const struct samsung_mux_clock cpif_mux_clks[] __initconst = { 833 /* MUX_SEL_CPIF0 */ 834 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, 835 0, 1), 836 }; 837 838 static const struct samsung_div_clock cpif_div_clks[] __initconst = { 839 /* DIV_CPIF */ 840 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, 841 0, 6), 842 }; 843 844 static const struct samsung_gate_clock cpif_gate_clks[] __initconst = { 845 /* ENABLE_SCLK_CPIF */ 846 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", 847 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0), 848 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy", 849 ENABLE_SCLK_CPIF, 4, 0, 0), 850 }; 851 852 static const struct samsung_cmu_info cpif_cmu_info __initconst = { 853 .pll_clks = cpif_pll_clks, 854 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), 855 .mux_clks = cpif_mux_clks, 856 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks), 857 .div_clks = cpif_div_clks, 858 .nr_div_clks = ARRAY_SIZE(cpif_div_clks), 859 .gate_clks = cpif_gate_clks, 860 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks), 861 .nr_clk_ids = CPIF_NR_CLK, 862 .clk_regs = cpif_clk_regs, 863 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), 864 }; 865 866 static void __init exynos5433_cmu_cpif_init(struct device_node *np) 867 { 868 samsung_cmu_register_one(np, &cpif_cmu_info); 869 } 870 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", 871 exynos5433_cmu_cpif_init); 872 873 /* 874 * Register offset definitions for CMU_MIF 875 */ 876 #define MEM0_PLL_LOCK 0x0000 877 #define MEM1_PLL_LOCK 0x0004 878 #define BUS_PLL_LOCK 0x0008 879 #define MFC_PLL_LOCK 0x000c 880 #define MEM0_PLL_CON0 0x0100 881 #define MEM0_PLL_CON1 0x0104 882 #define MEM0_PLL_FREQ_DET 0x010c 883 #define MEM1_PLL_CON0 0x0110 884 #define MEM1_PLL_CON1 0x0114 885 #define MEM1_PLL_FREQ_DET 0x011c 886 #define BUS_PLL_CON0 0x0120 887 #define BUS_PLL_CON1 0x0124 888 #define BUS_PLL_FREQ_DET 0x012c 889 #define MFC_PLL_CON0 0x0130 890 #define MFC_PLL_CON1 0x0134 891 #define MFC_PLL_FREQ_DET 0x013c 892 #define MUX_SEL_MIF0 0x0200 893 #define MUX_SEL_MIF1 0x0204 894 #define MUX_SEL_MIF2 0x0208 895 #define MUX_SEL_MIF3 0x020c 896 #define MUX_SEL_MIF4 0x0210 897 #define MUX_SEL_MIF5 0x0214 898 #define MUX_SEL_MIF6 0x0218 899 #define MUX_SEL_MIF7 0x021c 900 #define MUX_ENABLE_MIF0 0x0300 901 #define MUX_ENABLE_MIF1 0x0304 902 #define MUX_ENABLE_MIF2 0x0308 903 #define MUX_ENABLE_MIF3 0x030c 904 #define MUX_ENABLE_MIF4 0x0310 905 #define MUX_ENABLE_MIF5 0x0314 906 #define MUX_ENABLE_MIF6 0x0318 907 #define MUX_ENABLE_MIF7 0x031c 908 #define MUX_STAT_MIF0 0x0400 909 #define MUX_STAT_MIF1 0x0404 910 #define MUX_STAT_MIF2 0x0408 911 #define MUX_STAT_MIF3 0x040c 912 #define MUX_STAT_MIF4 0x0410 913 #define MUX_STAT_MIF5 0x0414 914 #define MUX_STAT_MIF6 0x0418 915 #define MUX_STAT_MIF7 0x041c 916 #define DIV_MIF1 0x0604 917 #define DIV_MIF2 0x0608 918 #define DIV_MIF3 0x060c 919 #define DIV_MIF4 0x0610 920 #define DIV_MIF5 0x0614 921 #define DIV_MIF_PLL_FREQ_DET 0x0618 922 #define DIV_STAT_MIF1 0x0704 923 #define DIV_STAT_MIF2 0x0708 924 #define DIV_STAT_MIF3 0x070c 925 #define DIV_STAT_MIF4 0x0710 926 #define DIV_STAT_MIF5 0x0714 927 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718 928 #define ENABLE_ACLK_MIF0 0x0800 929 #define ENABLE_ACLK_MIF1 0x0804 930 #define ENABLE_ACLK_MIF2 0x0808 931 #define ENABLE_ACLK_MIF3 0x080c 932 #define ENABLE_PCLK_MIF 0x0900 933 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904 934 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908 935 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c 936 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910 937 #define ENABLE_SCLK_MIF 0x0a00 938 #define ENABLE_IP_MIF0 0x0b00 939 #define ENABLE_IP_MIF1 0x0b04 940 #define ENABLE_IP_MIF2 0x0b08 941 #define ENABLE_IP_MIF3 0x0b0c 942 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10 943 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14 944 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18 945 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c 946 #define CLKOUT_CMU_MIF 0x0c00 947 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 948 #define DREX_FREQ_CTRL0 0x1000 949 #define DREX_FREQ_CTRL1 0x1004 950 #define PAUSE 0x1008 951 #define DDRPHY_LOCK_CTRL 0x100c 952 953 static const unsigned long mif_clk_regs[] __initconst = { 954 MEM0_PLL_LOCK, 955 MEM1_PLL_LOCK, 956 BUS_PLL_LOCK, 957 MFC_PLL_LOCK, 958 MEM0_PLL_CON0, 959 MEM0_PLL_CON1, 960 MEM0_PLL_FREQ_DET, 961 MEM1_PLL_CON0, 962 MEM1_PLL_CON1, 963 MEM1_PLL_FREQ_DET, 964 BUS_PLL_CON0, 965 BUS_PLL_CON1, 966 BUS_PLL_FREQ_DET, 967 MFC_PLL_CON0, 968 MFC_PLL_CON1, 969 MFC_PLL_FREQ_DET, 970 MUX_SEL_MIF0, 971 MUX_SEL_MIF1, 972 MUX_SEL_MIF2, 973 MUX_SEL_MIF3, 974 MUX_SEL_MIF4, 975 MUX_SEL_MIF5, 976 MUX_SEL_MIF6, 977 MUX_SEL_MIF7, 978 MUX_ENABLE_MIF0, 979 MUX_ENABLE_MIF1, 980 MUX_ENABLE_MIF2, 981 MUX_ENABLE_MIF3, 982 MUX_ENABLE_MIF4, 983 MUX_ENABLE_MIF5, 984 MUX_ENABLE_MIF6, 985 MUX_ENABLE_MIF7, 986 DIV_MIF1, 987 DIV_MIF2, 988 DIV_MIF3, 989 DIV_MIF4, 990 DIV_MIF5, 991 DIV_MIF_PLL_FREQ_DET, 992 ENABLE_ACLK_MIF0, 993 ENABLE_ACLK_MIF1, 994 ENABLE_ACLK_MIF2, 995 ENABLE_ACLK_MIF3, 996 ENABLE_PCLK_MIF, 997 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 998 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 999 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 1000 ENABLE_PCLK_MIF_SECURE_RTC, 1001 ENABLE_SCLK_MIF, 1002 ENABLE_IP_MIF0, 1003 ENABLE_IP_MIF1, 1004 ENABLE_IP_MIF2, 1005 ENABLE_IP_MIF3, 1006 ENABLE_IP_MIF_SECURE_DREX0_TZ, 1007 ENABLE_IP_MIF_SECURE_DREX1_TZ, 1008 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT, 1009 ENABLE_IP_MIF_SECURE_RTC, 1010 CLKOUT_CMU_MIF, 1011 CLKOUT_CMU_MIF_DIV_STAT, 1012 DREX_FREQ_CTRL0, 1013 DREX_FREQ_CTRL1, 1014 PAUSE, 1015 DDRPHY_LOCK_CTRL, 1016 }; 1017 1018 static const struct samsung_pll_clock mif_pll_clks[] __initconst = { 1019 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", 1020 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates), 1021 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", 1022 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates), 1023 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk", 1024 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates), 1025 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk", 1026 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates), 1027 }; 1028 1029 /* list of all parent clock list */ 1030 PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", }; 1031 PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", }; 1032 PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", }; 1033 PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", }; 1034 PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", }; 1035 PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", }; 1036 PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", }; 1037 PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", }; 1038 1039 PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", }; 1040 PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", }; 1041 PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", }; 1042 PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", }; 1043 1044 PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", }; 1045 PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",}; 1046 1047 PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a", 1048 "mout_bus_pll_div2", }; 1049 PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", }; 1050 1051 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b", 1052 "sclk_mphy_pll", }; 1053 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a", 1054 "mout_mfc_pll_div2", }; 1055 PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", }; 1056 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b", 1057 "sclk_mphy_pll", }; 1058 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a", 1059 "mout_mfc_pll_div2", }; 1060 1061 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b", 1062 "sclk_mphy_pll", }; 1063 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a", 1064 "mout_mfc_pll_div2", }; 1065 PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", }; 1066 PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", }; 1067 PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", }; 1068 1069 PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", }; 1070 PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" }; 1071 1072 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b", 1073 "sclk_mphy_pll", }; 1074 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a", 1075 "mout_mfc_pll_div2", }; 1076 PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; 1077 PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; 1078 1079 static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = { 1080 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ 1081 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), 1082 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), 1083 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0), 1084 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), 1085 }; 1086 1087 static const struct samsung_mux_clock mif_mux_clks[] __initconst = { 1088 /* MUX_SEL_MIF0 */ 1089 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, 1090 MUX_SEL_MIF0, 28, 1), 1091 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p, 1092 MUX_SEL_MIF0, 24, 1), 1093 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p, 1094 MUX_SEL_MIF0, 20, 1), 1095 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p, 1096 MUX_SEL_MIF0, 16, 1), 1097 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0, 1098 12, 1), 1099 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0, 1100 8, 1), 1101 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0, 1102 4, 1), 1103 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0, 1104 0, 1), 1105 1106 /* MUX_SEL_MIF1 */ 1107 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p, 1108 MUX_SEL_MIF1, 24, 1), 1109 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p, 1110 MUX_SEL_MIF1, 20, 1), 1111 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p, 1112 MUX_SEL_MIF1, 16, 1), 1113 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p, 1114 MUX_SEL_MIF1, 12, 1), 1115 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p, 1116 MUX_SEL_MIF1, 8, 1), 1117 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p, 1118 MUX_SEL_MIF1, 4, 1), 1119 1120 /* MUX_SEL_MIF2 */ 1121 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200", 1122 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1), 1123 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400", 1124 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1), 1125 1126 /* MUX_SEL_MIF3 */ 1127 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b", 1128 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1), 1129 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a", 1130 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1), 1131 1132 /* MUX_SEL_MIF4 */ 1133 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c", 1134 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1), 1135 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b", 1136 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1), 1137 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a", 1138 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1), 1139 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c", 1140 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1), 1141 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b", 1142 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1), 1143 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a", 1144 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1), 1145 1146 /* MUX_SEL_MIF5 */ 1147 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c", 1148 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1), 1149 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b", 1150 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1), 1151 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a", 1152 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1), 1153 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p, 1154 MUX_SEL_MIF5, 8, 1), 1155 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p, 1156 MUX_SEL_MIF5, 4, 1), 1157 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p, 1158 MUX_SEL_MIF5, 0, 1), 1159 1160 /* MUX_SEL_MIF6 */ 1161 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p, 1162 MUX_SEL_MIF6, 8, 1), 1163 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p, 1164 MUX_SEL_MIF6, 4, 1), 1165 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p, 1166 MUX_SEL_MIF6, 0, 1), 1167 1168 /* MUX_SEL_MIF7 */ 1169 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c", 1170 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1), 1171 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b", 1172 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1), 1173 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a", 1174 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1), 1175 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p, 1176 MUX_SEL_MIF7, 8, 1), 1177 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p, 1178 MUX_SEL_MIF7, 4, 1), 1179 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p, 1180 MUX_SEL_MIF7, 0, 1), 1181 }; 1182 1183 static const struct samsung_div_clock mif_div_clks[] __initconst = { 1184 /* DIV_MIF1 */ 1185 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", 1186 DIV_MIF1, 16, 2), 1187 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1, 1188 12, 2), 1189 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1, 1190 8, 2), 1191 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1, 1192 4, 4), 1193 1194 /* DIV_MIF2 */ 1195 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2", 1196 DIV_MIF2, 20, 3), 1197 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre", 1198 DIV_MIF2, 16, 4), 1199 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre", 1200 DIV_MIF2, 12, 4), 1201 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200", 1202 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3), 1203 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400", 1204 DIV_MIF2, 4, 2), 1205 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400", 1206 DIV_MIF2, 0, 3), 1207 1208 /* DIV_MIF3 */ 1209 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre", 1210 DIV_MIF3, 16, 4), 1211 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b", 1212 DIV_MIF3, 4, 3), 1213 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200", 1214 DIV_MIF3, 0, 3), 1215 1216 /* DIV_MIF4 */ 1217 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c", 1218 DIV_MIF4, 24, 4), 1219 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk", 1220 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4), 1221 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c", 1222 DIV_MIF4, 16, 4), 1223 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c", 1224 DIV_MIF4, 12, 4), 1225 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk", 1226 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4), 1227 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk", 1228 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4), 1229 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk", 1230 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4), 1231 1232 /* DIV_MIF5 */ 1233 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5, 1234 0, 3), 1235 }; 1236 1237 static const struct samsung_gate_clock mif_gate_clks[] __initconst = { 1238 /* ENABLE_ACLK_MIF0 */ 1239 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1240 19, CLK_IGNORE_UNUSED, 0), 1241 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1242 18, CLK_IGNORE_UNUSED, 0), 1243 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, 1244 17, CLK_IGNORE_UNUSED, 0), 1245 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, 1246 16, CLK_IGNORE_UNUSED, 0), 1247 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0, 1248 15, CLK_IGNORE_UNUSED, 0), 1249 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0, 1250 14, CLK_IGNORE_UNUSED, 0), 1251 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1", 1252 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0), 1253 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0", 1254 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0), 1255 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1", 1256 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0), 1257 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0", 1258 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0), 1259 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1", 1260 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0), 1261 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0", 1262 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0), 1263 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1", 1264 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0), 1265 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0", 1266 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0), 1267 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1", 1268 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0), 1269 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0", 1270 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0), 1271 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1", 1272 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0), 1273 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0", 1274 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), 1275 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1", 1276 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), 1277 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0", 1278 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0), 1279 1280 /* ENABLE_ACLK_MIF1 */ 1281 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem", 1282 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28, 1283 CLK_IGNORE_UNUSED, 0), 1284 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci", 1285 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 1286 27, CLK_IGNORE_UNUSED, 0), 1287 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci", 1288 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1289 26, CLK_IGNORE_UNUSED, 0), 1290 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1", 1291 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, 1292 25, CLK_IGNORE_UNUSED, 0), 1293 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1", 1294 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1295 24, CLK_IGNORE_UNUSED, 0), 1296 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0", 1297 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, 1298 23, CLK_IGNORE_UNUSED, 0), 1299 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0", 1300 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1301 22, CLK_IGNORE_UNUSED, 0), 1302 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3", 1303 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1304 21, CLK_IGNORE_UNUSED, 0), 1305 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3", 1306 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1307 20, CLK_IGNORE_UNUSED, 0), 1308 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1", 1309 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1310 19, CLK_IGNORE_UNUSED, 0), 1311 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1", 1312 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1313 18, CLK_IGNORE_UNUSED, 0), 1314 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0", 1315 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1316 17, CLK_IGNORE_UNUSED, 0), 1317 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0", 1318 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1319 16, CLK_IGNORE_UNUSED, 0), 1320 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3", 1321 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1322 15, CLK_IGNORE_UNUSED, 0), 1323 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3", 1324 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1325 14, CLK_IGNORE_UNUSED, 0), 1326 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1", 1327 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1328 13, CLK_IGNORE_UNUSED, 0), 1329 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1", 1330 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1331 12, CLK_IGNORE_UNUSED, 0), 1332 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0", 1333 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1334 11, CLK_IGNORE_UNUSED, 0), 1335 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0", 1336 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1337 10, CLK_IGNORE_UNUSED, 0), 1338 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133", 1339 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0), 1340 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133", 1341 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0), 1342 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133", 1343 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0), 1344 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400", 1345 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0), 1346 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200", 1347 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0), 1348 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133", 1349 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0), 1350 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200", 1351 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0), 1352 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133", 1353 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0), 1354 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400", 1355 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0), 1356 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1, 1357 0, CLK_IGNORE_UNUSED, 0), 1358 1359 /* ENABLE_ACLK_MIF2 */ 1360 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266", 1361 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0), 1362 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1", 1363 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0), 1364 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1", 1365 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0), 1366 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1", 1367 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0), 1368 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0", 1369 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0), 1370 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0", 1371 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0), 1372 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0", 1373 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0), 1374 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx", 1375 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7, 1376 CLK_IGNORE_UNUSED, 0), 1377 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci", 1378 "div_aclk_mif_400", ENABLE_ACLK_MIF2, 1379 5, CLK_IGNORE_UNUSED, 0), 1380 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400", 1381 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0), 1382 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d", 1383 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 1384 3, CLK_IGNORE_UNUSED, 0), 1385 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys", 1386 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0), 1387 1388 /* ENABLE_ACLK_MIF3 */ 1389 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400", 1390 ENABLE_ACLK_MIF3, 4, 1391 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 1392 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333", 1393 ENABLE_ACLK_MIF3, 1, 1394 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 1395 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200", 1396 ENABLE_ACLK_MIF3, 0, 1397 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1398 1399 /* ENABLE_PCLK_MIF */ 1400 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1", 1401 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0), 1402 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1", 1403 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0), 1404 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1", 1405 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0), 1406 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0", 1407 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0), 1408 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0", 1409 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0), 1410 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0", 1411 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0), 1412 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci", 1413 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21, 1414 CLK_IGNORE_UNUSED, 0), 1415 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133", 1416 ENABLE_PCLK_MIF, 19, 0, 0), 1417 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133", 1418 ENABLE_PCLK_MIF, 18, 0, 0), 1419 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3", 1420 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0), 1421 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1", 1422 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0), 1423 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0", 1424 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0), 1425 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3", 1426 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0), 1427 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1", 1428 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0), 1429 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0", 1430 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0), 1431 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133", 1432 ENABLE_PCLK_MIF, 11, 0, 0), 1433 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133", 1434 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0), 1435 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133", 1436 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), 1437 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133", 1438 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), 1439 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133", 1440 ENABLE_PCLK_MIF, 7, 0, 0), 1441 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133", 1442 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0), 1443 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133", 1444 ENABLE_PCLK_MIF, 5, 0, 0), 1445 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133", 1446 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), 1447 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133", 1448 ENABLE_PCLK_MIF, 2, 0, 0), 1449 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133", 1450 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1451 1452 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ 1453 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133", 1454 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 1455 CLK_IGNORE_UNUSED, 0), 1456 1457 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ 1458 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133", 1459 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 1460 CLK_IGNORE_UNUSED, 0), 1461 1462 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ 1463 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", 1464 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0), 1465 1466 /* ENABLE_PCLK_MIF_SECURE_RTC */ 1467 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133", 1468 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), 1469 1470 /* ENABLE_SCLK_MIF */ 1471 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1", 1472 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0), 1473 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp", 1474 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, 1475 14, CLK_IGNORE_UNUSED, 0), 1476 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0", 1477 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), 1478 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd", 1479 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), 1480 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp", 1481 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, 1482 7, CLK_IGNORE_UNUSED, 0), 1483 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp", 1484 "div_sclk_decon_vclk", ENABLE_SCLK_MIF, 1485 6, CLK_IGNORE_UNUSED, 0), 1486 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp", 1487 "div_sclk_decon_eclk", ENABLE_SCLK_MIF, 1488 5, CLK_IGNORE_UNUSED, 0), 1489 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif", 1490 ENABLE_SCLK_MIF, 4, 1491 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1492 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2", 1493 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), 1494 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2", 1495 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0), 1496 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll", 1497 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0), 1498 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll", 1499 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1500 }; 1501 1502 static const struct samsung_cmu_info mif_cmu_info __initconst = { 1503 .pll_clks = mif_pll_clks, 1504 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), 1505 .mux_clks = mif_mux_clks, 1506 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks), 1507 .div_clks = mif_div_clks, 1508 .nr_div_clks = ARRAY_SIZE(mif_div_clks), 1509 .gate_clks = mif_gate_clks, 1510 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), 1511 .fixed_factor_clks = mif_fixed_factor_clks, 1512 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks), 1513 .nr_clk_ids = MIF_NR_CLK, 1514 .clk_regs = mif_clk_regs, 1515 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), 1516 }; 1517 1518 static void __init exynos5433_cmu_mif_init(struct device_node *np) 1519 { 1520 samsung_cmu_register_one(np, &mif_cmu_info); 1521 } 1522 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", 1523 exynos5433_cmu_mif_init); 1524 1525 /* 1526 * Register offset definitions for CMU_PERIC 1527 */ 1528 #define DIV_PERIC 0x0600 1529 #define DIV_STAT_PERIC 0x0700 1530 #define ENABLE_ACLK_PERIC 0x0800 1531 #define ENABLE_PCLK_PERIC0 0x0900 1532 #define ENABLE_PCLK_PERIC1 0x0904 1533 #define ENABLE_SCLK_PERIC 0x0A00 1534 #define ENABLE_IP_PERIC0 0x0B00 1535 #define ENABLE_IP_PERIC1 0x0B04 1536 #define ENABLE_IP_PERIC2 0x0B08 1537 1538 static const unsigned long peric_clk_regs[] __initconst = { 1539 DIV_PERIC, 1540 ENABLE_ACLK_PERIC, 1541 ENABLE_PCLK_PERIC0, 1542 ENABLE_PCLK_PERIC1, 1543 ENABLE_SCLK_PERIC, 1544 ENABLE_IP_PERIC0, 1545 ENABLE_IP_PERIC1, 1546 ENABLE_IP_PERIC2, 1547 }; 1548 1549 static const struct samsung_div_clock peric_div_clks[] __initconst = { 1550 /* DIV_PERIC */ 1551 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), 1552 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), 1553 }; 1554 1555 static const struct samsung_gate_clock peric_gate_clks[] __initconst = { 1556 /* ENABLE_ACLK_PERIC */ 1557 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", 1558 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), 1559 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66", 1560 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0), 1561 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66", 1562 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0), 1563 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66", 1564 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0), 1565 1566 /* ENABLE_PCLK_PERIC0 */ 1567 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1568 31, CLK_SET_RATE_PARENT, 0), 1569 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66", 1570 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0), 1571 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66", 1572 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0), 1573 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1574 28, CLK_SET_RATE_PARENT, 0), 1575 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1576 26, CLK_SET_RATE_PARENT, 0), 1577 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1578 25, CLK_SET_RATE_PARENT, 0), 1579 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1580 24, CLK_SET_RATE_PARENT, 0), 1581 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1582 23, CLK_SET_RATE_PARENT, 0), 1583 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1584 22, CLK_SET_RATE_PARENT, 0), 1585 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1586 21, CLK_SET_RATE_PARENT, 0), 1587 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1588 20, CLK_SET_RATE_PARENT, 0), 1589 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66", 1590 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0), 1591 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66", 1592 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0), 1593 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66", 1594 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0), 1595 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66", 1596 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0), 1597 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66", 1598 ENABLE_PCLK_PERIC0, 15, 1599 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1600 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1601 14, CLK_SET_RATE_PARENT, 0), 1602 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1603 13, CLK_SET_RATE_PARENT, 0), 1604 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1605 12, CLK_SET_RATE_PARENT, 0), 1606 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66", 1607 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0), 1608 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66", 1609 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0), 1610 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66", 1611 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0), 1612 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66", 1613 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 1614 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1615 7, CLK_SET_RATE_PARENT, 0), 1616 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1617 6, CLK_SET_RATE_PARENT, 0), 1618 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1619 5, CLK_SET_RATE_PARENT, 0), 1620 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1621 4, CLK_SET_RATE_PARENT, 0), 1622 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1623 3, CLK_SET_RATE_PARENT, 0), 1624 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1625 2, CLK_SET_RATE_PARENT, 0), 1626 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1627 1, CLK_SET_RATE_PARENT, 0), 1628 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1629 0, CLK_SET_RATE_PARENT, 0), 1630 1631 /* ENABLE_PCLK_PERIC1 */ 1632 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1, 1633 9, CLK_SET_RATE_PARENT, 0), 1634 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1, 1635 8, CLK_SET_RATE_PARENT, 0), 1636 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66", 1637 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0), 1638 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66", 1639 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0), 1640 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66", 1641 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0), 1642 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66", 1643 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 1644 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66", 1645 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0), 1646 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66", 1647 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0), 1648 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66", 1649 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0), 1650 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66", 1651 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 1652 1653 /* ENABLE_SCLK_PERIC */ 1654 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in", 1655 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0), 1656 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in", 1657 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0), 1658 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC, 1659 19, CLK_SET_RATE_PARENT, 0), 1660 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC, 1661 18, CLK_SET_RATE_PARENT, 0), 1662 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC, 1663 17, 0, 0), 1664 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC, 1665 16, 0, 0), 1666 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0), 1667 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in", 1668 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), 1669 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", 1670 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0), 1671 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", 1672 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1673 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", 1674 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10, 1675 CLK_SET_RATE_PARENT, 0), 1676 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric", 1677 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 1678 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric", 1679 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 1680 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric", 1681 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 1682 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, 1683 5, CLK_SET_RATE_PARENT, 0), 1684 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, 1685 4, CLK_SET_RATE_PARENT, 0), 1686 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, 1687 3, CLK_SET_RATE_PARENT, 0), 1688 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", 1689 ENABLE_SCLK_PERIC, 2, 1690 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1691 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric", 1692 ENABLE_SCLK_PERIC, 1, 1693 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1694 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric", 1695 ENABLE_SCLK_PERIC, 0, 1696 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1697 }; 1698 1699 static const struct samsung_cmu_info peric_cmu_info __initconst = { 1700 .div_clks = peric_div_clks, 1701 .nr_div_clks = ARRAY_SIZE(peric_div_clks), 1702 .gate_clks = peric_gate_clks, 1703 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), 1704 .nr_clk_ids = PERIC_NR_CLK, 1705 .clk_regs = peric_clk_regs, 1706 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), 1707 }; 1708 1709 static void __init exynos5433_cmu_peric_init(struct device_node *np) 1710 { 1711 samsung_cmu_register_one(np, &peric_cmu_info); 1712 } 1713 1714 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", 1715 exynos5433_cmu_peric_init); 1716 1717 /* 1718 * Register offset definitions for CMU_PERIS 1719 */ 1720 #define ENABLE_ACLK_PERIS 0x0800 1721 #define ENABLE_PCLK_PERIS 0x0900 1722 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904 1723 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908 1724 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c 1725 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910 1726 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914 1727 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918 1728 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c 1729 #define ENABLE_SCLK_PERIS 0x0a00 1730 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04 1731 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08 1732 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c 1733 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10 1734 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14 1735 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18 1736 #define ENABLE_IP_PERIS0 0x0b00 1737 #define ENABLE_IP_PERIS1 0x0b04 1738 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08 1739 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c 1740 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10 1741 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14 1742 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18 1743 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c 1744 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 1745 1746 static const unsigned long peris_clk_regs[] __initconst = { 1747 ENABLE_ACLK_PERIS, 1748 ENABLE_PCLK_PERIS, 1749 ENABLE_PCLK_PERIS_SECURE_TZPC, 1750 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 1751 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 1752 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 1753 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 1754 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 1755 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 1756 ENABLE_SCLK_PERIS, 1757 ENABLE_SCLK_PERIS_SECURE_SECKEY, 1758 ENABLE_SCLK_PERIS_SECURE_CHIPID, 1759 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 1760 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 1761 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 1762 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 1763 ENABLE_IP_PERIS0, 1764 ENABLE_IP_PERIS1, 1765 ENABLE_IP_PERIS_SECURE_TZPC, 1766 ENABLE_IP_PERIS_SECURE_SECKEY, 1767 ENABLE_IP_PERIS_SECURE_CHIPID, 1768 ENABLE_IP_PERIS_SECURE_TOPRTC, 1769 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE, 1770 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT, 1771 ENABLE_IP_PERIS_SECURE_OTP_CON, 1772 }; 1773 1774 static const struct samsung_gate_clock peris_gate_clks[] __initconst = { 1775 /* ENABLE_ACLK_PERIS */ 1776 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", 1777 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), 1778 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66", 1779 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1780 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66", 1781 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1782 1783 /* ENABLE_PCLK_PERIS */ 1784 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66", 1785 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0), 1786 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66", 1787 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0), 1788 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66", 1789 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0), 1790 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66", 1791 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0), 1792 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66", 1793 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0), 1794 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66", 1795 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0), 1796 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66", 1797 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0), 1798 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66", 1799 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0), 1800 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66", 1801 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0), 1802 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66", 1803 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0), 1804 1805 /* ENABLE_PCLK_PERIS_SECURE_TZPC */ 1806 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66", 1807 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0), 1808 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66", 1809 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0), 1810 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66", 1811 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0), 1812 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66", 1813 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0), 1814 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66", 1815 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0), 1816 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66", 1817 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0), 1818 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66", 1819 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0), 1820 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66", 1821 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0), 1822 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66", 1823 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0), 1824 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66", 1825 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0), 1826 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66", 1827 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0), 1828 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66", 1829 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0), 1830 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66", 1831 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0), 1832 1833 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ 1834 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66", 1835 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0), 1836 1837 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ 1838 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66", 1839 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0), 1840 1841 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ 1842 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66", 1843 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), 1844 1845 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */ 1846 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif", 1847 "aclk_peris_66", 1848 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0), 1849 1850 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */ 1851 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif", 1852 "aclk_peris_66", 1853 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0), 1854 1855 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */ 1856 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif", 1857 "aclk_peris_66", 1858 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0), 1859 1860 /* ENABLE_SCLK_PERIS */ 1861 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common", 1862 ENABLE_SCLK_PERIS, 10, 0, 0), 1863 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common", 1864 ENABLE_SCLK_PERIS, 4, 0, 0), 1865 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common", 1866 ENABLE_SCLK_PERIS, 3, 0, 0), 1867 1868 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */ 1869 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common", 1870 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0), 1871 1872 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */ 1873 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common", 1874 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0), 1875 1876 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ 1877 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common", 1878 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), 1879 1880 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */ 1881 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common", 1882 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0), 1883 1884 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */ 1885 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common", 1886 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0), 1887 1888 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */ 1889 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common", 1890 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), 1891 }; 1892 1893 static const struct samsung_cmu_info peris_cmu_info __initconst = { 1894 .gate_clks = peris_gate_clks, 1895 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 1896 .nr_clk_ids = PERIS_NR_CLK, 1897 .clk_regs = peris_clk_regs, 1898 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 1899 }; 1900 1901 static void __init exynos5433_cmu_peris_init(struct device_node *np) 1902 { 1903 samsung_cmu_register_one(np, &peris_cmu_info); 1904 } 1905 1906 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", 1907 exynos5433_cmu_peris_init); 1908 1909 /* 1910 * Register offset definitions for CMU_FSYS 1911 */ 1912 #define MUX_SEL_FSYS0 0x0200 1913 #define MUX_SEL_FSYS1 0x0204 1914 #define MUX_SEL_FSYS2 0x0208 1915 #define MUX_SEL_FSYS3 0x020c 1916 #define MUX_SEL_FSYS4 0x0210 1917 #define MUX_ENABLE_FSYS0 0x0300 1918 #define MUX_ENABLE_FSYS1 0x0304 1919 #define MUX_ENABLE_FSYS2 0x0308 1920 #define MUX_ENABLE_FSYS3 0x030c 1921 #define MUX_ENABLE_FSYS4 0x0310 1922 #define MUX_STAT_FSYS0 0x0400 1923 #define MUX_STAT_FSYS1 0x0404 1924 #define MUX_STAT_FSYS2 0x0408 1925 #define MUX_STAT_FSYS3 0x040c 1926 #define MUX_STAT_FSYS4 0x0410 1927 #define MUX_IGNORE_FSYS2 0x0508 1928 #define MUX_IGNORE_FSYS3 0x050c 1929 #define ENABLE_ACLK_FSYS0 0x0800 1930 #define ENABLE_ACLK_FSYS1 0x0804 1931 #define ENABLE_PCLK_FSYS 0x0900 1932 #define ENABLE_SCLK_FSYS 0x0a00 1933 #define ENABLE_IP_FSYS0 0x0b00 1934 #define ENABLE_IP_FSYS1 0x0b04 1935 1936 /* list of all parent clock list */ 1937 PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", }; 1938 PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "aclk_fsys_200", }; 1939 PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",}; 1940 PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",}; 1941 PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", }; 1942 PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", }; 1943 PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", }; 1944 PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",}; 1945 PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", }; 1946 1947 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p) 1948 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", }; 1949 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p) 1950 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", }; 1951 PNAME(mout_phyclk_usbhost20_phy_hsic1_p) 1952 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", }; 1953 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p) 1954 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", }; 1955 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p) 1956 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", }; 1957 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p) 1958 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", }; 1959 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p) 1960 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", }; 1961 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p) 1962 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", }; 1963 PNAME(mout_phyclk_ufs_rx1_symbol_user_p) 1964 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", }; 1965 PNAME(mout_phyclk_ufs_rx0_symbol_user_p) 1966 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", }; 1967 PNAME(mout_phyclk_ufs_tx1_symbol_user_p) 1968 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", }; 1969 PNAME(mout_phyclk_ufs_tx0_symbol_user_p) 1970 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", }; 1971 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p) 1972 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", }; 1973 PNAME(mout_sclk_mphy_p) 1974 = { "mout_sclk_ufs_mphy_user", 1975 "mout_phyclk_lli_mphy_to_ufs_user", }; 1976 1977 static const unsigned long fsys_clk_regs[] __initconst = { 1978 MUX_SEL_FSYS0, 1979 MUX_SEL_FSYS1, 1980 MUX_SEL_FSYS2, 1981 MUX_SEL_FSYS3, 1982 MUX_SEL_FSYS4, 1983 MUX_ENABLE_FSYS0, 1984 MUX_ENABLE_FSYS1, 1985 MUX_ENABLE_FSYS2, 1986 MUX_ENABLE_FSYS3, 1987 MUX_ENABLE_FSYS4, 1988 MUX_IGNORE_FSYS2, 1989 MUX_IGNORE_FSYS3, 1990 ENABLE_ACLK_FSYS0, 1991 ENABLE_ACLK_FSYS1, 1992 ENABLE_PCLK_FSYS, 1993 ENABLE_SCLK_FSYS, 1994 ENABLE_IP_FSYS0, 1995 ENABLE_IP_FSYS1, 1996 }; 1997 1998 static const struct samsung_clk_reg_dump fsys_suspend_regs[] = { 1999 { MUX_SEL_FSYS0, 0 }, 2000 { MUX_SEL_FSYS1, 0 }, 2001 { MUX_SEL_FSYS2, 0 }, 2002 { MUX_SEL_FSYS3, 0 }, 2003 { MUX_SEL_FSYS4, 0 }, 2004 }; 2005 2006 static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = { 2007 /* PHY clocks from USBDRD30_PHY */ 2008 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, 2009 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, 2010 0, 60000000), 2011 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY, 2012 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL, 2013 0, 125000000), 2014 /* PHY clocks from USBHOST30_PHY */ 2015 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY, 2016 "phyclk_usbhost30_uhost30_phyclock_phy", NULL, 2017 0, 60000000), 2018 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY, 2019 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL, 2020 0, 125000000), 2021 /* PHY clocks from USBHOST20_PHY */ 2022 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY, 2023 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000), 2024 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY, 2025 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000), 2026 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY, 2027 "phyclk_usbhost20_phy_clk48mohci_phy", NULL, 2028 0, 48000000), 2029 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY, 2030 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0, 2031 60000000), 2032 /* PHY clocks from UFS_PHY */ 2033 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy", 2034 NULL, 0, 300000000), 2035 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy", 2036 NULL, 0, 300000000), 2037 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy", 2038 NULL, 0, 300000000), 2039 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy", 2040 NULL, 0, 300000000), 2041 /* PHY clocks from LLI_PHY */ 2042 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy", 2043 NULL, 0, 26000000), 2044 }; 2045 2046 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { 2047 /* MUX_SEL_FSYS0 */ 2048 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user", 2049 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1), 2050 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user", 2051 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1), 2052 2053 /* MUX_SEL_FSYS1 */ 2054 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user", 2055 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1), 2056 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user", 2057 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1), 2058 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user", 2059 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1), 2060 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user", 2061 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1), 2062 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user", 2063 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1), 2064 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user", 2065 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1), 2066 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user", 2067 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1), 2068 2069 /* MUX_SEL_FSYS2 */ 2070 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER, 2071 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", 2072 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p, 2073 MUX_SEL_FSYS2, 28, 1), 2074 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER, 2075 "mout_phyclk_usbhost30_uhost30_phyclock_user", 2076 mout_phyclk_usbhost30_uhost30_phyclock_user_p, 2077 MUX_SEL_FSYS2, 24, 1), 2078 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER, 2079 "mout_phyclk_usbhost20_phy_hsic1", 2080 mout_phyclk_usbhost20_phy_hsic1_p, 2081 MUX_SEL_FSYS2, 20, 1), 2082 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER, 2083 "mout_phyclk_usbhost20_phy_clk48mohci_user", 2084 mout_phyclk_usbhost20_phy_clk48mohci_user_p, 2085 MUX_SEL_FSYS2, 16, 1), 2086 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER, 2087 "mout_phyclk_usbhost20_phy_phyclock_user", 2088 mout_phyclk_usbhost20_phy_phyclock_user_p, 2089 MUX_SEL_FSYS2, 12, 1), 2090 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER, 2091 "mout_phyclk_usbhost20_phy_freeclk_user", 2092 mout_phyclk_usbhost20_phy_freeclk_user_p, 2093 MUX_SEL_FSYS2, 8, 1), 2094 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, 2095 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", 2096 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p, 2097 MUX_SEL_FSYS2, 4, 1), 2098 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, 2099 "mout_phyclk_usbdrd30_udrd30_phyclock_user", 2100 mout_phyclk_usbdrd30_udrd30_phyclock_user_p, 2101 MUX_SEL_FSYS2, 0, 1), 2102 2103 /* MUX_SEL_FSYS3 */ 2104 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER, 2105 "mout_phyclk_ufs_rx1_symbol_user", 2106 mout_phyclk_ufs_rx1_symbol_user_p, 2107 MUX_SEL_FSYS3, 16, 1), 2108 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER, 2109 "mout_phyclk_ufs_rx0_symbol_user", 2110 mout_phyclk_ufs_rx0_symbol_user_p, 2111 MUX_SEL_FSYS3, 12, 1), 2112 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER, 2113 "mout_phyclk_ufs_tx1_symbol_user", 2114 mout_phyclk_ufs_tx1_symbol_user_p, 2115 MUX_SEL_FSYS3, 8, 1), 2116 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER, 2117 "mout_phyclk_ufs_tx0_symbol_user", 2118 mout_phyclk_ufs_tx0_symbol_user_p, 2119 MUX_SEL_FSYS3, 4, 1), 2120 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER, 2121 "mout_phyclk_lli_mphy_to_ufs_user", 2122 mout_phyclk_lli_mphy_to_ufs_user_p, 2123 MUX_SEL_FSYS3, 0, 1), 2124 2125 /* MUX_SEL_FSYS4 */ 2126 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p, 2127 MUX_SEL_FSYS4, 0, 1), 2128 }; 2129 2130 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { 2131 /* ENABLE_ACLK_FSYS0 */ 2132 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", 2133 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), 2134 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user", 2135 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0), 2136 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user", 2137 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 2138 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user", 2139 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0), 2140 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user", 2141 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0), 2142 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user", 2143 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0), 2144 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user", 2145 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0), 2146 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user", 2147 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0), 2148 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user", 2149 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0), 2150 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user", 2151 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0), 2152 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user", 2153 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0), 2154 2155 /* ENABLE_ACLK_FSYS1 */ 2156 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user", 2157 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0), 2158 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1", 2159 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2160 26, CLK_IGNORE_UNUSED, 0), 2161 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2162 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0), 2163 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user", 2164 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0), 2165 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1", 2166 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2167 22, CLK_IGNORE_UNUSED, 0), 2168 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user", 2169 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0), 2170 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user", 2171 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0), 2172 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30", 2173 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2174 13, 0, 0), 2175 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30", 2176 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2177 12, 0, 0), 2178 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0", 2179 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2180 11, CLK_IGNORE_UNUSED, 0), 2181 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs", 2182 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2183 10, CLK_IGNORE_UNUSED, 0), 2184 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx", 2185 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2186 9, CLK_IGNORE_UNUSED, 0), 2187 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp", 2188 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2189 8, CLK_IGNORE_UNUSED, 0), 2190 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs", 2191 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2192 7, CLK_IGNORE_UNUSED, 0), 2193 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0", 2194 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2195 6, CLK_IGNORE_UNUSED, 0), 2196 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user", 2197 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0), 2198 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user", 2199 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0), 2200 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user", 2201 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0), 2202 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user", 2203 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0), 2204 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user", 2205 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0), 2206 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user", 2207 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0), 2208 2209 /* ENABLE_PCLK_FSYS */ 2210 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user", 2211 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0), 2212 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2213 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0), 2214 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user", 2215 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0), 2216 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user", 2217 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0), 2218 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user", 2219 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0), 2220 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user", 2221 ENABLE_PCLK_FSYS, 5, 0, 0), 2222 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30", 2223 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0), 2224 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30", 2225 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0), 2226 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user", 2227 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0), 2228 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user", 2229 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0), 2230 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys", 2231 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 2232 0, CLK_IGNORE_UNUSED, 0), 2233 2234 /* ENABLE_SCLK_FSYS */ 2235 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user", 2236 ENABLE_SCLK_FSYS, 21, 0, 0), 2237 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK, 2238 "phyclk_usbhost30_uhost30_pipe_pclk", 2239 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", 2240 ENABLE_SCLK_FSYS, 18, 0, 0), 2241 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK, 2242 "phyclk_usbhost30_uhost30_phyclock", 2243 "mout_phyclk_usbhost30_uhost30_phyclock_user", 2244 ENABLE_SCLK_FSYS, 17, 0, 0), 2245 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol", 2246 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS, 2247 16, 0, 0), 2248 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol", 2249 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS, 2250 15, 0, 0), 2251 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol", 2252 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS, 2253 14, 0, 0), 2254 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol", 2255 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS, 2256 13, 0, 0), 2257 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1", 2258 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS, 2259 12, 0, 0), 2260 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI, 2261 "phyclk_usbhost20_phy_clk48mohci", 2262 "mout_phyclk_usbhost20_phy_clk48mohci_user", 2263 ENABLE_SCLK_FSYS, 11, 0, 0), 2264 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK, 2265 "phyclk_usbhost20_phy_phyclock", 2266 "mout_phyclk_usbhost20_phy_phyclock_user", 2267 ENABLE_SCLK_FSYS, 10, 0, 0), 2268 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK, 2269 "phyclk_usbhost20_phy_freeclk", 2270 "mout_phyclk_usbhost20_phy_freeclk_user", 2271 ENABLE_SCLK_FSYS, 9, 0, 0), 2272 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, 2273 "phyclk_usbdrd30_udrd30_pipe_pclk", 2274 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", 2275 ENABLE_SCLK_FSYS, 8, 0, 0), 2276 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK, 2277 "phyclk_usbdrd30_udrd30_phyclock", 2278 "mout_phyclk_usbdrd30_udrd30_phyclock_user", 2279 ENABLE_SCLK_FSYS, 7, 0, 0), 2280 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy", 2281 ENABLE_SCLK_FSYS, 6, 0, 0), 2282 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user", 2283 ENABLE_SCLK_FSYS, 5, 0, 0), 2284 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user", 2285 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 2286 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user", 2287 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0), 2288 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user", 2289 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 2290 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user", 2291 ENABLE_SCLK_FSYS, 1, 0, 0), 2292 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user", 2293 ENABLE_SCLK_FSYS, 0, 0, 0), 2294 2295 /* ENABLE_IP_FSYS0 */ 2296 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0), 2297 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), 2298 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), 2299 }; 2300 2301 static const struct samsung_cmu_info fsys_cmu_info __initconst = { 2302 .mux_clks = fsys_mux_clks, 2303 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), 2304 .gate_clks = fsys_gate_clks, 2305 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), 2306 .fixed_clks = fsys_fixed_clks, 2307 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks), 2308 .nr_clk_ids = FSYS_NR_CLK, 2309 .clk_regs = fsys_clk_regs, 2310 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), 2311 .suspend_regs = fsys_suspend_regs, 2312 .nr_suspend_regs = ARRAY_SIZE(fsys_suspend_regs), 2313 .clk_name = "aclk_fsys_200", 2314 }; 2315 2316 /* 2317 * Register offset definitions for CMU_G2D 2318 */ 2319 #define MUX_SEL_G2D0 0x0200 2320 #define MUX_SEL_ENABLE_G2D0 0x0300 2321 #define MUX_SEL_STAT_G2D0 0x0400 2322 #define DIV_G2D 0x0600 2323 #define DIV_STAT_G2D 0x0700 2324 #define DIV_ENABLE_ACLK_G2D 0x0800 2325 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804 2326 #define DIV_ENABLE_PCLK_G2D 0x0900 2327 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904 2328 #define DIV_ENABLE_IP_G2D0 0x0b00 2329 #define DIV_ENABLE_IP_G2D1 0x0b04 2330 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 2331 2332 static const unsigned long g2d_clk_regs[] __initconst = { 2333 MUX_SEL_G2D0, 2334 MUX_SEL_ENABLE_G2D0, 2335 DIV_G2D, 2336 DIV_ENABLE_ACLK_G2D, 2337 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 2338 DIV_ENABLE_PCLK_G2D, 2339 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 2340 DIV_ENABLE_IP_G2D0, 2341 DIV_ENABLE_IP_G2D1, 2342 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D, 2343 }; 2344 2345 static const struct samsung_clk_reg_dump g2d_suspend_regs[] = { 2346 { MUX_SEL_G2D0, 0 }, 2347 }; 2348 2349 /* list of all parent clock list */ 2350 PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; 2351 PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; 2352 2353 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = { 2354 /* MUX_SEL_G2D0 */ 2355 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", 2356 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), 2357 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user", 2358 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), 2359 }; 2360 2361 static const struct samsung_div_clock g2d_div_clks[] __initconst = { 2362 /* DIV_G2D */ 2363 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", 2364 DIV_G2D, 0, 2), 2365 }; 2366 2367 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = { 2368 /* DIV_ENABLE_ACLK_G2D */ 2369 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", 2370 DIV_ENABLE_ACLK_G2D, 12, 0, 0), 2371 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user", 2372 DIV_ENABLE_ACLK_G2D, 11, 0, 0), 2373 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user", 2374 DIV_ENABLE_ACLK_G2D, 10, 0, 0), 2375 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user", 2376 DIV_ENABLE_ACLK_G2D, 9, 0, 0), 2377 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user", 2378 DIV_ENABLE_ACLK_G2D, 8, 0, 0), 2379 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx", 2380 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D, 2381 7, 0, 0), 2382 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d", 2383 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0), 2384 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d", 2385 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0), 2386 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user", 2387 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0), 2388 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d", 2389 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0), 2390 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user", 2391 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0), 2392 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user", 2393 DIV_ENABLE_ACLK_G2D, 1, 0, 0), 2394 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user", 2395 DIV_ENABLE_ACLK_G2D, 0, 0, 0), 2396 2397 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */ 2398 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user", 2399 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2400 2401 /* DIV_ENABLE_PCLK_G2D */ 2402 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d", 2403 DIV_ENABLE_PCLK_G2D, 7, 0, 0), 2404 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d", 2405 DIV_ENABLE_PCLK_G2D, 6, 0, 0), 2406 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d", 2407 DIV_ENABLE_PCLK_G2D, 5, 0, 0), 2408 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d", 2409 DIV_ENABLE_PCLK_G2D, 4, 0, 0), 2410 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d", 2411 DIV_ENABLE_PCLK_G2D, 3, 0, 0), 2412 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d", 2413 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0), 2414 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d", 2415 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0), 2416 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D, 2417 0, 0, 0), 2418 2419 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */ 2420 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d", 2421 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2422 }; 2423 2424 static const struct samsung_cmu_info g2d_cmu_info __initconst = { 2425 .mux_clks = g2d_mux_clks, 2426 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), 2427 .div_clks = g2d_div_clks, 2428 .nr_div_clks = ARRAY_SIZE(g2d_div_clks), 2429 .gate_clks = g2d_gate_clks, 2430 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), 2431 .nr_clk_ids = G2D_NR_CLK, 2432 .clk_regs = g2d_clk_regs, 2433 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), 2434 .suspend_regs = g2d_suspend_regs, 2435 .nr_suspend_regs = ARRAY_SIZE(g2d_suspend_regs), 2436 .clk_name = "aclk_g2d_400", 2437 }; 2438 2439 /* 2440 * Register offset definitions for CMU_DISP 2441 */ 2442 #define DISP_PLL_LOCK 0x0000 2443 #define DISP_PLL_CON0 0x0100 2444 #define DISP_PLL_CON1 0x0104 2445 #define DISP_PLL_FREQ_DET 0x0108 2446 #define MUX_SEL_DISP0 0x0200 2447 #define MUX_SEL_DISP1 0x0204 2448 #define MUX_SEL_DISP2 0x0208 2449 #define MUX_SEL_DISP3 0x020c 2450 #define MUX_SEL_DISP4 0x0210 2451 #define MUX_ENABLE_DISP0 0x0300 2452 #define MUX_ENABLE_DISP1 0x0304 2453 #define MUX_ENABLE_DISP2 0x0308 2454 #define MUX_ENABLE_DISP3 0x030c 2455 #define MUX_ENABLE_DISP4 0x0310 2456 #define MUX_STAT_DISP0 0x0400 2457 #define MUX_STAT_DISP1 0x0404 2458 #define MUX_STAT_DISP2 0x0408 2459 #define MUX_STAT_DISP3 0x040c 2460 #define MUX_STAT_DISP4 0x0410 2461 #define MUX_IGNORE_DISP2 0x0508 2462 #define DIV_DISP 0x0600 2463 #define DIV_DISP_PLL_FREQ_DET 0x0604 2464 #define DIV_STAT_DISP 0x0700 2465 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704 2466 #define ENABLE_ACLK_DISP0 0x0800 2467 #define ENABLE_ACLK_DISP1 0x0804 2468 #define ENABLE_PCLK_DISP 0x0900 2469 #define ENABLE_SCLK_DISP 0x0a00 2470 #define ENABLE_IP_DISP0 0x0b00 2471 #define ENABLE_IP_DISP1 0x0b04 2472 #define CLKOUT_CMU_DISP 0x0c00 2473 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 2474 2475 static const unsigned long disp_clk_regs[] __initconst = { 2476 DISP_PLL_LOCK, 2477 DISP_PLL_CON0, 2478 DISP_PLL_CON1, 2479 DISP_PLL_FREQ_DET, 2480 MUX_SEL_DISP0, 2481 MUX_SEL_DISP1, 2482 MUX_SEL_DISP2, 2483 MUX_SEL_DISP3, 2484 MUX_SEL_DISP4, 2485 MUX_ENABLE_DISP0, 2486 MUX_ENABLE_DISP1, 2487 MUX_ENABLE_DISP2, 2488 MUX_ENABLE_DISP3, 2489 MUX_ENABLE_DISP4, 2490 MUX_IGNORE_DISP2, 2491 DIV_DISP, 2492 DIV_DISP_PLL_FREQ_DET, 2493 ENABLE_ACLK_DISP0, 2494 ENABLE_ACLK_DISP1, 2495 ENABLE_PCLK_DISP, 2496 ENABLE_SCLK_DISP, 2497 ENABLE_IP_DISP0, 2498 ENABLE_IP_DISP1, 2499 CLKOUT_CMU_DISP, 2500 CLKOUT_CMU_DISP_DIV_STAT, 2501 }; 2502 2503 static const struct samsung_clk_reg_dump disp_suspend_regs[] = { 2504 /* PLL has to be enabled for suspend */ 2505 { DISP_PLL_CON0, 0x85f40502 }, 2506 /* ignore status of external PHY muxes during suspend to avoid hangs */ 2507 { MUX_IGNORE_DISP2, 0x00111111 }, 2508 { MUX_SEL_DISP0, 0 }, 2509 { MUX_SEL_DISP1, 0 }, 2510 { MUX_SEL_DISP2, 0 }, 2511 { MUX_SEL_DISP3, 0 }, 2512 { MUX_SEL_DISP4, 0 }, 2513 }; 2514 2515 /* list of all parent clock list */ 2516 PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", }; 2517 PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", }; 2518 PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", }; 2519 PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", }; 2520 PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk", 2521 "sclk_decon_tv_eclk_disp", }; 2522 PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk", 2523 "sclk_decon_vclk_disp", }; 2524 PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk", 2525 "sclk_decon_eclk_disp", }; 2526 PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk", 2527 "sclk_decon_tv_vclk_disp", }; 2528 PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", }; 2529 2530 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk", 2531 "phyclk_mipidphy1_bitclkdiv8_phy", }; 2532 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk", 2533 "phyclk_mipidphy1_rxclkesc0_phy", }; 2534 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk", 2535 "phyclk_mipidphy0_bitclkdiv8_phy", }; 2536 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk", 2537 "phyclk_mipidphy0_rxclkesc0_phy", }; 2538 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk", 2539 "phyclk_hdmiphy_tmds_clko_phy", }; 2540 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk", 2541 "phyclk_hdmiphy_pixel_clko_phy", }; 2542 2543 PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll", 2544 "mout_sclk_dsim0_user", }; 2545 PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll", 2546 "mout_sclk_decon_tv_eclk_user", }; 2547 PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll", 2548 "mout_sclk_decon_vclk_user", }; 2549 PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll", 2550 "mout_sclk_decon_eclk_user", }; 2551 2552 PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp", 2553 "mout_sclk_dsim1_user", }; 2554 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = { 2555 "mout_phyclk_hdmiphy_pixel_clko_user", 2556 "mout_sclk_decon_tv_vclk_b_disp", }; 2557 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", 2558 "mout_sclk_decon_tv_vclk_user", }; 2559 2560 static const struct samsung_pll_clock disp_pll_clks[] __initconst = { 2561 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", 2562 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates), 2563 }; 2564 2565 static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = { 2566 /* 2567 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. 2568 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} 2569 * and sclk_decon_{vclk|tv_vclk}. 2570 */ 2571 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk", 2572 1, 2, 0), 2573 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk", 2574 1, 2, 0), 2575 }; 2576 2577 static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = { 2578 /* PHY clocks from MIPI_DPHY1 */ 2579 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), 2580 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), 2581 /* PHY clocks from MIPI_DPHY0 */ 2582 FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy", 2583 NULL, 0, 188000000), 2584 FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy", 2585 NULL, 0, 100000000), 2586 /* PHY clocks from HDMI_PHY */ 2587 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", 2588 NULL, 0, 300000000), 2589 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy", 2590 NULL, 0, 166000000), 2591 }; 2592 2593 static const struct samsung_mux_clock disp_mux_clks[] __initconst = { 2594 /* MUX_SEL_DISP0 */ 2595 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, 2596 0, 1), 2597 2598 /* MUX_SEL_DISP1 */ 2599 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user", 2600 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1), 2601 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user", 2602 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1), 2603 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p, 2604 MUX_SEL_DISP1, 20, 1), 2605 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user", 2606 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1), 2607 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user", 2608 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1), 2609 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user", 2610 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1), 2611 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user", 2612 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1), 2613 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", 2614 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1), 2615 2616 /* MUX_SEL_DISP2 */ 2617 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, 2618 "mout_phyclk_mipidphy1_bitclkdiv8_user", 2619 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2, 2620 20, 1), 2621 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, 2622 "mout_phyclk_mipidphy1_rxclkesc0_user", 2623 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2, 2624 16, 1), 2625 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, 2626 "mout_phyclk_mipidphy0_bitclkdiv8_user", 2627 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2, 2628 12, 1), 2629 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, 2630 "mout_phyclk_mipidphy0_rxclkesc0_user", 2631 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2, 2632 8, 1), 2633 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER, 2634 "mout_phyclk_hdmiphy_tmds_clko_user", 2635 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2, 2636 4, 1), 2637 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, 2638 "mout_phyclk_hdmiphy_pixel_clko_user", 2639 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2, 2640 0, 1), 2641 2642 /* MUX_SEL_DISP3 */ 2643 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p, 2644 MUX_SEL_DISP3, 12, 1), 2645 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk", 2646 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1), 2647 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk", 2648 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1), 2649 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk", 2650 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1), 2651 2652 /* MUX_SEL_DISP4 */ 2653 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp", 2654 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1), 2655 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp", 2656 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1), 2657 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP, 2658 "mout_sclk_decon_tv_vclk_c_disp", 2659 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1), 2660 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP, 2661 "mout_sclk_decon_tv_vclk_b_disp", 2662 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1), 2663 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP, 2664 "mout_sclk_decon_tv_vclk_a_disp", 2665 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), 2666 }; 2667 2668 static const struct samsung_div_clock disp_div_clks[] __initconst = { 2669 /* DIV_DISP */ 2670 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", 2671 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), 2672 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp", 2673 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3), 2674 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0", 2675 DIV_DISP, 16, 3), 2676 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp", 2677 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3), 2678 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp", 2679 "mout_sclk_decon_vclk", DIV_DISP, 8, 3), 2680 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp", 2681 "mout_sclk_decon_eclk", DIV_DISP, 4, 3), 2682 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user", 2683 DIV_DISP, 0, 2), 2684 }; 2685 2686 static const struct samsung_gate_clock disp_gate_clks[] __initconst = { 2687 /* ENABLE_ACLK_DISP0 */ 2688 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", 2689 ENABLE_ACLK_DISP0, 2, 0, 0), 2690 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user", 2691 ENABLE_ACLK_DISP0, 0, 0, 0), 2692 2693 /* ENABLE_ACLK_DISP1 */ 2694 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user", 2695 ENABLE_ACLK_DISP1, 25, 0, 0), 2696 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user", 2697 ENABLE_ACLK_DISP1, 24, 0, 0), 2698 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x", 2699 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0), 2700 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x", 2701 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0), 2702 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3", 2703 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0), 2704 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2", 2705 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0), 2706 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1", 2707 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0), 2708 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0", 2709 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0), 2710 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4", 2711 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0), 2712 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3", 2713 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0), 2714 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2", 2715 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0), 2716 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1", 2717 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0), 2718 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0", 2719 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0), 2720 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p", 2721 "div_pclk_disp", ENABLE_ACLK_DISP1, 2722 12, CLK_IGNORE_UNUSED, 0), 2723 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p", 2724 "div_pclk_disp", ENABLE_ACLK_DISP1, 2725 11, CLK_IGNORE_UNUSED, 0), 2726 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p", 2727 "div_pclk_disp", ENABLE_ACLK_DISP1, 2728 10, CLK_IGNORE_UNUSED, 0), 2729 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp", 2730 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0), 2731 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user", 2732 ENABLE_ACLK_DISP1, 7, 0, 0), 2733 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user", 2734 ENABLE_ACLK_DISP1, 6, 0, 0), 2735 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x", 2736 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0), 2737 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x", 2738 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0), 2739 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user", 2740 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0), 2741 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp", 2742 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0), 2743 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333", 2744 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1, 2745 CLK_IGNORE_UNUSED, 0), 2746 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333", 2747 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 2748 0, CLK_IGNORE_UNUSED, 0), 2749 2750 /* ENABLE_PCLK_DISP */ 2751 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp", 2752 ENABLE_PCLK_DISP, 23, 0, 0), 2753 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp", 2754 ENABLE_PCLK_DISP, 22, 0, 0), 2755 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp", 2756 ENABLE_PCLK_DISP, 21, 0, 0), 2757 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp", 2758 ENABLE_PCLK_DISP, 20, 0, 0), 2759 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp", 2760 ENABLE_PCLK_DISP, 19, 0, 0), 2761 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp", 2762 ENABLE_PCLK_DISP, 18, 0, 0), 2763 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp", 2764 ENABLE_PCLK_DISP, 17, 0, 0), 2765 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp", 2766 ENABLE_PCLK_DISP, 16, 0, 0), 2767 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp", 2768 ENABLE_PCLK_DISP, 15, 0, 0), 2769 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp", 2770 ENABLE_PCLK_DISP, 14, 0, 0), 2771 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp", 2772 ENABLE_PCLK_DISP, 13, 0, 0), 2773 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp", 2774 ENABLE_PCLK_DISP, 12, 0, 0), 2775 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp", 2776 ENABLE_PCLK_DISP, 11, 0, 0), 2777 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp", 2778 ENABLE_PCLK_DISP, 10, 0, 0), 2779 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp", 2780 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0), 2781 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp", 2782 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0), 2783 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp", 2784 ENABLE_PCLK_DISP, 7, 0, 0), 2785 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp", 2786 ENABLE_PCLK_DISP, 6, 0, 0), 2787 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp", 2788 ENABLE_PCLK_DISP, 5, 0, 0), 2789 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp", 2790 ENABLE_PCLK_DISP, 3, 0, 0), 2791 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp", 2792 ENABLE_PCLK_DISP, 2, 0, 0), 2793 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp", 2794 ENABLE_PCLK_DISP, 1, 0, 0), 2795 GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp", 2796 ENABLE_PCLK_DISP, 0, 0, 0), 2797 2798 /* ENABLE_SCLK_DISP */ 2799 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8", 2800 "mout_phyclk_mipidphy1_bitclkdiv8_user", 2801 ENABLE_SCLK_DISP, 26, 0, 0), 2802 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0", 2803 "mout_phyclk_mipidphy1_rxclkesc0_user", 2804 ENABLE_SCLK_DISP, 25, 0, 0), 2805 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1", 2806 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0), 2807 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1", 2808 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0), 2809 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp", 2810 ENABLE_SCLK_DISP, 22, 0, 0), 2811 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk", 2812 "div_sclk_decon_tv_vclk_disp", 2813 ENABLE_SCLK_DISP, 21, 0, 0), 2814 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8", 2815 "mout_phyclk_mipidphy0_bitclkdiv8_user", 2816 ENABLE_SCLK_DISP, 15, 0, 0), 2817 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0", 2818 "mout_phyclk_mipidphy0_rxclkesc0_user", 2819 ENABLE_SCLK_DISP, 14, 0, 0), 2820 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko", 2821 "mout_phyclk_hdmiphy_tmds_clko_user", 2822 ENABLE_SCLK_DISP, 13, 0, 0), 2823 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel", 2824 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0), 2825 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies", 2826 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0), 2827 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0", 2828 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0), 2829 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0", 2830 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0), 2831 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user", 2832 ENABLE_SCLK_DISP, 7, 0, 0), 2833 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp", 2834 ENABLE_SCLK_DISP, 6, 0, 0), 2835 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp", 2836 ENABLE_SCLK_DISP, 5, 0, 0), 2837 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk", 2838 "div_sclk_decon_tv_eclk_disp", 2839 ENABLE_SCLK_DISP, 4, 0, 0), 2840 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk", 2841 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0), 2842 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk", 2843 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), 2844 }; 2845 2846 static const struct samsung_cmu_info disp_cmu_info __initconst = { 2847 .pll_clks = disp_pll_clks, 2848 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), 2849 .mux_clks = disp_mux_clks, 2850 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks), 2851 .div_clks = disp_div_clks, 2852 .nr_div_clks = ARRAY_SIZE(disp_div_clks), 2853 .gate_clks = disp_gate_clks, 2854 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks), 2855 .fixed_clks = disp_fixed_clks, 2856 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks), 2857 .fixed_factor_clks = disp_fixed_factor_clks, 2858 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks), 2859 .nr_clk_ids = DISP_NR_CLK, 2860 .clk_regs = disp_clk_regs, 2861 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), 2862 .suspend_regs = disp_suspend_regs, 2863 .nr_suspend_regs = ARRAY_SIZE(disp_suspend_regs), 2864 .clk_name = "aclk_disp_333", 2865 }; 2866 2867 /* 2868 * Register offset definitions for CMU_AUD 2869 */ 2870 #define MUX_SEL_AUD0 0x0200 2871 #define MUX_SEL_AUD1 0x0204 2872 #define MUX_ENABLE_AUD0 0x0300 2873 #define MUX_ENABLE_AUD1 0x0304 2874 #define MUX_STAT_AUD0 0x0400 2875 #define DIV_AUD0 0x0600 2876 #define DIV_AUD1 0x0604 2877 #define DIV_STAT_AUD0 0x0700 2878 #define DIV_STAT_AUD1 0x0704 2879 #define ENABLE_ACLK_AUD 0x0800 2880 #define ENABLE_PCLK_AUD 0x0900 2881 #define ENABLE_SCLK_AUD0 0x0a00 2882 #define ENABLE_SCLK_AUD1 0x0a04 2883 #define ENABLE_IP_AUD0 0x0b00 2884 #define ENABLE_IP_AUD1 0x0b04 2885 2886 static const unsigned long aud_clk_regs[] __initconst = { 2887 MUX_SEL_AUD0, 2888 MUX_SEL_AUD1, 2889 MUX_ENABLE_AUD0, 2890 MUX_ENABLE_AUD1, 2891 DIV_AUD0, 2892 DIV_AUD1, 2893 ENABLE_ACLK_AUD, 2894 ENABLE_PCLK_AUD, 2895 ENABLE_SCLK_AUD0, 2896 ENABLE_SCLK_AUD1, 2897 ENABLE_IP_AUD0, 2898 ENABLE_IP_AUD1, 2899 }; 2900 2901 static const struct samsung_clk_reg_dump aud_suspend_regs[] = { 2902 { MUX_SEL_AUD0, 0 }, 2903 { MUX_SEL_AUD1, 0 }, 2904 }; 2905 2906 /* list of all parent clock list */ 2907 PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; 2908 PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; 2909 2910 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { 2911 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000), 2912 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000), 2913 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000), 2914 }; 2915 2916 static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 2917 /* MUX_SEL_AUD0 */ 2918 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", 2919 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), 2920 2921 /* MUX_SEL_AUD1 */ 2922 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, 2923 MUX_SEL_AUD1, 8, 1), 2924 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p, 2925 MUX_SEL_AUD1, 0, 1), 2926 }; 2927 2928 static const struct samsung_div_clock aud_div_clks[] __initconst = { 2929 /* DIV_AUD0 */ 2930 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0, 2931 12, 4), 2932 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0, 2933 8, 4), 2934 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0, 2935 4, 4), 2936 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 2937 0, 4), 2938 2939 /* DIV_AUD1 */ 2940 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus", 2941 "mout_aud_pll_user", DIV_AUD1, 16, 5), 2942 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user", 2943 DIV_AUD1, 12, 4), 2944 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm", 2945 DIV_AUD1, 4, 8), 2946 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s", 2947 DIV_AUD1, 0, 4), 2948 }; 2949 2950 static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 2951 /* ENABLE_ACLK_AUD */ 2952 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud", 2953 ENABLE_ACLK_AUD, 12, 0, 0), 2954 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud", 2955 ENABLE_ACLK_AUD, 7, 0, 0), 2956 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud", 2957 ENABLE_ACLK_AUD, 0, 4, 0), 2958 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud", 2959 ENABLE_ACLK_AUD, 0, 3, 0), 2960 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud", 2961 ENABLE_ACLK_AUD, 0, 2, 0), 2962 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD, 2963 0, 1, 0), 2964 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD, 2965 0, CLK_IGNORE_UNUSED, 0), 2966 2967 /* ENABLE_PCLK_AUD */ 2968 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD, 2969 13, 0, 0), 2970 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD, 2971 12, 0, 0), 2972 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD, 2973 11, 0, 0), 2974 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud", 2975 ENABLE_PCLK_AUD, 10, 0, 0), 2976 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud", 2977 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0), 2978 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud", 2979 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0), 2980 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud", 2981 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0), 2982 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud", 2983 ENABLE_PCLK_AUD, 6, 0, 0), 2984 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud", 2985 ENABLE_PCLK_AUD, 5, 0, 0), 2986 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud", 2987 ENABLE_PCLK_AUD, 4, 0, 0), 2988 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud", 2989 ENABLE_PCLK_AUD, 3, 0, 0), 2990 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD, 2991 2, 0, 0), 2992 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud", 2993 ENABLE_PCLK_AUD, 0, 0, 0), 2994 2995 /* ENABLE_SCLK_AUD0 */ 2996 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0, 2997 2, CLK_IGNORE_UNUSED, 0), 2998 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud", 2999 ENABLE_SCLK_AUD0, 1, 0, 0), 3000 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0, 3001 0, 0, 0), 3002 3003 /* ENABLE_SCLK_AUD1 */ 3004 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk", 3005 ENABLE_SCLK_AUD1, 6, 0, 0), 3006 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk", 3007 ENABLE_SCLK_AUD1, 5, 0, 0), 3008 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus", 3009 ENABLE_SCLK_AUD1, 4, 0, 0), 3010 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart", 3011 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0), 3012 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm", 3013 ENABLE_SCLK_AUD1, 2, 0, 0), 3014 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk", 3015 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0), 3016 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s", 3017 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0), 3018 }; 3019 3020 static const struct samsung_cmu_info aud_cmu_info __initconst = { 3021 .mux_clks = aud_mux_clks, 3022 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 3023 .div_clks = aud_div_clks, 3024 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 3025 .gate_clks = aud_gate_clks, 3026 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 3027 .fixed_clks = aud_fixed_clks, 3028 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), 3029 .nr_clk_ids = AUD_NR_CLK, 3030 .clk_regs = aud_clk_regs, 3031 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 3032 .suspend_regs = aud_suspend_regs, 3033 .nr_suspend_regs = ARRAY_SIZE(aud_suspend_regs), 3034 .clk_name = "fout_aud_pll", 3035 }; 3036 3037 /* 3038 * Register offset definitions for CMU_BUS{0|1|2} 3039 */ 3040 #define DIV_BUS 0x0600 3041 #define DIV_STAT_BUS 0x0700 3042 #define ENABLE_ACLK_BUS 0x0800 3043 #define ENABLE_PCLK_BUS 0x0900 3044 #define ENABLE_IP_BUS0 0x0b00 3045 #define ENABLE_IP_BUS1 0x0b04 3046 3047 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */ 3048 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */ 3049 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */ 3050 3051 /* list of all parent clock list */ 3052 PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", }; 3053 3054 #define CMU_BUS_COMMON_CLK_REGS \ 3055 DIV_BUS, \ 3056 ENABLE_ACLK_BUS, \ 3057 ENABLE_PCLK_BUS, \ 3058 ENABLE_IP_BUS0, \ 3059 ENABLE_IP_BUS1 3060 3061 static const unsigned long bus01_clk_regs[] __initconst = { 3062 CMU_BUS_COMMON_CLK_REGS, 3063 }; 3064 3065 static const unsigned long bus2_clk_regs[] __initconst = { 3066 MUX_SEL_BUS2, 3067 MUX_ENABLE_BUS2, 3068 CMU_BUS_COMMON_CLK_REGS, 3069 }; 3070 3071 static const struct samsung_div_clock bus0_div_clks[] __initconst = { 3072 /* DIV_BUS0 */ 3073 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400", 3074 DIV_BUS, 0, 3), 3075 }; 3076 3077 /* CMU_BUS0 clocks */ 3078 static const struct samsung_gate_clock bus0_gate_clks[] __initconst = { 3079 /* ENABLE_ACLK_BUS0 */ 3080 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133", 3081 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3082 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133", 3083 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3084 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400", 3085 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3086 3087 /* ENABLE_PCLK_BUS0 */ 3088 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133", 3089 ENABLE_PCLK_BUS, 2, 0, 0), 3090 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133", 3091 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3092 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133", 3093 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3094 }; 3095 3096 /* CMU_BUS1 clocks */ 3097 static const struct samsung_div_clock bus1_div_clks[] __initconst = { 3098 /* DIV_BUS1 */ 3099 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400", 3100 DIV_BUS, 0, 3), 3101 }; 3102 3103 static const struct samsung_gate_clock bus1_gate_clks[] __initconst = { 3104 /* ENABLE_ACLK_BUS1 */ 3105 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133", 3106 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3107 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133", 3108 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3109 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400", 3110 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3111 3112 /* ENABLE_PCLK_BUS1 */ 3113 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133", 3114 ENABLE_PCLK_BUS, 2, 0, 0), 3115 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133", 3116 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3117 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133", 3118 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3119 }; 3120 3121 /* CMU_BUS2 clocks */ 3122 static const struct samsung_mux_clock bus2_mux_clks[] __initconst = { 3123 /* MUX_SEL_BUS2 */ 3124 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user", 3125 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1), 3126 }; 3127 3128 static const struct samsung_div_clock bus2_div_clks[] __initconst = { 3129 /* DIV_BUS2 */ 3130 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133", 3131 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3), 3132 }; 3133 3134 static const struct samsung_gate_clock bus2_gate_clks[] __initconst = { 3135 /* ENABLE_ACLK_BUS2 */ 3136 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133", 3137 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0), 3138 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133", 3139 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3140 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400", 3141 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, 3142 1, CLK_IGNORE_UNUSED, 0), 3143 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400", 3144 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, 3145 0, CLK_IGNORE_UNUSED, 0), 3146 3147 /* ENABLE_PCLK_BUS2 */ 3148 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133", 3149 ENABLE_PCLK_BUS, 2, 0, 0), 3150 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133", 3151 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3152 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133", 3153 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3154 }; 3155 3156 #define CMU_BUS_INFO_CLKS(id) \ 3157 .div_clks = bus##id##_div_clks, \ 3158 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \ 3159 .gate_clks = bus##id##_gate_clks, \ 3160 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ 3161 .nr_clk_ids = BUSx_NR_CLK 3162 3163 static const struct samsung_cmu_info bus0_cmu_info __initconst = { 3164 CMU_BUS_INFO_CLKS(0), 3165 .clk_regs = bus01_clk_regs, 3166 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3167 }; 3168 3169 static const struct samsung_cmu_info bus1_cmu_info __initconst = { 3170 CMU_BUS_INFO_CLKS(1), 3171 .clk_regs = bus01_clk_regs, 3172 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3173 }; 3174 3175 static const struct samsung_cmu_info bus2_cmu_info __initconst = { 3176 CMU_BUS_INFO_CLKS(2), 3177 .mux_clks = bus2_mux_clks, 3178 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks), 3179 .clk_regs = bus2_clk_regs, 3180 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs), 3181 }; 3182 3183 #define exynos5433_cmu_bus_init(id) \ 3184 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\ 3185 { \ 3186 samsung_cmu_register_one(np, &bus##id##_cmu_info); \ 3187 } \ 3188 CLK_OF_DECLARE(exynos5433_cmu_bus##id, \ 3189 "samsung,exynos5433-cmu-bus"#id, \ 3190 exynos5433_cmu_bus##id##_init) 3191 3192 exynos5433_cmu_bus_init(0); 3193 exynos5433_cmu_bus_init(1); 3194 exynos5433_cmu_bus_init(2); 3195 3196 /* 3197 * Register offset definitions for CMU_G3D 3198 */ 3199 #define G3D_PLL_LOCK 0x0000 3200 #define G3D_PLL_CON0 0x0100 3201 #define G3D_PLL_CON1 0x0104 3202 #define G3D_PLL_FREQ_DET 0x010c 3203 #define MUX_SEL_G3D 0x0200 3204 #define MUX_ENABLE_G3D 0x0300 3205 #define MUX_STAT_G3D 0x0400 3206 #define DIV_G3D 0x0600 3207 #define DIV_G3D_PLL_FREQ_DET 0x0604 3208 #define DIV_STAT_G3D 0x0700 3209 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704 3210 #define ENABLE_ACLK_G3D 0x0800 3211 #define ENABLE_PCLK_G3D 0x0900 3212 #define ENABLE_SCLK_G3D 0x0a00 3213 #define ENABLE_IP_G3D0 0x0b00 3214 #define ENABLE_IP_G3D1 0x0b04 3215 #define CLKOUT_CMU_G3D 0x0c00 3216 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 3217 #define CLK_STOPCTRL 0x1000 3218 3219 static const unsigned long g3d_clk_regs[] __initconst = { 3220 G3D_PLL_LOCK, 3221 G3D_PLL_CON0, 3222 G3D_PLL_CON1, 3223 G3D_PLL_FREQ_DET, 3224 MUX_SEL_G3D, 3225 MUX_ENABLE_G3D, 3226 DIV_G3D, 3227 DIV_G3D_PLL_FREQ_DET, 3228 ENABLE_ACLK_G3D, 3229 ENABLE_PCLK_G3D, 3230 ENABLE_SCLK_G3D, 3231 ENABLE_IP_G3D0, 3232 ENABLE_IP_G3D1, 3233 CLKOUT_CMU_G3D, 3234 CLKOUT_CMU_G3D_DIV_STAT, 3235 CLK_STOPCTRL, 3236 }; 3237 3238 static const struct samsung_clk_reg_dump g3d_suspend_regs[] = { 3239 { MUX_SEL_G3D, 0 }, 3240 }; 3241 3242 /* list of all parent clock list */ 3243 PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", }; 3244 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; 3245 3246 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { 3247 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", 3248 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates), 3249 }; 3250 3251 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { 3252 /* MUX_SEL_G3D */ 3253 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, 3254 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0), 3255 MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, 3256 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0), 3257 }; 3258 3259 static const struct samsung_div_clock g3d_div_clks[] __initconst = { 3260 /* DIV_G3D */ 3261 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D, 3262 8, 2), 3263 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D, 3264 4, 3), 3265 DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D, 3266 0, 3, CLK_SET_RATE_PARENT, 0), 3267 }; 3268 3269 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { 3270 /* ENABLE_ACLK_G3D */ 3271 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d", 3272 ENABLE_ACLK_G3D, 7, 0, 0), 3273 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d", 3274 ENABLE_ACLK_G3D, 6, 0, 0), 3275 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d", 3276 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0), 3277 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d", 3278 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0), 3279 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d", 3280 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0), 3281 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d", 3282 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0), 3283 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d", 3284 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0), 3285 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d", 3286 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0), 3287 3288 /* ENABLE_PCLK_G3D */ 3289 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d", 3290 ENABLE_PCLK_G3D, 3, 0, 0), 3291 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d", 3292 ENABLE_PCLK_G3D, 2, 0, 0), 3293 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d", 3294 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0), 3295 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d", 3296 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0), 3297 3298 /* ENABLE_SCLK_G3D */ 3299 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d", 3300 ENABLE_SCLK_G3D, 0, 0, 0), 3301 }; 3302 3303 static const struct samsung_cmu_info g3d_cmu_info __initconst = { 3304 .pll_clks = g3d_pll_clks, 3305 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), 3306 .mux_clks = g3d_mux_clks, 3307 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), 3308 .div_clks = g3d_div_clks, 3309 .nr_div_clks = ARRAY_SIZE(g3d_div_clks), 3310 .gate_clks = g3d_gate_clks, 3311 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), 3312 .nr_clk_ids = G3D_NR_CLK, 3313 .clk_regs = g3d_clk_regs, 3314 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), 3315 .suspend_regs = g3d_suspend_regs, 3316 .nr_suspend_regs = ARRAY_SIZE(g3d_suspend_regs), 3317 .clk_name = "aclk_g3d_400", 3318 }; 3319 3320 /* 3321 * Register offset definitions for CMU_GSCL 3322 */ 3323 #define MUX_SEL_GSCL 0x0200 3324 #define MUX_ENABLE_GSCL 0x0300 3325 #define MUX_STAT_GSCL 0x0400 3326 #define ENABLE_ACLK_GSCL 0x0800 3327 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804 3328 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808 3329 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c 3330 #define ENABLE_PCLK_GSCL 0x0900 3331 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904 3332 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908 3333 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c 3334 #define ENABLE_IP_GSCL0 0x0b00 3335 #define ENABLE_IP_GSCL1 0x0b04 3336 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08 3337 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c 3338 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10 3339 3340 static const unsigned long gscl_clk_regs[] __initconst = { 3341 MUX_SEL_GSCL, 3342 MUX_ENABLE_GSCL, 3343 ENABLE_ACLK_GSCL, 3344 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 3345 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 3346 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 3347 ENABLE_PCLK_GSCL, 3348 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 3349 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 3350 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 3351 ENABLE_IP_GSCL0, 3352 ENABLE_IP_GSCL1, 3353 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0, 3354 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1, 3355 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2, 3356 }; 3357 3358 static const struct samsung_clk_reg_dump gscl_suspend_regs[] = { 3359 { MUX_SEL_GSCL, 0 }, 3360 { ENABLE_ACLK_GSCL, 0xfff }, 3361 { ENABLE_PCLK_GSCL, 0xff }, 3362 }; 3363 3364 /* list of all parent clock list */ 3365 PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", }; 3366 PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", }; 3367 3368 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = { 3369 /* MUX_SEL_GSCL */ 3370 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user", 3371 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1), 3372 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", 3373 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), 3374 }; 3375 3376 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = { 3377 /* ENABLE_ACLK_GSCL */ 3378 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user", 3379 ENABLE_ACLK_GSCL, 11, 0, 0), 3380 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user", 3381 ENABLE_ACLK_GSCL, 10, 0, 0), 3382 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user", 3383 ENABLE_ACLK_GSCL, 9, 0, 0), 3384 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp", 3385 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL, 3386 8, CLK_IGNORE_UNUSED, 0), 3387 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user", 3388 ENABLE_ACLK_GSCL, 7, 0, 0), 3389 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user", 3390 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0), 3391 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333", 3392 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 3393 CLK_IGNORE_UNUSED, 0), 3394 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333", 3395 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 3396 CLK_IGNORE_UNUSED, 0), 3397 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user", 3398 ENABLE_ACLK_GSCL, 3, 0, 0), 3399 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user", 3400 ENABLE_ACLK_GSCL, 2, 0, 0), 3401 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user", 3402 ENABLE_ACLK_GSCL, 1, 0, 0), 3403 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user", 3404 ENABLE_ACLK_GSCL, 0, 0, 0), 3405 3406 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */ 3407 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user", 3408 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), 3409 3410 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */ 3411 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user", 3412 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), 3413 3414 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */ 3415 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user", 3416 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3417 3418 /* ENABLE_PCLK_GSCL */ 3419 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user", 3420 ENABLE_PCLK_GSCL, 7, 0, 0), 3421 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user", 3422 ENABLE_PCLK_GSCL, 6, 0, 0), 3423 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user", 3424 ENABLE_PCLK_GSCL, 5, 0, 0), 3425 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user", 3426 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0), 3427 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl", 3428 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL, 3429 3, CLK_IGNORE_UNUSED, 0), 3430 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user", 3431 ENABLE_PCLK_GSCL, 2, 0, 0), 3432 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user", 3433 ENABLE_PCLK_GSCL, 1, 0, 0), 3434 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user", 3435 ENABLE_PCLK_GSCL, 0, 0, 0), 3436 3437 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */ 3438 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user", 3439 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), 3440 3441 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */ 3442 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user", 3443 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), 3444 3445 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */ 3446 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user", 3447 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3448 }; 3449 3450 static const struct samsung_cmu_info gscl_cmu_info __initconst = { 3451 .mux_clks = gscl_mux_clks, 3452 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), 3453 .gate_clks = gscl_gate_clks, 3454 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks), 3455 .nr_clk_ids = GSCL_NR_CLK, 3456 .clk_regs = gscl_clk_regs, 3457 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), 3458 .suspend_regs = gscl_suspend_regs, 3459 .nr_suspend_regs = ARRAY_SIZE(gscl_suspend_regs), 3460 .clk_name = "aclk_gscl_111", 3461 }; 3462 3463 /* 3464 * Register offset definitions for CMU_APOLLO 3465 */ 3466 #define APOLLO_PLL_LOCK 0x0000 3467 #define APOLLO_PLL_CON0 0x0100 3468 #define APOLLO_PLL_CON1 0x0104 3469 #define APOLLO_PLL_FREQ_DET 0x010c 3470 #define MUX_SEL_APOLLO0 0x0200 3471 #define MUX_SEL_APOLLO1 0x0204 3472 #define MUX_SEL_APOLLO2 0x0208 3473 #define MUX_ENABLE_APOLLO0 0x0300 3474 #define MUX_ENABLE_APOLLO1 0x0304 3475 #define MUX_ENABLE_APOLLO2 0x0308 3476 #define MUX_STAT_APOLLO0 0x0400 3477 #define MUX_STAT_APOLLO1 0x0404 3478 #define MUX_STAT_APOLLO2 0x0408 3479 #define DIV_APOLLO0 0x0600 3480 #define DIV_APOLLO1 0x0604 3481 #define DIV_APOLLO_PLL_FREQ_DET 0x0608 3482 #define DIV_STAT_APOLLO0 0x0700 3483 #define DIV_STAT_APOLLO1 0x0704 3484 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708 3485 #define ENABLE_ACLK_APOLLO 0x0800 3486 #define ENABLE_PCLK_APOLLO 0x0900 3487 #define ENABLE_SCLK_APOLLO 0x0a00 3488 #define ENABLE_IP_APOLLO0 0x0b00 3489 #define ENABLE_IP_APOLLO1 0x0b04 3490 #define CLKOUT_CMU_APOLLO 0x0c00 3491 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04 3492 #define ARMCLK_STOPCTRL 0x1000 3493 #define APOLLO_PWR_CTRL 0x1020 3494 #define APOLLO_PWR_CTRL2 0x1024 3495 #define APOLLO_INTR_SPREAD_ENABLE 0x1080 3496 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084 3497 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088 3498 3499 static const unsigned long apollo_clk_regs[] __initconst = { 3500 APOLLO_PLL_LOCK, 3501 APOLLO_PLL_CON0, 3502 APOLLO_PLL_CON1, 3503 APOLLO_PLL_FREQ_DET, 3504 MUX_SEL_APOLLO0, 3505 MUX_SEL_APOLLO1, 3506 MUX_SEL_APOLLO2, 3507 MUX_ENABLE_APOLLO0, 3508 MUX_ENABLE_APOLLO1, 3509 MUX_ENABLE_APOLLO2, 3510 DIV_APOLLO0, 3511 DIV_APOLLO1, 3512 DIV_APOLLO_PLL_FREQ_DET, 3513 ENABLE_ACLK_APOLLO, 3514 ENABLE_PCLK_APOLLO, 3515 ENABLE_SCLK_APOLLO, 3516 ENABLE_IP_APOLLO0, 3517 ENABLE_IP_APOLLO1, 3518 CLKOUT_CMU_APOLLO, 3519 CLKOUT_CMU_APOLLO_DIV_STAT, 3520 ARMCLK_STOPCTRL, 3521 APOLLO_PWR_CTRL, 3522 APOLLO_PWR_CTRL2, 3523 APOLLO_INTR_SPREAD_ENABLE, 3524 APOLLO_INTR_SPREAD_USE_STANDBYWFI, 3525 APOLLO_INTR_SPREAD_BLOCKING_DURATION, 3526 }; 3527 3528 /* list of all parent clock list */ 3529 PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", }; 3530 PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", }; 3531 PNAME(mout_apollo_p) = { "mout_apollo_pll", 3532 "mout_bus_pll_apollo_user", }; 3533 3534 static const struct samsung_pll_clock apollo_pll_clks[] __initconst = { 3535 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", 3536 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates), 3537 }; 3538 3539 static const struct samsung_mux_clock apollo_mux_clks[] __initconst = { 3540 /* MUX_SEL_APOLLO0 */ 3541 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, 3542 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT | 3543 CLK_RECALC_NEW_RATES, 0), 3544 3545 /* MUX_SEL_APOLLO1 */ 3546 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", 3547 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1), 3548 3549 /* MUX_SEL_APOLLO2 */ 3550 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2, 3551 0, 1, CLK_SET_RATE_PARENT, 0), 3552 }; 3553 3554 static const struct samsung_div_clock apollo_div_clks[] __initconst = { 3555 /* DIV_APOLLO0 */ 3556 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2", 3557 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE, 3558 CLK_DIVIDER_READ_ONLY), 3559 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2", 3560 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE, 3561 CLK_DIVIDER_READ_ONLY), 3562 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2", 3563 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE, 3564 CLK_DIVIDER_READ_ONLY), 3565 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2", 3566 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE, 3567 CLK_DIVIDER_READ_ONLY), 3568 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2", 3569 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE, 3570 CLK_DIVIDER_READ_ONLY), 3571 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1", 3572 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0), 3573 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo", 3574 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0), 3575 3576 /* DIV_APOLLO1 */ 3577 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo", 3578 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE, 3579 CLK_DIVIDER_READ_ONLY), 3580 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo", 3581 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE, 3582 CLK_DIVIDER_READ_ONLY), 3583 }; 3584 3585 static const struct samsung_gate_clock apollo_gate_clks[] __initconst = { 3586 /* ENABLE_ACLK_APOLLO */ 3587 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys", 3588 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3589 6, CLK_IGNORE_UNUSED, 0), 3590 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys", 3591 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3592 5, CLK_IGNORE_UNUSED, 0), 3593 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys", 3594 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3595 4, CLK_IGNORE_UNUSED, 0), 3596 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys", 3597 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3598 3, CLK_IGNORE_UNUSED, 0), 3599 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci", 3600 "div_aclk_apollo", ENABLE_ACLK_APOLLO, 3601 2, CLK_IGNORE_UNUSED, 0), 3602 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop", 3603 "div_pclk_apollo", ENABLE_ACLK_APOLLO, 3604 1, CLK_IGNORE_UNUSED, 0), 3605 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200", 3606 "div_pclk_apollo", ENABLE_ACLK_APOLLO, 3607 0, CLK_IGNORE_UNUSED, 0), 3608 3609 /* ENABLE_PCLK_APOLLO */ 3610 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo", 3611 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO, 3612 2, CLK_IGNORE_UNUSED, 0), 3613 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo", 3614 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), 3615 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo", 3616 "div_pclk_apollo", ENABLE_PCLK_APOLLO, 3617 0, CLK_IGNORE_UNUSED, 0), 3618 3619 /* ENABLE_SCLK_APOLLO */ 3620 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo", 3621 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), 3622 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", 3623 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), 3624 }; 3625 3626 #define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \ 3627 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \ 3628 ((pclk) << 12) | ((aclk) << 8)) 3629 3630 #define E5433_APOLLO_DIV1(hpm, copy) \ 3631 (((hpm) << 4) | ((copy) << 0)) 3632 3633 static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = { 3634 { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3635 { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3636 { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3637 { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3638 { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3639 { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3640 { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3641 { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3642 { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3643 { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3644 { 0 }, 3645 }; 3646 3647 static void __init exynos5433_cmu_apollo_init(struct device_node *np) 3648 { 3649 void __iomem *reg_base; 3650 struct samsung_clk_provider *ctx; 3651 3652 reg_base = of_iomap(np, 0); 3653 if (!reg_base) { 3654 panic("%s: failed to map registers\n", __func__); 3655 return; 3656 } 3657 3658 ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK); 3659 if (!ctx) { 3660 panic("%s: unable to allocate ctx\n", __func__); 3661 return; 3662 } 3663 3664 samsung_clk_register_pll(ctx, apollo_pll_clks, 3665 ARRAY_SIZE(apollo_pll_clks), reg_base); 3666 samsung_clk_register_mux(ctx, apollo_mux_clks, 3667 ARRAY_SIZE(apollo_mux_clks)); 3668 samsung_clk_register_div(ctx, apollo_div_clks, 3669 ARRAY_SIZE(apollo_div_clks)); 3670 samsung_clk_register_gate(ctx, apollo_gate_clks, 3671 ARRAY_SIZE(apollo_gate_clks)); 3672 3673 exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk", 3674 mout_apollo_p[0], mout_apollo_p[1], 0x200, 3675 exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d), 3676 CLK_CPU_HAS_E5433_REGS_LAYOUT); 3677 3678 samsung_clk_sleep_init(reg_base, apollo_clk_regs, 3679 ARRAY_SIZE(apollo_clk_regs)); 3680 3681 samsung_clk_of_add_provider(np, ctx); 3682 } 3683 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", 3684 exynos5433_cmu_apollo_init); 3685 3686 /* 3687 * Register offset definitions for CMU_ATLAS 3688 */ 3689 #define ATLAS_PLL_LOCK 0x0000 3690 #define ATLAS_PLL_CON0 0x0100 3691 #define ATLAS_PLL_CON1 0x0104 3692 #define ATLAS_PLL_FREQ_DET 0x010c 3693 #define MUX_SEL_ATLAS0 0x0200 3694 #define MUX_SEL_ATLAS1 0x0204 3695 #define MUX_SEL_ATLAS2 0x0208 3696 #define MUX_ENABLE_ATLAS0 0x0300 3697 #define MUX_ENABLE_ATLAS1 0x0304 3698 #define MUX_ENABLE_ATLAS2 0x0308 3699 #define MUX_STAT_ATLAS0 0x0400 3700 #define MUX_STAT_ATLAS1 0x0404 3701 #define MUX_STAT_ATLAS2 0x0408 3702 #define DIV_ATLAS0 0x0600 3703 #define DIV_ATLAS1 0x0604 3704 #define DIV_ATLAS_PLL_FREQ_DET 0x0608 3705 #define DIV_STAT_ATLAS0 0x0700 3706 #define DIV_STAT_ATLAS1 0x0704 3707 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708 3708 #define ENABLE_ACLK_ATLAS 0x0800 3709 #define ENABLE_PCLK_ATLAS 0x0900 3710 #define ENABLE_SCLK_ATLAS 0x0a00 3711 #define ENABLE_IP_ATLAS0 0x0b00 3712 #define ENABLE_IP_ATLAS1 0x0b04 3713 #define CLKOUT_CMU_ATLAS 0x0c00 3714 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04 3715 #define ARMCLK_STOPCTRL 0x1000 3716 #define ATLAS_PWR_CTRL 0x1020 3717 #define ATLAS_PWR_CTRL2 0x1024 3718 #define ATLAS_INTR_SPREAD_ENABLE 0x1080 3719 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084 3720 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088 3721 3722 static const unsigned long atlas_clk_regs[] __initconst = { 3723 ATLAS_PLL_LOCK, 3724 ATLAS_PLL_CON0, 3725 ATLAS_PLL_CON1, 3726 ATLAS_PLL_FREQ_DET, 3727 MUX_SEL_ATLAS0, 3728 MUX_SEL_ATLAS1, 3729 MUX_SEL_ATLAS2, 3730 MUX_ENABLE_ATLAS0, 3731 MUX_ENABLE_ATLAS1, 3732 MUX_ENABLE_ATLAS2, 3733 DIV_ATLAS0, 3734 DIV_ATLAS1, 3735 DIV_ATLAS_PLL_FREQ_DET, 3736 ENABLE_ACLK_ATLAS, 3737 ENABLE_PCLK_ATLAS, 3738 ENABLE_SCLK_ATLAS, 3739 ENABLE_IP_ATLAS0, 3740 ENABLE_IP_ATLAS1, 3741 CLKOUT_CMU_ATLAS, 3742 CLKOUT_CMU_ATLAS_DIV_STAT, 3743 ARMCLK_STOPCTRL, 3744 ATLAS_PWR_CTRL, 3745 ATLAS_PWR_CTRL2, 3746 ATLAS_INTR_SPREAD_ENABLE, 3747 ATLAS_INTR_SPREAD_USE_STANDBYWFI, 3748 ATLAS_INTR_SPREAD_BLOCKING_DURATION, 3749 }; 3750 3751 /* list of all parent clock list */ 3752 PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", }; 3753 PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", }; 3754 PNAME(mout_atlas_p) = { "mout_atlas_pll", 3755 "mout_bus_pll_atlas_user", }; 3756 3757 static const struct samsung_pll_clock atlas_pll_clks[] __initconst = { 3758 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk", 3759 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates), 3760 }; 3761 3762 static const struct samsung_mux_clock atlas_mux_clks[] __initconst = { 3763 /* MUX_SEL_ATLAS0 */ 3764 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, 3765 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT | 3766 CLK_RECALC_NEW_RATES, 0), 3767 3768 /* MUX_SEL_ATLAS1 */ 3769 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user", 3770 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1), 3771 3772 /* MUX_SEL_ATLAS2 */ 3773 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2, 3774 0, 1, CLK_SET_RATE_PARENT, 0), 3775 }; 3776 3777 static const struct samsung_div_clock atlas_div_clks[] __initconst = { 3778 /* DIV_ATLAS0 */ 3779 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2", 3780 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE, 3781 CLK_DIVIDER_READ_ONLY), 3782 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas", 3783 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE, 3784 CLK_DIVIDER_READ_ONLY), 3785 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2", 3786 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE, 3787 CLK_DIVIDER_READ_ONLY), 3788 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2", 3789 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE, 3790 CLK_DIVIDER_READ_ONLY), 3791 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2", 3792 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE, 3793 CLK_DIVIDER_READ_ONLY), 3794 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1", 3795 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0), 3796 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas", 3797 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0), 3798 3799 /* DIV_ATLAS1 */ 3800 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas", 3801 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE, 3802 CLK_DIVIDER_READ_ONLY), 3803 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas", 3804 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE, 3805 CLK_DIVIDER_READ_ONLY), 3806 }; 3807 3808 static const struct samsung_gate_clock atlas_gate_clks[] __initconst = { 3809 /* ENABLE_ACLK_ATLAS */ 3810 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys", 3811 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3812 9, CLK_IGNORE_UNUSED, 0), 3813 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys", 3814 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3815 8, CLK_IGNORE_UNUSED, 0), 3816 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys", 3817 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3818 7, CLK_IGNORE_UNUSED, 0), 3819 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys", 3820 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3821 6, CLK_IGNORE_UNUSED, 0), 3822 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys", 3823 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3824 5, CLK_IGNORE_UNUSED, 0), 3825 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss", 3826 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3827 4, CLK_IGNORE_UNUSED, 0), 3828 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix", 3829 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS, 3830 3, CLK_IGNORE_UNUSED, 0), 3831 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci", 3832 "div_aclk_atlas", ENABLE_ACLK_ATLAS, 3833 2, CLK_IGNORE_UNUSED, 0), 3834 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas", 3835 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3836 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas", 3837 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), 3838 3839 /* ENABLE_PCLK_ATLAS */ 3840 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys", 3841 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3842 5, CLK_IGNORE_UNUSED, 0), 3843 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys", 3844 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3845 4, CLK_IGNORE_UNUSED, 0), 3846 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys", 3847 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3848 3, CLK_IGNORE_UNUSED, 0), 3849 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas", 3850 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), 3851 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas", 3852 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3853 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas", 3854 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), 3855 3856 /* ENABLE_SCLK_ATLAS */ 3857 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas", 3858 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0), 3859 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas", 3860 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0), 3861 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas", 3862 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0), 3863 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas", 3864 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0), 3865 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas", 3866 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0), 3867 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas", 3868 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0), 3869 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas", 3870 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), 3871 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas", 3872 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3873 }; 3874 3875 #define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \ 3876 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \ 3877 ((pclk) << 12) | ((aclk) << 8)) 3878 3879 #define E5433_ATLAS_DIV1(hpm, copy) \ 3880 (((hpm) << 4) | ((copy) << 0)) 3881 3882 static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = { 3883 { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3884 { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3885 { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3886 { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3887 { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3888 { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3889 { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3890 { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3891 { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3892 { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3893 { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3894 { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3895 { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3896 { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3897 { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3898 { 0 }, 3899 }; 3900 3901 static void __init exynos5433_cmu_atlas_init(struct device_node *np) 3902 { 3903 void __iomem *reg_base; 3904 struct samsung_clk_provider *ctx; 3905 3906 reg_base = of_iomap(np, 0); 3907 if (!reg_base) { 3908 panic("%s: failed to map registers\n", __func__); 3909 return; 3910 } 3911 3912 ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK); 3913 if (!ctx) { 3914 panic("%s: unable to allocate ctx\n", __func__); 3915 return; 3916 } 3917 3918 samsung_clk_register_pll(ctx, atlas_pll_clks, 3919 ARRAY_SIZE(atlas_pll_clks), reg_base); 3920 samsung_clk_register_mux(ctx, atlas_mux_clks, 3921 ARRAY_SIZE(atlas_mux_clks)); 3922 samsung_clk_register_div(ctx, atlas_div_clks, 3923 ARRAY_SIZE(atlas_div_clks)); 3924 samsung_clk_register_gate(ctx, atlas_gate_clks, 3925 ARRAY_SIZE(atlas_gate_clks)); 3926 3927 exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk", 3928 mout_atlas_p[0], mout_atlas_p[1], 0x200, 3929 exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d), 3930 CLK_CPU_HAS_E5433_REGS_LAYOUT); 3931 3932 samsung_clk_sleep_init(reg_base, atlas_clk_regs, 3933 ARRAY_SIZE(atlas_clk_regs)); 3934 3935 samsung_clk_of_add_provider(np, ctx); 3936 } 3937 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", 3938 exynos5433_cmu_atlas_init); 3939 3940 /* 3941 * Register offset definitions for CMU_MSCL 3942 */ 3943 #define MUX_SEL_MSCL0 0x0200 3944 #define MUX_SEL_MSCL1 0x0204 3945 #define MUX_ENABLE_MSCL0 0x0300 3946 #define MUX_ENABLE_MSCL1 0x0304 3947 #define MUX_STAT_MSCL0 0x0400 3948 #define MUX_STAT_MSCL1 0x0404 3949 #define DIV_MSCL 0x0600 3950 #define DIV_STAT_MSCL 0x0700 3951 #define ENABLE_ACLK_MSCL 0x0800 3952 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804 3953 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808 3954 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c 3955 #define ENABLE_PCLK_MSCL 0x0900 3956 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904 3957 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908 3958 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c 3959 #define ENABLE_SCLK_MSCL 0x0a00 3960 #define ENABLE_IP_MSCL0 0x0b00 3961 #define ENABLE_IP_MSCL1 0x0b04 3962 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08 3963 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c 3964 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10 3965 3966 static const unsigned long mscl_clk_regs[] __initconst = { 3967 MUX_SEL_MSCL0, 3968 MUX_SEL_MSCL1, 3969 MUX_ENABLE_MSCL0, 3970 MUX_ENABLE_MSCL1, 3971 DIV_MSCL, 3972 ENABLE_ACLK_MSCL, 3973 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, 3974 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, 3975 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG, 3976 ENABLE_PCLK_MSCL, 3977 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0, 3978 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1, 3979 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG, 3980 ENABLE_SCLK_MSCL, 3981 ENABLE_IP_MSCL0, 3982 ENABLE_IP_MSCL1, 3983 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0, 3984 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1, 3985 ENABLE_IP_MSCL_SECURE_SMMU_JPEG, 3986 }; 3987 3988 static const struct samsung_clk_reg_dump mscl_suspend_regs[] = { 3989 { MUX_SEL_MSCL0, 0 }, 3990 { MUX_SEL_MSCL1, 0 }, 3991 }; 3992 3993 /* list of all parent clock list */ 3994 PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", }; 3995 PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", }; 3996 PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user", 3997 "mout_aclk_mscl_400_user", }; 3998 3999 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = { 4000 /* MUX_SEL_MSCL0 */ 4001 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user", 4002 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1), 4003 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user", 4004 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1), 4005 4006 /* MUX_SEL_MSCL1 */ 4007 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p, 4008 MUX_SEL_MSCL1, 0, 1), 4009 }; 4010 4011 static const struct samsung_div_clock mscl_div_clks[] __initconst = { 4012 /* DIV_MSCL */ 4013 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user", 4014 DIV_MSCL, 0, 3), 4015 }; 4016 4017 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = { 4018 /* ENABLE_ACLK_MSCL */ 4019 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user", 4020 ENABLE_ACLK_MSCL, 9, 0, 0), 4021 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1", 4022 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0), 4023 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0", 4024 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0), 4025 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl", 4026 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0), 4027 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user", 4028 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0), 4029 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl", 4030 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0), 4031 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user", 4032 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0), 4033 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user", 4034 ENABLE_ACLK_MSCL, 2, 0, 0), 4035 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user", 4036 ENABLE_ACLK_MSCL, 1, 0, 0), 4037 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user", 4038 ENABLE_ACLK_MSCL, 0, 0, 0), 4039 4040 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */ 4041 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0", 4042 "mout_aclk_mscl_400_user", 4043 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, 4044 0, CLK_IGNORE_UNUSED, 0), 4045 4046 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */ 4047 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1", 4048 "mout_aclk_mscl_400_user", 4049 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, 4050 0, CLK_IGNORE_UNUSED, 0), 4051 4052 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */ 4053 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user", 4054 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG, 4055 0, CLK_IGNORE_UNUSED, 0), 4056 4057 /* ENABLE_PCLK_MSCL */ 4058 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl", 4059 ENABLE_PCLK_MSCL, 7, 0, 0), 4060 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl", 4061 ENABLE_PCLK_MSCL, 6, 0, 0), 4062 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl", 4063 ENABLE_PCLK_MSCL, 5, 0, 0), 4064 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl", 4065 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0), 4066 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl", 4067 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0), 4068 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl", 4069 ENABLE_PCLK_MSCL, 2, 0, 0), 4070 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl", 4071 ENABLE_PCLK_MSCL, 1, 0, 0), 4072 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl", 4073 ENABLE_PCLK_MSCL, 0, 0, 0), 4074 4075 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */ 4076 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl", 4077 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0, 4078 0, CLK_IGNORE_UNUSED, 0), 4079 4080 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */ 4081 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl", 4082 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1, 4083 0, CLK_IGNORE_UNUSED, 0), 4084 4085 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */ 4086 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl", 4087 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG, 4088 0, CLK_IGNORE_UNUSED, 0), 4089 4090 /* ENABLE_SCLK_MSCL */ 4091 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0, 4092 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 4093 }; 4094 4095 static const struct samsung_cmu_info mscl_cmu_info __initconst = { 4096 .mux_clks = mscl_mux_clks, 4097 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 4098 .div_clks = mscl_div_clks, 4099 .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 4100 .gate_clks = mscl_gate_clks, 4101 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 4102 .nr_clk_ids = MSCL_NR_CLK, 4103 .clk_regs = mscl_clk_regs, 4104 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 4105 .suspend_regs = mscl_suspend_regs, 4106 .nr_suspend_regs = ARRAY_SIZE(mscl_suspend_regs), 4107 .clk_name = "aclk_mscl_400", 4108 }; 4109 4110 /* 4111 * Register offset definitions for CMU_MFC 4112 */ 4113 #define MUX_SEL_MFC 0x0200 4114 #define MUX_ENABLE_MFC 0x0300 4115 #define MUX_STAT_MFC 0x0400 4116 #define DIV_MFC 0x0600 4117 #define DIV_STAT_MFC 0x0700 4118 #define ENABLE_ACLK_MFC 0x0800 4119 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804 4120 #define ENABLE_PCLK_MFC 0x0900 4121 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904 4122 #define ENABLE_IP_MFC0 0x0b00 4123 #define ENABLE_IP_MFC1 0x0b04 4124 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08 4125 4126 static const unsigned long mfc_clk_regs[] __initconst = { 4127 MUX_SEL_MFC, 4128 MUX_ENABLE_MFC, 4129 DIV_MFC, 4130 ENABLE_ACLK_MFC, 4131 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4132 ENABLE_PCLK_MFC, 4133 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4134 ENABLE_IP_MFC0, 4135 ENABLE_IP_MFC1, 4136 ENABLE_IP_MFC_SECURE_SMMU_MFC, 4137 }; 4138 4139 static const struct samsung_clk_reg_dump mfc_suspend_regs[] = { 4140 { MUX_SEL_MFC, 0 }, 4141 }; 4142 4143 PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", }; 4144 4145 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { 4146 /* MUX_SEL_MFC */ 4147 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user", 4148 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0), 4149 }; 4150 4151 static const struct samsung_div_clock mfc_div_clks[] __initconst = { 4152 /* DIV_MFC */ 4153 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user", 4154 DIV_MFC, 0, 2), 4155 }; 4156 4157 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { 4158 /* ENABLE_ACLK_MFC */ 4159 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user", 4160 ENABLE_ACLK_MFC, 6, 0, 0), 4161 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user", 4162 ENABLE_ACLK_MFC, 5, 0, 0), 4163 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc", 4164 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0), 4165 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user", 4166 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0), 4167 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc", 4168 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0), 4169 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user", 4170 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0), 4171 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user", 4172 ENABLE_ACLK_MFC, 0, 0, 0), 4173 4174 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */ 4175 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user", 4176 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4177 1, CLK_IGNORE_UNUSED, 0), 4178 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user", 4179 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4180 0, CLK_IGNORE_UNUSED, 0), 4181 4182 /* ENABLE_PCLK_MFC */ 4183 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc", 4184 ENABLE_PCLK_MFC, 4, 0, 0), 4185 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc", 4186 ENABLE_PCLK_MFC, 3, 0, 0), 4187 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc", 4188 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0), 4189 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc", 4190 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0), 4191 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc", 4192 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0), 4193 4194 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */ 4195 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc", 4196 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4197 1, CLK_IGNORE_UNUSED, 0), 4198 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc", 4199 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4200 0, CLK_IGNORE_UNUSED, 0), 4201 }; 4202 4203 static const struct samsung_cmu_info mfc_cmu_info __initconst = { 4204 .mux_clks = mfc_mux_clks, 4205 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), 4206 .div_clks = mfc_div_clks, 4207 .nr_div_clks = ARRAY_SIZE(mfc_div_clks), 4208 .gate_clks = mfc_gate_clks, 4209 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), 4210 .nr_clk_ids = MFC_NR_CLK, 4211 .clk_regs = mfc_clk_regs, 4212 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), 4213 .suspend_regs = mfc_suspend_regs, 4214 .nr_suspend_regs = ARRAY_SIZE(mfc_suspend_regs), 4215 .clk_name = "aclk_mfc_400", 4216 }; 4217 4218 /* 4219 * Register offset definitions for CMU_HEVC 4220 */ 4221 #define MUX_SEL_HEVC 0x0200 4222 #define MUX_ENABLE_HEVC 0x0300 4223 #define MUX_STAT_HEVC 0x0400 4224 #define DIV_HEVC 0x0600 4225 #define DIV_STAT_HEVC 0x0700 4226 #define ENABLE_ACLK_HEVC 0x0800 4227 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804 4228 #define ENABLE_PCLK_HEVC 0x0900 4229 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904 4230 #define ENABLE_IP_HEVC0 0x0b00 4231 #define ENABLE_IP_HEVC1 0x0b04 4232 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08 4233 4234 static const unsigned long hevc_clk_regs[] __initconst = { 4235 MUX_SEL_HEVC, 4236 MUX_ENABLE_HEVC, 4237 DIV_HEVC, 4238 ENABLE_ACLK_HEVC, 4239 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4240 ENABLE_PCLK_HEVC, 4241 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4242 ENABLE_IP_HEVC0, 4243 ENABLE_IP_HEVC1, 4244 ENABLE_IP_HEVC_SECURE_SMMU_HEVC, 4245 }; 4246 4247 static const struct samsung_clk_reg_dump hevc_suspend_regs[] = { 4248 { MUX_SEL_HEVC, 0 }, 4249 }; 4250 4251 PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", }; 4252 4253 static const struct samsung_mux_clock hevc_mux_clks[] __initconst = { 4254 /* MUX_SEL_HEVC */ 4255 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user", 4256 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0), 4257 }; 4258 4259 static const struct samsung_div_clock hevc_div_clks[] __initconst = { 4260 /* DIV_HEVC */ 4261 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user", 4262 DIV_HEVC, 0, 2), 4263 }; 4264 4265 static const struct samsung_gate_clock hevc_gate_clks[] __initconst = { 4266 /* ENABLE_ACLK_HEVC */ 4267 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user", 4268 ENABLE_ACLK_HEVC, 6, 0, 0), 4269 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user", 4270 ENABLE_ACLK_HEVC, 5, 0, 0), 4271 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc", 4272 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0), 4273 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user", 4274 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0), 4275 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc", 4276 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0), 4277 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user", 4278 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0), 4279 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user", 4280 ENABLE_ACLK_HEVC, 0, 0, 0), 4281 4282 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */ 4283 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1", 4284 "mout_aclk_hevc_400_user", 4285 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4286 1, CLK_IGNORE_UNUSED, 0), 4287 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0", 4288 "mout_aclk_hevc_400_user", 4289 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4290 0, CLK_IGNORE_UNUSED, 0), 4291 4292 /* ENABLE_PCLK_HEVC */ 4293 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc", 4294 ENABLE_PCLK_HEVC, 4, 0, 0), 4295 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc", 4296 ENABLE_PCLK_HEVC, 3, 0, 0), 4297 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc", 4298 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0), 4299 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc", 4300 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0), 4301 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc", 4302 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0), 4303 4304 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */ 4305 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc", 4306 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4307 1, CLK_IGNORE_UNUSED, 0), 4308 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc", 4309 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4310 0, CLK_IGNORE_UNUSED, 0), 4311 }; 4312 4313 static const struct samsung_cmu_info hevc_cmu_info __initconst = { 4314 .mux_clks = hevc_mux_clks, 4315 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks), 4316 .div_clks = hevc_div_clks, 4317 .nr_div_clks = ARRAY_SIZE(hevc_div_clks), 4318 .gate_clks = hevc_gate_clks, 4319 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks), 4320 .nr_clk_ids = HEVC_NR_CLK, 4321 .clk_regs = hevc_clk_regs, 4322 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs), 4323 .suspend_regs = hevc_suspend_regs, 4324 .nr_suspend_regs = ARRAY_SIZE(hevc_suspend_regs), 4325 .clk_name = "aclk_hevc_400", 4326 }; 4327 4328 /* 4329 * Register offset definitions for CMU_ISP 4330 */ 4331 #define MUX_SEL_ISP 0x0200 4332 #define MUX_ENABLE_ISP 0x0300 4333 #define MUX_STAT_ISP 0x0400 4334 #define DIV_ISP 0x0600 4335 #define DIV_STAT_ISP 0x0700 4336 #define ENABLE_ACLK_ISP0 0x0800 4337 #define ENABLE_ACLK_ISP1 0x0804 4338 #define ENABLE_ACLK_ISP2 0x0808 4339 #define ENABLE_PCLK_ISP 0x0900 4340 #define ENABLE_SCLK_ISP 0x0a00 4341 #define ENABLE_IP_ISP0 0x0b00 4342 #define ENABLE_IP_ISP1 0x0b04 4343 #define ENABLE_IP_ISP2 0x0b08 4344 #define ENABLE_IP_ISP3 0x0b0c 4345 4346 static const unsigned long isp_clk_regs[] __initconst = { 4347 MUX_SEL_ISP, 4348 MUX_ENABLE_ISP, 4349 DIV_ISP, 4350 ENABLE_ACLK_ISP0, 4351 ENABLE_ACLK_ISP1, 4352 ENABLE_ACLK_ISP2, 4353 ENABLE_PCLK_ISP, 4354 ENABLE_SCLK_ISP, 4355 ENABLE_IP_ISP0, 4356 ENABLE_IP_ISP1, 4357 ENABLE_IP_ISP2, 4358 ENABLE_IP_ISP3, 4359 }; 4360 4361 static const struct samsung_clk_reg_dump isp_suspend_regs[] = { 4362 { MUX_SEL_ISP, 0 }, 4363 }; 4364 4365 PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", }; 4366 PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", }; 4367 4368 static const struct samsung_mux_clock isp_mux_clks[] __initconst = { 4369 /* MUX_SEL_ISP */ 4370 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user", 4371 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0), 4372 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user", 4373 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0), 4374 }; 4375 4376 static const struct samsung_div_clock isp_div_clks[] __initconst = { 4377 /* DIV_ISP */ 4378 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis", 4379 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3), 4380 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user", 4381 DIV_ISP, 8, 3), 4382 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200", 4383 "mout_aclk_isp_400_user", DIV_ISP, 4, 3), 4384 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200", 4385 "mout_aclk_isp_400_user", DIV_ISP, 0, 3), 4386 }; 4387 4388 static const struct samsung_gate_clock isp_gate_clks[] __initconst = { 4389 /* ENABLE_ACLK_ISP0 */ 4390 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user", 4391 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0), 4392 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user", 4393 ENABLE_ACLK_ISP0, 5, 0, 0), 4394 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user", 4395 ENABLE_ACLK_ISP0, 4, 0, 0), 4396 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user", 4397 ENABLE_ACLK_ISP0, 3, 0, 0), 4398 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user", 4399 ENABLE_ACLK_ISP0, 2, 0, 0), 4400 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user", 4401 ENABLE_ACLK_ISP0, 1, 0, 0), 4402 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user", 4403 ENABLE_ACLK_ISP0, 0, 0, 0), 4404 4405 /* ENABLE_ACLK_ISP1 */ 4406 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp", 4407 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4408 17, CLK_IGNORE_UNUSED, 0), 4409 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc", 4410 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4411 16, CLK_IGNORE_UNUSED, 0), 4412 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc", 4413 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4414 15, CLK_IGNORE_UNUSED, 0), 4415 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p", 4416 "div_pclk_isp", ENABLE_ACLK_ISP1, 4417 14, CLK_IGNORE_UNUSED, 0), 4418 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p", 4419 "div_pclk_isp", ENABLE_ACLK_ISP1, 4420 13, CLK_IGNORE_UNUSED, 0), 4421 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1", 4422 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, 4423 12, CLK_IGNORE_UNUSED, 0), 4424 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0", 4425 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, 4426 11, CLK_IGNORE_UNUSED, 0), 4427 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1", 4428 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4429 10, CLK_IGNORE_UNUSED, 0), 4430 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0", 4431 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4432 9, CLK_IGNORE_UNUSED, 0), 4433 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p", 4434 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, 4435 8, CLK_IGNORE_UNUSED, 0), 4436 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p", 4437 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, 4438 7, CLK_IGNORE_UNUSED, 0), 4439 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp", 4440 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0), 4441 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp", 4442 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0), 4443 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p", 4444 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, 4445 4, CLK_IGNORE_UNUSED, 0), 4446 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p", 4447 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, 4448 3, CLK_IGNORE_UNUSED, 0), 4449 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user", 4450 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0), 4451 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user", 4452 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), 4453 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user", 4454 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), 4455 4456 /* ENABLE_ACLK_ISP2 */ 4457 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp", 4458 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4459 13, CLK_IGNORE_UNUSED, 0), 4460 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user", 4461 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0), 4462 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user", 4463 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0), 4464 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user", 4465 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0), 4466 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc", 4467 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4468 9, CLK_IGNORE_UNUSED, 0), 4469 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user", 4470 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0), 4471 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user", 4472 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0), 4473 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp", 4474 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4475 6, CLK_IGNORE_UNUSED, 0), 4476 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user", 4477 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0), 4478 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user", 4479 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0), 4480 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user", 4481 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0), 4482 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc", 4483 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4484 2, CLK_IGNORE_UNUSED, 0), 4485 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user", 4486 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0), 4487 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user", 4488 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0), 4489 4490 /* ENABLE_PCLK_ISP */ 4491 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200", 4492 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0), 4493 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200", 4494 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0), 4495 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200", 4496 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0), 4497 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200", 4498 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0), 4499 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200", 4500 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0), 4501 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200", 4502 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0), 4503 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200", 4504 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0), 4505 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp", 4506 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0), 4507 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp", 4508 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0), 4509 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp", 4510 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0), 4511 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp", 4512 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0), 4513 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp", 4514 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0), 4515 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp", 4516 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0), 4517 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp", 4518 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0), 4519 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp", 4520 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0), 4521 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp", 4522 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0), 4523 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp", 4524 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0), 4525 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp", 4526 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0), 4527 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local", 4528 "div_aclk_isp_c_200", ENABLE_PCLK_ISP, 4529 7, CLK_IGNORE_UNUSED, 0), 4530 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200", 4531 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0), 4532 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200", 4533 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0), 4534 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis", 4535 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0), 4536 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200", 4537 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0), 4538 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200", 4539 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0), 4540 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200", 4541 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0), 4542 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200", 4543 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0), 4544 4545 /* ENABLE_SCLK_ISP */ 4546 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis", 4547 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, 4548 5, CLK_IGNORE_UNUSED, 0), 4549 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis", 4550 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, 4551 4, CLK_IGNORE_UNUSED, 0), 4552 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp", 4553 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4554 3, CLK_IGNORE_UNUSED, 0), 4555 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd", 4556 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4557 2, CLK_IGNORE_UNUSED, 0), 4558 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc", 4559 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4560 1, CLK_IGNORE_UNUSED, 0), 4561 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc", 4562 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4563 0, CLK_IGNORE_UNUSED, 0), 4564 }; 4565 4566 static const struct samsung_cmu_info isp_cmu_info __initconst = { 4567 .mux_clks = isp_mux_clks, 4568 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), 4569 .div_clks = isp_div_clks, 4570 .nr_div_clks = ARRAY_SIZE(isp_div_clks), 4571 .gate_clks = isp_gate_clks, 4572 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), 4573 .nr_clk_ids = ISP_NR_CLK, 4574 .clk_regs = isp_clk_regs, 4575 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), 4576 .suspend_regs = isp_suspend_regs, 4577 .nr_suspend_regs = ARRAY_SIZE(isp_suspend_regs), 4578 .clk_name = "aclk_isp_400", 4579 }; 4580 4581 /* 4582 * Register offset definitions for CMU_CAM0 4583 */ 4584 #define MUX_SEL_CAM00 0x0200 4585 #define MUX_SEL_CAM01 0x0204 4586 #define MUX_SEL_CAM02 0x0208 4587 #define MUX_SEL_CAM03 0x020c 4588 #define MUX_SEL_CAM04 0x0210 4589 #define MUX_ENABLE_CAM00 0x0300 4590 #define MUX_ENABLE_CAM01 0x0304 4591 #define MUX_ENABLE_CAM02 0x0308 4592 #define MUX_ENABLE_CAM03 0x030c 4593 #define MUX_ENABLE_CAM04 0x0310 4594 #define MUX_STAT_CAM00 0x0400 4595 #define MUX_STAT_CAM01 0x0404 4596 #define MUX_STAT_CAM02 0x0408 4597 #define MUX_STAT_CAM03 0x040c 4598 #define MUX_STAT_CAM04 0x0410 4599 #define MUX_IGNORE_CAM01 0x0504 4600 #define DIV_CAM00 0x0600 4601 #define DIV_CAM01 0x0604 4602 #define DIV_CAM02 0x0608 4603 #define DIV_CAM03 0x060c 4604 #define DIV_STAT_CAM00 0x0700 4605 #define DIV_STAT_CAM01 0x0704 4606 #define DIV_STAT_CAM02 0x0708 4607 #define DIV_STAT_CAM03 0x070c 4608 #define ENABLE_ACLK_CAM00 0X0800 4609 #define ENABLE_ACLK_CAM01 0X0804 4610 #define ENABLE_ACLK_CAM02 0X0808 4611 #define ENABLE_PCLK_CAM0 0X0900 4612 #define ENABLE_SCLK_CAM0 0X0a00 4613 #define ENABLE_IP_CAM00 0X0b00 4614 #define ENABLE_IP_CAM01 0X0b04 4615 #define ENABLE_IP_CAM02 0X0b08 4616 #define ENABLE_IP_CAM03 0X0b0C 4617 4618 static const unsigned long cam0_clk_regs[] __initconst = { 4619 MUX_SEL_CAM00, 4620 MUX_SEL_CAM01, 4621 MUX_SEL_CAM02, 4622 MUX_SEL_CAM03, 4623 MUX_SEL_CAM04, 4624 MUX_ENABLE_CAM00, 4625 MUX_ENABLE_CAM01, 4626 MUX_ENABLE_CAM02, 4627 MUX_ENABLE_CAM03, 4628 MUX_ENABLE_CAM04, 4629 MUX_IGNORE_CAM01, 4630 DIV_CAM00, 4631 DIV_CAM01, 4632 DIV_CAM02, 4633 DIV_CAM03, 4634 ENABLE_ACLK_CAM00, 4635 ENABLE_ACLK_CAM01, 4636 ENABLE_ACLK_CAM02, 4637 ENABLE_PCLK_CAM0, 4638 ENABLE_SCLK_CAM0, 4639 ENABLE_IP_CAM00, 4640 ENABLE_IP_CAM01, 4641 ENABLE_IP_CAM02, 4642 ENABLE_IP_CAM03, 4643 }; 4644 4645 static const struct samsung_clk_reg_dump cam0_suspend_regs[] = { 4646 { MUX_SEL_CAM00, 0 }, 4647 { MUX_SEL_CAM01, 0 }, 4648 { MUX_SEL_CAM02, 0 }, 4649 { MUX_SEL_CAM03, 0 }, 4650 { MUX_SEL_CAM04, 0 }, 4651 }; 4652 4653 PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", }; 4654 PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", }; 4655 PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", }; 4656 4657 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk", 4658 "phyclk_rxbyteclkhs0_s4_phy", }; 4659 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk", 4660 "phyclk_rxbyteclkhs0_s2a_phy", }; 4661 4662 PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a", 4663 "mout_aclk_cam0_333_user", }; 4664 PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user", 4665 "mout_aclk_cam0_400_user", }; 4666 PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a", 4667 "mout_aclk_cam0_333_user", }; 4668 PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user", 4669 "mout_aclk_cam0_400_user", }; 4670 PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a", 4671 "mout_aclk_cam0_333_user", }; 4672 PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user", 4673 "mout_aclk_cam0_400_user", }; 4674 PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user", 4675 "mout_aclk_cam0_333_user", }; 4676 4677 PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a", 4678 "mout_aclk_cam0_333_user" }; 4679 PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user", 4680 "mout_aclk_cam0_400_user", }; 4681 PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a", 4682 "mout_aclk_cam0_333_user", }; 4683 PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user", 4684 "mout_aclk-cam0_400_user", }; 4685 PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a", 4686 "mout_aclk_cam0_333_user", }; 4687 PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user", 4688 "mout_aclk_cam0_400_user", }; 4689 PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a", 4690 "mout_aclk_cam0_333_user", }; 4691 PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user", 4692 "mout_aclk_cam0_400_user", }; 4693 4694 PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b", 4695 "div_pclk_lite_d", }; 4696 PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a", 4697 "div_pclk_pixelasync_lite_c", }; 4698 PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a", 4699 "div_pclk_lite_b", }; 4700 PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a", 4701 "mout_aclk_cam0_333_user", }; 4702 PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user", 4703 "mout_aclk_cam0_400_user", }; 4704 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = { 4705 "mout_sclk_pixelasync_lite_c_init_a", 4706 "mout_aclk_cam0_400_user", }; 4707 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = { 4708 "mout_aclk_cam0_552_user", 4709 "mout_aclk_cam0_400_user", }; 4710 4711 static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = { 4712 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy", 4713 NULL, 0, 100000000), 4714 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy", 4715 NULL, 0, 100000000), 4716 }; 4717 4718 static const struct samsung_mux_clock cam0_mux_clks[] __initconst = { 4719 /* MUX_SEL_CAM00 */ 4720 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user", 4721 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1), 4722 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user", 4723 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1), 4724 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user", 4725 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1), 4726 4727 /* MUX_SEL_CAM01 */ 4728 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER, 4729 "mout_phyclk_rxbyteclkhs0_s4_user", 4730 mout_phyclk_rxbyteclkhs0_s4_user_p, 4731 MUX_SEL_CAM01, 4, 1), 4732 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER, 4733 "mout_phyclk_rxbyteclkhs0_s2a_user", 4734 mout_phyclk_rxbyteclkhs0_s2a_user_p, 4735 MUX_SEL_CAM01, 0, 1), 4736 4737 /* MUX_SEL_CAM02 */ 4738 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p, 4739 MUX_SEL_CAM02, 24, 1), 4740 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p, 4741 MUX_SEL_CAM02, 20, 1), 4742 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p, 4743 MUX_SEL_CAM02, 16, 1), 4744 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p, 4745 MUX_SEL_CAM02, 12, 1), 4746 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p, 4747 MUX_SEL_CAM02, 8, 1), 4748 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p, 4749 MUX_SEL_CAM02, 4, 1), 4750 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p, 4751 MUX_SEL_CAM02, 0, 1), 4752 4753 /* MUX_SEL_CAM03 */ 4754 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p, 4755 MUX_SEL_CAM03, 28, 1), 4756 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p, 4757 MUX_SEL_CAM03, 24, 1), 4758 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p, 4759 MUX_SEL_CAM03, 20, 1), 4760 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p, 4761 MUX_SEL_CAM03, 16, 1), 4762 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p, 4763 MUX_SEL_CAM03, 12, 1), 4764 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p, 4765 MUX_SEL_CAM03, 8, 1), 4766 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p, 4767 MUX_SEL_CAM03, 4, 1), 4768 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p, 4769 MUX_SEL_CAM03, 0, 1), 4770 4771 /* MUX_SEL_CAM04 */ 4772 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c", 4773 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1), 4774 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b", 4775 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1), 4776 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a", 4777 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1), 4778 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b", 4779 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1), 4780 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a", 4781 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1), 4782 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B, 4783 "mout_sclk_pixelasync_lite_c_init_b", 4784 mout_sclk_pixelasync_lite_c_init_b_p, 4785 MUX_SEL_CAM04, 4, 1), 4786 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A, 4787 "mout_sclk_pixelasync_lite_c_init_a", 4788 mout_sclk_pixelasync_lite_c_init_a_p, 4789 MUX_SEL_CAM04, 0, 1), 4790 }; 4791 4792 static const struct samsung_div_clock cam0_div_clks[] __initconst = { 4793 /* DIV_CAM00 */ 4794 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200", 4795 DIV_CAM00, 8, 2), 4796 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400", 4797 DIV_CAM00, 4, 3), 4798 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400", 4799 "mout_aclk_cam0_400", DIV_CAM00, 0, 3), 4800 4801 /* DIV_CAM01 */ 4802 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d", 4803 DIV_CAM01, 20, 2), 4804 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b", 4805 DIV_CAM01, 16, 3), 4806 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b", 4807 DIV_CAM01, 12, 2), 4808 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b", 4809 DIV_CAM01, 8, 3), 4810 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a", 4811 DIV_CAM01, 4, 2), 4812 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b", 4813 DIV_CAM01, 0, 3), 4814 4815 /* DIV_CAM02 */ 4816 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b", 4817 DIV_CAM02, 20, 3), 4818 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b", 4819 DIV_CAM02, 16, 3), 4820 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1", 4821 DIV_CAM02, 12, 2), 4822 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b", 4823 DIV_CAM02, 8, 3), 4824 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0", 4825 DIV_CAM02, 4, 2), 4826 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b", 4827 DIV_CAM02, 0, 3), 4828 4829 /* DIV_CAM03 */ 4830 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c", 4831 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3), 4832 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c", 4833 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2), 4834 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT, 4835 "div_sclk_pixelasync_lite_c_init", 4836 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3), 4837 }; 4838 4839 static const struct samsung_gate_clock cam0_gate_clks[] __initconst = { 4840 /* ENABLE_ACLK_CAM00 */ 4841 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00, 4842 6, 0, 0), 4843 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00, 4844 5, 0, 0), 4845 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00, 4846 4, 0, 0), 4847 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00, 4848 3, 0, 0), 4849 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d", 4850 ENABLE_ACLK_CAM00, 2, 0, 0), 4851 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b", 4852 ENABLE_ACLK_CAM00, 1, 0, 0), 4853 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a", 4854 ENABLE_ACLK_CAM00, 0, 0, 0), 4855 4856 /* ENABLE_ACLK_CAM01 */ 4857 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200", 4858 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0), 4859 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400", 4860 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0), 4861 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400", 4862 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0), 4863 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400", 4864 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0), 4865 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1", 4866 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0), 4867 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1", 4868 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0), 4869 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0", 4870 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0), 4871 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0", 4872 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0), 4873 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d", 4874 "div_pclk_lite_d", ENABLE_ACLK_CAM01, 4875 23, CLK_IGNORE_UNUSED, 0), 4876 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d", 4877 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4878 22, CLK_IGNORE_UNUSED, 0), 4879 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b", 4880 "div_pclk_lite_b", ENABLE_ACLK_CAM01, 4881 21, CLK_IGNORE_UNUSED, 0), 4882 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b", 4883 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4884 20, CLK_IGNORE_UNUSED, 0), 4885 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a", 4886 "div_pclk_lite_a", ENABLE_ACLK_CAM01, 4887 19, CLK_IGNORE_UNUSED, 0), 4888 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a", 4889 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4890 18, CLK_IGNORE_UNUSED, 0), 4891 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p", 4892 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4893 17, CLK_IGNORE_UNUSED, 0), 4894 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1", 4895 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4896 16, CLK_IGNORE_UNUSED, 0), 4897 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1", 4898 "div_aclk_3aa1", ENABLE_ACLK_CAM01, 4899 15, CLK_IGNORE_UNUSED, 0), 4900 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0", 4901 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4902 14, CLK_IGNORE_UNUSED, 0), 4903 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0", 4904 "div_aclk_3aa0", ENABLE_ACLK_CAM01, 4905 13, CLK_IGNORE_UNUSED, 0), 4906 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d", 4907 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4908 12, CLK_IGNORE_UNUSED, 0), 4909 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d", 4910 "div_aclk_lite_d", ENABLE_ACLK_CAM01, 4911 11, CLK_IGNORE_UNUSED, 0), 4912 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b", 4913 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4914 10, CLK_IGNORE_UNUSED, 0), 4915 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b", 4916 "div_aclk_lite_b", ENABLE_ACLK_CAM01, 4917 9, CLK_IGNORE_UNUSED, 0), 4918 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a", 4919 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4920 8, CLK_IGNORE_UNUSED, 0), 4921 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a", 4922 "div_aclk_lite_a", ENABLE_ACLK_CAM01, 4923 7, CLK_IGNORE_UNUSED, 0), 4924 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp", 4925 "div_pclk_cam0_50", ENABLE_ACLK_CAM01, 4926 6, CLK_IGNORE_UNUSED, 0), 4927 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200", 4928 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0), 4929 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200", 4930 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0), 4931 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200", 4932 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0), 4933 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400", 4934 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0), 4935 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200", 4936 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0), 4937 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400", 4938 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0), 4939 4940 /* ENABLE_ACLK_CAM02 */ 4941 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400", 4942 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0), 4943 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400", 4944 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0), 4945 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400", 4946 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0), 4947 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400", 4948 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0), 4949 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400", 4950 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0), 4951 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400", 4952 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0), 4953 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400", 4954 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0), 4955 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400", 4956 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0), 4957 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400", 4958 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0), 4959 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400", 4960 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0), 4961 4962 /* ENABLE_PCLK_CAM0 */ 4963 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200", 4964 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0), 4965 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200", 4966 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0), 4967 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200", 4968 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0), 4969 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200", 4970 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0), 4971 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200", 4972 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0), 4973 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50", 4974 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0), 4975 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50", 4976 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0), 4977 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50", 4978 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0), 4979 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50", 4980 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0), 4981 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50", 4982 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0), 4983 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50", 4984 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0), 4985 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50", 4986 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0), 4987 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50", 4988 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0), 4989 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d", 4990 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 4991 12, CLK_IGNORE_UNUSED, 0), 4992 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b", 4993 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 4994 11, CLK_IGNORE_UNUSED, 0), 4995 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a", 4996 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 4997 10, CLK_IGNORE_UNUSED, 0), 4998 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50", 4999 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0), 5000 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50", 5001 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0), 5002 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local", 5003 "div_aclk_cam0_200", ENABLE_PCLK_CAM0, 5004 7, CLK_IGNORE_UNUSED, 0), 5005 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200", 5006 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0), 5007 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200", 5008 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0), 5009 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1", 5010 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0), 5011 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0", 5012 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0), 5013 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d", 5014 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0), 5015 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b", 5016 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0), 5017 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a", 5018 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0), 5019 5020 /* ENABLE_SCLK_CAM0 */ 5021 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4", 5022 "mout_phyclk_rxbyteclkhs0_s4_user", 5023 ENABLE_SCLK_CAM0, 8, 0, 0), 5024 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a", 5025 "mout_phyclk_rxbyteclkhs0_s2a_user", 5026 ENABLE_SCLK_CAM0, 7, 0, 0), 5027 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt", 5028 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0), 5029 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1", 5030 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0), 5031 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0", 5032 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0), 5033 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0", 5034 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0), 5035 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c", 5036 "div_sclk_pixelasync_lite_c", 5037 ENABLE_SCLK_CAM0, 2, 0, 0), 5038 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init", 5039 "div_sclk_pixelasync_lite_c_init", 5040 ENABLE_SCLK_CAM0, 1, 0, 0), 5041 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init", 5042 "div_sclk_pixelasync_lite_c", 5043 ENABLE_SCLK_CAM0, 0, 0, 0), 5044 }; 5045 5046 static const struct samsung_cmu_info cam0_cmu_info __initconst = { 5047 .mux_clks = cam0_mux_clks, 5048 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks), 5049 .div_clks = cam0_div_clks, 5050 .nr_div_clks = ARRAY_SIZE(cam0_div_clks), 5051 .gate_clks = cam0_gate_clks, 5052 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks), 5053 .fixed_clks = cam0_fixed_clks, 5054 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks), 5055 .nr_clk_ids = CAM0_NR_CLK, 5056 .clk_regs = cam0_clk_regs, 5057 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs), 5058 .suspend_regs = cam0_suspend_regs, 5059 .nr_suspend_regs = ARRAY_SIZE(cam0_suspend_regs), 5060 .clk_name = "aclk_cam0_400", 5061 }; 5062 5063 /* 5064 * Register offset definitions for CMU_CAM1 5065 */ 5066 #define MUX_SEL_CAM10 0x0200 5067 #define MUX_SEL_CAM11 0x0204 5068 #define MUX_SEL_CAM12 0x0208 5069 #define MUX_ENABLE_CAM10 0x0300 5070 #define MUX_ENABLE_CAM11 0x0304 5071 #define MUX_ENABLE_CAM12 0x0308 5072 #define MUX_STAT_CAM10 0x0400 5073 #define MUX_STAT_CAM11 0x0404 5074 #define MUX_STAT_CAM12 0x0408 5075 #define MUX_IGNORE_CAM11 0x0504 5076 #define DIV_CAM10 0x0600 5077 #define DIV_CAM11 0x0604 5078 #define DIV_STAT_CAM10 0x0700 5079 #define DIV_STAT_CAM11 0x0704 5080 #define ENABLE_ACLK_CAM10 0X0800 5081 #define ENABLE_ACLK_CAM11 0X0804 5082 #define ENABLE_ACLK_CAM12 0X0808 5083 #define ENABLE_PCLK_CAM1 0X0900 5084 #define ENABLE_SCLK_CAM1 0X0a00 5085 #define ENABLE_IP_CAM10 0X0b00 5086 #define ENABLE_IP_CAM11 0X0b04 5087 #define ENABLE_IP_CAM12 0X0b08 5088 5089 static const unsigned long cam1_clk_regs[] __initconst = { 5090 MUX_SEL_CAM10, 5091 MUX_SEL_CAM11, 5092 MUX_SEL_CAM12, 5093 MUX_ENABLE_CAM10, 5094 MUX_ENABLE_CAM11, 5095 MUX_ENABLE_CAM12, 5096 MUX_IGNORE_CAM11, 5097 DIV_CAM10, 5098 DIV_CAM11, 5099 ENABLE_ACLK_CAM10, 5100 ENABLE_ACLK_CAM11, 5101 ENABLE_ACLK_CAM12, 5102 ENABLE_PCLK_CAM1, 5103 ENABLE_SCLK_CAM1, 5104 ENABLE_IP_CAM10, 5105 ENABLE_IP_CAM11, 5106 ENABLE_IP_CAM12, 5107 }; 5108 5109 static const struct samsung_clk_reg_dump cam1_suspend_regs[] = { 5110 { MUX_SEL_CAM10, 0 }, 5111 { MUX_SEL_CAM11, 0 }, 5112 { MUX_SEL_CAM12, 0 }, 5113 }; 5114 5115 PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", }; 5116 PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", }; 5117 PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", }; 5118 5119 PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", }; 5120 PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", }; 5121 PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", }; 5122 5123 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk", 5124 "phyclk_rxbyteclkhs0_s2b_phy", }; 5125 5126 PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a", 5127 "mout_aclk_cam1_333_user", }; 5128 PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user", 5129 "mout_aclk_cam1_400_user", }; 5130 5131 PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a", 5132 "mout_aclk_cam1_333_user", }; 5133 PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user", 5134 "mout_aclk_cam1_400_user", }; 5135 5136 PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a", 5137 "mout_aclk_cam1_333_user", }; 5138 PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user", 5139 "mout_aclk_cam1_400_user", }; 5140 5141 static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = { 5142 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL, 5143 0, 100000000), 5144 }; 5145 5146 static const struct samsung_mux_clock cam1_mux_clks[] __initconst = { 5147 /* MUX_SEL_CAM10 */ 5148 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user", 5149 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1), 5150 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user", 5151 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1), 5152 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user", 5153 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1), 5154 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user", 5155 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1), 5156 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user", 5157 mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1), 5158 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user", 5159 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1), 5160 5161 /* MUX_SEL_CAM11 */ 5162 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER, 5163 "mout_phyclk_rxbyteclkhs0_s2b_user", 5164 mout_phyclk_rxbyteclkhs0_s2b_user_p, 5165 MUX_SEL_CAM11, 0, 1), 5166 5167 /* MUX_SEL_CAM12 */ 5168 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p, 5169 MUX_SEL_CAM12, 20, 1), 5170 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p, 5171 MUX_SEL_CAM12, 16, 1), 5172 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p, 5173 MUX_SEL_CAM12, 12, 1), 5174 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p, 5175 MUX_SEL_CAM12, 8, 1), 5176 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p, 5177 MUX_SEL_CAM12, 4, 1), 5178 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p, 5179 MUX_SEL_CAM12, 0, 1), 5180 }; 5181 5182 static const struct samsung_div_clock cam1_div_clks[] __initconst = { 5183 /* DIV_CAM10 */ 5184 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm", 5185 "div_pclk_cam1_83", DIV_CAM10, 16, 2), 5186 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83", 5187 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2), 5188 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166", 5189 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2), 5190 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1", 5191 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3), 5192 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user", 5193 DIV_CAM10, 0, 3), 5194 5195 /* DIV_CAM11 */ 5196 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b", 5197 DIV_CAM11, 16, 3), 5198 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2), 5199 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3), 5200 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c", 5201 DIV_CAM11, 4, 2), 5202 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b", 5203 DIV_CAM11, 0, 3), 5204 }; 5205 5206 static const struct samsung_gate_clock cam1_gate_clks[] __initconst = { 5207 /* ENABLE_ACLK_CAM10 */ 5208 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user", 5209 ENABLE_ACLK_CAM10, 4, 0, 0), 5210 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd", 5211 ENABLE_ACLK_CAM10, 3, 0, 0), 5212 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c", 5213 ENABLE_ACLK_CAM10, 1, 0, 0), 5214 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2", 5215 ENABLE_ACLK_CAM10, 0, 0, 0), 5216 5217 /* ENABLE_ACLK_CAM11 */ 5218 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd", 5219 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0), 5220 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166", 5221 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0), 5222 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c", 5223 "div_pclk_lite_c", ENABLE_ACLK_CAM11, 5224 27, CLK_IGNORE_UNUSED, 0), 5225 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c", 5226 "div_pclk_cam1_166", ENABLE_ACLK_CAM11, 5227 26, CLK_IGNORE_UNUSED, 0), 5228 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2", 5229 "div_pclk_cam1_83", ENABLE_ACLK_CAM11, 5230 25, CLK_IGNORE_UNUSED, 0), 5231 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1", 5232 "div_pclk_cam1_83", ENABLE_ACLK_CAM11, 5233 24, CLK_IGNORE_UNUSED, 0), 5234 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5", 5235 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5236 23, CLK_IGNORE_UNUSED, 0), 5237 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5", 5238 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11, 5239 22, CLK_IGNORE_UNUSED, 0), 5240 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2", 5241 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5242 21, CLK_IGNORE_UNUSED, 0), 5243 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1", 5244 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5245 20, CLK_IGNORE_UNUSED, 0), 5246 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0", 5247 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5248 19, CLK_IGNORE_UNUSED, 0), 5249 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex", 5250 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5251 18, CLK_IGNORE_UNUSED, 0), 5252 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p", 5253 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5254 17, CLK_IGNORE_UNUSED, 0), 5255 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p", 5256 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5257 16, CLK_IGNORE_UNUSED, 0), 5258 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd", 5259 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5260 15, CLK_IGNORE_UNUSED, 0), 5261 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd", 5262 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0), 5263 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c", 5264 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5265 13, CLK_IGNORE_UNUSED, 0), 5266 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c", 5267 "div_aclk_lite_c", ENABLE_ACLK_CAM11, 5268 12, CLK_IGNORE_UNUSED, 0), 5269 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83", 5270 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0), 5271 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83", 5272 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0), 5273 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p", 5274 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5275 9, CLK_IGNORE_UNUSED, 0), 5276 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83", 5277 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0), 5278 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166", 5279 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0), 5280 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166", 5281 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0), 5282 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user", 5283 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0), 5284 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user", 5285 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0), 5286 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user", 5287 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0), 5288 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user", 5289 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0), 5290 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user", 5291 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0), 5292 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user", 5293 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0), 5294 5295 /* ENABLE_ACLK_CAM12 */ 5296 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu", 5297 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5298 10, CLK_IGNORE_UNUSED, 0), 5299 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user", 5300 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0), 5301 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c", 5302 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5303 8, CLK_IGNORE_UNUSED, 0), 5304 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user", 5305 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0), 5306 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user", 5307 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0), 5308 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user", 5309 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0), 5310 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h", 5311 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12, 5312 4, CLK_IGNORE_UNUSED, 0), 5313 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p", 5314 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12, 5315 3, CLK_IGNORE_UNUSED, 0), 5316 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p", 5317 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5318 2, CLK_IGNORE_UNUSED, 0), 5319 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user", 5320 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0), 5321 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c", 5322 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5323 0, CLK_IGNORE_UNUSED, 0), 5324 5325 /* ENABLE_PCLK_CAM1 */ 5326 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166", 5327 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0), 5328 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166", 5329 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0), 5330 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166", 5331 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0), 5332 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83", 5333 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0), 5334 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83", 5335 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0), 5336 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83", 5337 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0), 5338 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166", 5339 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0), 5340 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex", 5341 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5342 20, CLK_IGNORE_UNUSED, 0), 5343 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p", 5344 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5345 19, CLK_IGNORE_UNUSED, 0), 5346 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83", 5347 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0), 5348 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c", 5349 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5350 17, CLK_IGNORE_UNUSED, 0), 5351 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83", 5352 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0), 5353 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83", 5354 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0), 5355 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local", 5356 "div_pclk_cam1_166", ENABLE_PCLK_CAM1, 5357 14, CLK_IGNORE_UNUSED, 0), 5358 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83", 5359 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0), 5360 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83", 5361 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0), 5362 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83", 5363 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0), 5364 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83", 5365 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0), 5366 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83", 5367 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0), 5368 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83", 5369 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0), 5370 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83", 5371 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0), 5372 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83", 5373 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0), 5374 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83", 5375 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0), 5376 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83", 5377 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0), 5378 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83", 5379 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), 5380 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd", 5381 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), 5382 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c", 5383 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0), 5384 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166", 5385 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0), 5386 5387 /* ENABLE_SCLK_CAM1 */ 5388 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1, 5389 15, 0, 0), 5390 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1, 5391 14, 0, 0), 5392 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1, 5393 13, 0, 0), 5394 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1, 5395 12, 0, 0), 5396 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b", 5397 "mout_phyclk_rxbyteclkhs0_s2b_user", 5398 ENABLE_SCLK_CAM1, 11, 0, 0), 5399 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c", 5400 ENABLE_SCLK_CAM1, 10, 0, 0), 5401 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd", 5402 ENABLE_SCLK_CAM1, 9, 0, 0), 5403 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1", 5404 ENABLE_SCLK_CAM1, 7, 0, 0), 5405 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user", 5406 ENABLE_SCLK_CAM1, 6, 0, 0), 5407 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user", 5408 ENABLE_SCLK_CAM1, 5, 0, 0), 5409 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user", 5410 ENABLE_SCLK_CAM1, 4, 0, 0), 5411 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm", 5412 ENABLE_SCLK_CAM1, 3, 0, 0), 5413 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1", 5414 ENABLE_SCLK_CAM1, 2, 0, 0), 5415 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1", 5416 ENABLE_SCLK_CAM1, 1, 0, 0), 5417 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user", 5418 ENABLE_SCLK_CAM1, 0, 0, 0), 5419 }; 5420 5421 static const struct samsung_cmu_info cam1_cmu_info __initconst = { 5422 .mux_clks = cam1_mux_clks, 5423 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks), 5424 .div_clks = cam1_div_clks, 5425 .nr_div_clks = ARRAY_SIZE(cam1_div_clks), 5426 .gate_clks = cam1_gate_clks, 5427 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks), 5428 .fixed_clks = cam1_fixed_clks, 5429 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks), 5430 .nr_clk_ids = CAM1_NR_CLK, 5431 .clk_regs = cam1_clk_regs, 5432 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs), 5433 .suspend_regs = cam1_suspend_regs, 5434 .nr_suspend_regs = ARRAY_SIZE(cam1_suspend_regs), 5435 .clk_name = "aclk_cam1_400", 5436 }; 5437 5438 5439 struct exynos5433_cmu_data { 5440 struct samsung_clk_reg_dump *clk_save; 5441 unsigned int nr_clk_save; 5442 const struct samsung_clk_reg_dump *clk_suspend; 5443 unsigned int nr_clk_suspend; 5444 5445 struct clk *clk; 5446 struct clk **pclks; 5447 int nr_pclks; 5448 5449 /* must be the last entry */ 5450 struct samsung_clk_provider ctx; 5451 }; 5452 5453 static int __maybe_unused exynos5433_cmu_suspend(struct device *dev) 5454 { 5455 struct exynos5433_cmu_data *data = dev_get_drvdata(dev); 5456 int i; 5457 5458 samsung_clk_save(data->ctx.reg_base, data->clk_save, 5459 data->nr_clk_save); 5460 5461 for (i = 0; i < data->nr_pclks; i++) 5462 clk_prepare_enable(data->pclks[i]); 5463 5464 /* for suspend some registers have to be set to certain values */ 5465 samsung_clk_restore(data->ctx.reg_base, data->clk_suspend, 5466 data->nr_clk_suspend); 5467 5468 for (i = 0; i < data->nr_pclks; i++) 5469 clk_disable_unprepare(data->pclks[i]); 5470 5471 clk_disable_unprepare(data->clk); 5472 5473 return 0; 5474 } 5475 5476 static int __maybe_unused exynos5433_cmu_resume(struct device *dev) 5477 { 5478 struct exynos5433_cmu_data *data = dev_get_drvdata(dev); 5479 int i; 5480 5481 clk_prepare_enable(data->clk); 5482 5483 for (i = 0; i < data->nr_pclks; i++) 5484 clk_prepare_enable(data->pclks[i]); 5485 5486 samsung_clk_restore(data->ctx.reg_base, data->clk_save, 5487 data->nr_clk_save); 5488 5489 for (i = 0; i < data->nr_pclks; i++) 5490 clk_disable_unprepare(data->pclks[i]); 5491 5492 return 0; 5493 } 5494 5495 static int __init exynos5433_cmu_probe(struct platform_device *pdev) 5496 { 5497 const struct samsung_cmu_info *info; 5498 struct exynos5433_cmu_data *data; 5499 struct samsung_clk_provider *ctx; 5500 struct device *dev = &pdev->dev; 5501 struct resource *res; 5502 void __iomem *reg_base; 5503 int i; 5504 5505 info = of_device_get_match_data(dev); 5506 5507 data = devm_kzalloc(dev, sizeof(*data) + 5508 sizeof(*data->ctx.clk_data.hws) * info->nr_clk_ids, 5509 GFP_KERNEL); 5510 if (!data) 5511 return -ENOMEM; 5512 ctx = &data->ctx; 5513 5514 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5515 reg_base = devm_ioremap_resource(dev, res); 5516 if (IS_ERR(reg_base)) { 5517 dev_err(dev, "failed to map registers\n"); 5518 return PTR_ERR(reg_base); 5519 } 5520 5521 for (i = 0; i < info->nr_clk_ids; ++i) 5522 ctx->clk_data.hws[i] = ERR_PTR(-ENOENT); 5523 5524 ctx->clk_data.num = info->nr_clk_ids; 5525 ctx->reg_base = reg_base; 5526 ctx->dev = dev; 5527 spin_lock_init(&ctx->lock); 5528 5529 data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs, 5530 info->nr_clk_regs); 5531 data->nr_clk_save = info->nr_clk_regs; 5532 data->clk_suspend = info->suspend_regs; 5533 data->nr_clk_suspend = info->nr_suspend_regs; 5534 data->nr_pclks = of_count_phandle_with_args(dev->of_node, "clocks", 5535 "#clock-cells"); 5536 if (data->nr_pclks > 0) { 5537 data->pclks = devm_kcalloc(dev, sizeof(struct clk *), 5538 data->nr_pclks, GFP_KERNEL); 5539 5540 for (i = 0; i < data->nr_pclks; i++) { 5541 struct clk *clk = of_clk_get(dev->of_node, i); 5542 5543 if (IS_ERR(clk)) 5544 return PTR_ERR(clk); 5545 data->pclks[i] = clk; 5546 } 5547 } 5548 5549 if (info->clk_name) 5550 data->clk = clk_get(dev, info->clk_name); 5551 clk_prepare_enable(data->clk); 5552 5553 platform_set_drvdata(pdev, data); 5554 5555 /* 5556 * Enable runtime PM here to allow the clock core using runtime PM 5557 * for the registered clocks. Additionally, we increase the runtime 5558 * PM usage count before registering the clocks, to prevent the 5559 * clock core from runtime suspending the device. 5560 */ 5561 pm_runtime_get_noresume(dev); 5562 pm_runtime_set_active(dev); 5563 pm_runtime_enable(dev); 5564 5565 if (info->pll_clks) 5566 samsung_clk_register_pll(ctx, info->pll_clks, info->nr_pll_clks, 5567 reg_base); 5568 if (info->mux_clks) 5569 samsung_clk_register_mux(ctx, info->mux_clks, 5570 info->nr_mux_clks); 5571 if (info->div_clks) 5572 samsung_clk_register_div(ctx, info->div_clks, 5573 info->nr_div_clks); 5574 if (info->gate_clks) 5575 samsung_clk_register_gate(ctx, info->gate_clks, 5576 info->nr_gate_clks); 5577 if (info->fixed_clks) 5578 samsung_clk_register_fixed_rate(ctx, info->fixed_clks, 5579 info->nr_fixed_clks); 5580 if (info->fixed_factor_clks) 5581 samsung_clk_register_fixed_factor(ctx, info->fixed_factor_clks, 5582 info->nr_fixed_factor_clks); 5583 5584 samsung_clk_of_add_provider(dev->of_node, ctx); 5585 pm_runtime_put_sync(dev); 5586 5587 return 0; 5588 } 5589 5590 static const struct of_device_id exynos5433_cmu_of_match[] = { 5591 { 5592 .compatible = "samsung,exynos5433-cmu-aud", 5593 .data = &aud_cmu_info, 5594 }, { 5595 .compatible = "samsung,exynos5433-cmu-cam0", 5596 .data = &cam0_cmu_info, 5597 }, { 5598 .compatible = "samsung,exynos5433-cmu-cam1", 5599 .data = &cam1_cmu_info, 5600 }, { 5601 .compatible = "samsung,exynos5433-cmu-disp", 5602 .data = &disp_cmu_info, 5603 }, { 5604 .compatible = "samsung,exynos5433-cmu-g2d", 5605 .data = &g2d_cmu_info, 5606 }, { 5607 .compatible = "samsung,exynos5433-cmu-g3d", 5608 .data = &g3d_cmu_info, 5609 }, { 5610 .compatible = "samsung,exynos5433-cmu-fsys", 5611 .data = &fsys_cmu_info, 5612 }, { 5613 .compatible = "samsung,exynos5433-cmu-gscl", 5614 .data = &gscl_cmu_info, 5615 }, { 5616 .compatible = "samsung,exynos5433-cmu-mfc", 5617 .data = &mfc_cmu_info, 5618 }, { 5619 .compatible = "samsung,exynos5433-cmu-hevc", 5620 .data = &hevc_cmu_info, 5621 }, { 5622 .compatible = "samsung,exynos5433-cmu-isp", 5623 .data = &isp_cmu_info, 5624 }, { 5625 .compatible = "samsung,exynos5433-cmu-mscl", 5626 .data = &mscl_cmu_info, 5627 }, { 5628 }, 5629 }; 5630 5631 static const struct dev_pm_ops exynos5433_cmu_pm_ops = { 5632 SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume, 5633 NULL) 5634 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5635 pm_runtime_force_resume) 5636 }; 5637 5638 static struct platform_driver exynos5433_cmu_driver __refdata = { 5639 .driver = { 5640 .name = "exynos5433-cmu", 5641 .of_match_table = exynos5433_cmu_of_match, 5642 .suppress_bind_attrs = true, 5643 .pm = &exynos5433_cmu_pm_ops, 5644 }, 5645 .probe = exynos5433_cmu_probe, 5646 }; 5647 5648 static int __init exynos5433_cmu_init(void) 5649 { 5650 return platform_driver_register(&exynos5433_cmu_driver); 5651 } 5652 core_initcall(exynos5433_cmu_init); 5653