1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Common Clock Framework support for Exynos5433 SoC. 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 16 #include <dt-bindings/clock/exynos5433.h> 17 18 #include "clk.h" 19 #include "clk-cpu.h" 20 #include "clk-pll.h" 21 22 /* 23 * Register offset definitions for CMU_TOP 24 */ 25 #define ISP_PLL_LOCK 0x0000 26 #define AUD_PLL_LOCK 0x0004 27 #define ISP_PLL_CON0 0x0100 28 #define ISP_PLL_CON1 0x0104 29 #define ISP_PLL_FREQ_DET 0x0108 30 #define AUD_PLL_CON0 0x0110 31 #define AUD_PLL_CON1 0x0114 32 #define AUD_PLL_CON2 0x0118 33 #define AUD_PLL_FREQ_DET 0x011c 34 #define MUX_SEL_TOP0 0x0200 35 #define MUX_SEL_TOP1 0x0204 36 #define MUX_SEL_TOP2 0x0208 37 #define MUX_SEL_TOP3 0x020c 38 #define MUX_SEL_TOP4 0x0210 39 #define MUX_SEL_TOP_MSCL 0x0220 40 #define MUX_SEL_TOP_CAM1 0x0224 41 #define MUX_SEL_TOP_DISP 0x0228 42 #define MUX_SEL_TOP_FSYS0 0x0230 43 #define MUX_SEL_TOP_FSYS1 0x0234 44 #define MUX_SEL_TOP_PERIC0 0x0238 45 #define MUX_SEL_TOP_PERIC1 0x023c 46 #define MUX_ENABLE_TOP0 0x0300 47 #define MUX_ENABLE_TOP1 0x0304 48 #define MUX_ENABLE_TOP2 0x0308 49 #define MUX_ENABLE_TOP3 0x030c 50 #define MUX_ENABLE_TOP4 0x0310 51 #define MUX_ENABLE_TOP_MSCL 0x0320 52 #define MUX_ENABLE_TOP_CAM1 0x0324 53 #define MUX_ENABLE_TOP_DISP 0x0328 54 #define MUX_ENABLE_TOP_FSYS0 0x0330 55 #define MUX_ENABLE_TOP_FSYS1 0x0334 56 #define MUX_ENABLE_TOP_PERIC0 0x0338 57 #define MUX_ENABLE_TOP_PERIC1 0x033c 58 #define MUX_STAT_TOP0 0x0400 59 #define MUX_STAT_TOP1 0x0404 60 #define MUX_STAT_TOP2 0x0408 61 #define MUX_STAT_TOP3 0x040c 62 #define MUX_STAT_TOP4 0x0410 63 #define MUX_STAT_TOP_MSCL 0x0420 64 #define MUX_STAT_TOP_CAM1 0x0424 65 #define MUX_STAT_TOP_FSYS0 0x0430 66 #define MUX_STAT_TOP_FSYS1 0x0434 67 #define MUX_STAT_TOP_PERIC0 0x0438 68 #define MUX_STAT_TOP_PERIC1 0x043c 69 #define DIV_TOP0 0x0600 70 #define DIV_TOP1 0x0604 71 #define DIV_TOP2 0x0608 72 #define DIV_TOP3 0x060c 73 #define DIV_TOP4 0x0610 74 #define DIV_TOP_MSCL 0x0618 75 #define DIV_TOP_CAM10 0x061c 76 #define DIV_TOP_CAM11 0x0620 77 #define DIV_TOP_FSYS0 0x062c 78 #define DIV_TOP_FSYS1 0x0630 79 #define DIV_TOP_FSYS2 0x0634 80 #define DIV_TOP_PERIC0 0x0638 81 #define DIV_TOP_PERIC1 0x063c 82 #define DIV_TOP_PERIC2 0x0640 83 #define DIV_TOP_PERIC3 0x0644 84 #define DIV_TOP_PERIC4 0x0648 85 #define DIV_TOP_PLL_FREQ_DET 0x064c 86 #define DIV_STAT_TOP0 0x0700 87 #define DIV_STAT_TOP1 0x0704 88 #define DIV_STAT_TOP2 0x0708 89 #define DIV_STAT_TOP3 0x070c 90 #define DIV_STAT_TOP4 0x0710 91 #define DIV_STAT_TOP_MSCL 0x0718 92 #define DIV_STAT_TOP_CAM10 0x071c 93 #define DIV_STAT_TOP_CAM11 0x0720 94 #define DIV_STAT_TOP_FSYS0 0x072c 95 #define DIV_STAT_TOP_FSYS1 0x0730 96 #define DIV_STAT_TOP_FSYS2 0x0734 97 #define DIV_STAT_TOP_PERIC0 0x0738 98 #define DIV_STAT_TOP_PERIC1 0x073c 99 #define DIV_STAT_TOP_PERIC2 0x0740 100 #define DIV_STAT_TOP_PERIC3 0x0744 101 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c 102 #define ENABLE_ACLK_TOP 0x0800 103 #define ENABLE_SCLK_TOP 0x0a00 104 #define ENABLE_SCLK_TOP_MSCL 0x0a04 105 #define ENABLE_SCLK_TOP_CAM1 0x0a08 106 #define ENABLE_SCLK_TOP_DISP 0x0a0c 107 #define ENABLE_SCLK_TOP_FSYS 0x0a10 108 #define ENABLE_SCLK_TOP_PERIC 0x0a14 109 #define ENABLE_IP_TOP 0x0b00 110 #define ENABLE_CMU_TOP 0x0c00 111 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04 112 113 static const unsigned long top_clk_regs[] __initconst = { 114 ISP_PLL_LOCK, 115 AUD_PLL_LOCK, 116 ISP_PLL_CON0, 117 ISP_PLL_CON1, 118 ISP_PLL_FREQ_DET, 119 AUD_PLL_CON0, 120 AUD_PLL_CON1, 121 AUD_PLL_CON2, 122 AUD_PLL_FREQ_DET, 123 MUX_SEL_TOP0, 124 MUX_SEL_TOP1, 125 MUX_SEL_TOP2, 126 MUX_SEL_TOP3, 127 MUX_SEL_TOP4, 128 MUX_SEL_TOP_MSCL, 129 MUX_SEL_TOP_CAM1, 130 MUX_SEL_TOP_DISP, 131 MUX_SEL_TOP_FSYS0, 132 MUX_SEL_TOP_FSYS1, 133 MUX_SEL_TOP_PERIC0, 134 MUX_SEL_TOP_PERIC1, 135 MUX_ENABLE_TOP0, 136 MUX_ENABLE_TOP1, 137 MUX_ENABLE_TOP2, 138 MUX_ENABLE_TOP3, 139 MUX_ENABLE_TOP4, 140 MUX_ENABLE_TOP_MSCL, 141 MUX_ENABLE_TOP_CAM1, 142 MUX_ENABLE_TOP_DISP, 143 MUX_ENABLE_TOP_FSYS0, 144 MUX_ENABLE_TOP_FSYS1, 145 MUX_ENABLE_TOP_PERIC0, 146 MUX_ENABLE_TOP_PERIC1, 147 DIV_TOP0, 148 DIV_TOP1, 149 DIV_TOP2, 150 DIV_TOP3, 151 DIV_TOP4, 152 DIV_TOP_MSCL, 153 DIV_TOP_CAM10, 154 DIV_TOP_CAM11, 155 DIV_TOP_FSYS0, 156 DIV_TOP_FSYS1, 157 DIV_TOP_FSYS2, 158 DIV_TOP_PERIC0, 159 DIV_TOP_PERIC1, 160 DIV_TOP_PERIC2, 161 DIV_TOP_PERIC3, 162 DIV_TOP_PERIC4, 163 DIV_TOP_PLL_FREQ_DET, 164 ENABLE_ACLK_TOP, 165 ENABLE_SCLK_TOP, 166 ENABLE_SCLK_TOP_MSCL, 167 ENABLE_SCLK_TOP_CAM1, 168 ENABLE_SCLK_TOP_DISP, 169 ENABLE_SCLK_TOP_FSYS, 170 ENABLE_SCLK_TOP_PERIC, 171 ENABLE_IP_TOP, 172 ENABLE_CMU_TOP, 173 ENABLE_CMU_TOP_DIV_STAT, 174 }; 175 176 /* list of all parent clock list */ 177 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; 178 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; 179 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", }; 180 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", }; 181 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", }; 182 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", }; 183 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", }; 184 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", }; 185 186 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",}; 187 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",}; 188 PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a", 189 "mout_mfc_pll_user", }; 190 PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", }; 191 192 PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b", 193 "mout_mphy_pll_user", }; 194 PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a", 195 "mout_bus_pll_user", }; 196 PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", }; 197 198 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user", 199 "mout_mphy_pll_user", }; 200 PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a", 201 "mout_mphy_pll_user", }; 202 PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a", 203 "mout_mphy_pll_user", }; 204 205 PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",}; 206 PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", }; 207 208 PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",}; 209 PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",}; 210 PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", }; 211 PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",}; 212 PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", }; 213 214 PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1", 215 "oscclk", "ioclk_spdif_extclk", }; 216 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk", 217 "mout_aud_pll_user_t",}; 218 PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk", 219 "mout_aud_pll_user_t",}; 220 221 PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; 222 223 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = { 224 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), 225 }; 226 227 static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = { 228 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ 229 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000), 230 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000), 231 /* Xi2s1SDI input clock for SPDIF */ 232 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000), 233 /* XspiCLK[4:0] input clock for SPI */ 234 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000), 235 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000), 236 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000), 237 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000), 238 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000), 239 /* Xi2s1SCLK input clock for I2S1_BCLK */ 240 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000), 241 }; 242 243 static const struct samsung_mux_clock top_mux_clks[] __initconst = { 244 /* MUX_SEL_TOP0 */ 245 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, 246 4, 1), 247 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0, 248 0, 1), 249 250 /* MUX_SEL_TOP1 */ 251 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t", 252 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1), 253 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p, 254 MUX_SEL_TOP1, 8, 1), 255 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p, 256 MUX_SEL_TOP1, 4, 1), 257 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p, 258 MUX_SEL_TOP1, 0, 1), 259 260 /* MUX_SEL_TOP2 */ 261 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400", 262 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1), 263 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333", 264 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1), 265 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b", 266 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1), 267 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a", 268 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1), 269 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400", 270 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1), 271 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400", 272 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1), 273 274 /* MUX_SEL_TOP3 */ 275 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400", 276 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1), 277 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b", 278 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1), 279 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a", 280 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1), 281 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333", 282 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1), 283 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b", 284 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1), 285 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a", 286 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1), 287 288 /* MUX_SEL_TOP4 */ 289 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c", 290 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1), 291 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b", 292 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1), 293 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a", 294 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1), 295 296 /* MUX_SEL_TOP_MSCL */ 297 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p, 298 MUX_SEL_TOP_MSCL, 8, 1), 299 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p, 300 MUX_SEL_TOP_MSCL, 4, 1), 301 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p, 302 MUX_SEL_TOP_MSCL, 0, 1), 303 304 /* MUX_SEL_TOP_CAM1 */ 305 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2", 306 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1), 307 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1", 308 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1), 309 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0", 310 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1), 311 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart", 312 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1), 313 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1", 314 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1), 315 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0", 316 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1), 317 318 /* MUX_SEL_TOP_FSYS0 */ 319 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p, 320 MUX_SEL_TOP_FSYS0, 28, 1), 321 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p, 322 MUX_SEL_TOP_FSYS0, 24, 1), 323 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p, 324 MUX_SEL_TOP_FSYS0, 20, 1), 325 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p, 326 MUX_SEL_TOP_FSYS0, 16, 1), 327 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p, 328 MUX_SEL_TOP_FSYS0, 12, 1), 329 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p, 330 MUX_SEL_TOP_FSYS0, 8, 1), 331 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p, 332 MUX_SEL_TOP_FSYS0, 4, 1), 333 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p, 334 MUX_SEL_TOP_FSYS0, 0, 1), 335 336 /* MUX_SEL_TOP_FSYS1 */ 337 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p, 338 MUX_SEL_TOP_FSYS1, 12, 1), 339 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro", 340 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1), 341 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30", 342 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1), 343 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30", 344 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1), 345 346 /* MUX_SEL_TOP_PERIC0 */ 347 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p, 348 MUX_SEL_TOP_PERIC0, 28, 1), 349 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p, 350 MUX_SEL_TOP_PERIC0, 24, 1), 351 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p, 352 MUX_SEL_TOP_PERIC0, 20, 1), 353 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p, 354 MUX_SEL_TOP_PERIC0, 16, 1), 355 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p, 356 MUX_SEL_TOP_PERIC0, 12, 1), 357 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p, 358 MUX_SEL_TOP_PERIC0, 8, 1), 359 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p, 360 MUX_SEL_TOP_PERIC0, 4, 1), 361 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p, 362 MUX_SEL_TOP_PERIC0, 0, 1), 363 364 /* MUX_SEL_TOP_PERIC1 */ 365 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p, 366 MUX_SEL_TOP_PERIC1, 16, 1), 367 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p, 368 MUX_SEL_TOP_PERIC1, 12, 2), 369 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p, 370 MUX_SEL_TOP_PERIC1, 4, 2), 371 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p, 372 MUX_SEL_TOP_PERIC1, 0, 2), 373 374 /* MUX_SEL_TOP_DISP */ 375 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif", 376 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), 377 }; 378 379 static const struct samsung_div_clock top_div_clks[] __initconst = { 380 /* DIV_TOP0 */ 381 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333", 382 DIV_TOP0, 28, 3), 383 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user", 384 DIV_TOP0, 24, 3), 385 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b", 386 DIV_TOP0, 20, 3), 387 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user", 388 DIV_TOP0, 16, 3), 389 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user", 390 DIV_TOP0, 12, 3), 391 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll", 392 DIV_TOP0, 8, 3), 393 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400", 394 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4), 395 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400", 396 "mout_aclk_isp_400", DIV_TOP0, 0, 4), 397 398 /* DIV_TOP1 */ 399 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333", 400 DIV_TOP1, 28, 3), 401 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333", 402 DIV_TOP1, 24, 3), 403 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400", 404 DIV_TOP1, 20, 3), 405 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c", 406 DIV_TOP1, 12, 3), 407 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user", 408 DIV_TOP1, 8, 3), 409 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b", 410 DIV_TOP1, 0, 3), 411 412 /* DIV_TOP2 */ 413 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b", 414 DIV_TOP2, 4, 3), 415 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user", 416 DIV_TOP2, 0, 3), 417 418 /* DIV_TOP3 */ 419 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266", 420 "mout_bus_pll_user", DIV_TOP3, 24, 3), 421 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200", 422 "mout_bus_pll_user", DIV_TOP3, 20, 3), 423 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266", 424 "mout_bus_pll_user", DIV_TOP3, 16, 3), 425 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b", 426 "div_aclk_peric_66_a", DIV_TOP3, 12, 3), 427 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a", 428 "mout_bus_pll_user", DIV_TOP3, 8, 3), 429 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b", 430 "div_aclk_peris_66_a", DIV_TOP3, 4, 3), 431 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a", 432 "mout_bus_pll_user", DIV_TOP3, 0, 3), 433 434 /* DIV_TOP4 */ 435 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user", 436 DIV_TOP4, 8, 3), 437 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400", 438 DIV_TOP4, 4, 3), 439 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user", 440 DIV_TOP4, 0, 3), 441 442 /* DIV_TOP_MSCL */ 443 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c", 444 DIV_TOP_MSCL, 0, 4), 445 446 /* DIV_TOP_CAM10 */ 447 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart", 448 DIV_TOP_CAM10, 24, 5), 449 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b", 450 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8), 451 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a", 452 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4), 453 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b", 454 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8), 455 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a", 456 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4), 457 458 /* DIV_TOP_CAM11 */ 459 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b", 460 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4), 461 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a", 462 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4), 463 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b", 464 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4), 465 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a", 466 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4), 467 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b", 468 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4), 469 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a", 470 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4), 471 472 /* DIV_TOP_FSYS0 */ 473 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a", 474 DIV_TOP_FSYS0, 16, 8), 475 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b", 476 DIV_TOP_FSYS0, 12, 4), 477 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a", 478 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0), 479 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d", 480 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0), 481 482 /* DIV_TOP_FSYS1 */ 483 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a", 484 DIV_TOP_FSYS1, 4, 8), 485 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b", 486 DIV_TOP_FSYS1, 0, 4), 487 488 /* DIV_TOP_FSYS2 */ 489 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100", 490 DIV_TOP_FSYS2, 12, 3), 491 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30", 492 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4), 493 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro", 494 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4), 495 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30", 496 DIV_TOP_FSYS2, 0, 4), 497 498 /* DIV_TOP_PERIC0 */ 499 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a", 500 DIV_TOP_PERIC0, 16, 8), 501 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1", 502 DIV_TOP_PERIC0, 12, 4), 503 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a", 504 DIV_TOP_PERIC0, 4, 8), 505 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0", 506 DIV_TOP_PERIC0, 0, 4), 507 508 /* DIV_TOP_PERIC1 */ 509 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a", 510 DIV_TOP_PERIC1, 4, 8), 511 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2", 512 DIV_TOP_PERIC1, 0, 4), 513 514 /* DIV_TOP_PERIC2 */ 515 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2", 516 DIV_TOP_PERIC2, 8, 4), 517 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0", 518 DIV_TOP_PERIC2, 4, 4), 519 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1", 520 DIV_TOP_PERIC2, 0, 4), 521 522 /* DIV_TOP_PERIC3 */ 523 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1", 524 DIV_TOP_PERIC3, 16, 6), 525 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1", 526 DIV_TOP_PERIC3, 8, 8), 527 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1", 528 DIV_TOP_PERIC3, 4, 4), 529 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0", 530 DIV_TOP_PERIC3, 0, 4), 531 532 /* DIV_TOP_PERIC4 */ 533 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a", 534 DIV_TOP_PERIC4, 16, 8), 535 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4", 536 DIV_TOP_PERIC4, 12, 4), 537 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a", 538 DIV_TOP_PERIC4, 4, 8), 539 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3", 540 DIV_TOP_PERIC4, 0, 4), 541 }; 542 543 static const struct samsung_gate_clock top_gate_clks[] __initconst = { 544 /* ENABLE_ACLK_TOP */ 545 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", 546 ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0), 547 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266", 548 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP, 549 29, CLK_IGNORE_UNUSED, 0), 550 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400", 551 ENABLE_ACLK_TOP, 26, 552 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 553 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400", 554 ENABLE_ACLK_TOP, 25, 555 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 556 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266", 557 ENABLE_ACLK_TOP, 24, 558 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 559 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200", 560 ENABLE_ACLK_TOP, 23, 561 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 562 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b", 563 ENABLE_ACLK_TOP, 22, 564 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 565 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b", 566 ENABLE_ACLK_TOP, 21, 567 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 568 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400", 569 ENABLE_ACLK_TOP, 19, 570 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 571 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200", 572 ENABLE_ACLK_TOP, 18, 573 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 574 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111", 575 ENABLE_ACLK_TOP, 15, 576 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 577 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333", 578 ENABLE_ACLK_TOP, 14, 579 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 580 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333", 581 ENABLE_ACLK_TOP, 13, 582 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 583 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400", 584 ENABLE_ACLK_TOP, 12, 585 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 586 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552", 587 ENABLE_ACLK_TOP, 11, 588 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 589 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333", 590 ENABLE_ACLK_TOP, 10, 591 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 592 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400", 593 ENABLE_ACLK_TOP, 9, 594 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 595 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552", 596 ENABLE_ACLK_TOP, 8, 597 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 598 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400", 599 ENABLE_ACLK_TOP, 7, 600 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 601 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400", 602 ENABLE_ACLK_TOP, 6, 603 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 604 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400", 605 ENABLE_ACLK_TOP, 5, 606 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 607 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400", 608 ENABLE_ACLK_TOP, 3, 609 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 610 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266", 611 ENABLE_ACLK_TOP, 2, 612 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 613 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400", 614 ENABLE_ACLK_TOP, 0, 615 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), 616 617 /* ENABLE_SCLK_TOP_MSCL */ 618 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg", 619 ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0), 620 621 /* ENABLE_SCLK_TOP_CAM1 */ 622 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b", 623 ENABLE_SCLK_TOP_CAM1, 7, 0, 0), 624 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b", 625 ENABLE_SCLK_TOP_CAM1, 6, 0, 0), 626 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b", 627 ENABLE_SCLK_TOP_CAM1, 5, 0, 0), 628 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk", 629 ENABLE_SCLK_TOP_CAM1, 4, 0, 0), 630 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart", 631 ENABLE_SCLK_TOP_CAM1, 2, 0, 0), 632 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b", 633 ENABLE_SCLK_TOP_CAM1, 1, 0, 0), 634 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b", 635 ENABLE_SCLK_TOP_CAM1, 0, 0, 0), 636 637 /* ENABLE_SCLK_TOP_DISP */ 638 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp", 639 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0, 640 CLK_IGNORE_UNUSED, 0), 641 642 /* ENABLE_SCLK_TOP_FSYS */ 643 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100", 644 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0), 645 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", 646 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), 647 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", 648 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0), 649 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b", 650 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0), 651 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys", 652 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS, 653 3, CLK_SET_RATE_PARENT, 0), 654 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys", 655 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS, 656 1, CLK_SET_RATE_PARENT, 0), 657 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys", 658 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS, 659 0, CLK_SET_RATE_PARENT, 0), 660 661 /* ENABLE_SCLK_TOP_PERIC */ 662 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b", 663 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0), 664 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b", 665 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0), 666 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif", 667 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0), 668 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1", 669 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0), 670 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1", 671 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0), 672 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2", 673 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT | 674 CLK_IGNORE_UNUSED, 0), 675 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1", 676 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT | 677 CLK_IGNORE_UNUSED, 0), 678 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0", 679 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT | 680 CLK_IGNORE_UNUSED, 0), 681 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b", 682 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0), 683 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b", 684 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0), 685 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b", 686 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0), 687 688 /* MUX_ENABLE_TOP_PERIC1 */ 689 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus", 690 MUX_ENABLE_TOP_PERIC1, 16, 0, 0), 691 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1", 692 MUX_ENABLE_TOP_PERIC1, 4, 0, 0), 693 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0", 694 MUX_ENABLE_TOP_PERIC1, 0, 0, 0), 695 }; 696 697 /* 698 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL 699 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL 700 */ 701 static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = { 702 PLL_35XX_RATE(2500000000U, 625, 6, 0), 703 PLL_35XX_RATE(2400000000U, 500, 5, 0), 704 PLL_35XX_RATE(2300000000U, 575, 6, 0), 705 PLL_35XX_RATE(2200000000U, 550, 6, 0), 706 PLL_35XX_RATE(2100000000U, 350, 4, 0), 707 PLL_35XX_RATE(2000000000U, 500, 6, 0), 708 PLL_35XX_RATE(1900000000U, 475, 6, 0), 709 PLL_35XX_RATE(1800000000U, 375, 5, 0), 710 PLL_35XX_RATE(1700000000U, 425, 6, 0), 711 PLL_35XX_RATE(1600000000U, 400, 6, 0), 712 PLL_35XX_RATE(1500000000U, 250, 4, 0), 713 PLL_35XX_RATE(1400000000U, 350, 6, 0), 714 PLL_35XX_RATE(1332000000U, 222, 4, 0), 715 PLL_35XX_RATE(1300000000U, 325, 6, 0), 716 PLL_35XX_RATE(1200000000U, 500, 5, 1), 717 PLL_35XX_RATE(1100000000U, 550, 6, 1), 718 PLL_35XX_RATE(1086000000U, 362, 4, 1), 719 PLL_35XX_RATE(1066000000U, 533, 6, 1), 720 PLL_35XX_RATE(1000000000U, 500, 6, 1), 721 PLL_35XX_RATE(933000000U, 311, 4, 1), 722 PLL_35XX_RATE(921000000U, 307, 4, 1), 723 PLL_35XX_RATE(900000000U, 375, 5, 1), 724 PLL_35XX_RATE(825000000U, 275, 4, 1), 725 PLL_35XX_RATE(800000000U, 400, 6, 1), 726 PLL_35XX_RATE(733000000U, 733, 12, 1), 727 PLL_35XX_RATE(700000000U, 175, 3, 1), 728 PLL_35XX_RATE(667000000U, 222, 4, 1), 729 PLL_35XX_RATE(633000000U, 211, 4, 1), 730 PLL_35XX_RATE(600000000U, 500, 5, 2), 731 PLL_35XX_RATE(552000000U, 460, 5, 2), 732 PLL_35XX_RATE(550000000U, 550, 6, 2), 733 PLL_35XX_RATE(543000000U, 362, 4, 2), 734 PLL_35XX_RATE(533000000U, 533, 6, 2), 735 PLL_35XX_RATE(500000000U, 500, 6, 2), 736 PLL_35XX_RATE(444000000U, 370, 5, 2), 737 PLL_35XX_RATE(420000000U, 350, 5, 2), 738 PLL_35XX_RATE(400000000U, 400, 6, 2), 739 PLL_35XX_RATE(350000000U, 350, 6, 2), 740 PLL_35XX_RATE(333000000U, 222, 4, 2), 741 PLL_35XX_RATE(300000000U, 500, 5, 3), 742 PLL_35XX_RATE(278000000U, 556, 6, 3), 743 PLL_35XX_RATE(266000000U, 532, 6, 3), 744 PLL_35XX_RATE(250000000U, 500, 6, 3), 745 PLL_35XX_RATE(200000000U, 400, 6, 3), 746 PLL_35XX_RATE(166000000U, 332, 6, 3), 747 PLL_35XX_RATE(160000000U, 320, 6, 3), 748 PLL_35XX_RATE(133000000U, 532, 6, 4), 749 PLL_35XX_RATE(100000000U, 400, 6, 4), 750 { /* sentinel */ } 751 }; 752 753 /* AUD_PLL */ 754 static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = { 755 PLL_36XX_RATE(400000000U, 200, 3, 2, 0), 756 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), 757 PLL_36XX_RATE(384000000U, 128, 2, 2, 0), 758 PLL_36XX_RATE(368640000U, 246, 4, 2, -15729), 759 PLL_36XX_RATE(361507200U, 181, 3, 2, -16148), 760 PLL_36XX_RATE(338688000U, 113, 2, 2, -6816), 761 PLL_36XX_RATE(294912000U, 98, 1, 3, 19923), 762 PLL_36XX_RATE(288000000U, 96, 1, 3, 0), 763 PLL_36XX_RATE(252000000U, 84, 1, 3, 0), 764 { /* sentinel */ } 765 }; 766 767 static const struct samsung_pll_clock top_pll_clks[] __initconst = { 768 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", 769 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates), 770 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 771 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates), 772 }; 773 774 static const struct samsung_cmu_info top_cmu_info __initconst = { 775 .pll_clks = top_pll_clks, 776 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 777 .mux_clks = top_mux_clks, 778 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 779 .div_clks = top_div_clks, 780 .nr_div_clks = ARRAY_SIZE(top_div_clks), 781 .gate_clks = top_gate_clks, 782 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 783 .fixed_clks = top_fixed_clks, 784 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks), 785 .fixed_factor_clks = top_fixed_factor_clks, 786 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), 787 .nr_clk_ids = TOP_NR_CLK, 788 .clk_regs = top_clk_regs, 789 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 790 }; 791 792 static void __init exynos5433_cmu_top_init(struct device_node *np) 793 { 794 samsung_cmu_register_one(np, &top_cmu_info); 795 } 796 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", 797 exynos5433_cmu_top_init); 798 799 /* 800 * Register offset definitions for CMU_CPIF 801 */ 802 #define MPHY_PLL_LOCK 0x0000 803 #define MPHY_PLL_CON0 0x0100 804 #define MPHY_PLL_CON1 0x0104 805 #define MPHY_PLL_FREQ_DET 0x010c 806 #define MUX_SEL_CPIF0 0x0200 807 #define DIV_CPIF 0x0600 808 #define ENABLE_SCLK_CPIF 0x0a00 809 810 static const unsigned long cpif_clk_regs[] __initconst = { 811 MPHY_PLL_LOCK, 812 MPHY_PLL_CON0, 813 MPHY_PLL_CON1, 814 MPHY_PLL_FREQ_DET, 815 MUX_SEL_CPIF0, 816 DIV_CPIF, 817 ENABLE_SCLK_CPIF, 818 }; 819 820 /* list of all parent clock list */ 821 PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; 822 823 static const struct samsung_pll_clock cpif_pll_clks[] __initconst = { 824 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", 825 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates), 826 }; 827 828 static const struct samsung_mux_clock cpif_mux_clks[] __initconst = { 829 /* MUX_SEL_CPIF0 */ 830 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, 831 0, 1), 832 }; 833 834 static const struct samsung_div_clock cpif_div_clks[] __initconst = { 835 /* DIV_CPIF */ 836 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, 837 0, 6), 838 }; 839 840 static const struct samsung_gate_clock cpif_gate_clks[] __initconst = { 841 /* ENABLE_SCLK_CPIF */ 842 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", 843 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0), 844 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy", 845 ENABLE_SCLK_CPIF, 4, 0, 0), 846 }; 847 848 static const struct samsung_cmu_info cpif_cmu_info __initconst = { 849 .pll_clks = cpif_pll_clks, 850 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), 851 .mux_clks = cpif_mux_clks, 852 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks), 853 .div_clks = cpif_div_clks, 854 .nr_div_clks = ARRAY_SIZE(cpif_div_clks), 855 .gate_clks = cpif_gate_clks, 856 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks), 857 .nr_clk_ids = CPIF_NR_CLK, 858 .clk_regs = cpif_clk_regs, 859 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), 860 }; 861 862 static void __init exynos5433_cmu_cpif_init(struct device_node *np) 863 { 864 samsung_cmu_register_one(np, &cpif_cmu_info); 865 } 866 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", 867 exynos5433_cmu_cpif_init); 868 869 /* 870 * Register offset definitions for CMU_MIF 871 */ 872 #define MEM0_PLL_LOCK 0x0000 873 #define MEM1_PLL_LOCK 0x0004 874 #define BUS_PLL_LOCK 0x0008 875 #define MFC_PLL_LOCK 0x000c 876 #define MEM0_PLL_CON0 0x0100 877 #define MEM0_PLL_CON1 0x0104 878 #define MEM0_PLL_FREQ_DET 0x010c 879 #define MEM1_PLL_CON0 0x0110 880 #define MEM1_PLL_CON1 0x0114 881 #define MEM1_PLL_FREQ_DET 0x011c 882 #define BUS_PLL_CON0 0x0120 883 #define BUS_PLL_CON1 0x0124 884 #define BUS_PLL_FREQ_DET 0x012c 885 #define MFC_PLL_CON0 0x0130 886 #define MFC_PLL_CON1 0x0134 887 #define MFC_PLL_FREQ_DET 0x013c 888 #define MUX_SEL_MIF0 0x0200 889 #define MUX_SEL_MIF1 0x0204 890 #define MUX_SEL_MIF2 0x0208 891 #define MUX_SEL_MIF3 0x020c 892 #define MUX_SEL_MIF4 0x0210 893 #define MUX_SEL_MIF5 0x0214 894 #define MUX_SEL_MIF6 0x0218 895 #define MUX_SEL_MIF7 0x021c 896 #define MUX_ENABLE_MIF0 0x0300 897 #define MUX_ENABLE_MIF1 0x0304 898 #define MUX_ENABLE_MIF2 0x0308 899 #define MUX_ENABLE_MIF3 0x030c 900 #define MUX_ENABLE_MIF4 0x0310 901 #define MUX_ENABLE_MIF5 0x0314 902 #define MUX_ENABLE_MIF6 0x0318 903 #define MUX_ENABLE_MIF7 0x031c 904 #define MUX_STAT_MIF0 0x0400 905 #define MUX_STAT_MIF1 0x0404 906 #define MUX_STAT_MIF2 0x0408 907 #define MUX_STAT_MIF3 0x040c 908 #define MUX_STAT_MIF4 0x0410 909 #define MUX_STAT_MIF5 0x0414 910 #define MUX_STAT_MIF6 0x0418 911 #define MUX_STAT_MIF7 0x041c 912 #define DIV_MIF1 0x0604 913 #define DIV_MIF2 0x0608 914 #define DIV_MIF3 0x060c 915 #define DIV_MIF4 0x0610 916 #define DIV_MIF5 0x0614 917 #define DIV_MIF_PLL_FREQ_DET 0x0618 918 #define DIV_STAT_MIF1 0x0704 919 #define DIV_STAT_MIF2 0x0708 920 #define DIV_STAT_MIF3 0x070c 921 #define DIV_STAT_MIF4 0x0710 922 #define DIV_STAT_MIF5 0x0714 923 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718 924 #define ENABLE_ACLK_MIF0 0x0800 925 #define ENABLE_ACLK_MIF1 0x0804 926 #define ENABLE_ACLK_MIF2 0x0808 927 #define ENABLE_ACLK_MIF3 0x080c 928 #define ENABLE_PCLK_MIF 0x0900 929 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904 930 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908 931 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c 932 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910 933 #define ENABLE_SCLK_MIF 0x0a00 934 #define ENABLE_IP_MIF0 0x0b00 935 #define ENABLE_IP_MIF1 0x0b04 936 #define ENABLE_IP_MIF2 0x0b08 937 #define ENABLE_IP_MIF3 0x0b0c 938 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10 939 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14 940 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18 941 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c 942 #define CLKOUT_CMU_MIF 0x0c00 943 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 944 #define DREX_FREQ_CTRL0 0x1000 945 #define DREX_FREQ_CTRL1 0x1004 946 #define PAUSE 0x1008 947 #define DDRPHY_LOCK_CTRL 0x100c 948 949 static const unsigned long mif_clk_regs[] __initconst = { 950 MEM0_PLL_LOCK, 951 MEM1_PLL_LOCK, 952 BUS_PLL_LOCK, 953 MFC_PLL_LOCK, 954 MEM0_PLL_CON0, 955 MEM0_PLL_CON1, 956 MEM0_PLL_FREQ_DET, 957 MEM1_PLL_CON0, 958 MEM1_PLL_CON1, 959 MEM1_PLL_FREQ_DET, 960 BUS_PLL_CON0, 961 BUS_PLL_CON1, 962 BUS_PLL_FREQ_DET, 963 MFC_PLL_CON0, 964 MFC_PLL_CON1, 965 MFC_PLL_FREQ_DET, 966 MUX_SEL_MIF0, 967 MUX_SEL_MIF1, 968 MUX_SEL_MIF2, 969 MUX_SEL_MIF3, 970 MUX_SEL_MIF4, 971 MUX_SEL_MIF5, 972 MUX_SEL_MIF6, 973 MUX_SEL_MIF7, 974 MUX_ENABLE_MIF0, 975 MUX_ENABLE_MIF1, 976 MUX_ENABLE_MIF2, 977 MUX_ENABLE_MIF3, 978 MUX_ENABLE_MIF4, 979 MUX_ENABLE_MIF5, 980 MUX_ENABLE_MIF6, 981 MUX_ENABLE_MIF7, 982 DIV_MIF1, 983 DIV_MIF2, 984 DIV_MIF3, 985 DIV_MIF4, 986 DIV_MIF5, 987 DIV_MIF_PLL_FREQ_DET, 988 ENABLE_ACLK_MIF0, 989 ENABLE_ACLK_MIF1, 990 ENABLE_ACLK_MIF2, 991 ENABLE_ACLK_MIF3, 992 ENABLE_PCLK_MIF, 993 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 994 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 995 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 996 ENABLE_PCLK_MIF_SECURE_RTC, 997 ENABLE_SCLK_MIF, 998 ENABLE_IP_MIF0, 999 ENABLE_IP_MIF1, 1000 ENABLE_IP_MIF2, 1001 ENABLE_IP_MIF3, 1002 ENABLE_IP_MIF_SECURE_DREX0_TZ, 1003 ENABLE_IP_MIF_SECURE_DREX1_TZ, 1004 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT, 1005 ENABLE_IP_MIF_SECURE_RTC, 1006 CLKOUT_CMU_MIF, 1007 CLKOUT_CMU_MIF_DIV_STAT, 1008 DREX_FREQ_CTRL0, 1009 DREX_FREQ_CTRL1, 1010 PAUSE, 1011 DDRPHY_LOCK_CTRL, 1012 }; 1013 1014 static const struct samsung_pll_clock mif_pll_clks[] __initconst = { 1015 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", 1016 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates), 1017 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", 1018 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates), 1019 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk", 1020 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates), 1021 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk", 1022 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates), 1023 }; 1024 1025 /* list of all parent clock list */ 1026 PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", }; 1027 PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", }; 1028 PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", }; 1029 PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", }; 1030 PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", }; 1031 PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", }; 1032 PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", }; 1033 PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", }; 1034 1035 PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", }; 1036 PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", }; 1037 PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", }; 1038 PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", }; 1039 1040 PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", }; 1041 PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",}; 1042 1043 PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a", 1044 "mout_bus_pll_div2", }; 1045 PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", }; 1046 1047 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b", 1048 "sclk_mphy_pll", }; 1049 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a", 1050 "mout_mfc_pll_div2", }; 1051 PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", }; 1052 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b", 1053 "sclk_mphy_pll", }; 1054 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a", 1055 "mout_mfc_pll_div2", }; 1056 1057 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b", 1058 "sclk_mphy_pll", }; 1059 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a", 1060 "mout_mfc_pll_div2", }; 1061 PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", }; 1062 PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", }; 1063 PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", }; 1064 1065 PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", }; 1066 PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" }; 1067 1068 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b", 1069 "sclk_mphy_pll", }; 1070 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a", 1071 "mout_mfc_pll_div2", }; 1072 PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; 1073 PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; 1074 1075 static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = { 1076 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ 1077 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), 1078 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), 1079 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0), 1080 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), 1081 }; 1082 1083 static const struct samsung_mux_clock mif_mux_clks[] __initconst = { 1084 /* MUX_SEL_MIF0 */ 1085 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, 1086 MUX_SEL_MIF0, 28, 1), 1087 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p, 1088 MUX_SEL_MIF0, 24, 1), 1089 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p, 1090 MUX_SEL_MIF0, 20, 1), 1091 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p, 1092 MUX_SEL_MIF0, 16, 1), 1093 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0, 1094 12, 1), 1095 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0, 1096 8, 1), 1097 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0, 1098 4, 1), 1099 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0, 1100 0, 1), 1101 1102 /* MUX_SEL_MIF1 */ 1103 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p, 1104 MUX_SEL_MIF1, 24, 1), 1105 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p, 1106 MUX_SEL_MIF1, 20, 1), 1107 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p, 1108 MUX_SEL_MIF1, 16, 1), 1109 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p, 1110 MUX_SEL_MIF1, 12, 1), 1111 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p, 1112 MUX_SEL_MIF1, 8, 1), 1113 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p, 1114 MUX_SEL_MIF1, 4, 1), 1115 1116 /* MUX_SEL_MIF2 */ 1117 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200", 1118 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1), 1119 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400", 1120 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1), 1121 1122 /* MUX_SEL_MIF3 */ 1123 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b", 1124 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1), 1125 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a", 1126 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1), 1127 1128 /* MUX_SEL_MIF4 */ 1129 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c", 1130 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1), 1131 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b", 1132 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1), 1133 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a", 1134 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1), 1135 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c", 1136 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1), 1137 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b", 1138 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1), 1139 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a", 1140 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1), 1141 1142 /* MUX_SEL_MIF5 */ 1143 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c", 1144 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1), 1145 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b", 1146 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1), 1147 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a", 1148 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1), 1149 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p, 1150 MUX_SEL_MIF5, 8, 1), 1151 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p, 1152 MUX_SEL_MIF5, 4, 1), 1153 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p, 1154 MUX_SEL_MIF5, 0, 1), 1155 1156 /* MUX_SEL_MIF6 */ 1157 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p, 1158 MUX_SEL_MIF6, 8, 1), 1159 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p, 1160 MUX_SEL_MIF6, 4, 1), 1161 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p, 1162 MUX_SEL_MIF6, 0, 1), 1163 1164 /* MUX_SEL_MIF7 */ 1165 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c", 1166 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1), 1167 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b", 1168 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1), 1169 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a", 1170 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1), 1171 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p, 1172 MUX_SEL_MIF7, 8, 1), 1173 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p, 1174 MUX_SEL_MIF7, 4, 1), 1175 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p, 1176 MUX_SEL_MIF7, 0, 1), 1177 }; 1178 1179 static const struct samsung_div_clock mif_div_clks[] __initconst = { 1180 /* DIV_MIF1 */ 1181 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", 1182 DIV_MIF1, 16, 2), 1183 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1, 1184 12, 2), 1185 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1, 1186 8, 2), 1187 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1, 1188 4, 4), 1189 1190 /* DIV_MIF2 */ 1191 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2", 1192 DIV_MIF2, 20, 3), 1193 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre", 1194 DIV_MIF2, 16, 4), 1195 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre", 1196 DIV_MIF2, 12, 4), 1197 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200", 1198 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3), 1199 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400", 1200 DIV_MIF2, 4, 2), 1201 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400", 1202 DIV_MIF2, 0, 3), 1203 1204 /* DIV_MIF3 */ 1205 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre", 1206 DIV_MIF3, 16, 4), 1207 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b", 1208 DIV_MIF3, 4, 3), 1209 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200", 1210 DIV_MIF3, 0, 3), 1211 1212 /* DIV_MIF4 */ 1213 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c", 1214 DIV_MIF4, 24, 4), 1215 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk", 1216 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4), 1217 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c", 1218 DIV_MIF4, 16, 4), 1219 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c", 1220 DIV_MIF4, 12, 4), 1221 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk", 1222 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4), 1223 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk", 1224 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4), 1225 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk", 1226 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4), 1227 1228 /* DIV_MIF5 */ 1229 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5, 1230 0, 3), 1231 }; 1232 1233 static const struct samsung_gate_clock mif_gate_clks[] __initconst = { 1234 /* ENABLE_ACLK_MIF0 */ 1235 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1236 19, CLK_IGNORE_UNUSED, 0), 1237 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1238 18, CLK_IGNORE_UNUSED, 0), 1239 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, 1240 17, CLK_IGNORE_UNUSED, 0), 1241 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, 1242 16, CLK_IGNORE_UNUSED, 0), 1243 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0, 1244 15, CLK_IGNORE_UNUSED, 0), 1245 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0, 1246 14, CLK_IGNORE_UNUSED, 0), 1247 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1", 1248 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0), 1249 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0", 1250 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0), 1251 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1", 1252 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0), 1253 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0", 1254 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0), 1255 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1", 1256 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0), 1257 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0", 1258 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0), 1259 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1", 1260 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0), 1261 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0", 1262 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0), 1263 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1", 1264 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0), 1265 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0", 1266 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0), 1267 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1", 1268 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0), 1269 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0", 1270 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), 1271 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1", 1272 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), 1273 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0", 1274 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0), 1275 1276 /* ENABLE_ACLK_MIF1 */ 1277 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem", 1278 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28, 1279 CLK_IGNORE_UNUSED, 0), 1280 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci", 1281 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 1282 27, CLK_IGNORE_UNUSED, 0), 1283 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci", 1284 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1285 26, CLK_IGNORE_UNUSED, 0), 1286 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1", 1287 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, 1288 25, CLK_IGNORE_UNUSED, 0), 1289 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1", 1290 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1291 24, CLK_IGNORE_UNUSED, 0), 1292 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0", 1293 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, 1294 23, CLK_IGNORE_UNUSED, 0), 1295 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0", 1296 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1297 22, CLK_IGNORE_UNUSED, 0), 1298 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3", 1299 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1300 21, CLK_IGNORE_UNUSED, 0), 1301 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3", 1302 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1303 20, CLK_IGNORE_UNUSED, 0), 1304 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1", 1305 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1306 19, CLK_IGNORE_UNUSED, 0), 1307 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1", 1308 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1309 18, CLK_IGNORE_UNUSED, 0), 1310 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0", 1311 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1312 17, CLK_IGNORE_UNUSED, 0), 1313 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0", 1314 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1315 16, CLK_IGNORE_UNUSED, 0), 1316 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3", 1317 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1318 15, CLK_IGNORE_UNUSED, 0), 1319 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3", 1320 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1321 14, CLK_IGNORE_UNUSED, 0), 1322 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1", 1323 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1324 13, CLK_IGNORE_UNUSED, 0), 1325 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1", 1326 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1327 12, CLK_IGNORE_UNUSED, 0), 1328 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0", 1329 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1330 11, CLK_IGNORE_UNUSED, 0), 1331 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0", 1332 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1333 10, CLK_IGNORE_UNUSED, 0), 1334 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133", 1335 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0), 1336 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133", 1337 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0), 1338 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133", 1339 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0), 1340 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400", 1341 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0), 1342 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200", 1343 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0), 1344 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133", 1345 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0), 1346 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200", 1347 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0), 1348 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133", 1349 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0), 1350 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400", 1351 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0), 1352 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1, 1353 0, CLK_IGNORE_UNUSED, 0), 1354 1355 /* ENABLE_ACLK_MIF2 */ 1356 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266", 1357 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0), 1358 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1", 1359 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0), 1360 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1", 1361 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0), 1362 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1", 1363 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0), 1364 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0", 1365 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0), 1366 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0", 1367 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0), 1368 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0", 1369 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0), 1370 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx", 1371 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7, 1372 CLK_IGNORE_UNUSED, 0), 1373 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci", 1374 "div_aclk_mif_400", ENABLE_ACLK_MIF2, 1375 5, CLK_IGNORE_UNUSED, 0), 1376 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400", 1377 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0), 1378 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d", 1379 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 1380 3, CLK_IGNORE_UNUSED, 0), 1381 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys", 1382 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0), 1383 1384 /* ENABLE_ACLK_MIF3 */ 1385 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400", 1386 ENABLE_ACLK_MIF3, 4, 1387 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 1388 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333", 1389 ENABLE_ACLK_MIF3, 1, 1390 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 1391 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200", 1392 ENABLE_ACLK_MIF3, 0, 1393 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1394 1395 /* ENABLE_PCLK_MIF */ 1396 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1", 1397 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0), 1398 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1", 1399 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0), 1400 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1", 1401 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0), 1402 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0", 1403 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0), 1404 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0", 1405 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0), 1406 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0", 1407 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0), 1408 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci", 1409 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21, 1410 CLK_IGNORE_UNUSED, 0), 1411 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133", 1412 ENABLE_PCLK_MIF, 19, 0, 0), 1413 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133", 1414 ENABLE_PCLK_MIF, 18, 0, 0), 1415 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3", 1416 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0), 1417 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1", 1418 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0), 1419 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0", 1420 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0), 1421 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3", 1422 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0), 1423 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1", 1424 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0), 1425 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0", 1426 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0), 1427 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133", 1428 ENABLE_PCLK_MIF, 11, 0, 0), 1429 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133", 1430 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0), 1431 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133", 1432 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), 1433 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133", 1434 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), 1435 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133", 1436 ENABLE_PCLK_MIF, 7, 0, 0), 1437 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133", 1438 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0), 1439 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133", 1440 ENABLE_PCLK_MIF, 5, 0, 0), 1441 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133", 1442 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), 1443 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133", 1444 ENABLE_PCLK_MIF, 2, 0, 0), 1445 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133", 1446 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1447 1448 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ 1449 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133", 1450 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 1451 CLK_IGNORE_UNUSED, 0), 1452 1453 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ 1454 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133", 1455 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 1456 CLK_IGNORE_UNUSED, 0), 1457 1458 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ 1459 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", 1460 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0), 1461 1462 /* ENABLE_PCLK_MIF_SECURE_RTC */ 1463 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133", 1464 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), 1465 1466 /* ENABLE_SCLK_MIF */ 1467 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1", 1468 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0), 1469 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp", 1470 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, 1471 14, CLK_IGNORE_UNUSED, 0), 1472 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0", 1473 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), 1474 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd", 1475 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), 1476 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp", 1477 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, 1478 7, CLK_IGNORE_UNUSED, 0), 1479 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp", 1480 "div_sclk_decon_vclk", ENABLE_SCLK_MIF, 1481 6, CLK_IGNORE_UNUSED, 0), 1482 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp", 1483 "div_sclk_decon_eclk", ENABLE_SCLK_MIF, 1484 5, CLK_IGNORE_UNUSED, 0), 1485 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif", 1486 ENABLE_SCLK_MIF, 4, 1487 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1488 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2", 1489 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), 1490 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2", 1491 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0), 1492 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll", 1493 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0), 1494 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll", 1495 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1496 }; 1497 1498 static const struct samsung_cmu_info mif_cmu_info __initconst = { 1499 .pll_clks = mif_pll_clks, 1500 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), 1501 .mux_clks = mif_mux_clks, 1502 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks), 1503 .div_clks = mif_div_clks, 1504 .nr_div_clks = ARRAY_SIZE(mif_div_clks), 1505 .gate_clks = mif_gate_clks, 1506 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), 1507 .fixed_factor_clks = mif_fixed_factor_clks, 1508 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks), 1509 .nr_clk_ids = MIF_NR_CLK, 1510 .clk_regs = mif_clk_regs, 1511 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), 1512 }; 1513 1514 static void __init exynos5433_cmu_mif_init(struct device_node *np) 1515 { 1516 samsung_cmu_register_one(np, &mif_cmu_info); 1517 } 1518 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", 1519 exynos5433_cmu_mif_init); 1520 1521 /* 1522 * Register offset definitions for CMU_PERIC 1523 */ 1524 #define DIV_PERIC 0x0600 1525 #define DIV_STAT_PERIC 0x0700 1526 #define ENABLE_ACLK_PERIC 0x0800 1527 #define ENABLE_PCLK_PERIC0 0x0900 1528 #define ENABLE_PCLK_PERIC1 0x0904 1529 #define ENABLE_SCLK_PERIC 0x0A00 1530 #define ENABLE_IP_PERIC0 0x0B00 1531 #define ENABLE_IP_PERIC1 0x0B04 1532 #define ENABLE_IP_PERIC2 0x0B08 1533 1534 static const unsigned long peric_clk_regs[] __initconst = { 1535 DIV_PERIC, 1536 ENABLE_ACLK_PERIC, 1537 ENABLE_PCLK_PERIC0, 1538 ENABLE_PCLK_PERIC1, 1539 ENABLE_SCLK_PERIC, 1540 ENABLE_IP_PERIC0, 1541 ENABLE_IP_PERIC1, 1542 ENABLE_IP_PERIC2, 1543 }; 1544 1545 static const struct samsung_div_clock peric_div_clks[] __initconst = { 1546 /* DIV_PERIC */ 1547 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), 1548 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), 1549 }; 1550 1551 static const struct samsung_gate_clock peric_gate_clks[] __initconst = { 1552 /* ENABLE_ACLK_PERIC */ 1553 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", 1554 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), 1555 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66", 1556 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0), 1557 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66", 1558 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0), 1559 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66", 1560 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0), 1561 1562 /* ENABLE_PCLK_PERIC0 */ 1563 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1564 31, CLK_SET_RATE_PARENT, 0), 1565 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66", 1566 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0), 1567 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66", 1568 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0), 1569 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1570 28, CLK_SET_RATE_PARENT, 0), 1571 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1572 26, CLK_SET_RATE_PARENT, 0), 1573 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1574 25, CLK_SET_RATE_PARENT, 0), 1575 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1576 24, CLK_SET_RATE_PARENT, 0), 1577 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1578 23, CLK_SET_RATE_PARENT, 0), 1579 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1580 22, CLK_SET_RATE_PARENT, 0), 1581 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1582 21, CLK_SET_RATE_PARENT, 0), 1583 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1584 20, CLK_SET_RATE_PARENT, 0), 1585 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66", 1586 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0), 1587 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66", 1588 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0), 1589 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66", 1590 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0), 1591 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66", 1592 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0), 1593 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66", 1594 ENABLE_PCLK_PERIC0, 15, 1595 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1596 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1597 14, CLK_SET_RATE_PARENT, 0), 1598 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1599 13, CLK_SET_RATE_PARENT, 0), 1600 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1601 12, CLK_SET_RATE_PARENT, 0), 1602 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66", 1603 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0), 1604 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66", 1605 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0), 1606 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66", 1607 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0), 1608 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66", 1609 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 1610 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1611 7, CLK_SET_RATE_PARENT, 0), 1612 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1613 6, CLK_SET_RATE_PARENT, 0), 1614 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1615 5, CLK_SET_RATE_PARENT, 0), 1616 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1617 4, CLK_SET_RATE_PARENT, 0), 1618 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1619 3, CLK_SET_RATE_PARENT, 0), 1620 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1621 2, CLK_SET_RATE_PARENT, 0), 1622 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1623 1, CLK_SET_RATE_PARENT, 0), 1624 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1625 0, CLK_SET_RATE_PARENT, 0), 1626 1627 /* ENABLE_PCLK_PERIC1 */ 1628 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1, 1629 9, CLK_SET_RATE_PARENT, 0), 1630 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1, 1631 8, CLK_SET_RATE_PARENT, 0), 1632 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66", 1633 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0), 1634 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66", 1635 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0), 1636 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66", 1637 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0), 1638 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66", 1639 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 1640 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66", 1641 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0), 1642 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66", 1643 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0), 1644 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66", 1645 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0), 1646 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66", 1647 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 1648 1649 /* ENABLE_SCLK_PERIC */ 1650 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in", 1651 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0), 1652 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in", 1653 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0), 1654 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC, 1655 19, CLK_SET_RATE_PARENT, 0), 1656 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC, 1657 18, CLK_SET_RATE_PARENT, 0), 1658 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC, 1659 17, 0, 0), 1660 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC, 1661 16, 0, 0), 1662 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0), 1663 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in", 1664 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), 1665 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", 1666 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0), 1667 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", 1668 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1669 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", 1670 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10, 1671 CLK_SET_RATE_PARENT, 0), 1672 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric", 1673 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 1674 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric", 1675 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 1676 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric", 1677 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 1678 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, 1679 5, CLK_SET_RATE_PARENT, 0), 1680 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, 1681 4, CLK_SET_RATE_PARENT, 0), 1682 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, 1683 3, CLK_SET_RATE_PARENT, 0), 1684 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", 1685 ENABLE_SCLK_PERIC, 2, 1686 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1687 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric", 1688 ENABLE_SCLK_PERIC, 1, 1689 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1690 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric", 1691 ENABLE_SCLK_PERIC, 0, 1692 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1693 }; 1694 1695 static const struct samsung_cmu_info peric_cmu_info __initconst = { 1696 .div_clks = peric_div_clks, 1697 .nr_div_clks = ARRAY_SIZE(peric_div_clks), 1698 .gate_clks = peric_gate_clks, 1699 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), 1700 .nr_clk_ids = PERIC_NR_CLK, 1701 .clk_regs = peric_clk_regs, 1702 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), 1703 }; 1704 1705 static void __init exynos5433_cmu_peric_init(struct device_node *np) 1706 { 1707 samsung_cmu_register_one(np, &peric_cmu_info); 1708 } 1709 1710 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", 1711 exynos5433_cmu_peric_init); 1712 1713 /* 1714 * Register offset definitions for CMU_PERIS 1715 */ 1716 #define ENABLE_ACLK_PERIS 0x0800 1717 #define ENABLE_PCLK_PERIS 0x0900 1718 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904 1719 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908 1720 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c 1721 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910 1722 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914 1723 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918 1724 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c 1725 #define ENABLE_SCLK_PERIS 0x0a00 1726 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04 1727 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08 1728 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c 1729 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10 1730 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14 1731 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18 1732 #define ENABLE_IP_PERIS0 0x0b00 1733 #define ENABLE_IP_PERIS1 0x0b04 1734 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08 1735 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c 1736 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10 1737 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14 1738 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18 1739 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c 1740 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 1741 1742 static const unsigned long peris_clk_regs[] __initconst = { 1743 ENABLE_ACLK_PERIS, 1744 ENABLE_PCLK_PERIS, 1745 ENABLE_PCLK_PERIS_SECURE_TZPC, 1746 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 1747 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 1748 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 1749 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 1750 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 1751 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 1752 ENABLE_SCLK_PERIS, 1753 ENABLE_SCLK_PERIS_SECURE_SECKEY, 1754 ENABLE_SCLK_PERIS_SECURE_CHIPID, 1755 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 1756 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 1757 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 1758 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 1759 ENABLE_IP_PERIS0, 1760 ENABLE_IP_PERIS1, 1761 ENABLE_IP_PERIS_SECURE_TZPC, 1762 ENABLE_IP_PERIS_SECURE_SECKEY, 1763 ENABLE_IP_PERIS_SECURE_CHIPID, 1764 ENABLE_IP_PERIS_SECURE_TOPRTC, 1765 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE, 1766 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT, 1767 ENABLE_IP_PERIS_SECURE_OTP_CON, 1768 }; 1769 1770 static const struct samsung_gate_clock peris_gate_clks[] __initconst = { 1771 /* ENABLE_ACLK_PERIS */ 1772 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", 1773 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), 1774 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66", 1775 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1776 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66", 1777 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1778 1779 /* ENABLE_PCLK_PERIS */ 1780 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66", 1781 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0), 1782 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66", 1783 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0), 1784 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66", 1785 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0), 1786 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66", 1787 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0), 1788 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66", 1789 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0), 1790 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66", 1791 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0), 1792 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66", 1793 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0), 1794 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66", 1795 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0), 1796 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66", 1797 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0), 1798 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66", 1799 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0), 1800 1801 /* ENABLE_PCLK_PERIS_SECURE_TZPC */ 1802 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66", 1803 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0), 1804 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66", 1805 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0), 1806 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66", 1807 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0), 1808 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66", 1809 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0), 1810 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66", 1811 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0), 1812 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66", 1813 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0), 1814 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66", 1815 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0), 1816 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66", 1817 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0), 1818 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66", 1819 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0), 1820 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66", 1821 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0), 1822 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66", 1823 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0), 1824 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66", 1825 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0), 1826 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66", 1827 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0), 1828 1829 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ 1830 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66", 1831 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0), 1832 1833 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ 1834 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66", 1835 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0), 1836 1837 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ 1838 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66", 1839 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), 1840 1841 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */ 1842 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif", 1843 "aclk_peris_66", 1844 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0), 1845 1846 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */ 1847 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif", 1848 "aclk_peris_66", 1849 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0), 1850 1851 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */ 1852 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif", 1853 "aclk_peris_66", 1854 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0), 1855 1856 /* ENABLE_SCLK_PERIS */ 1857 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common", 1858 ENABLE_SCLK_PERIS, 10, 0, 0), 1859 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common", 1860 ENABLE_SCLK_PERIS, 4, 0, 0), 1861 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common", 1862 ENABLE_SCLK_PERIS, 3, 0, 0), 1863 1864 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */ 1865 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common", 1866 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0), 1867 1868 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */ 1869 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common", 1870 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0), 1871 1872 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ 1873 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common", 1874 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), 1875 1876 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */ 1877 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common", 1878 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0), 1879 1880 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */ 1881 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common", 1882 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0), 1883 1884 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */ 1885 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common", 1886 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), 1887 }; 1888 1889 static const struct samsung_cmu_info peris_cmu_info __initconst = { 1890 .gate_clks = peris_gate_clks, 1891 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 1892 .nr_clk_ids = PERIS_NR_CLK, 1893 .clk_regs = peris_clk_regs, 1894 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 1895 }; 1896 1897 static void __init exynos5433_cmu_peris_init(struct device_node *np) 1898 { 1899 samsung_cmu_register_one(np, &peris_cmu_info); 1900 } 1901 1902 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", 1903 exynos5433_cmu_peris_init); 1904 1905 /* 1906 * Register offset definitions for CMU_FSYS 1907 */ 1908 #define MUX_SEL_FSYS0 0x0200 1909 #define MUX_SEL_FSYS1 0x0204 1910 #define MUX_SEL_FSYS2 0x0208 1911 #define MUX_SEL_FSYS3 0x020c 1912 #define MUX_SEL_FSYS4 0x0210 1913 #define MUX_ENABLE_FSYS0 0x0300 1914 #define MUX_ENABLE_FSYS1 0x0304 1915 #define MUX_ENABLE_FSYS2 0x0308 1916 #define MUX_ENABLE_FSYS3 0x030c 1917 #define MUX_ENABLE_FSYS4 0x0310 1918 #define MUX_STAT_FSYS0 0x0400 1919 #define MUX_STAT_FSYS1 0x0404 1920 #define MUX_STAT_FSYS2 0x0408 1921 #define MUX_STAT_FSYS3 0x040c 1922 #define MUX_STAT_FSYS4 0x0410 1923 #define MUX_IGNORE_FSYS2 0x0508 1924 #define MUX_IGNORE_FSYS3 0x050c 1925 #define ENABLE_ACLK_FSYS0 0x0800 1926 #define ENABLE_ACLK_FSYS1 0x0804 1927 #define ENABLE_PCLK_FSYS 0x0900 1928 #define ENABLE_SCLK_FSYS 0x0a00 1929 #define ENABLE_IP_FSYS0 0x0b00 1930 #define ENABLE_IP_FSYS1 0x0b04 1931 1932 /* list of all parent clock list */ 1933 PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", }; 1934 PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "aclk_fsys_200", }; 1935 PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",}; 1936 PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",}; 1937 PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", }; 1938 PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", }; 1939 PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", }; 1940 PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",}; 1941 PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", }; 1942 1943 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p) 1944 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", }; 1945 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p) 1946 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", }; 1947 PNAME(mout_phyclk_usbhost20_phy_hsic1_p) 1948 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", }; 1949 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p) 1950 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", }; 1951 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p) 1952 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", }; 1953 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p) 1954 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", }; 1955 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p) 1956 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", }; 1957 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p) 1958 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", }; 1959 PNAME(mout_phyclk_ufs_rx1_symbol_user_p) 1960 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", }; 1961 PNAME(mout_phyclk_ufs_rx0_symbol_user_p) 1962 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", }; 1963 PNAME(mout_phyclk_ufs_tx1_symbol_user_p) 1964 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", }; 1965 PNAME(mout_phyclk_ufs_tx0_symbol_user_p) 1966 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", }; 1967 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p) 1968 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", }; 1969 PNAME(mout_sclk_mphy_p) 1970 = { "mout_sclk_ufs_mphy_user", 1971 "mout_phyclk_lli_mphy_to_ufs_user", }; 1972 1973 static const unsigned long fsys_clk_regs[] __initconst = { 1974 MUX_SEL_FSYS0, 1975 MUX_SEL_FSYS1, 1976 MUX_SEL_FSYS2, 1977 MUX_SEL_FSYS3, 1978 MUX_SEL_FSYS4, 1979 MUX_ENABLE_FSYS0, 1980 MUX_ENABLE_FSYS1, 1981 MUX_ENABLE_FSYS2, 1982 MUX_ENABLE_FSYS3, 1983 MUX_ENABLE_FSYS4, 1984 MUX_IGNORE_FSYS2, 1985 MUX_IGNORE_FSYS3, 1986 ENABLE_ACLK_FSYS0, 1987 ENABLE_ACLK_FSYS1, 1988 ENABLE_PCLK_FSYS, 1989 ENABLE_SCLK_FSYS, 1990 ENABLE_IP_FSYS0, 1991 ENABLE_IP_FSYS1, 1992 }; 1993 1994 static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = { 1995 /* PHY clocks from USBDRD30_PHY */ 1996 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, 1997 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, 1998 0, 60000000), 1999 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY, 2000 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL, 2001 0, 125000000), 2002 /* PHY clocks from USBHOST30_PHY */ 2003 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY, 2004 "phyclk_usbhost30_uhost30_phyclock_phy", NULL, 2005 0, 60000000), 2006 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY, 2007 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL, 2008 0, 125000000), 2009 /* PHY clocks from USBHOST20_PHY */ 2010 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY, 2011 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000), 2012 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY, 2013 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000), 2014 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY, 2015 "phyclk_usbhost20_phy_clk48mohci_phy", NULL, 2016 0, 48000000), 2017 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY, 2018 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0, 2019 60000000), 2020 /* PHY clocks from UFS_PHY */ 2021 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy", 2022 NULL, 0, 300000000), 2023 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy", 2024 NULL, 0, 300000000), 2025 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy", 2026 NULL, 0, 300000000), 2027 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy", 2028 NULL, 0, 300000000), 2029 /* PHY clocks from LLI_PHY */ 2030 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy", 2031 NULL, 0, 26000000), 2032 }; 2033 2034 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { 2035 /* MUX_SEL_FSYS0 */ 2036 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user", 2037 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1), 2038 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user", 2039 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1), 2040 2041 /* MUX_SEL_FSYS1 */ 2042 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user", 2043 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1), 2044 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user", 2045 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1), 2046 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user", 2047 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1), 2048 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user", 2049 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1), 2050 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user", 2051 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1), 2052 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user", 2053 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1), 2054 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user", 2055 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1), 2056 2057 /* MUX_SEL_FSYS2 */ 2058 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER, 2059 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", 2060 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p, 2061 MUX_SEL_FSYS2, 28, 1), 2062 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER, 2063 "mout_phyclk_usbhost30_uhost30_phyclock_user", 2064 mout_phyclk_usbhost30_uhost30_phyclock_user_p, 2065 MUX_SEL_FSYS2, 24, 1), 2066 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER, 2067 "mout_phyclk_usbhost20_phy_hsic1", 2068 mout_phyclk_usbhost20_phy_hsic1_p, 2069 MUX_SEL_FSYS2, 20, 1), 2070 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER, 2071 "mout_phyclk_usbhost20_phy_clk48mohci_user", 2072 mout_phyclk_usbhost20_phy_clk48mohci_user_p, 2073 MUX_SEL_FSYS2, 16, 1), 2074 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER, 2075 "mout_phyclk_usbhost20_phy_phyclock_user", 2076 mout_phyclk_usbhost20_phy_phyclock_user_p, 2077 MUX_SEL_FSYS2, 12, 1), 2078 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER, 2079 "mout_phyclk_usbhost20_phy_freeclk_user", 2080 mout_phyclk_usbhost20_phy_freeclk_user_p, 2081 MUX_SEL_FSYS2, 8, 1), 2082 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, 2083 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", 2084 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p, 2085 MUX_SEL_FSYS2, 4, 1), 2086 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, 2087 "mout_phyclk_usbdrd30_udrd30_phyclock_user", 2088 mout_phyclk_usbdrd30_udrd30_phyclock_user_p, 2089 MUX_SEL_FSYS2, 0, 1), 2090 2091 /* MUX_SEL_FSYS3 */ 2092 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER, 2093 "mout_phyclk_ufs_rx1_symbol_user", 2094 mout_phyclk_ufs_rx1_symbol_user_p, 2095 MUX_SEL_FSYS3, 16, 1), 2096 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER, 2097 "mout_phyclk_ufs_rx0_symbol_user", 2098 mout_phyclk_ufs_rx0_symbol_user_p, 2099 MUX_SEL_FSYS3, 12, 1), 2100 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER, 2101 "mout_phyclk_ufs_tx1_symbol_user", 2102 mout_phyclk_ufs_tx1_symbol_user_p, 2103 MUX_SEL_FSYS3, 8, 1), 2104 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER, 2105 "mout_phyclk_ufs_tx0_symbol_user", 2106 mout_phyclk_ufs_tx0_symbol_user_p, 2107 MUX_SEL_FSYS3, 4, 1), 2108 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER, 2109 "mout_phyclk_lli_mphy_to_ufs_user", 2110 mout_phyclk_lli_mphy_to_ufs_user_p, 2111 MUX_SEL_FSYS3, 0, 1), 2112 2113 /* MUX_SEL_FSYS4 */ 2114 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p, 2115 MUX_SEL_FSYS4, 0, 1), 2116 }; 2117 2118 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { 2119 /* ENABLE_ACLK_FSYS0 */ 2120 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", 2121 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), 2122 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user", 2123 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0), 2124 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user", 2125 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 2126 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user", 2127 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0), 2128 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user", 2129 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0), 2130 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user", 2131 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0), 2132 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user", 2133 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0), 2134 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user", 2135 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0), 2136 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user", 2137 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0), 2138 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user", 2139 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0), 2140 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user", 2141 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0), 2142 2143 /* ENABLE_ACLK_FSYS1 */ 2144 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user", 2145 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0), 2146 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1", 2147 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2148 26, CLK_IGNORE_UNUSED, 0), 2149 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2150 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0), 2151 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user", 2152 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0), 2153 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1", 2154 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2155 22, CLK_IGNORE_UNUSED, 0), 2156 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user", 2157 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0), 2158 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user", 2159 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0), 2160 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30", 2161 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2162 13, 0, 0), 2163 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30", 2164 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2165 12, 0, 0), 2166 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0", 2167 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2168 11, CLK_IGNORE_UNUSED, 0), 2169 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs", 2170 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2171 10, CLK_IGNORE_UNUSED, 0), 2172 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx", 2173 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2174 9, CLK_IGNORE_UNUSED, 0), 2175 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp", 2176 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2177 8, CLK_IGNORE_UNUSED, 0), 2178 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs", 2179 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2180 7, CLK_IGNORE_UNUSED, 0), 2181 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0", 2182 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2183 6, CLK_IGNORE_UNUSED, 0), 2184 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user", 2185 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0), 2186 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user", 2187 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0), 2188 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user", 2189 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0), 2190 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user", 2191 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0), 2192 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user", 2193 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0), 2194 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user", 2195 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0), 2196 2197 /* ENABLE_PCLK_FSYS */ 2198 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user", 2199 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0), 2200 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2201 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0), 2202 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user", 2203 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0), 2204 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user", 2205 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0), 2206 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user", 2207 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0), 2208 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user", 2209 ENABLE_PCLK_FSYS, 5, 0, 0), 2210 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30", 2211 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0), 2212 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30", 2213 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0), 2214 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user", 2215 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0), 2216 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user", 2217 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0), 2218 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys", 2219 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 2220 0, CLK_IGNORE_UNUSED, 0), 2221 2222 /* ENABLE_SCLK_FSYS */ 2223 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user", 2224 ENABLE_SCLK_FSYS, 21, 0, 0), 2225 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK, 2226 "phyclk_usbhost30_uhost30_pipe_pclk", 2227 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", 2228 ENABLE_SCLK_FSYS, 18, 0, 0), 2229 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK, 2230 "phyclk_usbhost30_uhost30_phyclock", 2231 "mout_phyclk_usbhost30_uhost30_phyclock_user", 2232 ENABLE_SCLK_FSYS, 17, 0, 0), 2233 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol", 2234 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS, 2235 16, 0, 0), 2236 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol", 2237 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS, 2238 15, 0, 0), 2239 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol", 2240 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS, 2241 14, 0, 0), 2242 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol", 2243 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS, 2244 13, 0, 0), 2245 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1", 2246 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS, 2247 12, 0, 0), 2248 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI, 2249 "phyclk_usbhost20_phy_clk48mohci", 2250 "mout_phyclk_usbhost20_phy_clk48mohci_user", 2251 ENABLE_SCLK_FSYS, 11, 0, 0), 2252 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK, 2253 "phyclk_usbhost20_phy_phyclock", 2254 "mout_phyclk_usbhost20_phy_phyclock_user", 2255 ENABLE_SCLK_FSYS, 10, 0, 0), 2256 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK, 2257 "phyclk_usbhost20_phy_freeclk", 2258 "mout_phyclk_usbhost20_phy_freeclk_user", 2259 ENABLE_SCLK_FSYS, 9, 0, 0), 2260 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, 2261 "phyclk_usbdrd30_udrd30_pipe_pclk", 2262 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", 2263 ENABLE_SCLK_FSYS, 8, 0, 0), 2264 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK, 2265 "phyclk_usbdrd30_udrd30_phyclock", 2266 "mout_phyclk_usbdrd30_udrd30_phyclock_user", 2267 ENABLE_SCLK_FSYS, 7, 0, 0), 2268 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy", 2269 ENABLE_SCLK_FSYS, 6, 0, 0), 2270 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user", 2271 ENABLE_SCLK_FSYS, 5, 0, 0), 2272 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user", 2273 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 2274 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user", 2275 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0), 2276 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user", 2277 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 2278 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user", 2279 ENABLE_SCLK_FSYS, 1, 0, 0), 2280 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user", 2281 ENABLE_SCLK_FSYS, 0, 0, 0), 2282 2283 /* ENABLE_IP_FSYS0 */ 2284 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0), 2285 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), 2286 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), 2287 }; 2288 2289 static const struct samsung_cmu_info fsys_cmu_info __initconst = { 2290 .mux_clks = fsys_mux_clks, 2291 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), 2292 .gate_clks = fsys_gate_clks, 2293 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), 2294 .fixed_clks = fsys_fixed_clks, 2295 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks), 2296 .nr_clk_ids = FSYS_NR_CLK, 2297 .clk_regs = fsys_clk_regs, 2298 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), 2299 }; 2300 2301 static void __init exynos5433_cmu_fsys_init(struct device_node *np) 2302 { 2303 samsung_cmu_register_one(np, &fsys_cmu_info); 2304 } 2305 2306 CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys", 2307 exynos5433_cmu_fsys_init); 2308 2309 /* 2310 * Register offset definitions for CMU_G2D 2311 */ 2312 #define MUX_SEL_G2D0 0x0200 2313 #define MUX_SEL_ENABLE_G2D0 0x0300 2314 #define MUX_SEL_STAT_G2D0 0x0400 2315 #define DIV_G2D 0x0600 2316 #define DIV_STAT_G2D 0x0700 2317 #define DIV_ENABLE_ACLK_G2D 0x0800 2318 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804 2319 #define DIV_ENABLE_PCLK_G2D 0x0900 2320 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904 2321 #define DIV_ENABLE_IP_G2D0 0x0b00 2322 #define DIV_ENABLE_IP_G2D1 0x0b04 2323 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 2324 2325 static const unsigned long g2d_clk_regs[] __initconst = { 2326 MUX_SEL_G2D0, 2327 MUX_SEL_ENABLE_G2D0, 2328 DIV_G2D, 2329 DIV_ENABLE_ACLK_G2D, 2330 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 2331 DIV_ENABLE_PCLK_G2D, 2332 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 2333 DIV_ENABLE_IP_G2D0, 2334 DIV_ENABLE_IP_G2D1, 2335 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D, 2336 }; 2337 2338 /* list of all parent clock list */ 2339 PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; 2340 PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; 2341 2342 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = { 2343 /* MUX_SEL_G2D0 */ 2344 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", 2345 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), 2346 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user", 2347 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), 2348 }; 2349 2350 static const struct samsung_div_clock g2d_div_clks[] __initconst = { 2351 /* DIV_G2D */ 2352 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", 2353 DIV_G2D, 0, 2), 2354 }; 2355 2356 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = { 2357 /* DIV_ENABLE_ACLK_G2D */ 2358 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", 2359 DIV_ENABLE_ACLK_G2D, 12, 0, 0), 2360 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user", 2361 DIV_ENABLE_ACLK_G2D, 11, 0, 0), 2362 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user", 2363 DIV_ENABLE_ACLK_G2D, 10, 0, 0), 2364 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user", 2365 DIV_ENABLE_ACLK_G2D, 9, 0, 0), 2366 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user", 2367 DIV_ENABLE_ACLK_G2D, 8, 0, 0), 2368 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx", 2369 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D, 2370 7, 0, 0), 2371 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d", 2372 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0), 2373 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d", 2374 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0), 2375 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user", 2376 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0), 2377 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d", 2378 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0), 2379 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user", 2380 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0), 2381 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user", 2382 DIV_ENABLE_ACLK_G2D, 1, 0, 0), 2383 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user", 2384 DIV_ENABLE_ACLK_G2D, 0, 0, 0), 2385 2386 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */ 2387 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user", 2388 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2389 2390 /* DIV_ENABLE_PCLK_G2D */ 2391 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d", 2392 DIV_ENABLE_PCLK_G2D, 7, 0, 0), 2393 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d", 2394 DIV_ENABLE_PCLK_G2D, 6, 0, 0), 2395 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d", 2396 DIV_ENABLE_PCLK_G2D, 5, 0, 0), 2397 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d", 2398 DIV_ENABLE_PCLK_G2D, 4, 0, 0), 2399 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d", 2400 DIV_ENABLE_PCLK_G2D, 3, 0, 0), 2401 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d", 2402 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0), 2403 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d", 2404 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0), 2405 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D, 2406 0, 0, 0), 2407 2408 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */ 2409 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d", 2410 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2411 }; 2412 2413 static const struct samsung_cmu_info g2d_cmu_info __initconst = { 2414 .mux_clks = g2d_mux_clks, 2415 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), 2416 .div_clks = g2d_div_clks, 2417 .nr_div_clks = ARRAY_SIZE(g2d_div_clks), 2418 .gate_clks = g2d_gate_clks, 2419 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), 2420 .nr_clk_ids = G2D_NR_CLK, 2421 .clk_regs = g2d_clk_regs, 2422 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), 2423 }; 2424 2425 static void __init exynos5433_cmu_g2d_init(struct device_node *np) 2426 { 2427 samsung_cmu_register_one(np, &g2d_cmu_info); 2428 } 2429 2430 CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d", 2431 exynos5433_cmu_g2d_init); 2432 2433 /* 2434 * Register offset definitions for CMU_DISP 2435 */ 2436 #define DISP_PLL_LOCK 0x0000 2437 #define DISP_PLL_CON0 0x0100 2438 #define DISP_PLL_CON1 0x0104 2439 #define DISP_PLL_FREQ_DET 0x0108 2440 #define MUX_SEL_DISP0 0x0200 2441 #define MUX_SEL_DISP1 0x0204 2442 #define MUX_SEL_DISP2 0x0208 2443 #define MUX_SEL_DISP3 0x020c 2444 #define MUX_SEL_DISP4 0x0210 2445 #define MUX_ENABLE_DISP0 0x0300 2446 #define MUX_ENABLE_DISP1 0x0304 2447 #define MUX_ENABLE_DISP2 0x0308 2448 #define MUX_ENABLE_DISP3 0x030c 2449 #define MUX_ENABLE_DISP4 0x0310 2450 #define MUX_STAT_DISP0 0x0400 2451 #define MUX_STAT_DISP1 0x0404 2452 #define MUX_STAT_DISP2 0x0408 2453 #define MUX_STAT_DISP3 0x040c 2454 #define MUX_STAT_DISP4 0x0410 2455 #define MUX_IGNORE_DISP2 0x0508 2456 #define DIV_DISP 0x0600 2457 #define DIV_DISP_PLL_FREQ_DET 0x0604 2458 #define DIV_STAT_DISP 0x0700 2459 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704 2460 #define ENABLE_ACLK_DISP0 0x0800 2461 #define ENABLE_ACLK_DISP1 0x0804 2462 #define ENABLE_PCLK_DISP 0x0900 2463 #define ENABLE_SCLK_DISP 0x0a00 2464 #define ENABLE_IP_DISP0 0x0b00 2465 #define ENABLE_IP_DISP1 0x0b04 2466 #define CLKOUT_CMU_DISP 0x0c00 2467 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 2468 2469 static const unsigned long disp_clk_regs[] __initconst = { 2470 DISP_PLL_LOCK, 2471 DISP_PLL_CON0, 2472 DISP_PLL_CON1, 2473 DISP_PLL_FREQ_DET, 2474 MUX_SEL_DISP0, 2475 MUX_SEL_DISP1, 2476 MUX_SEL_DISP2, 2477 MUX_SEL_DISP3, 2478 MUX_SEL_DISP4, 2479 MUX_ENABLE_DISP0, 2480 MUX_ENABLE_DISP1, 2481 MUX_ENABLE_DISP2, 2482 MUX_ENABLE_DISP3, 2483 MUX_ENABLE_DISP4, 2484 MUX_IGNORE_DISP2, 2485 DIV_DISP, 2486 DIV_DISP_PLL_FREQ_DET, 2487 ENABLE_ACLK_DISP0, 2488 ENABLE_ACLK_DISP1, 2489 ENABLE_PCLK_DISP, 2490 ENABLE_SCLK_DISP, 2491 ENABLE_IP_DISP0, 2492 ENABLE_IP_DISP1, 2493 CLKOUT_CMU_DISP, 2494 CLKOUT_CMU_DISP_DIV_STAT, 2495 }; 2496 2497 /* list of all parent clock list */ 2498 PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", }; 2499 PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", }; 2500 PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", }; 2501 PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", }; 2502 PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk", 2503 "sclk_decon_tv_eclk_disp", }; 2504 PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk", 2505 "sclk_decon_vclk_disp", }; 2506 PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk", 2507 "sclk_decon_eclk_disp", }; 2508 PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk", 2509 "sclk_decon_tv_vclk_disp", }; 2510 PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", }; 2511 2512 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk", 2513 "phyclk_mipidphy1_bitclkdiv8_phy", }; 2514 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk", 2515 "phyclk_mipidphy1_rxclkesc0_phy", }; 2516 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk", 2517 "phyclk_mipidphy0_bitclkdiv8_phy", }; 2518 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk", 2519 "phyclk_mipidphy0_rxclkesc0_phy", }; 2520 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk", 2521 "phyclk_hdmiphy_tmds_clko_phy", }; 2522 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk", 2523 "phyclk_hdmiphy_pixel_clko_phy", }; 2524 2525 PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll", 2526 "mout_sclk_dsim0_user", }; 2527 PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll", 2528 "mout_sclk_decon_tv_eclk_user", }; 2529 PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll", 2530 "mout_sclk_decon_vclk_user", }; 2531 PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll", 2532 "mout_sclk_decon_eclk_user", }; 2533 2534 PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp", 2535 "mout_sclk_dsim1_user", }; 2536 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = { 2537 "mout_phyclk_hdmiphy_pixel_clko_user", 2538 "mout_sclk_decon_tv_vclk_b_disp", }; 2539 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", 2540 "mout_sclk_decon_tv_vclk_user", }; 2541 2542 static const struct samsung_pll_clock disp_pll_clks[] __initconst = { 2543 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", 2544 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates), 2545 }; 2546 2547 static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = { 2548 /* 2549 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. 2550 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} 2551 * and sclk_decon_{vclk|tv_vclk}. 2552 */ 2553 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk", 2554 1, 2, 0), 2555 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk", 2556 1, 2, 0), 2557 }; 2558 2559 static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = { 2560 /* PHY clocks from MIPI_DPHY1 */ 2561 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), 2562 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), 2563 /* PHY clocks from MIPI_DPHY0 */ 2564 FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy", 2565 NULL, 0, 188000000), 2566 FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy", 2567 NULL, 0, 100000000), 2568 /* PHY clocks from HDMI_PHY */ 2569 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", 2570 NULL, 0, 300000000), 2571 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy", 2572 NULL, 0, 166000000), 2573 }; 2574 2575 static const struct samsung_mux_clock disp_mux_clks[] __initconst = { 2576 /* MUX_SEL_DISP0 */ 2577 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, 2578 0, 1), 2579 2580 /* MUX_SEL_DISP1 */ 2581 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user", 2582 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1), 2583 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user", 2584 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1), 2585 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p, 2586 MUX_SEL_DISP1, 20, 1), 2587 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user", 2588 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1), 2589 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user", 2590 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1), 2591 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user", 2592 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1), 2593 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user", 2594 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1), 2595 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", 2596 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1), 2597 2598 /* MUX_SEL_DISP2 */ 2599 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, 2600 "mout_phyclk_mipidphy1_bitclkdiv8_user", 2601 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2, 2602 20, 1), 2603 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, 2604 "mout_phyclk_mipidphy1_rxclkesc0_user", 2605 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2, 2606 16, 1), 2607 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, 2608 "mout_phyclk_mipidphy0_bitclkdiv8_user", 2609 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2, 2610 12, 1), 2611 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, 2612 "mout_phyclk_mipidphy0_rxclkesc0_user", 2613 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2, 2614 8, 1), 2615 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER, 2616 "mout_phyclk_hdmiphy_tmds_clko_user", 2617 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2, 2618 4, 1), 2619 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, 2620 "mout_phyclk_hdmiphy_pixel_clko_user", 2621 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2, 2622 0, 1), 2623 2624 /* MUX_SEL_DISP3 */ 2625 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p, 2626 MUX_SEL_DISP3, 12, 1), 2627 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk", 2628 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1), 2629 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk", 2630 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1), 2631 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk", 2632 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1), 2633 2634 /* MUX_SEL_DISP4 */ 2635 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp", 2636 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1), 2637 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp", 2638 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1), 2639 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP, 2640 "mout_sclk_decon_tv_vclk_c_disp", 2641 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1), 2642 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP, 2643 "mout_sclk_decon_tv_vclk_b_disp", 2644 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1), 2645 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP, 2646 "mout_sclk_decon_tv_vclk_a_disp", 2647 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), 2648 }; 2649 2650 static const struct samsung_div_clock disp_div_clks[] __initconst = { 2651 /* DIV_DISP */ 2652 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", 2653 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), 2654 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp", 2655 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3), 2656 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0", 2657 DIV_DISP, 16, 3), 2658 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp", 2659 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3), 2660 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp", 2661 "mout_sclk_decon_vclk", DIV_DISP, 8, 3), 2662 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp", 2663 "mout_sclk_decon_eclk", DIV_DISP, 4, 3), 2664 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user", 2665 DIV_DISP, 0, 2), 2666 }; 2667 2668 static const struct samsung_gate_clock disp_gate_clks[] __initconst = { 2669 /* ENABLE_ACLK_DISP0 */ 2670 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", 2671 ENABLE_ACLK_DISP0, 2, 0, 0), 2672 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user", 2673 ENABLE_ACLK_DISP0, 0, 0, 0), 2674 2675 /* ENABLE_ACLK_DISP1 */ 2676 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user", 2677 ENABLE_ACLK_DISP1, 25, 0, 0), 2678 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user", 2679 ENABLE_ACLK_DISP1, 24, 0, 0), 2680 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x", 2681 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0), 2682 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x", 2683 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0), 2684 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3", 2685 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0), 2686 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2", 2687 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0), 2688 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1", 2689 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0), 2690 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0", 2691 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0), 2692 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4", 2693 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0), 2694 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3", 2695 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0), 2696 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2", 2697 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0), 2698 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1", 2699 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0), 2700 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0", 2701 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0), 2702 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p", 2703 "div_pclk_disp", ENABLE_ACLK_DISP1, 2704 12, CLK_IGNORE_UNUSED, 0), 2705 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p", 2706 "div_pclk_disp", ENABLE_ACLK_DISP1, 2707 11, CLK_IGNORE_UNUSED, 0), 2708 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p", 2709 "div_pclk_disp", ENABLE_ACLK_DISP1, 2710 10, CLK_IGNORE_UNUSED, 0), 2711 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp", 2712 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0), 2713 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user", 2714 ENABLE_ACLK_DISP1, 7, 0, 0), 2715 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user", 2716 ENABLE_ACLK_DISP1, 6, 0, 0), 2717 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x", 2718 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0), 2719 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x", 2720 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0), 2721 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user", 2722 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0), 2723 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp", 2724 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0), 2725 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333", 2726 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1, 2727 CLK_IGNORE_UNUSED, 0), 2728 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333", 2729 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 2730 0, CLK_IGNORE_UNUSED, 0), 2731 2732 /* ENABLE_PCLK_DISP */ 2733 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp", 2734 ENABLE_PCLK_DISP, 23, 0, 0), 2735 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp", 2736 ENABLE_PCLK_DISP, 22, 0, 0), 2737 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp", 2738 ENABLE_PCLK_DISP, 21, 0, 0), 2739 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp", 2740 ENABLE_PCLK_DISP, 20, 0, 0), 2741 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp", 2742 ENABLE_PCLK_DISP, 19, 0, 0), 2743 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp", 2744 ENABLE_PCLK_DISP, 18, 0, 0), 2745 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp", 2746 ENABLE_PCLK_DISP, 17, 0, 0), 2747 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp", 2748 ENABLE_PCLK_DISP, 16, 0, 0), 2749 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp", 2750 ENABLE_PCLK_DISP, 15, 0, 0), 2751 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp", 2752 ENABLE_PCLK_DISP, 14, 0, 0), 2753 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp", 2754 ENABLE_PCLK_DISP, 13, 0, 0), 2755 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp", 2756 ENABLE_PCLK_DISP, 12, 0, 0), 2757 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp", 2758 ENABLE_PCLK_DISP, 11, 0, 0), 2759 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp", 2760 ENABLE_PCLK_DISP, 10, 0, 0), 2761 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp", 2762 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0), 2763 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp", 2764 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0), 2765 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp", 2766 ENABLE_PCLK_DISP, 7, 0, 0), 2767 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp", 2768 ENABLE_PCLK_DISP, 6, 0, 0), 2769 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp", 2770 ENABLE_PCLK_DISP, 5, 0, 0), 2771 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp", 2772 ENABLE_PCLK_DISP, 3, 0, 0), 2773 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp", 2774 ENABLE_PCLK_DISP, 2, 0, 0), 2775 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp", 2776 ENABLE_PCLK_DISP, 1, 0, 0), 2777 GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp", 2778 ENABLE_PCLK_DISP, 0, 0, 0), 2779 2780 /* ENABLE_SCLK_DISP */ 2781 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8", 2782 "mout_phyclk_mipidphy1_bitclkdiv8_user", 2783 ENABLE_SCLK_DISP, 26, 0, 0), 2784 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0", 2785 "mout_phyclk_mipidphy1_rxclkesc0_user", 2786 ENABLE_SCLK_DISP, 25, 0, 0), 2787 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1", 2788 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0), 2789 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1", 2790 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0), 2791 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp", 2792 ENABLE_SCLK_DISP, 22, 0, 0), 2793 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk", 2794 "div_sclk_decon_tv_vclk_disp", 2795 ENABLE_SCLK_DISP, 21, 0, 0), 2796 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8", 2797 "mout_phyclk_mipidphy0_bitclkdiv8_user", 2798 ENABLE_SCLK_DISP, 15, 0, 0), 2799 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0", 2800 "mout_phyclk_mipidphy0_rxclkesc0_user", 2801 ENABLE_SCLK_DISP, 14, 0, 0), 2802 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko", 2803 "mout_phyclk_hdmiphy_tmds_clko_user", 2804 ENABLE_SCLK_DISP, 13, 0, 0), 2805 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel", 2806 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0), 2807 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies", 2808 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0), 2809 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0", 2810 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0), 2811 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0", 2812 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0), 2813 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user", 2814 ENABLE_SCLK_DISP, 7, 0, 0), 2815 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp", 2816 ENABLE_SCLK_DISP, 6, 0, 0), 2817 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp", 2818 ENABLE_SCLK_DISP, 5, 0, 0), 2819 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk", 2820 "div_sclk_decon_tv_eclk_disp", 2821 ENABLE_SCLK_DISP, 4, 0, 0), 2822 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk", 2823 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0), 2824 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk", 2825 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), 2826 }; 2827 2828 static const struct samsung_cmu_info disp_cmu_info __initconst = { 2829 .pll_clks = disp_pll_clks, 2830 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), 2831 .mux_clks = disp_mux_clks, 2832 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks), 2833 .div_clks = disp_div_clks, 2834 .nr_div_clks = ARRAY_SIZE(disp_div_clks), 2835 .gate_clks = disp_gate_clks, 2836 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks), 2837 .fixed_clks = disp_fixed_clks, 2838 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks), 2839 .fixed_factor_clks = disp_fixed_factor_clks, 2840 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks), 2841 .nr_clk_ids = DISP_NR_CLK, 2842 .clk_regs = disp_clk_regs, 2843 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), 2844 }; 2845 2846 static void __init exynos5433_cmu_disp_init(struct device_node *np) 2847 { 2848 samsung_cmu_register_one(np, &disp_cmu_info); 2849 } 2850 2851 CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp", 2852 exynos5433_cmu_disp_init); 2853 2854 /* 2855 * Register offset definitions for CMU_AUD 2856 */ 2857 #define MUX_SEL_AUD0 0x0200 2858 #define MUX_SEL_AUD1 0x0204 2859 #define MUX_ENABLE_AUD0 0x0300 2860 #define MUX_ENABLE_AUD1 0x0304 2861 #define MUX_STAT_AUD0 0x0400 2862 #define DIV_AUD0 0x0600 2863 #define DIV_AUD1 0x0604 2864 #define DIV_STAT_AUD0 0x0700 2865 #define DIV_STAT_AUD1 0x0704 2866 #define ENABLE_ACLK_AUD 0x0800 2867 #define ENABLE_PCLK_AUD 0x0900 2868 #define ENABLE_SCLK_AUD0 0x0a00 2869 #define ENABLE_SCLK_AUD1 0x0a04 2870 #define ENABLE_IP_AUD0 0x0b00 2871 #define ENABLE_IP_AUD1 0x0b04 2872 2873 static const unsigned long aud_clk_regs[] __initconst = { 2874 MUX_SEL_AUD0, 2875 MUX_SEL_AUD1, 2876 MUX_ENABLE_AUD0, 2877 MUX_ENABLE_AUD1, 2878 DIV_AUD0, 2879 DIV_AUD1, 2880 ENABLE_ACLK_AUD, 2881 ENABLE_PCLK_AUD, 2882 ENABLE_SCLK_AUD0, 2883 ENABLE_SCLK_AUD1, 2884 ENABLE_IP_AUD0, 2885 ENABLE_IP_AUD1, 2886 }; 2887 2888 /* list of all parent clock list */ 2889 PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; 2890 PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; 2891 2892 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { 2893 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000), 2894 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000), 2895 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000), 2896 }; 2897 2898 static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 2899 /* MUX_SEL_AUD0 */ 2900 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", 2901 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), 2902 2903 /* MUX_SEL_AUD1 */ 2904 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, 2905 MUX_SEL_AUD1, 8, 1), 2906 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p, 2907 MUX_SEL_AUD1, 0, 1), 2908 }; 2909 2910 static const struct samsung_div_clock aud_div_clks[] __initconst = { 2911 /* DIV_AUD0 */ 2912 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0, 2913 12, 4), 2914 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0, 2915 8, 4), 2916 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0, 2917 4, 4), 2918 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 2919 0, 4), 2920 2921 /* DIV_AUD1 */ 2922 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus", 2923 "mout_aud_pll_user", DIV_AUD1, 16, 5), 2924 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user", 2925 DIV_AUD1, 12, 4), 2926 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm", 2927 DIV_AUD1, 4, 8), 2928 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s", 2929 DIV_AUD1, 0, 4), 2930 }; 2931 2932 static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 2933 /* ENABLE_ACLK_AUD */ 2934 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud", 2935 ENABLE_ACLK_AUD, 12, 0, 0), 2936 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud", 2937 ENABLE_ACLK_AUD, 7, 0, 0), 2938 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud", 2939 ENABLE_ACLK_AUD, 0, 4, 0), 2940 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud", 2941 ENABLE_ACLK_AUD, 0, 3, 0), 2942 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud", 2943 ENABLE_ACLK_AUD, 0, 2, 0), 2944 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD, 2945 0, 1, 0), 2946 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD, 2947 0, CLK_IGNORE_UNUSED, 0), 2948 2949 /* ENABLE_PCLK_AUD */ 2950 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD, 2951 13, 0, 0), 2952 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD, 2953 12, 0, 0), 2954 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD, 2955 11, 0, 0), 2956 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud", 2957 ENABLE_PCLK_AUD, 10, 0, 0), 2958 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud", 2959 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0), 2960 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud", 2961 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0), 2962 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud", 2963 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0), 2964 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud", 2965 ENABLE_PCLK_AUD, 6, 0, 0), 2966 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud", 2967 ENABLE_PCLK_AUD, 5, 0, 0), 2968 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud", 2969 ENABLE_PCLK_AUD, 4, 0, 0), 2970 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud", 2971 ENABLE_PCLK_AUD, 3, 0, 0), 2972 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD, 2973 2, 0, 0), 2974 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud", 2975 ENABLE_PCLK_AUD, 0, 0, 0), 2976 2977 /* ENABLE_SCLK_AUD0 */ 2978 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0, 2979 2, CLK_IGNORE_UNUSED, 0), 2980 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud", 2981 ENABLE_SCLK_AUD0, 1, 0, 0), 2982 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0, 2983 0, 0, 0), 2984 2985 /* ENABLE_SCLK_AUD1 */ 2986 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk", 2987 ENABLE_SCLK_AUD1, 6, 0, 0), 2988 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk", 2989 ENABLE_SCLK_AUD1, 5, 0, 0), 2990 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus", 2991 ENABLE_SCLK_AUD1, 4, 0, 0), 2992 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart", 2993 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0), 2994 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm", 2995 ENABLE_SCLK_AUD1, 2, 0, 0), 2996 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk", 2997 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0), 2998 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s", 2999 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0), 3000 }; 3001 3002 static const struct samsung_cmu_info aud_cmu_info __initconst = { 3003 .mux_clks = aud_mux_clks, 3004 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 3005 .div_clks = aud_div_clks, 3006 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 3007 .gate_clks = aud_gate_clks, 3008 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 3009 .fixed_clks = aud_fixed_clks, 3010 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), 3011 .nr_clk_ids = AUD_NR_CLK, 3012 .clk_regs = aud_clk_regs, 3013 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 3014 }; 3015 3016 static void __init exynos5433_cmu_aud_init(struct device_node *np) 3017 { 3018 samsung_cmu_register_one(np, &aud_cmu_info); 3019 } 3020 CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud", 3021 exynos5433_cmu_aud_init); 3022 3023 3024 /* 3025 * Register offset definitions for CMU_BUS{0|1|2} 3026 */ 3027 #define DIV_BUS 0x0600 3028 #define DIV_STAT_BUS 0x0700 3029 #define ENABLE_ACLK_BUS 0x0800 3030 #define ENABLE_PCLK_BUS 0x0900 3031 #define ENABLE_IP_BUS0 0x0b00 3032 #define ENABLE_IP_BUS1 0x0b04 3033 3034 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */ 3035 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */ 3036 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */ 3037 3038 /* list of all parent clock list */ 3039 PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", }; 3040 3041 #define CMU_BUS_COMMON_CLK_REGS \ 3042 DIV_BUS, \ 3043 ENABLE_ACLK_BUS, \ 3044 ENABLE_PCLK_BUS, \ 3045 ENABLE_IP_BUS0, \ 3046 ENABLE_IP_BUS1 3047 3048 static const unsigned long bus01_clk_regs[] __initconst = { 3049 CMU_BUS_COMMON_CLK_REGS, 3050 }; 3051 3052 static const unsigned long bus2_clk_regs[] __initconst = { 3053 MUX_SEL_BUS2, 3054 MUX_ENABLE_BUS2, 3055 CMU_BUS_COMMON_CLK_REGS, 3056 }; 3057 3058 static const struct samsung_div_clock bus0_div_clks[] __initconst = { 3059 /* DIV_BUS0 */ 3060 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400", 3061 DIV_BUS, 0, 3), 3062 }; 3063 3064 /* CMU_BUS0 clocks */ 3065 static const struct samsung_gate_clock bus0_gate_clks[] __initconst = { 3066 /* ENABLE_ACLK_BUS0 */ 3067 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133", 3068 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3069 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133", 3070 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3071 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400", 3072 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3073 3074 /* ENABLE_PCLK_BUS0 */ 3075 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133", 3076 ENABLE_PCLK_BUS, 2, 0, 0), 3077 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133", 3078 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3079 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133", 3080 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3081 }; 3082 3083 /* CMU_BUS1 clocks */ 3084 static const struct samsung_div_clock bus1_div_clks[] __initconst = { 3085 /* DIV_BUS1 */ 3086 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400", 3087 DIV_BUS, 0, 3), 3088 }; 3089 3090 static const struct samsung_gate_clock bus1_gate_clks[] __initconst = { 3091 /* ENABLE_ACLK_BUS1 */ 3092 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133", 3093 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3094 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133", 3095 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3096 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400", 3097 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3098 3099 /* ENABLE_PCLK_BUS1 */ 3100 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133", 3101 ENABLE_PCLK_BUS, 2, 0, 0), 3102 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133", 3103 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3104 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133", 3105 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3106 }; 3107 3108 /* CMU_BUS2 clocks */ 3109 static const struct samsung_mux_clock bus2_mux_clks[] __initconst = { 3110 /* MUX_SEL_BUS2 */ 3111 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user", 3112 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1), 3113 }; 3114 3115 static const struct samsung_div_clock bus2_div_clks[] __initconst = { 3116 /* DIV_BUS2 */ 3117 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133", 3118 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3), 3119 }; 3120 3121 static const struct samsung_gate_clock bus2_gate_clks[] __initconst = { 3122 /* ENABLE_ACLK_BUS2 */ 3123 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133", 3124 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0), 3125 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133", 3126 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3127 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400", 3128 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, 3129 1, CLK_IGNORE_UNUSED, 0), 3130 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400", 3131 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, 3132 0, CLK_IGNORE_UNUSED, 0), 3133 3134 /* ENABLE_PCLK_BUS2 */ 3135 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133", 3136 ENABLE_PCLK_BUS, 2, 0, 0), 3137 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133", 3138 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3139 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133", 3140 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3141 }; 3142 3143 #define CMU_BUS_INFO_CLKS(id) \ 3144 .div_clks = bus##id##_div_clks, \ 3145 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \ 3146 .gate_clks = bus##id##_gate_clks, \ 3147 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ 3148 .nr_clk_ids = BUSx_NR_CLK 3149 3150 static const struct samsung_cmu_info bus0_cmu_info __initconst = { 3151 CMU_BUS_INFO_CLKS(0), 3152 .clk_regs = bus01_clk_regs, 3153 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3154 }; 3155 3156 static const struct samsung_cmu_info bus1_cmu_info __initconst = { 3157 CMU_BUS_INFO_CLKS(1), 3158 .clk_regs = bus01_clk_regs, 3159 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3160 }; 3161 3162 static const struct samsung_cmu_info bus2_cmu_info __initconst = { 3163 CMU_BUS_INFO_CLKS(2), 3164 .mux_clks = bus2_mux_clks, 3165 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks), 3166 .clk_regs = bus2_clk_regs, 3167 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs), 3168 }; 3169 3170 #define exynos5433_cmu_bus_init(id) \ 3171 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\ 3172 { \ 3173 samsung_cmu_register_one(np, &bus##id##_cmu_info); \ 3174 } \ 3175 CLK_OF_DECLARE(exynos5433_cmu_bus##id, \ 3176 "samsung,exynos5433-cmu-bus"#id, \ 3177 exynos5433_cmu_bus##id##_init) 3178 3179 exynos5433_cmu_bus_init(0); 3180 exynos5433_cmu_bus_init(1); 3181 exynos5433_cmu_bus_init(2); 3182 3183 /* 3184 * Register offset definitions for CMU_G3D 3185 */ 3186 #define G3D_PLL_LOCK 0x0000 3187 #define G3D_PLL_CON0 0x0100 3188 #define G3D_PLL_CON1 0x0104 3189 #define G3D_PLL_FREQ_DET 0x010c 3190 #define MUX_SEL_G3D 0x0200 3191 #define MUX_ENABLE_G3D 0x0300 3192 #define MUX_STAT_G3D 0x0400 3193 #define DIV_G3D 0x0600 3194 #define DIV_G3D_PLL_FREQ_DET 0x0604 3195 #define DIV_STAT_G3D 0x0700 3196 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704 3197 #define ENABLE_ACLK_G3D 0x0800 3198 #define ENABLE_PCLK_G3D 0x0900 3199 #define ENABLE_SCLK_G3D 0x0a00 3200 #define ENABLE_IP_G3D0 0x0b00 3201 #define ENABLE_IP_G3D1 0x0b04 3202 #define CLKOUT_CMU_G3D 0x0c00 3203 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 3204 #define CLK_STOPCTRL 0x1000 3205 3206 static const unsigned long g3d_clk_regs[] __initconst = { 3207 G3D_PLL_LOCK, 3208 G3D_PLL_CON0, 3209 G3D_PLL_CON1, 3210 G3D_PLL_FREQ_DET, 3211 MUX_SEL_G3D, 3212 MUX_ENABLE_G3D, 3213 DIV_G3D, 3214 DIV_G3D_PLL_FREQ_DET, 3215 ENABLE_ACLK_G3D, 3216 ENABLE_PCLK_G3D, 3217 ENABLE_SCLK_G3D, 3218 ENABLE_IP_G3D0, 3219 ENABLE_IP_G3D1, 3220 CLKOUT_CMU_G3D, 3221 CLKOUT_CMU_G3D_DIV_STAT, 3222 CLK_STOPCTRL, 3223 }; 3224 3225 /* list of all parent clock list */ 3226 PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", }; 3227 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; 3228 3229 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { 3230 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", 3231 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates), 3232 }; 3233 3234 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { 3235 /* MUX_SEL_G3D */ 3236 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, 3237 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0), 3238 MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, 3239 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0), 3240 }; 3241 3242 static const struct samsung_div_clock g3d_div_clks[] __initconst = { 3243 /* DIV_G3D */ 3244 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D, 3245 8, 2), 3246 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D, 3247 4, 3), 3248 DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D, 3249 0, 3, CLK_SET_RATE_PARENT, 0), 3250 }; 3251 3252 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { 3253 /* ENABLE_ACLK_G3D */ 3254 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d", 3255 ENABLE_ACLK_G3D, 7, 0, 0), 3256 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d", 3257 ENABLE_ACLK_G3D, 6, 0, 0), 3258 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d", 3259 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0), 3260 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d", 3261 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0), 3262 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d", 3263 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0), 3264 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d", 3265 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0), 3266 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d", 3267 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0), 3268 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d", 3269 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0), 3270 3271 /* ENABLE_PCLK_G3D */ 3272 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d", 3273 ENABLE_PCLK_G3D, 3, 0, 0), 3274 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d", 3275 ENABLE_PCLK_G3D, 2, 0, 0), 3276 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d", 3277 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0), 3278 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d", 3279 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0), 3280 3281 /* ENABLE_SCLK_G3D */ 3282 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d", 3283 ENABLE_SCLK_G3D, 0, 0, 0), 3284 }; 3285 3286 static const struct samsung_cmu_info g3d_cmu_info __initconst = { 3287 .pll_clks = g3d_pll_clks, 3288 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), 3289 .mux_clks = g3d_mux_clks, 3290 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), 3291 .div_clks = g3d_div_clks, 3292 .nr_div_clks = ARRAY_SIZE(g3d_div_clks), 3293 .gate_clks = g3d_gate_clks, 3294 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), 3295 .nr_clk_ids = G3D_NR_CLK, 3296 .clk_regs = g3d_clk_regs, 3297 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), 3298 }; 3299 3300 static void __init exynos5433_cmu_g3d_init(struct device_node *np) 3301 { 3302 samsung_cmu_register_one(np, &g3d_cmu_info); 3303 } 3304 CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d", 3305 exynos5433_cmu_g3d_init); 3306 3307 /* 3308 * Register offset definitions for CMU_GSCL 3309 */ 3310 #define MUX_SEL_GSCL 0x0200 3311 #define MUX_ENABLE_GSCL 0x0300 3312 #define MUX_STAT_GSCL 0x0400 3313 #define ENABLE_ACLK_GSCL 0x0800 3314 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804 3315 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808 3316 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c 3317 #define ENABLE_PCLK_GSCL 0x0900 3318 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904 3319 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908 3320 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c 3321 #define ENABLE_IP_GSCL0 0x0b00 3322 #define ENABLE_IP_GSCL1 0x0b04 3323 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08 3324 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c 3325 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10 3326 3327 static const unsigned long gscl_clk_regs[] __initconst = { 3328 MUX_SEL_GSCL, 3329 MUX_ENABLE_GSCL, 3330 ENABLE_ACLK_GSCL, 3331 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 3332 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 3333 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 3334 ENABLE_PCLK_GSCL, 3335 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 3336 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 3337 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 3338 ENABLE_IP_GSCL0, 3339 ENABLE_IP_GSCL1, 3340 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0, 3341 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1, 3342 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2, 3343 }; 3344 3345 /* list of all parent clock list */ 3346 PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", }; 3347 PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", }; 3348 3349 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = { 3350 /* MUX_SEL_GSCL */ 3351 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user", 3352 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1), 3353 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", 3354 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), 3355 }; 3356 3357 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = { 3358 /* ENABLE_ACLK_GSCL */ 3359 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user", 3360 ENABLE_ACLK_GSCL, 11, 0, 0), 3361 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user", 3362 ENABLE_ACLK_GSCL, 10, 0, 0), 3363 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user", 3364 ENABLE_ACLK_GSCL, 9, 0, 0), 3365 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp", 3366 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL, 3367 8, CLK_IGNORE_UNUSED, 0), 3368 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user", 3369 ENABLE_ACLK_GSCL, 7, 0, 0), 3370 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user", 3371 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0), 3372 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333", 3373 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 3374 CLK_IGNORE_UNUSED, 0), 3375 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333", 3376 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 3377 CLK_IGNORE_UNUSED, 0), 3378 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user", 3379 ENABLE_ACLK_GSCL, 3, 0, 0), 3380 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user", 3381 ENABLE_ACLK_GSCL, 2, 0, 0), 3382 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user", 3383 ENABLE_ACLK_GSCL, 1, 0, 0), 3384 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user", 3385 ENABLE_ACLK_GSCL, 0, 0, 0), 3386 3387 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */ 3388 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user", 3389 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), 3390 3391 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */ 3392 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user", 3393 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), 3394 3395 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */ 3396 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user", 3397 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3398 3399 /* ENABLE_PCLK_GSCL */ 3400 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user", 3401 ENABLE_PCLK_GSCL, 7, 0, 0), 3402 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user", 3403 ENABLE_PCLK_GSCL, 6, 0, 0), 3404 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user", 3405 ENABLE_PCLK_GSCL, 5, 0, 0), 3406 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user", 3407 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0), 3408 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl", 3409 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL, 3410 3, CLK_IGNORE_UNUSED, 0), 3411 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user", 3412 ENABLE_PCLK_GSCL, 2, 0, 0), 3413 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user", 3414 ENABLE_PCLK_GSCL, 1, 0, 0), 3415 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user", 3416 ENABLE_PCLK_GSCL, 0, 0, 0), 3417 3418 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */ 3419 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user", 3420 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), 3421 3422 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */ 3423 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user", 3424 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), 3425 3426 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */ 3427 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user", 3428 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3429 }; 3430 3431 static const struct samsung_cmu_info gscl_cmu_info __initconst = { 3432 .mux_clks = gscl_mux_clks, 3433 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), 3434 .gate_clks = gscl_gate_clks, 3435 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks), 3436 .nr_clk_ids = GSCL_NR_CLK, 3437 .clk_regs = gscl_clk_regs, 3438 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), 3439 }; 3440 3441 static void __init exynos5433_cmu_gscl_init(struct device_node *np) 3442 { 3443 samsung_cmu_register_one(np, &gscl_cmu_info); 3444 } 3445 CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl", 3446 exynos5433_cmu_gscl_init); 3447 3448 /* 3449 * Register offset definitions for CMU_APOLLO 3450 */ 3451 #define APOLLO_PLL_LOCK 0x0000 3452 #define APOLLO_PLL_CON0 0x0100 3453 #define APOLLO_PLL_CON1 0x0104 3454 #define APOLLO_PLL_FREQ_DET 0x010c 3455 #define MUX_SEL_APOLLO0 0x0200 3456 #define MUX_SEL_APOLLO1 0x0204 3457 #define MUX_SEL_APOLLO2 0x0208 3458 #define MUX_ENABLE_APOLLO0 0x0300 3459 #define MUX_ENABLE_APOLLO1 0x0304 3460 #define MUX_ENABLE_APOLLO2 0x0308 3461 #define MUX_STAT_APOLLO0 0x0400 3462 #define MUX_STAT_APOLLO1 0x0404 3463 #define MUX_STAT_APOLLO2 0x0408 3464 #define DIV_APOLLO0 0x0600 3465 #define DIV_APOLLO1 0x0604 3466 #define DIV_APOLLO_PLL_FREQ_DET 0x0608 3467 #define DIV_STAT_APOLLO0 0x0700 3468 #define DIV_STAT_APOLLO1 0x0704 3469 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708 3470 #define ENABLE_ACLK_APOLLO 0x0800 3471 #define ENABLE_PCLK_APOLLO 0x0900 3472 #define ENABLE_SCLK_APOLLO 0x0a00 3473 #define ENABLE_IP_APOLLO0 0x0b00 3474 #define ENABLE_IP_APOLLO1 0x0b04 3475 #define CLKOUT_CMU_APOLLO 0x0c00 3476 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04 3477 #define ARMCLK_STOPCTRL 0x1000 3478 #define APOLLO_PWR_CTRL 0x1020 3479 #define APOLLO_PWR_CTRL2 0x1024 3480 #define APOLLO_INTR_SPREAD_ENABLE 0x1080 3481 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084 3482 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088 3483 3484 static const unsigned long apollo_clk_regs[] __initconst = { 3485 APOLLO_PLL_LOCK, 3486 APOLLO_PLL_CON0, 3487 APOLLO_PLL_CON1, 3488 APOLLO_PLL_FREQ_DET, 3489 MUX_SEL_APOLLO0, 3490 MUX_SEL_APOLLO1, 3491 MUX_SEL_APOLLO2, 3492 MUX_ENABLE_APOLLO0, 3493 MUX_ENABLE_APOLLO1, 3494 MUX_ENABLE_APOLLO2, 3495 DIV_APOLLO0, 3496 DIV_APOLLO1, 3497 DIV_APOLLO_PLL_FREQ_DET, 3498 ENABLE_ACLK_APOLLO, 3499 ENABLE_PCLK_APOLLO, 3500 ENABLE_SCLK_APOLLO, 3501 ENABLE_IP_APOLLO0, 3502 ENABLE_IP_APOLLO1, 3503 CLKOUT_CMU_APOLLO, 3504 CLKOUT_CMU_APOLLO_DIV_STAT, 3505 ARMCLK_STOPCTRL, 3506 APOLLO_PWR_CTRL, 3507 APOLLO_PWR_CTRL2, 3508 APOLLO_INTR_SPREAD_ENABLE, 3509 APOLLO_INTR_SPREAD_USE_STANDBYWFI, 3510 APOLLO_INTR_SPREAD_BLOCKING_DURATION, 3511 }; 3512 3513 /* list of all parent clock list */ 3514 PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", }; 3515 PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", }; 3516 PNAME(mout_apollo_p) = { "mout_apollo_pll", 3517 "mout_bus_pll_apollo_user", }; 3518 3519 static const struct samsung_pll_clock apollo_pll_clks[] __initconst = { 3520 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", 3521 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates), 3522 }; 3523 3524 static const struct samsung_mux_clock apollo_mux_clks[] __initconst = { 3525 /* MUX_SEL_APOLLO0 */ 3526 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, 3527 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT | 3528 CLK_RECALC_NEW_RATES, 0), 3529 3530 /* MUX_SEL_APOLLO1 */ 3531 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", 3532 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1), 3533 3534 /* MUX_SEL_APOLLO2 */ 3535 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2, 3536 0, 1, CLK_SET_RATE_PARENT, 0), 3537 }; 3538 3539 static const struct samsung_div_clock apollo_div_clks[] __initconst = { 3540 /* DIV_APOLLO0 */ 3541 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2", 3542 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE, 3543 CLK_DIVIDER_READ_ONLY), 3544 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2", 3545 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE, 3546 CLK_DIVIDER_READ_ONLY), 3547 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2", 3548 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE, 3549 CLK_DIVIDER_READ_ONLY), 3550 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2", 3551 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE, 3552 CLK_DIVIDER_READ_ONLY), 3553 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2", 3554 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE, 3555 CLK_DIVIDER_READ_ONLY), 3556 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1", 3557 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0), 3558 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo", 3559 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0), 3560 3561 /* DIV_APOLLO1 */ 3562 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo", 3563 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE, 3564 CLK_DIVIDER_READ_ONLY), 3565 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo", 3566 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE, 3567 CLK_DIVIDER_READ_ONLY), 3568 }; 3569 3570 static const struct samsung_gate_clock apollo_gate_clks[] __initconst = { 3571 /* ENABLE_ACLK_APOLLO */ 3572 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys", 3573 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3574 6, CLK_IGNORE_UNUSED, 0), 3575 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys", 3576 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3577 5, CLK_IGNORE_UNUSED, 0), 3578 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys", 3579 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3580 4, CLK_IGNORE_UNUSED, 0), 3581 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys", 3582 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3583 3, CLK_IGNORE_UNUSED, 0), 3584 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci", 3585 "div_aclk_apollo", ENABLE_ACLK_APOLLO, 3586 2, CLK_IGNORE_UNUSED, 0), 3587 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop", 3588 "div_pclk_apollo", ENABLE_ACLK_APOLLO, 3589 1, CLK_IGNORE_UNUSED, 0), 3590 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200", 3591 "div_pclk_apollo", ENABLE_ACLK_APOLLO, 3592 0, CLK_IGNORE_UNUSED, 0), 3593 3594 /* ENABLE_PCLK_APOLLO */ 3595 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo", 3596 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO, 3597 2, CLK_IGNORE_UNUSED, 0), 3598 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo", 3599 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), 3600 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo", 3601 "div_pclk_apollo", ENABLE_PCLK_APOLLO, 3602 0, CLK_IGNORE_UNUSED, 0), 3603 3604 /* ENABLE_SCLK_APOLLO */ 3605 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo", 3606 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), 3607 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", 3608 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), 3609 }; 3610 3611 #define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \ 3612 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \ 3613 ((pclk) << 12) | ((aclk) << 8)) 3614 3615 #define E5433_APOLLO_DIV1(hpm, copy) \ 3616 (((hpm) << 4) | ((copy) << 0)) 3617 3618 static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = { 3619 { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3620 { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3621 { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3622 { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3623 { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3624 { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3625 { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3626 { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3627 { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3628 { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3629 { 0 }, 3630 }; 3631 3632 static void __init exynos5433_cmu_apollo_init(struct device_node *np) 3633 { 3634 void __iomem *reg_base; 3635 struct samsung_clk_provider *ctx; 3636 3637 reg_base = of_iomap(np, 0); 3638 if (!reg_base) { 3639 panic("%s: failed to map registers\n", __func__); 3640 return; 3641 } 3642 3643 ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK); 3644 if (!ctx) { 3645 panic("%s: unable to allocate ctx\n", __func__); 3646 return; 3647 } 3648 3649 samsung_clk_register_pll(ctx, apollo_pll_clks, 3650 ARRAY_SIZE(apollo_pll_clks), reg_base); 3651 samsung_clk_register_mux(ctx, apollo_mux_clks, 3652 ARRAY_SIZE(apollo_mux_clks)); 3653 samsung_clk_register_div(ctx, apollo_div_clks, 3654 ARRAY_SIZE(apollo_div_clks)); 3655 samsung_clk_register_gate(ctx, apollo_gate_clks, 3656 ARRAY_SIZE(apollo_gate_clks)); 3657 3658 exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk", 3659 mout_apollo_p[0], mout_apollo_p[1], 0x200, 3660 exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d), 3661 CLK_CPU_HAS_E5433_REGS_LAYOUT); 3662 3663 samsung_clk_sleep_init(reg_base, apollo_clk_regs, 3664 ARRAY_SIZE(apollo_clk_regs)); 3665 3666 samsung_clk_of_add_provider(np, ctx); 3667 } 3668 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", 3669 exynos5433_cmu_apollo_init); 3670 3671 /* 3672 * Register offset definitions for CMU_ATLAS 3673 */ 3674 #define ATLAS_PLL_LOCK 0x0000 3675 #define ATLAS_PLL_CON0 0x0100 3676 #define ATLAS_PLL_CON1 0x0104 3677 #define ATLAS_PLL_FREQ_DET 0x010c 3678 #define MUX_SEL_ATLAS0 0x0200 3679 #define MUX_SEL_ATLAS1 0x0204 3680 #define MUX_SEL_ATLAS2 0x0208 3681 #define MUX_ENABLE_ATLAS0 0x0300 3682 #define MUX_ENABLE_ATLAS1 0x0304 3683 #define MUX_ENABLE_ATLAS2 0x0308 3684 #define MUX_STAT_ATLAS0 0x0400 3685 #define MUX_STAT_ATLAS1 0x0404 3686 #define MUX_STAT_ATLAS2 0x0408 3687 #define DIV_ATLAS0 0x0600 3688 #define DIV_ATLAS1 0x0604 3689 #define DIV_ATLAS_PLL_FREQ_DET 0x0608 3690 #define DIV_STAT_ATLAS0 0x0700 3691 #define DIV_STAT_ATLAS1 0x0704 3692 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708 3693 #define ENABLE_ACLK_ATLAS 0x0800 3694 #define ENABLE_PCLK_ATLAS 0x0900 3695 #define ENABLE_SCLK_ATLAS 0x0a00 3696 #define ENABLE_IP_ATLAS0 0x0b00 3697 #define ENABLE_IP_ATLAS1 0x0b04 3698 #define CLKOUT_CMU_ATLAS 0x0c00 3699 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04 3700 #define ARMCLK_STOPCTRL 0x1000 3701 #define ATLAS_PWR_CTRL 0x1020 3702 #define ATLAS_PWR_CTRL2 0x1024 3703 #define ATLAS_INTR_SPREAD_ENABLE 0x1080 3704 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084 3705 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088 3706 3707 static const unsigned long atlas_clk_regs[] __initconst = { 3708 ATLAS_PLL_LOCK, 3709 ATLAS_PLL_CON0, 3710 ATLAS_PLL_CON1, 3711 ATLAS_PLL_FREQ_DET, 3712 MUX_SEL_ATLAS0, 3713 MUX_SEL_ATLAS1, 3714 MUX_SEL_ATLAS2, 3715 MUX_ENABLE_ATLAS0, 3716 MUX_ENABLE_ATLAS1, 3717 MUX_ENABLE_ATLAS2, 3718 DIV_ATLAS0, 3719 DIV_ATLAS1, 3720 DIV_ATLAS_PLL_FREQ_DET, 3721 ENABLE_ACLK_ATLAS, 3722 ENABLE_PCLK_ATLAS, 3723 ENABLE_SCLK_ATLAS, 3724 ENABLE_IP_ATLAS0, 3725 ENABLE_IP_ATLAS1, 3726 CLKOUT_CMU_ATLAS, 3727 CLKOUT_CMU_ATLAS_DIV_STAT, 3728 ARMCLK_STOPCTRL, 3729 ATLAS_PWR_CTRL, 3730 ATLAS_PWR_CTRL2, 3731 ATLAS_INTR_SPREAD_ENABLE, 3732 ATLAS_INTR_SPREAD_USE_STANDBYWFI, 3733 ATLAS_INTR_SPREAD_BLOCKING_DURATION, 3734 }; 3735 3736 /* list of all parent clock list */ 3737 PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", }; 3738 PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", }; 3739 PNAME(mout_atlas_p) = { "mout_atlas_pll", 3740 "mout_bus_pll_atlas_user", }; 3741 3742 static const struct samsung_pll_clock atlas_pll_clks[] __initconst = { 3743 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk", 3744 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates), 3745 }; 3746 3747 static const struct samsung_mux_clock atlas_mux_clks[] __initconst = { 3748 /* MUX_SEL_ATLAS0 */ 3749 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, 3750 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT | 3751 CLK_RECALC_NEW_RATES, 0), 3752 3753 /* MUX_SEL_ATLAS1 */ 3754 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user", 3755 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1), 3756 3757 /* MUX_SEL_ATLAS2 */ 3758 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2, 3759 0, 1, CLK_SET_RATE_PARENT, 0), 3760 }; 3761 3762 static const struct samsung_div_clock atlas_div_clks[] __initconst = { 3763 /* DIV_ATLAS0 */ 3764 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2", 3765 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE, 3766 CLK_DIVIDER_READ_ONLY), 3767 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas", 3768 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE, 3769 CLK_DIVIDER_READ_ONLY), 3770 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2", 3771 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE, 3772 CLK_DIVIDER_READ_ONLY), 3773 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2", 3774 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE, 3775 CLK_DIVIDER_READ_ONLY), 3776 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2", 3777 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE, 3778 CLK_DIVIDER_READ_ONLY), 3779 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1", 3780 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0), 3781 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas", 3782 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0), 3783 3784 /* DIV_ATLAS1 */ 3785 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas", 3786 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE, 3787 CLK_DIVIDER_READ_ONLY), 3788 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas", 3789 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE, 3790 CLK_DIVIDER_READ_ONLY), 3791 }; 3792 3793 static const struct samsung_gate_clock atlas_gate_clks[] __initconst = { 3794 /* ENABLE_ACLK_ATLAS */ 3795 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys", 3796 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3797 9, CLK_IGNORE_UNUSED, 0), 3798 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys", 3799 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3800 8, CLK_IGNORE_UNUSED, 0), 3801 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys", 3802 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3803 7, CLK_IGNORE_UNUSED, 0), 3804 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys", 3805 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3806 6, CLK_IGNORE_UNUSED, 0), 3807 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys", 3808 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3809 5, CLK_IGNORE_UNUSED, 0), 3810 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss", 3811 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3812 4, CLK_IGNORE_UNUSED, 0), 3813 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix", 3814 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS, 3815 3, CLK_IGNORE_UNUSED, 0), 3816 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci", 3817 "div_aclk_atlas", ENABLE_ACLK_ATLAS, 3818 2, CLK_IGNORE_UNUSED, 0), 3819 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas", 3820 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3821 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas", 3822 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), 3823 3824 /* ENABLE_PCLK_ATLAS */ 3825 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys", 3826 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3827 5, CLK_IGNORE_UNUSED, 0), 3828 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys", 3829 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3830 4, CLK_IGNORE_UNUSED, 0), 3831 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys", 3832 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3833 3, CLK_IGNORE_UNUSED, 0), 3834 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas", 3835 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), 3836 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas", 3837 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3838 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas", 3839 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), 3840 3841 /* ENABLE_SCLK_ATLAS */ 3842 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas", 3843 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0), 3844 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas", 3845 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0), 3846 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas", 3847 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0), 3848 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas", 3849 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0), 3850 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas", 3851 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0), 3852 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas", 3853 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0), 3854 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas", 3855 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), 3856 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas", 3857 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3858 }; 3859 3860 #define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \ 3861 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \ 3862 ((pclk) << 12) | ((aclk) << 8)) 3863 3864 #define E5433_ATLAS_DIV1(hpm, copy) \ 3865 (((hpm) << 4) | ((copy) << 0)) 3866 3867 static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = { 3868 { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3869 { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3870 { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3871 { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3872 { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3873 { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3874 { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3875 { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3876 { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3877 { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3878 { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3879 { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3880 { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3881 { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3882 { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3883 { 0 }, 3884 }; 3885 3886 static void __init exynos5433_cmu_atlas_init(struct device_node *np) 3887 { 3888 void __iomem *reg_base; 3889 struct samsung_clk_provider *ctx; 3890 3891 reg_base = of_iomap(np, 0); 3892 if (!reg_base) { 3893 panic("%s: failed to map registers\n", __func__); 3894 return; 3895 } 3896 3897 ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK); 3898 if (!ctx) { 3899 panic("%s: unable to allocate ctx\n", __func__); 3900 return; 3901 } 3902 3903 samsung_clk_register_pll(ctx, atlas_pll_clks, 3904 ARRAY_SIZE(atlas_pll_clks), reg_base); 3905 samsung_clk_register_mux(ctx, atlas_mux_clks, 3906 ARRAY_SIZE(atlas_mux_clks)); 3907 samsung_clk_register_div(ctx, atlas_div_clks, 3908 ARRAY_SIZE(atlas_div_clks)); 3909 samsung_clk_register_gate(ctx, atlas_gate_clks, 3910 ARRAY_SIZE(atlas_gate_clks)); 3911 3912 exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk", 3913 mout_atlas_p[0], mout_atlas_p[1], 0x200, 3914 exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d), 3915 CLK_CPU_HAS_E5433_REGS_LAYOUT); 3916 3917 samsung_clk_sleep_init(reg_base, atlas_clk_regs, 3918 ARRAY_SIZE(atlas_clk_regs)); 3919 3920 samsung_clk_of_add_provider(np, ctx); 3921 } 3922 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", 3923 exynos5433_cmu_atlas_init); 3924 3925 /* 3926 * Register offset definitions for CMU_MSCL 3927 */ 3928 #define MUX_SEL_MSCL0 0x0200 3929 #define MUX_SEL_MSCL1 0x0204 3930 #define MUX_ENABLE_MSCL0 0x0300 3931 #define MUX_ENABLE_MSCL1 0x0304 3932 #define MUX_STAT_MSCL0 0x0400 3933 #define MUX_STAT_MSCL1 0x0404 3934 #define DIV_MSCL 0x0600 3935 #define DIV_STAT_MSCL 0x0700 3936 #define ENABLE_ACLK_MSCL 0x0800 3937 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804 3938 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808 3939 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c 3940 #define ENABLE_PCLK_MSCL 0x0900 3941 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904 3942 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908 3943 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c 3944 #define ENABLE_SCLK_MSCL 0x0a00 3945 #define ENABLE_IP_MSCL0 0x0b00 3946 #define ENABLE_IP_MSCL1 0x0b04 3947 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08 3948 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c 3949 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10 3950 3951 static const unsigned long mscl_clk_regs[] __initconst = { 3952 MUX_SEL_MSCL0, 3953 MUX_SEL_MSCL1, 3954 MUX_ENABLE_MSCL0, 3955 MUX_ENABLE_MSCL1, 3956 DIV_MSCL, 3957 ENABLE_ACLK_MSCL, 3958 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, 3959 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, 3960 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG, 3961 ENABLE_PCLK_MSCL, 3962 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0, 3963 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1, 3964 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG, 3965 ENABLE_SCLK_MSCL, 3966 ENABLE_IP_MSCL0, 3967 ENABLE_IP_MSCL1, 3968 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0, 3969 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1, 3970 ENABLE_IP_MSCL_SECURE_SMMU_JPEG, 3971 }; 3972 3973 /* list of all parent clock list */ 3974 PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", }; 3975 PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", }; 3976 PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user", 3977 "mout_aclk_mscl_400_user", }; 3978 3979 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = { 3980 /* MUX_SEL_MSCL0 */ 3981 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user", 3982 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1), 3983 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user", 3984 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1), 3985 3986 /* MUX_SEL_MSCL1 */ 3987 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p, 3988 MUX_SEL_MSCL1, 0, 1), 3989 }; 3990 3991 static const struct samsung_div_clock mscl_div_clks[] __initconst = { 3992 /* DIV_MSCL */ 3993 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user", 3994 DIV_MSCL, 0, 3), 3995 }; 3996 3997 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = { 3998 /* ENABLE_ACLK_MSCL */ 3999 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user", 4000 ENABLE_ACLK_MSCL, 9, 0, 0), 4001 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1", 4002 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0), 4003 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0", 4004 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0), 4005 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl", 4006 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0), 4007 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user", 4008 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0), 4009 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl", 4010 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0), 4011 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user", 4012 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0), 4013 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user", 4014 ENABLE_ACLK_MSCL, 2, 0, 0), 4015 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user", 4016 ENABLE_ACLK_MSCL, 1, 0, 0), 4017 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user", 4018 ENABLE_ACLK_MSCL, 0, 0, 0), 4019 4020 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */ 4021 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0", 4022 "mout_aclk_mscl_400_user", 4023 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, 4024 0, CLK_IGNORE_UNUSED, 0), 4025 4026 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */ 4027 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1", 4028 "mout_aclk_mscl_400_user", 4029 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, 4030 0, CLK_IGNORE_UNUSED, 0), 4031 4032 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */ 4033 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user", 4034 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG, 4035 0, CLK_IGNORE_UNUSED, 0), 4036 4037 /* ENABLE_PCLK_MSCL */ 4038 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl", 4039 ENABLE_PCLK_MSCL, 7, 0, 0), 4040 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl", 4041 ENABLE_PCLK_MSCL, 6, 0, 0), 4042 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl", 4043 ENABLE_PCLK_MSCL, 5, 0, 0), 4044 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl", 4045 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0), 4046 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl", 4047 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0), 4048 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl", 4049 ENABLE_PCLK_MSCL, 2, 0, 0), 4050 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl", 4051 ENABLE_PCLK_MSCL, 1, 0, 0), 4052 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl", 4053 ENABLE_PCLK_MSCL, 0, 0, 0), 4054 4055 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */ 4056 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl", 4057 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0, 4058 0, CLK_IGNORE_UNUSED, 0), 4059 4060 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */ 4061 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl", 4062 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1, 4063 0, CLK_IGNORE_UNUSED, 0), 4064 4065 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */ 4066 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl", 4067 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG, 4068 0, CLK_IGNORE_UNUSED, 0), 4069 4070 /* ENABLE_SCLK_MSCL */ 4071 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0, 4072 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 4073 }; 4074 4075 static const struct samsung_cmu_info mscl_cmu_info __initconst = { 4076 .mux_clks = mscl_mux_clks, 4077 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 4078 .div_clks = mscl_div_clks, 4079 .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 4080 .gate_clks = mscl_gate_clks, 4081 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 4082 .nr_clk_ids = MSCL_NR_CLK, 4083 .clk_regs = mscl_clk_regs, 4084 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 4085 }; 4086 4087 static void __init exynos5433_cmu_mscl_init(struct device_node *np) 4088 { 4089 samsung_cmu_register_one(np, &mscl_cmu_info); 4090 } 4091 CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl", 4092 exynos5433_cmu_mscl_init); 4093 4094 /* 4095 * Register offset definitions for CMU_MFC 4096 */ 4097 #define MUX_SEL_MFC 0x0200 4098 #define MUX_ENABLE_MFC 0x0300 4099 #define MUX_STAT_MFC 0x0400 4100 #define DIV_MFC 0x0600 4101 #define DIV_STAT_MFC 0x0700 4102 #define ENABLE_ACLK_MFC 0x0800 4103 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804 4104 #define ENABLE_PCLK_MFC 0x0900 4105 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904 4106 #define ENABLE_IP_MFC0 0x0b00 4107 #define ENABLE_IP_MFC1 0x0b04 4108 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08 4109 4110 static const unsigned long mfc_clk_regs[] __initconst = { 4111 MUX_SEL_MFC, 4112 MUX_ENABLE_MFC, 4113 DIV_MFC, 4114 ENABLE_ACLK_MFC, 4115 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4116 ENABLE_PCLK_MFC, 4117 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4118 ENABLE_IP_MFC0, 4119 ENABLE_IP_MFC1, 4120 ENABLE_IP_MFC_SECURE_SMMU_MFC, 4121 }; 4122 4123 PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", }; 4124 4125 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { 4126 /* MUX_SEL_MFC */ 4127 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user", 4128 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0), 4129 }; 4130 4131 static const struct samsung_div_clock mfc_div_clks[] __initconst = { 4132 /* DIV_MFC */ 4133 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user", 4134 DIV_MFC, 0, 2), 4135 }; 4136 4137 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { 4138 /* ENABLE_ACLK_MFC */ 4139 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user", 4140 ENABLE_ACLK_MFC, 6, 0, 0), 4141 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user", 4142 ENABLE_ACLK_MFC, 5, 0, 0), 4143 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc", 4144 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0), 4145 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user", 4146 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0), 4147 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc", 4148 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0), 4149 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user", 4150 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0), 4151 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user", 4152 ENABLE_ACLK_MFC, 0, 0, 0), 4153 4154 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */ 4155 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user", 4156 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4157 1, CLK_IGNORE_UNUSED, 0), 4158 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user", 4159 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4160 0, CLK_IGNORE_UNUSED, 0), 4161 4162 /* ENABLE_PCLK_MFC */ 4163 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc", 4164 ENABLE_PCLK_MFC, 4, 0, 0), 4165 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc", 4166 ENABLE_PCLK_MFC, 3, 0, 0), 4167 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc", 4168 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0), 4169 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc", 4170 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0), 4171 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc", 4172 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0), 4173 4174 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */ 4175 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc", 4176 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4177 1, CLK_IGNORE_UNUSED, 0), 4178 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc", 4179 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4180 0, CLK_IGNORE_UNUSED, 0), 4181 }; 4182 4183 static const struct samsung_cmu_info mfc_cmu_info __initconst = { 4184 .mux_clks = mfc_mux_clks, 4185 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), 4186 .div_clks = mfc_div_clks, 4187 .nr_div_clks = ARRAY_SIZE(mfc_div_clks), 4188 .gate_clks = mfc_gate_clks, 4189 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), 4190 .nr_clk_ids = MFC_NR_CLK, 4191 .clk_regs = mfc_clk_regs, 4192 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), 4193 }; 4194 4195 static void __init exynos5433_cmu_mfc_init(struct device_node *np) 4196 { 4197 samsung_cmu_register_one(np, &mfc_cmu_info); 4198 } 4199 CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc", 4200 exynos5433_cmu_mfc_init); 4201 4202 /* 4203 * Register offset definitions for CMU_HEVC 4204 */ 4205 #define MUX_SEL_HEVC 0x0200 4206 #define MUX_ENABLE_HEVC 0x0300 4207 #define MUX_STAT_HEVC 0x0400 4208 #define DIV_HEVC 0x0600 4209 #define DIV_STAT_HEVC 0x0700 4210 #define ENABLE_ACLK_HEVC 0x0800 4211 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804 4212 #define ENABLE_PCLK_HEVC 0x0900 4213 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904 4214 #define ENABLE_IP_HEVC0 0x0b00 4215 #define ENABLE_IP_HEVC1 0x0b04 4216 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08 4217 4218 static const unsigned long hevc_clk_regs[] __initconst = { 4219 MUX_SEL_HEVC, 4220 MUX_ENABLE_HEVC, 4221 DIV_HEVC, 4222 ENABLE_ACLK_HEVC, 4223 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4224 ENABLE_PCLK_HEVC, 4225 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4226 ENABLE_IP_HEVC0, 4227 ENABLE_IP_HEVC1, 4228 ENABLE_IP_HEVC_SECURE_SMMU_HEVC, 4229 }; 4230 4231 PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", }; 4232 4233 static const struct samsung_mux_clock hevc_mux_clks[] __initconst = { 4234 /* MUX_SEL_HEVC */ 4235 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user", 4236 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0), 4237 }; 4238 4239 static const struct samsung_div_clock hevc_div_clks[] __initconst = { 4240 /* DIV_HEVC */ 4241 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user", 4242 DIV_HEVC, 0, 2), 4243 }; 4244 4245 static const struct samsung_gate_clock hevc_gate_clks[] __initconst = { 4246 /* ENABLE_ACLK_HEVC */ 4247 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user", 4248 ENABLE_ACLK_HEVC, 6, 0, 0), 4249 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user", 4250 ENABLE_ACLK_HEVC, 5, 0, 0), 4251 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc", 4252 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0), 4253 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user", 4254 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0), 4255 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc", 4256 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0), 4257 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user", 4258 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0), 4259 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user", 4260 ENABLE_ACLK_HEVC, 0, 0, 0), 4261 4262 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */ 4263 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1", 4264 "mout_aclk_hevc_400_user", 4265 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4266 1, CLK_IGNORE_UNUSED, 0), 4267 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0", 4268 "mout_aclk_hevc_400_user", 4269 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4270 0, CLK_IGNORE_UNUSED, 0), 4271 4272 /* ENABLE_PCLK_HEVC */ 4273 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc", 4274 ENABLE_PCLK_HEVC, 4, 0, 0), 4275 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc", 4276 ENABLE_PCLK_HEVC, 3, 0, 0), 4277 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc", 4278 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0), 4279 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc", 4280 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0), 4281 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc", 4282 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0), 4283 4284 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */ 4285 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc", 4286 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4287 1, CLK_IGNORE_UNUSED, 0), 4288 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc", 4289 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4290 0, CLK_IGNORE_UNUSED, 0), 4291 }; 4292 4293 static const struct samsung_cmu_info hevc_cmu_info __initconst = { 4294 .mux_clks = hevc_mux_clks, 4295 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks), 4296 .div_clks = hevc_div_clks, 4297 .nr_div_clks = ARRAY_SIZE(hevc_div_clks), 4298 .gate_clks = hevc_gate_clks, 4299 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks), 4300 .nr_clk_ids = HEVC_NR_CLK, 4301 .clk_regs = hevc_clk_regs, 4302 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs), 4303 }; 4304 4305 static void __init exynos5433_cmu_hevc_init(struct device_node *np) 4306 { 4307 samsung_cmu_register_one(np, &hevc_cmu_info); 4308 } 4309 CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc", 4310 exynos5433_cmu_hevc_init); 4311 4312 /* 4313 * Register offset definitions for CMU_ISP 4314 */ 4315 #define MUX_SEL_ISP 0x0200 4316 #define MUX_ENABLE_ISP 0x0300 4317 #define MUX_STAT_ISP 0x0400 4318 #define DIV_ISP 0x0600 4319 #define DIV_STAT_ISP 0x0700 4320 #define ENABLE_ACLK_ISP0 0x0800 4321 #define ENABLE_ACLK_ISP1 0x0804 4322 #define ENABLE_ACLK_ISP2 0x0808 4323 #define ENABLE_PCLK_ISP 0x0900 4324 #define ENABLE_SCLK_ISP 0x0a00 4325 #define ENABLE_IP_ISP0 0x0b00 4326 #define ENABLE_IP_ISP1 0x0b04 4327 #define ENABLE_IP_ISP2 0x0b08 4328 #define ENABLE_IP_ISP3 0x0b0c 4329 4330 static const unsigned long isp_clk_regs[] __initconst = { 4331 MUX_SEL_ISP, 4332 MUX_ENABLE_ISP, 4333 DIV_ISP, 4334 ENABLE_ACLK_ISP0, 4335 ENABLE_ACLK_ISP1, 4336 ENABLE_ACLK_ISP2, 4337 ENABLE_PCLK_ISP, 4338 ENABLE_SCLK_ISP, 4339 ENABLE_IP_ISP0, 4340 ENABLE_IP_ISP1, 4341 ENABLE_IP_ISP2, 4342 ENABLE_IP_ISP3, 4343 }; 4344 4345 PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", }; 4346 PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", }; 4347 4348 static const struct samsung_mux_clock isp_mux_clks[] __initconst = { 4349 /* MUX_SEL_ISP */ 4350 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user", 4351 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0), 4352 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user", 4353 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0), 4354 }; 4355 4356 static const struct samsung_div_clock isp_div_clks[] __initconst = { 4357 /* DIV_ISP */ 4358 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis", 4359 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3), 4360 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user", 4361 DIV_ISP, 8, 3), 4362 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200", 4363 "mout_aclk_isp_400_user", DIV_ISP, 4, 3), 4364 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200", 4365 "mout_aclk_isp_400_user", DIV_ISP, 0, 3), 4366 }; 4367 4368 static const struct samsung_gate_clock isp_gate_clks[] __initconst = { 4369 /* ENABLE_ACLK_ISP0 */ 4370 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user", 4371 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0), 4372 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user", 4373 ENABLE_ACLK_ISP0, 5, 0, 0), 4374 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user", 4375 ENABLE_ACLK_ISP0, 4, 0, 0), 4376 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user", 4377 ENABLE_ACLK_ISP0, 3, 0, 0), 4378 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user", 4379 ENABLE_ACLK_ISP0, 2, 0, 0), 4380 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user", 4381 ENABLE_ACLK_ISP0, 1, 0, 0), 4382 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user", 4383 ENABLE_ACLK_ISP0, 0, 0, 0), 4384 4385 /* ENABLE_ACLK_ISP1 */ 4386 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp", 4387 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4388 17, CLK_IGNORE_UNUSED, 0), 4389 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc", 4390 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4391 16, CLK_IGNORE_UNUSED, 0), 4392 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc", 4393 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4394 15, CLK_IGNORE_UNUSED, 0), 4395 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p", 4396 "div_pclk_isp", ENABLE_ACLK_ISP1, 4397 14, CLK_IGNORE_UNUSED, 0), 4398 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p", 4399 "div_pclk_isp", ENABLE_ACLK_ISP1, 4400 13, CLK_IGNORE_UNUSED, 0), 4401 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1", 4402 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, 4403 12, CLK_IGNORE_UNUSED, 0), 4404 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0", 4405 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, 4406 11, CLK_IGNORE_UNUSED, 0), 4407 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1", 4408 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4409 10, CLK_IGNORE_UNUSED, 0), 4410 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0", 4411 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4412 9, CLK_IGNORE_UNUSED, 0), 4413 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p", 4414 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, 4415 8, CLK_IGNORE_UNUSED, 0), 4416 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p", 4417 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, 4418 7, CLK_IGNORE_UNUSED, 0), 4419 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp", 4420 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0), 4421 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp", 4422 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0), 4423 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p", 4424 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, 4425 4, CLK_IGNORE_UNUSED, 0), 4426 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p", 4427 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, 4428 3, CLK_IGNORE_UNUSED, 0), 4429 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user", 4430 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0), 4431 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user", 4432 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), 4433 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user", 4434 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), 4435 4436 /* ENABLE_ACLK_ISP2 */ 4437 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp", 4438 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4439 13, CLK_IGNORE_UNUSED, 0), 4440 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user", 4441 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0), 4442 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user", 4443 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0), 4444 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user", 4445 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0), 4446 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc", 4447 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4448 9, CLK_IGNORE_UNUSED, 0), 4449 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user", 4450 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0), 4451 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user", 4452 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0), 4453 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp", 4454 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4455 6, CLK_IGNORE_UNUSED, 0), 4456 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user", 4457 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0), 4458 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user", 4459 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0), 4460 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user", 4461 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0), 4462 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc", 4463 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4464 2, CLK_IGNORE_UNUSED, 0), 4465 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user", 4466 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0), 4467 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user", 4468 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0), 4469 4470 /* ENABLE_PCLK_ISP */ 4471 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200", 4472 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0), 4473 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200", 4474 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0), 4475 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200", 4476 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0), 4477 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200", 4478 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0), 4479 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200", 4480 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0), 4481 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200", 4482 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0), 4483 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200", 4484 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0), 4485 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp", 4486 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0), 4487 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp", 4488 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0), 4489 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp", 4490 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0), 4491 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp", 4492 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0), 4493 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp", 4494 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0), 4495 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp", 4496 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0), 4497 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp", 4498 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0), 4499 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp", 4500 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0), 4501 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp", 4502 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0), 4503 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp", 4504 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0), 4505 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp", 4506 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0), 4507 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local", 4508 "div_aclk_isp_c_200", ENABLE_PCLK_ISP, 4509 7, CLK_IGNORE_UNUSED, 0), 4510 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200", 4511 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0), 4512 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200", 4513 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0), 4514 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis", 4515 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0), 4516 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200", 4517 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0), 4518 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200", 4519 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0), 4520 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200", 4521 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0), 4522 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200", 4523 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0), 4524 4525 /* ENABLE_SCLK_ISP */ 4526 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis", 4527 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, 4528 5, CLK_IGNORE_UNUSED, 0), 4529 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis", 4530 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, 4531 4, CLK_IGNORE_UNUSED, 0), 4532 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp", 4533 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4534 3, CLK_IGNORE_UNUSED, 0), 4535 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd", 4536 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4537 2, CLK_IGNORE_UNUSED, 0), 4538 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc", 4539 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4540 1, CLK_IGNORE_UNUSED, 0), 4541 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc", 4542 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4543 0, CLK_IGNORE_UNUSED, 0), 4544 }; 4545 4546 static const struct samsung_cmu_info isp_cmu_info __initconst = { 4547 .mux_clks = isp_mux_clks, 4548 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), 4549 .div_clks = isp_div_clks, 4550 .nr_div_clks = ARRAY_SIZE(isp_div_clks), 4551 .gate_clks = isp_gate_clks, 4552 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), 4553 .nr_clk_ids = ISP_NR_CLK, 4554 .clk_regs = isp_clk_regs, 4555 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), 4556 }; 4557 4558 static void __init exynos5433_cmu_isp_init(struct device_node *np) 4559 { 4560 samsung_cmu_register_one(np, &isp_cmu_info); 4561 } 4562 CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp", 4563 exynos5433_cmu_isp_init); 4564 4565 /* 4566 * Register offset definitions for CMU_CAM0 4567 */ 4568 #define MUX_SEL_CAM00 0x0200 4569 #define MUX_SEL_CAM01 0x0204 4570 #define MUX_SEL_CAM02 0x0208 4571 #define MUX_SEL_CAM03 0x020c 4572 #define MUX_SEL_CAM04 0x0210 4573 #define MUX_ENABLE_CAM00 0x0300 4574 #define MUX_ENABLE_CAM01 0x0304 4575 #define MUX_ENABLE_CAM02 0x0308 4576 #define MUX_ENABLE_CAM03 0x030c 4577 #define MUX_ENABLE_CAM04 0x0310 4578 #define MUX_STAT_CAM00 0x0400 4579 #define MUX_STAT_CAM01 0x0404 4580 #define MUX_STAT_CAM02 0x0408 4581 #define MUX_STAT_CAM03 0x040c 4582 #define MUX_STAT_CAM04 0x0410 4583 #define MUX_IGNORE_CAM01 0x0504 4584 #define DIV_CAM00 0x0600 4585 #define DIV_CAM01 0x0604 4586 #define DIV_CAM02 0x0608 4587 #define DIV_CAM03 0x060c 4588 #define DIV_STAT_CAM00 0x0700 4589 #define DIV_STAT_CAM01 0x0704 4590 #define DIV_STAT_CAM02 0x0708 4591 #define DIV_STAT_CAM03 0x070c 4592 #define ENABLE_ACLK_CAM00 0X0800 4593 #define ENABLE_ACLK_CAM01 0X0804 4594 #define ENABLE_ACLK_CAM02 0X0808 4595 #define ENABLE_PCLK_CAM0 0X0900 4596 #define ENABLE_SCLK_CAM0 0X0a00 4597 #define ENABLE_IP_CAM00 0X0b00 4598 #define ENABLE_IP_CAM01 0X0b04 4599 #define ENABLE_IP_CAM02 0X0b08 4600 #define ENABLE_IP_CAM03 0X0b0C 4601 4602 static const unsigned long cam0_clk_regs[] __initconst = { 4603 MUX_SEL_CAM00, 4604 MUX_SEL_CAM01, 4605 MUX_SEL_CAM02, 4606 MUX_SEL_CAM03, 4607 MUX_SEL_CAM04, 4608 MUX_ENABLE_CAM00, 4609 MUX_ENABLE_CAM01, 4610 MUX_ENABLE_CAM02, 4611 MUX_ENABLE_CAM03, 4612 MUX_ENABLE_CAM04, 4613 MUX_IGNORE_CAM01, 4614 DIV_CAM00, 4615 DIV_CAM01, 4616 DIV_CAM02, 4617 DIV_CAM03, 4618 ENABLE_ACLK_CAM00, 4619 ENABLE_ACLK_CAM01, 4620 ENABLE_ACLK_CAM02, 4621 ENABLE_PCLK_CAM0, 4622 ENABLE_SCLK_CAM0, 4623 ENABLE_IP_CAM00, 4624 ENABLE_IP_CAM01, 4625 ENABLE_IP_CAM02, 4626 ENABLE_IP_CAM03, 4627 }; 4628 PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", }; 4629 PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", }; 4630 PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", }; 4631 4632 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk", 4633 "phyclk_rxbyteclkhs0_s4_phy", }; 4634 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk", 4635 "phyclk_rxbyteclkhs0_s2a_phy", }; 4636 4637 PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a", 4638 "mout_aclk_cam0_333_user", }; 4639 PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user", 4640 "mout_aclk_cam0_400_user", }; 4641 PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a", 4642 "mout_aclk_cam0_333_user", }; 4643 PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user", 4644 "mout_aclk_cam0_400_user", }; 4645 PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a", 4646 "mout_aclk_cam0_333_user", }; 4647 PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user", 4648 "mout_aclk_cam0_400_user", }; 4649 PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user", 4650 "mout_aclk_cam0_333_user", }; 4651 4652 PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a", 4653 "mout_aclk_cam0_333_user" }; 4654 PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user", 4655 "mout_aclk_cam0_400_user", }; 4656 PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a", 4657 "mout_aclk_cam0_333_user", }; 4658 PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user", 4659 "mout_aclk-cam0_400_user", }; 4660 PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a", 4661 "mout_aclk_cam0_333_user", }; 4662 PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user", 4663 "mout_aclk_cam0_400_user", }; 4664 PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a", 4665 "mout_aclk_cam0_333_user", }; 4666 PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user", 4667 "mout_aclk_cam0_400_user", }; 4668 4669 PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b", 4670 "div_pclk_lite_d", }; 4671 PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a", 4672 "div_pclk_pixelasync_lite_c", }; 4673 PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a", 4674 "div_pclk_lite_b", }; 4675 PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a", 4676 "mout_aclk_cam0_333_user", }; 4677 PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user", 4678 "mout_aclk_cam0_400_user", }; 4679 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = { 4680 "mout_sclk_pixelasync_lite_c_init_a", 4681 "mout_aclk_cam0_400_user", }; 4682 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = { 4683 "mout_aclk_cam0_552_user", 4684 "mout_aclk_cam0_400_user", }; 4685 4686 static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = { 4687 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy", 4688 NULL, 0, 100000000), 4689 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy", 4690 NULL, 0, 100000000), 4691 }; 4692 4693 static const struct samsung_mux_clock cam0_mux_clks[] __initconst = { 4694 /* MUX_SEL_CAM00 */ 4695 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user", 4696 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1), 4697 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user", 4698 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1), 4699 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user", 4700 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1), 4701 4702 /* MUX_SEL_CAM01 */ 4703 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER, 4704 "mout_phyclk_rxbyteclkhs0_s4_user", 4705 mout_phyclk_rxbyteclkhs0_s4_user_p, 4706 MUX_SEL_CAM01, 4, 1), 4707 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER, 4708 "mout_phyclk_rxbyteclkhs0_s2a_user", 4709 mout_phyclk_rxbyteclkhs0_s2a_user_p, 4710 MUX_SEL_CAM01, 0, 1), 4711 4712 /* MUX_SEL_CAM02 */ 4713 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p, 4714 MUX_SEL_CAM02, 24, 1), 4715 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p, 4716 MUX_SEL_CAM02, 20, 1), 4717 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p, 4718 MUX_SEL_CAM02, 16, 1), 4719 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p, 4720 MUX_SEL_CAM02, 12, 1), 4721 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p, 4722 MUX_SEL_CAM02, 8, 1), 4723 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p, 4724 MUX_SEL_CAM02, 4, 1), 4725 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p, 4726 MUX_SEL_CAM02, 0, 1), 4727 4728 /* MUX_SEL_CAM03 */ 4729 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p, 4730 MUX_SEL_CAM03, 28, 1), 4731 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p, 4732 MUX_SEL_CAM03, 24, 1), 4733 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p, 4734 MUX_SEL_CAM03, 20, 1), 4735 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p, 4736 MUX_SEL_CAM03, 16, 1), 4737 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p, 4738 MUX_SEL_CAM03, 12, 1), 4739 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p, 4740 MUX_SEL_CAM03, 8, 1), 4741 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p, 4742 MUX_SEL_CAM03, 4, 1), 4743 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p, 4744 MUX_SEL_CAM03, 0, 1), 4745 4746 /* MUX_SEL_CAM04 */ 4747 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c", 4748 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1), 4749 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b", 4750 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1), 4751 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a", 4752 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1), 4753 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b", 4754 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1), 4755 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a", 4756 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1), 4757 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B, 4758 "mout_sclk_pixelasync_lite_c_init_b", 4759 mout_sclk_pixelasync_lite_c_init_b_p, 4760 MUX_SEL_CAM04, 4, 1), 4761 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A, 4762 "mout_sclk_pixelasync_lite_c_init_a", 4763 mout_sclk_pixelasync_lite_c_init_a_p, 4764 MUX_SEL_CAM04, 0, 1), 4765 }; 4766 4767 static const struct samsung_div_clock cam0_div_clks[] __initconst = { 4768 /* DIV_CAM00 */ 4769 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200", 4770 DIV_CAM00, 8, 2), 4771 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400", 4772 DIV_CAM00, 4, 3), 4773 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400", 4774 "mout_aclk_cam0_400", DIV_CAM00, 0, 3), 4775 4776 /* DIV_CAM01 */ 4777 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d", 4778 DIV_CAM01, 20, 2), 4779 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b", 4780 DIV_CAM01, 16, 3), 4781 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b", 4782 DIV_CAM01, 12, 2), 4783 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b", 4784 DIV_CAM01, 8, 3), 4785 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a", 4786 DIV_CAM01, 4, 2), 4787 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b", 4788 DIV_CAM01, 0, 3), 4789 4790 /* DIV_CAM02 */ 4791 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b", 4792 DIV_CAM02, 20, 3), 4793 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b", 4794 DIV_CAM02, 16, 3), 4795 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1", 4796 DIV_CAM02, 12, 2), 4797 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b", 4798 DIV_CAM02, 8, 3), 4799 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0", 4800 DIV_CAM02, 4, 2), 4801 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b", 4802 DIV_CAM02, 0, 3), 4803 4804 /* DIV_CAM03 */ 4805 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c", 4806 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3), 4807 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c", 4808 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2), 4809 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT, 4810 "div_sclk_pixelasync_lite_c_init", 4811 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3), 4812 }; 4813 4814 static const struct samsung_gate_clock cam0_gate_clks[] __initconst = { 4815 /* ENABLE_ACLK_CAM00 */ 4816 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00, 4817 6, 0, 0), 4818 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00, 4819 5, 0, 0), 4820 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00, 4821 4, 0, 0), 4822 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00, 4823 3, 0, 0), 4824 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d", 4825 ENABLE_ACLK_CAM00, 2, 0, 0), 4826 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b", 4827 ENABLE_ACLK_CAM00, 1, 0, 0), 4828 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a", 4829 ENABLE_ACLK_CAM00, 0, 0, 0), 4830 4831 /* ENABLE_ACLK_CAM01 */ 4832 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200", 4833 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0), 4834 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400", 4835 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0), 4836 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400", 4837 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0), 4838 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400", 4839 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0), 4840 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1", 4841 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0), 4842 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1", 4843 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0), 4844 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0", 4845 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0), 4846 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0", 4847 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0), 4848 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d", 4849 "div_pclk_lite_d", ENABLE_ACLK_CAM01, 4850 23, CLK_IGNORE_UNUSED, 0), 4851 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d", 4852 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4853 22, CLK_IGNORE_UNUSED, 0), 4854 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b", 4855 "div_pclk_lite_b", ENABLE_ACLK_CAM01, 4856 21, CLK_IGNORE_UNUSED, 0), 4857 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b", 4858 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4859 20, CLK_IGNORE_UNUSED, 0), 4860 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a", 4861 "div_pclk_lite_a", ENABLE_ACLK_CAM01, 4862 19, CLK_IGNORE_UNUSED, 0), 4863 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a", 4864 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4865 18, CLK_IGNORE_UNUSED, 0), 4866 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p", 4867 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4868 17, CLK_IGNORE_UNUSED, 0), 4869 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1", 4870 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4871 16, CLK_IGNORE_UNUSED, 0), 4872 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1", 4873 "div_aclk_3aa1", ENABLE_ACLK_CAM01, 4874 15, CLK_IGNORE_UNUSED, 0), 4875 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0", 4876 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4877 14, CLK_IGNORE_UNUSED, 0), 4878 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0", 4879 "div_aclk_3aa0", ENABLE_ACLK_CAM01, 4880 13, CLK_IGNORE_UNUSED, 0), 4881 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d", 4882 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4883 12, CLK_IGNORE_UNUSED, 0), 4884 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d", 4885 "div_aclk_lite_d", ENABLE_ACLK_CAM01, 4886 11, CLK_IGNORE_UNUSED, 0), 4887 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b", 4888 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4889 10, CLK_IGNORE_UNUSED, 0), 4890 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b", 4891 "div_aclk_lite_b", ENABLE_ACLK_CAM01, 4892 9, CLK_IGNORE_UNUSED, 0), 4893 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a", 4894 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4895 8, CLK_IGNORE_UNUSED, 0), 4896 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a", 4897 "div_aclk_lite_a", ENABLE_ACLK_CAM01, 4898 7, CLK_IGNORE_UNUSED, 0), 4899 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp", 4900 "div_pclk_cam0_50", ENABLE_ACLK_CAM01, 4901 6, CLK_IGNORE_UNUSED, 0), 4902 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200", 4903 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0), 4904 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200", 4905 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0), 4906 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200", 4907 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0), 4908 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400", 4909 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0), 4910 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200", 4911 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0), 4912 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400", 4913 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0), 4914 4915 /* ENABLE_ACLK_CAM02 */ 4916 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400", 4917 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0), 4918 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400", 4919 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0), 4920 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400", 4921 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0), 4922 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400", 4923 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0), 4924 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400", 4925 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0), 4926 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400", 4927 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0), 4928 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400", 4929 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0), 4930 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400", 4931 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0), 4932 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400", 4933 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0), 4934 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400", 4935 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0), 4936 4937 /* ENABLE_PCLK_CAM0 */ 4938 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200", 4939 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0), 4940 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200", 4941 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0), 4942 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200", 4943 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0), 4944 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200", 4945 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0), 4946 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200", 4947 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0), 4948 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50", 4949 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0), 4950 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50", 4951 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0), 4952 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50", 4953 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0), 4954 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50", 4955 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0), 4956 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50", 4957 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0), 4958 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50", 4959 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0), 4960 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50", 4961 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0), 4962 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50", 4963 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0), 4964 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d", 4965 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 4966 12, CLK_IGNORE_UNUSED, 0), 4967 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b", 4968 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 4969 11, CLK_IGNORE_UNUSED, 0), 4970 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a", 4971 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 4972 10, CLK_IGNORE_UNUSED, 0), 4973 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50", 4974 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0), 4975 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50", 4976 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0), 4977 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local", 4978 "div_aclk_cam0_200", ENABLE_PCLK_CAM0, 4979 7, CLK_IGNORE_UNUSED, 0), 4980 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200", 4981 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0), 4982 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200", 4983 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0), 4984 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1", 4985 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0), 4986 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0", 4987 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0), 4988 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d", 4989 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0), 4990 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b", 4991 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0), 4992 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a", 4993 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0), 4994 4995 /* ENABLE_SCLK_CAM0 */ 4996 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4", 4997 "mout_phyclk_rxbyteclkhs0_s4_user", 4998 ENABLE_SCLK_CAM0, 8, 0, 0), 4999 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a", 5000 "mout_phyclk_rxbyteclkhs0_s2a_user", 5001 ENABLE_SCLK_CAM0, 7, 0, 0), 5002 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt", 5003 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0), 5004 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1", 5005 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0), 5006 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0", 5007 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0), 5008 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0", 5009 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0), 5010 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c", 5011 "div_sclk_pixelasync_lite_c", 5012 ENABLE_SCLK_CAM0, 2, 0, 0), 5013 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init", 5014 "div_sclk_pixelasync_lite_c_init", 5015 ENABLE_SCLK_CAM0, 1, 0, 0), 5016 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init", 5017 "div_sclk_pixelasync_lite_c", 5018 ENABLE_SCLK_CAM0, 0, 0, 0), 5019 }; 5020 5021 static const struct samsung_cmu_info cam0_cmu_info __initconst = { 5022 .mux_clks = cam0_mux_clks, 5023 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks), 5024 .div_clks = cam0_div_clks, 5025 .nr_div_clks = ARRAY_SIZE(cam0_div_clks), 5026 .gate_clks = cam0_gate_clks, 5027 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks), 5028 .fixed_clks = cam0_fixed_clks, 5029 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks), 5030 .nr_clk_ids = CAM0_NR_CLK, 5031 .clk_regs = cam0_clk_regs, 5032 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs), 5033 }; 5034 5035 static void __init exynos5433_cmu_cam0_init(struct device_node *np) 5036 { 5037 samsung_cmu_register_one(np, &cam0_cmu_info); 5038 } 5039 CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0", 5040 exynos5433_cmu_cam0_init); 5041 5042 /* 5043 * Register offset definitions for CMU_CAM1 5044 */ 5045 #define MUX_SEL_CAM10 0x0200 5046 #define MUX_SEL_CAM11 0x0204 5047 #define MUX_SEL_CAM12 0x0208 5048 #define MUX_ENABLE_CAM10 0x0300 5049 #define MUX_ENABLE_CAM11 0x0304 5050 #define MUX_ENABLE_CAM12 0x0308 5051 #define MUX_STAT_CAM10 0x0400 5052 #define MUX_STAT_CAM11 0x0404 5053 #define MUX_STAT_CAM12 0x0408 5054 #define MUX_IGNORE_CAM11 0x0504 5055 #define DIV_CAM10 0x0600 5056 #define DIV_CAM11 0x0604 5057 #define DIV_STAT_CAM10 0x0700 5058 #define DIV_STAT_CAM11 0x0704 5059 #define ENABLE_ACLK_CAM10 0X0800 5060 #define ENABLE_ACLK_CAM11 0X0804 5061 #define ENABLE_ACLK_CAM12 0X0808 5062 #define ENABLE_PCLK_CAM1 0X0900 5063 #define ENABLE_SCLK_CAM1 0X0a00 5064 #define ENABLE_IP_CAM10 0X0b00 5065 #define ENABLE_IP_CAM11 0X0b04 5066 #define ENABLE_IP_CAM12 0X0b08 5067 5068 static const unsigned long cam1_clk_regs[] __initconst = { 5069 MUX_SEL_CAM10, 5070 MUX_SEL_CAM11, 5071 MUX_SEL_CAM12, 5072 MUX_ENABLE_CAM10, 5073 MUX_ENABLE_CAM11, 5074 MUX_ENABLE_CAM12, 5075 MUX_IGNORE_CAM11, 5076 DIV_CAM10, 5077 DIV_CAM11, 5078 ENABLE_ACLK_CAM10, 5079 ENABLE_ACLK_CAM11, 5080 ENABLE_ACLK_CAM12, 5081 ENABLE_PCLK_CAM1, 5082 ENABLE_SCLK_CAM1, 5083 ENABLE_IP_CAM10, 5084 ENABLE_IP_CAM11, 5085 ENABLE_IP_CAM12, 5086 }; 5087 5088 PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", }; 5089 PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", }; 5090 PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", }; 5091 5092 PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", }; 5093 PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", }; 5094 PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", }; 5095 5096 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk", 5097 "phyclk_rxbyteclkhs0_s2b_phy", }; 5098 5099 PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a", 5100 "mout_aclk_cam1_333_user", }; 5101 PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user", 5102 "mout_aclk_cam1_400_user", }; 5103 5104 PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a", 5105 "mout_aclk_cam1_333_user", }; 5106 PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user", 5107 "mout_aclk_cam1_400_user", }; 5108 5109 PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a", 5110 "mout_aclk_cam1_333_user", }; 5111 PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user", 5112 "mout_aclk_cam1_400_user", }; 5113 5114 static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = { 5115 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL, 5116 0, 100000000), 5117 }; 5118 5119 static const struct samsung_mux_clock cam1_mux_clks[] __initconst = { 5120 /* MUX_SEL_CAM10 */ 5121 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user", 5122 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1), 5123 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user", 5124 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1), 5125 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user", 5126 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1), 5127 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user", 5128 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1), 5129 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user", 5130 mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1), 5131 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user", 5132 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1), 5133 5134 /* MUX_SEL_CAM11 */ 5135 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER, 5136 "mout_phyclk_rxbyteclkhs0_s2b_user", 5137 mout_phyclk_rxbyteclkhs0_s2b_user_p, 5138 MUX_SEL_CAM11, 0, 1), 5139 5140 /* MUX_SEL_CAM12 */ 5141 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p, 5142 MUX_SEL_CAM12, 20, 1), 5143 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p, 5144 MUX_SEL_CAM12, 16, 1), 5145 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p, 5146 MUX_SEL_CAM12, 12, 1), 5147 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p, 5148 MUX_SEL_CAM12, 8, 1), 5149 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p, 5150 MUX_SEL_CAM12, 4, 1), 5151 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p, 5152 MUX_SEL_CAM12, 0, 1), 5153 }; 5154 5155 static const struct samsung_div_clock cam1_div_clks[] __initconst = { 5156 /* DIV_CAM10 */ 5157 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm", 5158 "div_pclk_cam1_83", DIV_CAM10, 16, 2), 5159 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83", 5160 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2), 5161 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166", 5162 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2), 5163 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1", 5164 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3), 5165 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user", 5166 DIV_CAM10, 0, 3), 5167 5168 /* DIV_CAM11 */ 5169 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b", 5170 DIV_CAM11, 16, 3), 5171 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2), 5172 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3), 5173 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c", 5174 DIV_CAM11, 4, 2), 5175 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b", 5176 DIV_CAM11, 0, 3), 5177 }; 5178 5179 static const struct samsung_gate_clock cam1_gate_clks[] __initconst = { 5180 /* ENABLE_ACLK_CAM10 */ 5181 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user", 5182 ENABLE_ACLK_CAM10, 4, 0, 0), 5183 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd", 5184 ENABLE_ACLK_CAM10, 3, 0, 0), 5185 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c", 5186 ENABLE_ACLK_CAM10, 1, 0, 0), 5187 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2", 5188 ENABLE_ACLK_CAM10, 0, 0, 0), 5189 5190 /* ENABLE_ACLK_CAM11 */ 5191 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd", 5192 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0), 5193 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166", 5194 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0), 5195 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c", 5196 "div_pclk_lite_c", ENABLE_ACLK_CAM11, 5197 27, CLK_IGNORE_UNUSED, 0), 5198 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c", 5199 "div_pclk_cam1_166", ENABLE_ACLK_CAM11, 5200 26, CLK_IGNORE_UNUSED, 0), 5201 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2", 5202 "div_pclk_cam1_83", ENABLE_ACLK_CAM11, 5203 25, CLK_IGNORE_UNUSED, 0), 5204 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1", 5205 "div_pclk_cam1_83", ENABLE_ACLK_CAM11, 5206 24, CLK_IGNORE_UNUSED, 0), 5207 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5", 5208 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5209 23, CLK_IGNORE_UNUSED, 0), 5210 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5", 5211 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11, 5212 22, CLK_IGNORE_UNUSED, 0), 5213 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2", 5214 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5215 21, CLK_IGNORE_UNUSED, 0), 5216 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1", 5217 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5218 20, CLK_IGNORE_UNUSED, 0), 5219 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0", 5220 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5221 19, CLK_IGNORE_UNUSED, 0), 5222 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex", 5223 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5224 18, CLK_IGNORE_UNUSED, 0), 5225 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p", 5226 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5227 17, CLK_IGNORE_UNUSED, 0), 5228 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p", 5229 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5230 16, CLK_IGNORE_UNUSED, 0), 5231 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd", 5232 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5233 15, CLK_IGNORE_UNUSED, 0), 5234 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd", 5235 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0), 5236 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c", 5237 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5238 13, CLK_IGNORE_UNUSED, 0), 5239 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c", 5240 "div_aclk_lite_c", ENABLE_ACLK_CAM11, 5241 12, CLK_IGNORE_UNUSED, 0), 5242 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83", 5243 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0), 5244 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83", 5245 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0), 5246 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p", 5247 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5248 9, CLK_IGNORE_UNUSED, 0), 5249 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83", 5250 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0), 5251 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166", 5252 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0), 5253 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166", 5254 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0), 5255 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user", 5256 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0), 5257 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user", 5258 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0), 5259 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user", 5260 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0), 5261 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user", 5262 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0), 5263 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user", 5264 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0), 5265 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user", 5266 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0), 5267 5268 /* ENABLE_ACLK_CAM12 */ 5269 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu", 5270 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5271 10, CLK_IGNORE_UNUSED, 0), 5272 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user", 5273 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0), 5274 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c", 5275 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5276 8, CLK_IGNORE_UNUSED, 0), 5277 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user", 5278 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0), 5279 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user", 5280 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0), 5281 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user", 5282 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0), 5283 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h", 5284 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12, 5285 4, CLK_IGNORE_UNUSED, 0), 5286 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p", 5287 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12, 5288 3, CLK_IGNORE_UNUSED, 0), 5289 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p", 5290 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5291 2, CLK_IGNORE_UNUSED, 0), 5292 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user", 5293 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0), 5294 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c", 5295 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5296 0, CLK_IGNORE_UNUSED, 0), 5297 5298 /* ENABLE_PCLK_CAM1 */ 5299 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166", 5300 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0), 5301 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166", 5302 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0), 5303 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166", 5304 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0), 5305 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83", 5306 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0), 5307 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83", 5308 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0), 5309 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83", 5310 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0), 5311 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166", 5312 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0), 5313 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex", 5314 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5315 20, CLK_IGNORE_UNUSED, 0), 5316 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p", 5317 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5318 19, CLK_IGNORE_UNUSED, 0), 5319 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83", 5320 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0), 5321 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c", 5322 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5323 17, CLK_IGNORE_UNUSED, 0), 5324 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83", 5325 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0), 5326 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83", 5327 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0), 5328 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local", 5329 "div_pclk_cam1_166", ENABLE_PCLK_CAM1, 5330 14, CLK_IGNORE_UNUSED, 0), 5331 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83", 5332 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0), 5333 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83", 5334 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0), 5335 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83", 5336 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0), 5337 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83", 5338 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0), 5339 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83", 5340 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0), 5341 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83", 5342 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0), 5343 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83", 5344 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0), 5345 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83", 5346 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0), 5347 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83", 5348 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0), 5349 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83", 5350 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0), 5351 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83", 5352 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), 5353 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd", 5354 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), 5355 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c", 5356 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0), 5357 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166", 5358 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0), 5359 5360 /* ENABLE_SCLK_CAM1 */ 5361 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1, 5362 15, 0, 0), 5363 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1, 5364 14, 0, 0), 5365 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1, 5366 13, 0, 0), 5367 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1, 5368 12, 0, 0), 5369 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b", 5370 "mout_phyclk_rxbyteclkhs0_s2b_user", 5371 ENABLE_SCLK_CAM1, 11, 0, 0), 5372 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c", 5373 ENABLE_SCLK_CAM1, 10, 0, 0), 5374 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd", 5375 ENABLE_SCLK_CAM1, 9, 0, 0), 5376 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1", 5377 ENABLE_SCLK_CAM1, 7, 0, 0), 5378 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user", 5379 ENABLE_SCLK_CAM1, 6, 0, 0), 5380 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user", 5381 ENABLE_SCLK_CAM1, 5, 0, 0), 5382 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user", 5383 ENABLE_SCLK_CAM1, 4, 0, 0), 5384 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm", 5385 ENABLE_SCLK_CAM1, 3, 0, 0), 5386 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1", 5387 ENABLE_SCLK_CAM1, 2, 0, 0), 5388 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1", 5389 ENABLE_SCLK_CAM1, 1, 0, 0), 5390 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user", 5391 ENABLE_SCLK_CAM1, 0, 0, 0), 5392 }; 5393 5394 static const struct samsung_cmu_info cam1_cmu_info __initconst = { 5395 .mux_clks = cam1_mux_clks, 5396 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks), 5397 .div_clks = cam1_div_clks, 5398 .nr_div_clks = ARRAY_SIZE(cam1_div_clks), 5399 .gate_clks = cam1_gate_clks, 5400 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks), 5401 .fixed_clks = cam1_fixed_clks, 5402 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks), 5403 .nr_clk_ids = CAM1_NR_CLK, 5404 .clk_regs = cam1_clk_regs, 5405 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs), 5406 }; 5407 5408 static void __init exynos5433_cmu_cam1_init(struct device_node *np) 5409 { 5410 samsung_cmu_register_one(np, &cam1_cmu_info); 5411 } 5412 CLK_OF_DECLARE(exynos5433_cmu_cam1, "samsung,exynos5433-cmu-cam1", 5413 exynos5433_cmu_cam1_init); 5414