1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Authors: Thomas Abraham <thomas.ab@samsung.com> 4 * Chander Kashyap <k.chander@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for Exynos5420 SoC. 11 */ 12 13 #include <dt-bindings/clock/exynos5420.h> 14 #include <linux/slab.h> 15 #include <linux/clk-provider.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/syscore_ops.h> 19 20 #include "clk.h" 21 #include "clk-cpu.h" 22 23 #define APLL_LOCK 0x0 24 #define APLL_CON0 0x100 25 #define SRC_CPU 0x200 26 #define DIV_CPU0 0x500 27 #define DIV_CPU1 0x504 28 #define GATE_BUS_CPU 0x700 29 #define GATE_SCLK_CPU 0x800 30 #define CLKOUT_CMU_CPU 0xa00 31 #define SRC_MASK_CPERI 0x4300 32 #define GATE_IP_G2D 0x8800 33 #define CPLL_LOCK 0x10020 34 #define DPLL_LOCK 0x10030 35 #define EPLL_LOCK 0x10040 36 #define RPLL_LOCK 0x10050 37 #define IPLL_LOCK 0x10060 38 #define SPLL_LOCK 0x10070 39 #define VPLL_LOCK 0x10080 40 #define MPLL_LOCK 0x10090 41 #define CPLL_CON0 0x10120 42 #define DPLL_CON0 0x10128 43 #define EPLL_CON0 0x10130 44 #define EPLL_CON1 0x10134 45 #define EPLL_CON2 0x10138 46 #define RPLL_CON0 0x10140 47 #define RPLL_CON1 0x10144 48 #define RPLL_CON2 0x10148 49 #define IPLL_CON0 0x10150 50 #define SPLL_CON0 0x10160 51 #define VPLL_CON0 0x10170 52 #define MPLL_CON0 0x10180 53 #define SRC_TOP0 0x10200 54 #define SRC_TOP1 0x10204 55 #define SRC_TOP2 0x10208 56 #define SRC_TOP3 0x1020c 57 #define SRC_TOP4 0x10210 58 #define SRC_TOP5 0x10214 59 #define SRC_TOP6 0x10218 60 #define SRC_TOP7 0x1021c 61 #define SRC_TOP8 0x10220 /* 5800 specific */ 62 #define SRC_TOP9 0x10224 /* 5800 specific */ 63 #define SRC_DISP10 0x1022c 64 #define SRC_MAU 0x10240 65 #define SRC_FSYS 0x10244 66 #define SRC_PERIC0 0x10250 67 #define SRC_PERIC1 0x10254 68 #define SRC_ISP 0x10270 69 #define SRC_CAM 0x10274 /* 5800 specific */ 70 #define SRC_TOP10 0x10280 71 #define SRC_TOP11 0x10284 72 #define SRC_TOP12 0x10288 73 #define SRC_TOP13 0x1028c /* 5800 specific */ 74 #define SRC_MASK_TOP0 0x10300 75 #define SRC_MASK_TOP1 0x10304 76 #define SRC_MASK_TOP2 0x10308 77 #define SRC_MASK_TOP7 0x1031c 78 #define SRC_MASK_DISP10 0x1032c 79 #define SRC_MASK_MAU 0x10334 80 #define SRC_MASK_FSYS 0x10340 81 #define SRC_MASK_PERIC0 0x10350 82 #define SRC_MASK_PERIC1 0x10354 83 #define SRC_MASK_ISP 0x10370 84 #define DIV_TOP0 0x10500 85 #define DIV_TOP1 0x10504 86 #define DIV_TOP2 0x10508 87 #define DIV_TOP8 0x10520 /* 5800 specific */ 88 #define DIV_TOP9 0x10524 /* 5800 specific */ 89 #define DIV_DISP10 0x1052c 90 #define DIV_MAU 0x10544 91 #define DIV_FSYS0 0x10548 92 #define DIV_FSYS1 0x1054c 93 #define DIV_FSYS2 0x10550 94 #define DIV_PERIC0 0x10558 95 #define DIV_PERIC1 0x1055c 96 #define DIV_PERIC2 0x10560 97 #define DIV_PERIC3 0x10564 98 #define DIV_PERIC4 0x10568 99 #define DIV_CAM 0x10574 /* 5800 specific */ 100 #define SCLK_DIV_ISP0 0x10580 101 #define SCLK_DIV_ISP1 0x10584 102 #define DIV2_RATIO0 0x10590 103 #define DIV4_RATIO 0x105a0 104 #define GATE_BUS_TOP 0x10700 105 #define GATE_BUS_DISP1 0x10728 106 #define GATE_BUS_GEN 0x1073c 107 #define GATE_BUS_FSYS0 0x10740 108 #define GATE_BUS_FSYS2 0x10748 109 #define GATE_BUS_PERIC 0x10750 110 #define GATE_BUS_PERIC1 0x10754 111 #define GATE_BUS_PERIS0 0x10760 112 #define GATE_BUS_PERIS1 0x10764 113 #define GATE_BUS_NOC 0x10770 114 #define GATE_TOP_SCLK_ISP 0x10870 115 #define GATE_IP_GSCL0 0x10910 116 #define GATE_IP_GSCL1 0x10920 117 #define GATE_IP_CAM 0x10924 /* 5800 specific */ 118 #define GATE_IP_MFC 0x1092c 119 #define GATE_IP_DISP1 0x10928 120 #define GATE_IP_G3D 0x10930 121 #define GATE_IP_GEN 0x10934 122 #define GATE_IP_FSYS 0x10944 123 #define GATE_IP_PERIC 0x10950 124 #define GATE_IP_PERIS 0x10960 125 #define GATE_IP_MSCL 0x10970 126 #define GATE_TOP_SCLK_GSCL 0x10820 127 #define GATE_TOP_SCLK_DISP1 0x10828 128 #define GATE_TOP_SCLK_MAU 0x1083c 129 #define GATE_TOP_SCLK_FSYS 0x10840 130 #define GATE_TOP_SCLK_PERIC 0x10850 131 #define TOP_SPARE2 0x10b08 132 #define BPLL_LOCK 0x20010 133 #define BPLL_CON0 0x20110 134 #define SRC_CDREX 0x20200 135 #define DIV_CDREX0 0x20500 136 #define DIV_CDREX1 0x20504 137 #define KPLL_LOCK 0x28000 138 #define KPLL_CON0 0x28100 139 #define SRC_KFC 0x28200 140 #define DIV_KFC0 0x28500 141 142 /* Exynos5x SoC type */ 143 enum exynos5x_soc { 144 EXYNOS5420, 145 EXYNOS5800, 146 }; 147 148 /* list of PLLs */ 149 enum exynos5x_plls { 150 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 151 bpll, kpll, 152 nr_plls /* number of PLLs */ 153 }; 154 155 static void __iomem *reg_base; 156 static enum exynos5x_soc exynos5x_soc; 157 158 #ifdef CONFIG_PM_SLEEP 159 static struct samsung_clk_reg_dump *exynos5x_save; 160 static struct samsung_clk_reg_dump *exynos5800_save; 161 162 /* 163 * list of controller registers to be saved and restored during a 164 * suspend/resume cycle. 165 */ 166 static const unsigned long exynos5x_clk_regs[] __initconst = { 167 SRC_CPU, 168 DIV_CPU0, 169 DIV_CPU1, 170 GATE_BUS_CPU, 171 GATE_SCLK_CPU, 172 CLKOUT_CMU_CPU, 173 EPLL_CON0, 174 EPLL_CON1, 175 EPLL_CON2, 176 RPLL_CON0, 177 RPLL_CON1, 178 RPLL_CON2, 179 SRC_TOP0, 180 SRC_TOP1, 181 SRC_TOP2, 182 SRC_TOP3, 183 SRC_TOP4, 184 SRC_TOP5, 185 SRC_TOP6, 186 SRC_TOP7, 187 SRC_DISP10, 188 SRC_MAU, 189 SRC_FSYS, 190 SRC_PERIC0, 191 SRC_PERIC1, 192 SRC_TOP10, 193 SRC_TOP11, 194 SRC_TOP12, 195 SRC_MASK_TOP2, 196 SRC_MASK_TOP7, 197 SRC_MASK_DISP10, 198 SRC_MASK_FSYS, 199 SRC_MASK_PERIC0, 200 SRC_MASK_PERIC1, 201 SRC_MASK_TOP0, 202 SRC_MASK_TOP1, 203 SRC_MASK_MAU, 204 SRC_MASK_ISP, 205 SRC_ISP, 206 DIV_TOP0, 207 DIV_TOP1, 208 DIV_TOP2, 209 DIV_DISP10, 210 DIV_MAU, 211 DIV_FSYS0, 212 DIV_FSYS1, 213 DIV_FSYS2, 214 DIV_PERIC0, 215 DIV_PERIC1, 216 DIV_PERIC2, 217 DIV_PERIC3, 218 DIV_PERIC4, 219 SCLK_DIV_ISP0, 220 SCLK_DIV_ISP1, 221 DIV2_RATIO0, 222 DIV4_RATIO, 223 GATE_BUS_DISP1, 224 GATE_BUS_TOP, 225 GATE_BUS_GEN, 226 GATE_BUS_FSYS0, 227 GATE_BUS_FSYS2, 228 GATE_BUS_PERIC, 229 GATE_BUS_PERIC1, 230 GATE_BUS_PERIS0, 231 GATE_BUS_PERIS1, 232 GATE_BUS_NOC, 233 GATE_TOP_SCLK_ISP, 234 GATE_IP_GSCL0, 235 GATE_IP_GSCL1, 236 GATE_IP_MFC, 237 GATE_IP_DISP1, 238 GATE_IP_G3D, 239 GATE_IP_GEN, 240 GATE_IP_FSYS, 241 GATE_IP_PERIC, 242 GATE_IP_PERIS, 243 GATE_IP_MSCL, 244 GATE_TOP_SCLK_GSCL, 245 GATE_TOP_SCLK_DISP1, 246 GATE_TOP_SCLK_MAU, 247 GATE_TOP_SCLK_FSYS, 248 GATE_TOP_SCLK_PERIC, 249 TOP_SPARE2, 250 SRC_CDREX, 251 DIV_CDREX0, 252 DIV_CDREX1, 253 SRC_KFC, 254 DIV_KFC0, 255 }; 256 257 static const unsigned long exynos5800_clk_regs[] __initconst = { 258 SRC_TOP8, 259 SRC_TOP9, 260 SRC_CAM, 261 SRC_TOP1, 262 DIV_TOP8, 263 DIV_TOP9, 264 DIV_CAM, 265 GATE_IP_CAM, 266 }; 267 268 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 269 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 270 { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 271 { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 272 { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 273 { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 274 { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 275 { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 276 { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 277 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 278 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 279 { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 280 { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 281 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 282 { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 283 }; 284 285 static int exynos5420_clk_suspend(void) 286 { 287 samsung_clk_save(reg_base, exynos5x_save, 288 ARRAY_SIZE(exynos5x_clk_regs)); 289 290 if (exynos5x_soc == EXYNOS5800) 291 samsung_clk_save(reg_base, exynos5800_save, 292 ARRAY_SIZE(exynos5800_clk_regs)); 293 294 samsung_clk_restore(reg_base, exynos5420_set_clksrc, 295 ARRAY_SIZE(exynos5420_set_clksrc)); 296 297 return 0; 298 } 299 300 static void exynos5420_clk_resume(void) 301 { 302 samsung_clk_restore(reg_base, exynos5x_save, 303 ARRAY_SIZE(exynos5x_clk_regs)); 304 305 if (exynos5x_soc == EXYNOS5800) 306 samsung_clk_restore(reg_base, exynos5800_save, 307 ARRAY_SIZE(exynos5800_clk_regs)); 308 } 309 310 static struct syscore_ops exynos5420_clk_syscore_ops = { 311 .suspend = exynos5420_clk_suspend, 312 .resume = exynos5420_clk_resume, 313 }; 314 315 static void __init exynos5420_clk_sleep_init(void) 316 { 317 exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs, 318 ARRAY_SIZE(exynos5x_clk_regs)); 319 if (!exynos5x_save) { 320 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 321 __func__); 322 return; 323 } 324 325 if (exynos5x_soc == EXYNOS5800) { 326 exynos5800_save = 327 samsung_clk_alloc_reg_dump(exynos5800_clk_regs, 328 ARRAY_SIZE(exynos5800_clk_regs)); 329 if (!exynos5800_save) 330 goto err_soc; 331 } 332 333 register_syscore_ops(&exynos5420_clk_syscore_ops); 334 return; 335 err_soc: 336 kfree(exynos5x_save); 337 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 338 __func__); 339 return; 340 } 341 #else 342 static void __init exynos5420_clk_sleep_init(void) {} 343 #endif 344 345 /* list of all parent clocks */ 346 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 347 "mout_sclk_mpll", "mout_sclk_spll"}; 348 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 349 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 350 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 351 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 352 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 353 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 354 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 355 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 356 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 357 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 358 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 359 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 360 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 361 362 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 363 "mout_sclk_mpll"}; 364 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 365 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 366 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 367 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 368 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 369 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 370 371 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 372 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 373 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 374 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 375 376 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 377 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 378 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 379 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 380 381 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 382 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 383 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 384 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 385 386 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 387 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 388 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 389 390 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 391 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 392 393 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 394 "mout_sclk_spll"}; 395 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 396 397 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 398 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 399 400 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 401 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 402 403 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 404 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 405 406 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 407 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 408 409 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 410 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 411 412 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 413 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 414 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 415 416 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 417 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 418 419 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 420 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 421 422 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 423 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 424 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 425 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 426 427 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 428 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 429 430 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 431 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 432 433 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 434 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 435 436 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 437 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 438 439 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 440 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 441 "mout_sclk_epll", "mout_sclk_rpll"}; 442 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 443 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 444 "mout_sclk_epll", "mout_sclk_rpll"}; 445 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 446 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 447 "mout_sclk_epll", "mout_sclk_rpll"}; 448 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 449 "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 450 "mout_sclk_epll", "mout_sclk_rpll"}; 451 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 452 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 453 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 454 "mout_sclk_epll", "mout_sclk_rpll"}; 455 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 456 "mout_sclk_mpll", "mout_sclk_spll"}; 457 PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"}; 458 459 /* List of parents specific to exynos5800 */ 460 PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 461 PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 462 "mout_sclk_mpll", "ff_dout_spll2" }; 463 PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 464 "mout_sclk_mpll", "ff_dout_spll2", 465 "mout_epll2", "mout_sclk_ipll" }; 466 PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 467 "mout_sclk_mpll", "ff_dout_spll2", 468 "mout_epll2" }; 469 PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 470 "mout_sclk_mpll", "mout_sclk_spll" }; 471 PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 472 "mout_sclk_mpll", "ff_dout_spll2" }; 473 PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 474 "mout_sclk_mpll", "mout_sclk_spll", 475 "mout_epll2", "mout_sclk_ipll" }; 476 PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll", 477 "mout_sclk_mpll", "ff_dout_spll2", 478 "mout_sclk_spll", "mout_sclk_epll"}; 479 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 480 "mout_sclk_mpll", 481 "ff_dout_spll2" }; 482 PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 483 PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 484 PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 485 PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 486 PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 487 PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 488 PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 489 PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 490 PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; 491 492 /* fixed rate clocks generated outside the soc */ 493 static struct samsung_fixed_rate_clock 494 exynos5x_fixed_rate_ext_clks[] __initdata = { 495 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 496 }; 497 498 /* fixed rate clocks generated inside the soc */ 499 static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { 500 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 501 FRATE(0, "sclk_pwi", NULL, 0, 24000000), 502 FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 503 FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 504 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 505 }; 506 507 static const struct samsung_fixed_factor_clock 508 exynos5x_fixed_factor_clks[] __initconst = { 509 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 510 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 511 }; 512 513 static const struct samsung_fixed_factor_clock 514 exynos5800_fixed_factor_clks[] __initconst = { 515 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 516 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 517 }; 518 519 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 520 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 521 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 522 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 523 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 524 525 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 526 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 527 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 528 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 529 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 530 531 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 532 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 533 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 534 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 535 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 536 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 537 538 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 539 mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), 540 MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, 541 SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), 542 MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 543 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 544 545 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 546 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 547 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 548 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 549 550 MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, 551 SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0), 552 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 553 SRC_TOP9, 16, 1), 554 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 555 SRC_TOP9, 20, 1), 556 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 557 SRC_TOP9, 24, 1), 558 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 559 SRC_TOP9, 28, 1), 560 561 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 562 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 563 SRC_TOP13, 20, 1), 564 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 565 SRC_TOP13, 24, 1), 566 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 567 SRC_TOP13, 28, 1), 568 569 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 570 }; 571 572 static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { 573 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 574 "mout_aclk400_wcore", DIV_TOP0, 16, 3), 575 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 576 DIV_TOP8, 16, 3), 577 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 578 DIV_TOP8, 20, 3), 579 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 580 DIV_TOP8, 24, 3), 581 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 582 DIV_TOP8, 28, 3), 583 584 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 585 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 586 }; 587 588 static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 589 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 590 GATE_BUS_TOP, 24, 0, 0), 591 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 592 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), 593 GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", 594 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 595 }; 596 597 static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 598 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 599 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 600 TOP_SPARE2, 4, 1), 601 602 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 603 MUX_A(0, "mout_aclk400_mscl", mout_group1_p, 604 SRC_TOP0, 4, 2, "aclk400_mscl"), 605 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 606 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 607 608 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 609 MUX(0, "mout_aclk333_432_isp", mout_group4_p, 610 SRC_TOP1, 4, 2), 611 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 612 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 613 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 614 615 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 616 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 617 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 618 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 619 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 620 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 621 622 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 623 mout_group5_5800_p, SRC_TOP7, 16, 2), 624 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2), 625 626 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 627 }; 628 629 static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 630 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 631 "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 632 }; 633 634 static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { 635 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 636 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 637 }; 638 639 static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 640 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 641 SRC_TOP7, 4, 1), 642 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 643 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 644 645 MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 646 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 647 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 648 MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 649 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 650 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 651 652 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 653 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 654 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 655 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 656 657 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 658 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 659 660 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 661 662 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 663 SRC_TOP3, 0, 1), 664 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 665 SRC_TOP3, 4, 1), 666 MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 667 mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 668 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 669 SRC_TOP3, 12, 1), 670 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 671 SRC_TOP3, 16, 1), 672 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 673 SRC_TOP3, 20, 1), 674 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 675 SRC_TOP3, 24, 1), 676 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 677 SRC_TOP3, 28, 1), 678 679 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 680 SRC_TOP4, 0, 1), 681 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 682 SRC_TOP4, 4, 1), 683 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 684 SRC_TOP4, 8, 1), 685 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 686 SRC_TOP4, 12, 1), 687 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 688 SRC_TOP4, 16, 1), 689 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 690 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 691 MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 692 SRC_TOP4, 28, 1), 693 694 MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 695 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 696 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 697 SRC_TOP5, 4, 1), 698 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 699 SRC_TOP5, 8, 1), 700 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 701 SRC_TOP5, 12, 1), 702 MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 703 SRC_TOP5, 16, 1), 704 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 705 SRC_TOP5, 20, 1), 706 MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 707 mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 708 MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 709 mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 710 711 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 712 MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 713 MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 714 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 715 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 716 MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, 717 CLK_SET_RATE_PARENT, 0), 718 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 719 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 720 721 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 722 SRC_TOP10, 0, 1), 723 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 724 SRC_TOP10, 4, 1), 725 MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 726 SRC_TOP10, 8, 1), 727 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 728 SRC_TOP10, 12, 1), 729 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 730 SRC_TOP10, 16, 1), 731 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 732 SRC_TOP10, 20, 1), 733 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 734 SRC_TOP10, 24, 1), 735 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 736 SRC_TOP10, 28, 1), 737 738 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 739 SRC_TOP11, 0, 1), 740 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 741 SRC_TOP11, 4, 1), 742 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 743 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 744 SRC_TOP11, 12, 1), 745 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 746 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 747 MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 748 SRC_TOP11, 28, 1), 749 750 MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 751 mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 752 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 753 SRC_TOP12, 8, 1), 754 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 755 SRC_TOP12, 12, 1), 756 MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 757 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 758 SRC_TOP12, 20, 1), 759 MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 760 mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 761 MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 762 mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 763 764 /* DISP1 Block */ 765 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 766 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 767 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 768 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 769 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 770 771 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 772 773 /* CDREX block */ 774 MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p, 775 SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0), 776 MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1, 777 CLK_SET_RATE_PARENT, 0), 778 779 /* MAU Block */ 780 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 781 782 /* FSYS Block */ 783 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 784 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 785 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 786 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 787 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 788 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 789 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 790 791 /* PERIC Block */ 792 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 793 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 794 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 795 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 796 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 797 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 798 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 799 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 800 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 801 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 802 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 803 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 804 805 /* ISP Block */ 806 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 807 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 808 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 809 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 810 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 811 }; 812 813 static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 814 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 815 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 816 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 817 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 818 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 819 820 DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 821 DIV_TOP0, 0, 3), 822 DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 823 DIV_TOP0, 4, 3), 824 DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 825 DIV_TOP0, 8, 3), 826 DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 827 DIV_TOP0, 12, 3), 828 DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 829 DIV_TOP0, 20, 3), 830 DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 831 DIV_TOP0, 24, 3), 832 DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 833 DIV_TOP0, 28, 3), 834 DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 835 "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 836 DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 837 "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 838 DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 839 DIV_TOP1, 8, 6), 840 DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 841 "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 842 DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 843 DIV_TOP1, 20, 3), 844 DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 845 DIV_TOP1, 24, 3), 846 DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 847 DIV_TOP1, 28, 3), 848 849 DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 850 DIV_TOP2, 8, 3), 851 DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 852 DIV_TOP2, 12, 3), 853 DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 854 16, 3), 855 DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 856 DIV_TOP2, 20, 3), 857 DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 858 "mout_aclk300_disp1", DIV_TOP2, 24, 3), 859 DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 860 DIV_TOP2, 28, 3), 861 862 /* DISP1 Block */ 863 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 864 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 865 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 866 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 867 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 868 DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 869 "mout_aclk400_disp1", DIV_TOP2, 4, 3), 870 871 /* CDREX Block */ 872 DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", 873 DIV_CDREX0, 28, 3), 874 DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", 875 DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), 876 DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", 877 DIV_CDREX0, 16, 3), 878 DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", 879 DIV_CDREX0, 8, 3), 880 DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", 881 DIV_CDREX0, 3, 5), 882 883 DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", 884 DIV_CDREX1, 8, 3), 885 886 /* Audio Block */ 887 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 888 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 889 890 /* USB3.0 */ 891 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 892 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 893 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 894 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 895 896 /* MMC */ 897 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 898 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 899 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 900 901 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 902 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 903 904 /* UART and PWM */ 905 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 906 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 907 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 908 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 909 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 910 911 /* SPI */ 912 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 913 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 914 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 915 916 /* Mfc Block */ 917 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 918 919 /* PCM */ 920 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 921 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 922 923 /* Audio - I2S */ 924 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 925 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 926 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 927 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 928 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 929 930 /* SPI Pre-Ratio */ 931 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 932 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 933 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 934 935 /* GSCL Block */ 936 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 937 DIV2_RATIO0, 4, 2), 938 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 939 940 /* MSCL Block */ 941 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 942 943 /* PSGEN */ 944 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 945 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 946 947 /* ISP Block */ 948 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 949 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 950 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 951 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 952 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 953 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 954 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 955 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 956 CLK_SET_RATE_PARENT, 0), 957 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 958 CLK_SET_RATE_PARENT, 0), 959 }; 960 961 static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 962 /* G2D */ 963 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 964 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 965 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 966 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 967 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 968 969 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 970 GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), 971 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 972 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 973 974 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 975 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 976 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 977 GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), 978 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 979 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 980 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 981 GATE_BUS_TOP, 5, 0, 0), 982 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 983 GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), 984 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 985 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 986 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 987 GATE_BUS_TOP, 8, 0, 0), 988 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 989 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 990 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 991 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 992 GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 993 GATE_BUS_TOP, 13, 0, 0), 994 GATE(0, "aclk166", "mout_user_aclk166", 995 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 996 GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", 997 GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), 998 GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 999 GATE_BUS_TOP, 16, 0, 0), 1000 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 1001 GATE_BUS_TOP, 17, 0, 0), 1002 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 1003 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), 1004 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 1005 GATE_BUS_TOP, 28, 0, 0), 1006 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 1007 GATE_BUS_TOP, 29, 0, 0), 1008 1009 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 1010 SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), 1011 1012 /* sclk */ 1013 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 1014 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 1015 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 1016 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 1017 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 1018 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 1019 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 1020 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 1021 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 1022 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 1023 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 1024 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 1025 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 1026 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 1027 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 1028 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 1029 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 1030 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1031 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 1032 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 1033 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 1034 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 1035 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 1036 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 1037 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 1038 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 1039 1040 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 1041 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 1042 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 1043 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 1044 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 1045 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 1046 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 1047 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 1048 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 1049 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 1050 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 1051 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 1052 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 1053 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 1054 1055 /* Display */ 1056 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 1057 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 1058 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 1059 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 1060 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 1061 GATE_TOP_SCLK_DISP1, 9, 0, 0), 1062 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 1063 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 1064 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 1065 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 1066 1067 /* Maudio Block */ 1068 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 1069 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1070 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 1071 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 1072 1073 /* FSYS Block */ 1074 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1075 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1076 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1077 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 1078 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 1079 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 1080 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 1081 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1082 GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 1083 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 1084 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 1085 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 1086 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 1087 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 1088 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 1089 1090 /* PERIC Block */ 1091 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 1092 GATE_IP_PERIC, 0, 0, 0), 1093 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 1094 GATE_IP_PERIC, 1, 0, 0), 1095 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 1096 GATE_IP_PERIC, 2, 0, 0), 1097 GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 1098 GATE_IP_PERIC, 3, 0, 0), 1099 GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 1100 GATE_IP_PERIC, 6, 0, 0), 1101 GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 1102 GATE_IP_PERIC, 7, 0, 0), 1103 GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 1104 GATE_IP_PERIC, 8, 0, 0), 1105 GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 1106 GATE_IP_PERIC, 9, 0, 0), 1107 GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 1108 GATE_IP_PERIC, 10, 0, 0), 1109 GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 1110 GATE_IP_PERIC, 11, 0, 0), 1111 GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 1112 GATE_IP_PERIC, 12, 0, 0), 1113 GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 1114 GATE_IP_PERIC, 13, 0, 0), 1115 GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 1116 GATE_IP_PERIC, 14, 0, 0), 1117 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 1118 GATE_IP_PERIC, 15, 0, 0), 1119 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 1120 GATE_IP_PERIC, 16, 0, 0), 1121 GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 1122 GATE_IP_PERIC, 17, 0, 0), 1123 GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 1124 GATE_IP_PERIC, 18, 0, 0), 1125 GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 1126 GATE_IP_PERIC, 20, 0, 0), 1127 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 1128 GATE_IP_PERIC, 21, 0, 0), 1129 GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 1130 GATE_IP_PERIC, 22, 0, 0), 1131 GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 1132 GATE_IP_PERIC, 23, 0, 0), 1133 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 1134 GATE_IP_PERIC, 24, 0, 0), 1135 GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 1136 GATE_IP_PERIC, 26, 0, 0), 1137 GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 1138 GATE_IP_PERIC, 28, 0, 0), 1139 GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 1140 GATE_IP_PERIC, 30, 0, 0), 1141 GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 1142 GATE_IP_PERIC, 31, 0, 0), 1143 1144 GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 1145 GATE_BUS_PERIC, 22, 0, 0), 1146 1147 /* PERIS Block */ 1148 GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 1149 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1150 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 1151 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1152 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 1153 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 1154 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 1155 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 1156 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 1157 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 1158 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 1159 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 1160 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 1161 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 1162 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 1163 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 1164 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 1165 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 1166 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 1167 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 1168 1169 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 1170 1171 /* GEN Block */ 1172 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 1173 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 1174 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 1175 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 1176 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 1177 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 1178 GATE_IP_GEN, 6, 0, 0), 1179 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 1180 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 1181 GATE_IP_GEN, 9, 0, 0), 1182 1183 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 1184 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 1185 GATE_BUS_GEN, 28, 0, 0), 1186 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 1187 1188 /* GSCL Block */ 1189 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 1190 GATE_TOP_SCLK_GSCL, 6, 0, 0), 1191 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 1192 GATE_TOP_SCLK_GSCL, 7, 0, 0), 1193 1194 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1195 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1196 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 1197 GATE_IP_GSCL0, 4, 0, 0), 1198 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 1199 GATE_IP_GSCL0, 5, 0, 0), 1200 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 1201 GATE_IP_GSCL0, 6, 0, 0), 1202 1203 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 1204 GATE_IP_GSCL1, 2, 0, 0), 1205 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 1206 GATE_IP_GSCL1, 3, 0, 0), 1207 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 1208 GATE_IP_GSCL1, 4, 0, 0), 1209 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 1210 GATE_IP_GSCL1, 6, 0, 0), 1211 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 1212 GATE_IP_GSCL1, 7, 0, 0), 1213 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 1214 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 1215 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 1216 GATE_IP_GSCL1, 16, 0, 0), 1217 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 1218 GATE_IP_GSCL1, 17, 0, 0), 1219 1220 /* MSCL Block */ 1221 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 1222 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 1223 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 1224 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 1225 GATE_IP_MSCL, 8, 0, 0), 1226 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 1227 GATE_IP_MSCL, 9, 0, 0), 1228 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 1229 GATE_IP_MSCL, 10, 0, 0), 1230 1231 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1232 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1233 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1234 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1235 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1236 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1237 GATE_IP_DISP1, 7, 0, 0), 1238 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1239 GATE_IP_DISP1, 8, 0, 0), 1240 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1241 GATE_IP_DISP1, 9, 0, 0), 1242 1243 /* ISP */ 1244 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 1245 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 1246 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 1247 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 1248 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 1249 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 1250 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 1251 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 1252 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 1253 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 1254 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 1255 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 1256 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 1257 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 1258 1259 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 1260 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 1261 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 1262 1263 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 1264 }; 1265 1266 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { 1267 PLL_35XX_RATE(2000000000, 250, 3, 0), 1268 PLL_35XX_RATE(1900000000, 475, 6, 0), 1269 PLL_35XX_RATE(1800000000, 225, 3, 0), 1270 PLL_35XX_RATE(1700000000, 425, 6, 0), 1271 PLL_35XX_RATE(1600000000, 200, 3, 0), 1272 PLL_35XX_RATE(1500000000, 250, 4, 0), 1273 PLL_35XX_RATE(1400000000, 175, 3, 0), 1274 PLL_35XX_RATE(1300000000, 325, 6, 0), 1275 PLL_35XX_RATE(1200000000, 200, 2, 1), 1276 PLL_35XX_RATE(1100000000, 275, 3, 1), 1277 PLL_35XX_RATE(1000000000, 250, 3, 1), 1278 PLL_35XX_RATE(900000000, 150, 2, 1), 1279 PLL_35XX_RATE(800000000, 200, 3, 1), 1280 PLL_35XX_RATE(700000000, 175, 3, 1), 1281 PLL_35XX_RATE(600000000, 200, 2, 2), 1282 PLL_35XX_RATE(500000000, 250, 3, 2), 1283 PLL_35XX_RATE(400000000, 200, 3, 2), 1284 PLL_35XX_RATE(300000000, 200, 2, 3), 1285 PLL_35XX_RATE(200000000, 200, 3, 3), 1286 }; 1287 1288 static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 1289 PLL_36XX_RATE(600000000U, 100, 2, 1, 0), 1290 PLL_36XX_RATE(400000000U, 200, 3, 2, 0), 1291 PLL_36XX_RATE(393216003U, 197, 3, 2, -25690), 1292 PLL_36XX_RATE(361267218U, 301, 5, 2, 3671), 1293 PLL_36XX_RATE(200000000U, 200, 3, 3, 0), 1294 PLL_36XX_RATE(196608001U, 197, 3, 3, -25690), 1295 PLL_36XX_RATE(180633609U, 301, 5, 3, 3671), 1296 PLL_36XX_RATE(131072006U, 131, 3, 3, 4719), 1297 PLL_36XX_RATE(100000000U, 200, 3, 4, 0), 1298 PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719), 1299 PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690), 1300 PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719), 1301 }; 1302 1303 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1304 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1305 APLL_CON0, NULL), 1306 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1307 CPLL_CON0, NULL), 1308 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 1309 DPLL_CON0, NULL), 1310 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 1311 EPLL_CON0, NULL), 1312 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 1313 RPLL_CON0, NULL), 1314 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 1315 IPLL_CON0, NULL), 1316 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 1317 SPLL_CON0, NULL), 1318 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 1319 VPLL_CON0, NULL), 1320 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 1321 MPLL_CON0, NULL), 1322 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 1323 BPLL_CON0, NULL), 1324 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 1325 KPLL_CON0, NULL), 1326 }; 1327 1328 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1329 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1330 ((cpud) << 4))) 1331 1332 static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1333 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1334 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1335 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1336 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1337 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1338 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1339 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1340 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1341 { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1342 { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1343 { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1344 { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1345 { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1346 { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1347 { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1348 { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1349 { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1350 { 0 }, 1351 }; 1352 1353 static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 1354 { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1355 { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1356 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1357 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1358 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1359 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1360 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1361 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1362 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1363 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1364 { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 1365 { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 1366 { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 1367 { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 1368 { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 1369 { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1370 { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1371 { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1372 { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1373 { 0 }, 1374 }; 1375 1376 #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1377 ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1378 1379 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 1380 { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1381 { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1382 { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1383 { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1384 { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1385 { 900000, E5420_KFC_DIV(3, 5, 2), }, 1386 { 800000, E5420_KFC_DIV(3, 5, 2), }, 1387 { 700000, E5420_KFC_DIV(3, 4, 2), }, 1388 { 600000, E5420_KFC_DIV(3, 4, 2), }, 1389 { 500000, E5420_KFC_DIV(3, 4, 2), }, 1390 { 400000, E5420_KFC_DIV(3, 3, 2), }, 1391 { 300000, E5420_KFC_DIV(3, 3, 2), }, 1392 { 200000, E5420_KFC_DIV(3, 3, 2), }, 1393 { 0 }, 1394 }; 1395 1396 static const struct of_device_id ext_clk_match[] __initconst = { 1397 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 1398 { }, 1399 }; 1400 1401 /* register exynos5420 clocks */ 1402 static void __init exynos5x_clk_init(struct device_node *np, 1403 enum exynos5x_soc soc) 1404 { 1405 struct samsung_clk_provider *ctx; 1406 1407 if (np) { 1408 reg_base = of_iomap(np, 0); 1409 if (!reg_base) 1410 panic("%s: failed to map registers\n", __func__); 1411 } else { 1412 panic("%s: unable to determine soc\n", __func__); 1413 } 1414 1415 exynos5x_soc = soc; 1416 1417 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1418 1419 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 1420 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 1421 ext_clk_match); 1422 1423 if (_get_rate("fin_pll") == 24 * MHZ) { 1424 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1425 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; 1426 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1427 exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1428 } 1429 1430 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1431 reg_base); 1432 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 1433 ARRAY_SIZE(exynos5x_fixed_rate_clks)); 1434 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 1435 ARRAY_SIZE(exynos5x_fixed_factor_clks)); 1436 samsung_clk_register_mux(ctx, exynos5x_mux_clks, 1437 ARRAY_SIZE(exynos5x_mux_clks)); 1438 samsung_clk_register_div(ctx, exynos5x_div_clks, 1439 ARRAY_SIZE(exynos5x_div_clks)); 1440 samsung_clk_register_gate(ctx, exynos5x_gate_clks, 1441 ARRAY_SIZE(exynos5x_gate_clks)); 1442 1443 if (soc == EXYNOS5420) { 1444 samsung_clk_register_mux(ctx, exynos5420_mux_clks, 1445 ARRAY_SIZE(exynos5420_mux_clks)); 1446 samsung_clk_register_div(ctx, exynos5420_div_clks, 1447 ARRAY_SIZE(exynos5420_div_clks)); 1448 samsung_clk_register_gate(ctx, exynos5420_gate_clks, 1449 ARRAY_SIZE(exynos5420_gate_clks)); 1450 } else { 1451 samsung_clk_register_fixed_factor( 1452 ctx, exynos5800_fixed_factor_clks, 1453 ARRAY_SIZE(exynos5800_fixed_factor_clks)); 1454 samsung_clk_register_mux(ctx, exynos5800_mux_clks, 1455 ARRAY_SIZE(exynos5800_mux_clks)); 1456 samsung_clk_register_div(ctx, exynos5800_div_clks, 1457 ARRAY_SIZE(exynos5800_div_clks)); 1458 samsung_clk_register_gate(ctx, exynos5800_gate_clks, 1459 ARRAY_SIZE(exynos5800_gate_clks)); 1460 } 1461 1462 if (soc == EXYNOS5420) { 1463 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1464 mout_cpu_p[0], mout_cpu_p[1], 0x200, 1465 exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); 1466 } else { 1467 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1468 mout_cpu_p[0], mout_cpu_p[1], 0x200, 1469 exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); 1470 } 1471 exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", 1472 mout_kfc_p[0], mout_kfc_p[1], 0x28200, 1473 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); 1474 1475 exynos5420_clk_sleep_init(); 1476 1477 samsung_clk_of_add_provider(np, ctx); 1478 } 1479 1480 static void __init exynos5420_clk_init(struct device_node *np) 1481 { 1482 exynos5x_clk_init(np, EXYNOS5420); 1483 } 1484 CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 1485 1486 static void __init exynos5800_clk_init(struct device_node *np) 1487 { 1488 exynos5x_clk_init(np, EXYNOS5800); 1489 } 1490 CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init); 1491