1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Authors: Thomas Abraham <thomas.ab@samsung.com> 4 * Chander Kashyap <k.chander@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for Exynos5420 SoC. 11 */ 12 13 #include <dt-bindings/clock/exynos5420.h> 14 #include <linux/slab.h> 15 #include <linux/clk-provider.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/syscore_ops.h> 19 20 #include "clk.h" 21 #include "clk-cpu.h" 22 #include "clk-exynos5-subcmu.h" 23 24 #define APLL_LOCK 0x0 25 #define APLL_CON0 0x100 26 #define SRC_CPU 0x200 27 #define DIV_CPU0 0x500 28 #define DIV_CPU1 0x504 29 #define GATE_BUS_CPU 0x700 30 #define GATE_SCLK_CPU 0x800 31 #define CLKOUT_CMU_CPU 0xa00 32 #define SRC_MASK_CPERI 0x4300 33 #define GATE_IP_G2D 0x8800 34 #define CPLL_LOCK 0x10020 35 #define DPLL_LOCK 0x10030 36 #define EPLL_LOCK 0x10040 37 #define RPLL_LOCK 0x10050 38 #define IPLL_LOCK 0x10060 39 #define SPLL_LOCK 0x10070 40 #define VPLL_LOCK 0x10080 41 #define MPLL_LOCK 0x10090 42 #define CPLL_CON0 0x10120 43 #define DPLL_CON0 0x10128 44 #define EPLL_CON0 0x10130 45 #define EPLL_CON1 0x10134 46 #define EPLL_CON2 0x10138 47 #define RPLL_CON0 0x10140 48 #define RPLL_CON1 0x10144 49 #define RPLL_CON2 0x10148 50 #define IPLL_CON0 0x10150 51 #define SPLL_CON0 0x10160 52 #define VPLL_CON0 0x10170 53 #define MPLL_CON0 0x10180 54 #define SRC_TOP0 0x10200 55 #define SRC_TOP1 0x10204 56 #define SRC_TOP2 0x10208 57 #define SRC_TOP3 0x1020c 58 #define SRC_TOP4 0x10210 59 #define SRC_TOP5 0x10214 60 #define SRC_TOP6 0x10218 61 #define SRC_TOP7 0x1021c 62 #define SRC_TOP8 0x10220 /* 5800 specific */ 63 #define SRC_TOP9 0x10224 /* 5800 specific */ 64 #define SRC_DISP10 0x1022c 65 #define SRC_MAU 0x10240 66 #define SRC_FSYS 0x10244 67 #define SRC_PERIC0 0x10250 68 #define SRC_PERIC1 0x10254 69 #define SRC_ISP 0x10270 70 #define SRC_CAM 0x10274 /* 5800 specific */ 71 #define SRC_TOP10 0x10280 72 #define SRC_TOP11 0x10284 73 #define SRC_TOP12 0x10288 74 #define SRC_TOP13 0x1028c /* 5800 specific */ 75 #define SRC_MASK_TOP0 0x10300 76 #define SRC_MASK_TOP1 0x10304 77 #define SRC_MASK_TOP2 0x10308 78 #define SRC_MASK_TOP7 0x1031c 79 #define SRC_MASK_DISP10 0x1032c 80 #define SRC_MASK_MAU 0x10334 81 #define SRC_MASK_FSYS 0x10340 82 #define SRC_MASK_PERIC0 0x10350 83 #define SRC_MASK_PERIC1 0x10354 84 #define SRC_MASK_ISP 0x10370 85 #define DIV_TOP0 0x10500 86 #define DIV_TOP1 0x10504 87 #define DIV_TOP2 0x10508 88 #define DIV_TOP8 0x10520 /* 5800 specific */ 89 #define DIV_TOP9 0x10524 /* 5800 specific */ 90 #define DIV_DISP10 0x1052c 91 #define DIV_MAU 0x10544 92 #define DIV_FSYS0 0x10548 93 #define DIV_FSYS1 0x1054c 94 #define DIV_FSYS2 0x10550 95 #define DIV_PERIC0 0x10558 96 #define DIV_PERIC1 0x1055c 97 #define DIV_PERIC2 0x10560 98 #define DIV_PERIC3 0x10564 99 #define DIV_PERIC4 0x10568 100 #define DIV_CAM 0x10574 /* 5800 specific */ 101 #define SCLK_DIV_ISP0 0x10580 102 #define SCLK_DIV_ISP1 0x10584 103 #define DIV2_RATIO0 0x10590 104 #define DIV4_RATIO 0x105a0 105 #define GATE_BUS_TOP 0x10700 106 #define GATE_BUS_DISP1 0x10728 107 #define GATE_BUS_GEN 0x1073c 108 #define GATE_BUS_FSYS0 0x10740 109 #define GATE_BUS_FSYS2 0x10748 110 #define GATE_BUS_PERIC 0x10750 111 #define GATE_BUS_PERIC1 0x10754 112 #define GATE_BUS_PERIS0 0x10760 113 #define GATE_BUS_PERIS1 0x10764 114 #define GATE_BUS_NOC 0x10770 115 #define GATE_TOP_SCLK_ISP 0x10870 116 #define GATE_IP_GSCL0 0x10910 117 #define GATE_IP_GSCL1 0x10920 118 #define GATE_IP_CAM 0x10924 /* 5800 specific */ 119 #define GATE_IP_MFC 0x1092c 120 #define GATE_IP_DISP1 0x10928 121 #define GATE_IP_G3D 0x10930 122 #define GATE_IP_GEN 0x10934 123 #define GATE_IP_FSYS 0x10944 124 #define GATE_IP_PERIC 0x10950 125 #define GATE_IP_PERIS 0x10960 126 #define GATE_IP_MSCL 0x10970 127 #define GATE_TOP_SCLK_GSCL 0x10820 128 #define GATE_TOP_SCLK_DISP1 0x10828 129 #define GATE_TOP_SCLK_MAU 0x1083c 130 #define GATE_TOP_SCLK_FSYS 0x10840 131 #define GATE_TOP_SCLK_PERIC 0x10850 132 #define TOP_SPARE2 0x10b08 133 #define BPLL_LOCK 0x20010 134 #define BPLL_CON0 0x20110 135 #define SRC_CDREX 0x20200 136 #define DIV_CDREX0 0x20500 137 #define DIV_CDREX1 0x20504 138 #define KPLL_LOCK 0x28000 139 #define KPLL_CON0 0x28100 140 #define SRC_KFC 0x28200 141 #define DIV_KFC0 0x28500 142 143 /* Exynos5x SoC type */ 144 enum exynos5x_soc { 145 EXYNOS5420, 146 EXYNOS5800, 147 }; 148 149 /* list of PLLs */ 150 enum exynos5x_plls { 151 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 152 bpll, kpll, 153 nr_plls /* number of PLLs */ 154 }; 155 156 static void __iomem *reg_base; 157 static enum exynos5x_soc exynos5x_soc; 158 159 #ifdef CONFIG_PM_SLEEP 160 static struct samsung_clk_reg_dump *exynos5x_save; 161 static struct samsung_clk_reg_dump *exynos5800_save; 162 163 /* 164 * list of controller registers to be saved and restored during a 165 * suspend/resume cycle. 166 */ 167 static const unsigned long exynos5x_clk_regs[] __initconst = { 168 SRC_CPU, 169 DIV_CPU0, 170 DIV_CPU1, 171 GATE_BUS_CPU, 172 GATE_SCLK_CPU, 173 CLKOUT_CMU_CPU, 174 EPLL_CON0, 175 EPLL_CON1, 176 EPLL_CON2, 177 RPLL_CON0, 178 RPLL_CON1, 179 RPLL_CON2, 180 SRC_TOP0, 181 SRC_TOP1, 182 SRC_TOP2, 183 SRC_TOP3, 184 SRC_TOP4, 185 SRC_TOP5, 186 SRC_TOP6, 187 SRC_TOP7, 188 SRC_DISP10, 189 SRC_MAU, 190 SRC_FSYS, 191 SRC_PERIC0, 192 SRC_PERIC1, 193 SRC_TOP10, 194 SRC_TOP11, 195 SRC_TOP12, 196 SRC_MASK_TOP2, 197 SRC_MASK_TOP7, 198 SRC_MASK_DISP10, 199 SRC_MASK_FSYS, 200 SRC_MASK_PERIC0, 201 SRC_MASK_PERIC1, 202 SRC_MASK_TOP0, 203 SRC_MASK_TOP1, 204 SRC_MASK_MAU, 205 SRC_MASK_ISP, 206 SRC_ISP, 207 DIV_TOP0, 208 DIV_TOP1, 209 DIV_TOP2, 210 DIV_DISP10, 211 DIV_MAU, 212 DIV_FSYS0, 213 DIV_FSYS1, 214 DIV_FSYS2, 215 DIV_PERIC0, 216 DIV_PERIC1, 217 DIV_PERIC2, 218 DIV_PERIC3, 219 DIV_PERIC4, 220 SCLK_DIV_ISP0, 221 SCLK_DIV_ISP1, 222 DIV2_RATIO0, 223 DIV4_RATIO, 224 GATE_BUS_DISP1, 225 GATE_BUS_TOP, 226 GATE_BUS_GEN, 227 GATE_BUS_FSYS0, 228 GATE_BUS_FSYS2, 229 GATE_BUS_PERIC, 230 GATE_BUS_PERIC1, 231 GATE_BUS_PERIS0, 232 GATE_BUS_PERIS1, 233 GATE_BUS_NOC, 234 GATE_TOP_SCLK_ISP, 235 GATE_IP_GSCL0, 236 GATE_IP_GSCL1, 237 GATE_IP_MFC, 238 GATE_IP_DISP1, 239 GATE_IP_G3D, 240 GATE_IP_GEN, 241 GATE_IP_FSYS, 242 GATE_IP_PERIC, 243 GATE_IP_PERIS, 244 GATE_IP_MSCL, 245 GATE_TOP_SCLK_GSCL, 246 GATE_TOP_SCLK_DISP1, 247 GATE_TOP_SCLK_MAU, 248 GATE_TOP_SCLK_FSYS, 249 GATE_TOP_SCLK_PERIC, 250 TOP_SPARE2, 251 SRC_CDREX, 252 DIV_CDREX0, 253 DIV_CDREX1, 254 SRC_KFC, 255 DIV_KFC0, 256 }; 257 258 static const unsigned long exynos5800_clk_regs[] __initconst = { 259 SRC_TOP8, 260 SRC_TOP9, 261 SRC_CAM, 262 SRC_TOP1, 263 DIV_TOP8, 264 DIV_TOP9, 265 DIV_CAM, 266 GATE_IP_CAM, 267 }; 268 269 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 270 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 271 { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 272 { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 273 { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 274 { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 275 { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 276 { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 277 { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 278 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 279 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 280 { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 281 { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 282 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 283 { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 284 }; 285 286 static int exynos5420_clk_suspend(void) 287 { 288 samsung_clk_save(reg_base, exynos5x_save, 289 ARRAY_SIZE(exynos5x_clk_regs)); 290 291 if (exynos5x_soc == EXYNOS5800) 292 samsung_clk_save(reg_base, exynos5800_save, 293 ARRAY_SIZE(exynos5800_clk_regs)); 294 295 samsung_clk_restore(reg_base, exynos5420_set_clksrc, 296 ARRAY_SIZE(exynos5420_set_clksrc)); 297 298 return 0; 299 } 300 301 static void exynos5420_clk_resume(void) 302 { 303 samsung_clk_restore(reg_base, exynos5x_save, 304 ARRAY_SIZE(exynos5x_clk_regs)); 305 306 if (exynos5x_soc == EXYNOS5800) 307 samsung_clk_restore(reg_base, exynos5800_save, 308 ARRAY_SIZE(exynos5800_clk_regs)); 309 } 310 311 static struct syscore_ops exynos5420_clk_syscore_ops = { 312 .suspend = exynos5420_clk_suspend, 313 .resume = exynos5420_clk_resume, 314 }; 315 316 static void __init exynos5420_clk_sleep_init(void) 317 { 318 exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs, 319 ARRAY_SIZE(exynos5x_clk_regs)); 320 if (!exynos5x_save) { 321 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 322 __func__); 323 return; 324 } 325 326 if (exynos5x_soc == EXYNOS5800) { 327 exynos5800_save = 328 samsung_clk_alloc_reg_dump(exynos5800_clk_regs, 329 ARRAY_SIZE(exynos5800_clk_regs)); 330 if (!exynos5800_save) 331 goto err_soc; 332 } 333 334 register_syscore_ops(&exynos5420_clk_syscore_ops); 335 return; 336 err_soc: 337 kfree(exynos5x_save); 338 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 339 __func__); 340 return; 341 } 342 #else 343 static void __init exynos5420_clk_sleep_init(void) {} 344 #endif 345 346 /* list of all parent clocks */ 347 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 348 "mout_sclk_mpll", "mout_sclk_spll"}; 349 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 350 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 351 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 352 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 353 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 354 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 355 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 356 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 357 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 358 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 359 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 360 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 361 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 362 363 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 364 "mout_sclk_mpll"}; 365 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 366 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 367 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 368 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 369 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 370 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 371 372 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 373 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 374 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 375 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 376 377 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 378 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 379 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 380 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 381 382 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 383 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 384 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 385 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 386 387 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 388 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 389 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 390 391 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 392 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 393 394 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 395 "mout_sclk_spll"}; 396 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 397 398 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 399 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 400 401 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 402 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 403 404 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 405 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 406 407 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 408 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 409 410 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 411 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 412 413 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 414 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 415 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 416 417 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 418 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 419 420 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 421 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 422 423 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 424 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 425 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 426 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 427 428 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 429 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 430 431 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 432 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 433 434 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 435 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 436 437 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 438 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 439 440 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 441 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 442 "mout_sclk_epll", "mout_sclk_rpll"}; 443 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 444 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 445 "mout_sclk_epll", "mout_sclk_rpll"}; 446 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 447 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 448 "mout_sclk_epll", "mout_sclk_rpll"}; 449 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 450 "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 451 "mout_sclk_epll", "mout_sclk_rpll"}; 452 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 453 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 454 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 455 "mout_sclk_epll", "mout_sclk_rpll"}; 456 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 457 "mout_sclk_mpll", "mout_sclk_spll"}; 458 PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"}; 459 460 /* List of parents specific to exynos5800 */ 461 PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 462 PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 463 "mout_sclk_mpll", "ff_dout_spll2" }; 464 PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 465 "mout_sclk_mpll", "ff_dout_spll2", 466 "mout_epll2", "mout_sclk_ipll" }; 467 PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 468 "mout_sclk_mpll", "ff_dout_spll2", 469 "mout_epll2" }; 470 PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 471 "mout_sclk_mpll", "mout_sclk_spll" }; 472 PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 473 "mout_sclk_mpll", "ff_dout_spll2" }; 474 PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 475 "mout_sclk_mpll", "mout_sclk_spll", 476 "mout_epll2", "mout_sclk_ipll" }; 477 PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll", 478 "mout_sclk_mpll", "ff_dout_spll2", 479 "mout_sclk_spll", "mout_sclk_epll"}; 480 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 481 "mout_sclk_mpll", 482 "ff_dout_spll2" }; 483 PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 484 PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 485 PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 486 PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 487 PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 488 PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 489 PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 490 PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 491 PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; 492 493 /* fixed rate clocks generated outside the soc */ 494 static struct samsung_fixed_rate_clock 495 exynos5x_fixed_rate_ext_clks[] __initdata = { 496 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 497 }; 498 499 /* fixed rate clocks generated inside the soc */ 500 static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { 501 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 502 FRATE(0, "sclk_pwi", NULL, 0, 24000000), 503 FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 504 FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 505 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 506 }; 507 508 static const struct samsung_fixed_factor_clock 509 exynos5x_fixed_factor_clks[] __initconst = { 510 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 511 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 512 }; 513 514 static const struct samsung_fixed_factor_clock 515 exynos5800_fixed_factor_clks[] __initconst = { 516 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 517 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 518 }; 519 520 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 521 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 522 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 523 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 524 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 525 526 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 527 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 528 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 529 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 530 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 531 532 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 533 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 534 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 535 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 536 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 537 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 538 539 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 540 mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), 541 MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, 542 SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), 543 MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 544 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 545 546 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 547 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 548 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 549 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 550 551 MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, 552 SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0), 553 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 554 SRC_TOP9, 16, 1), 555 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 556 SRC_TOP9, 20, 1), 557 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 558 SRC_TOP9, 24, 1), 559 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 560 SRC_TOP9, 28, 1), 561 562 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 563 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 564 SRC_TOP13, 20, 1), 565 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 566 SRC_TOP13, 24, 1), 567 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 568 SRC_TOP13, 28, 1), 569 570 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 571 }; 572 573 static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { 574 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 575 "mout_aclk400_wcore", DIV_TOP0, 16, 3), 576 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 577 DIV_TOP8, 16, 3), 578 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 579 DIV_TOP8, 20, 3), 580 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 581 DIV_TOP8, 24, 3), 582 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 583 DIV_TOP8, 28, 3), 584 585 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 586 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 587 }; 588 589 static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 590 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 591 GATE_BUS_TOP, 24, 0, 0), 592 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 593 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), 594 GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", 595 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 596 }; 597 598 static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 599 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 600 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 601 TOP_SPARE2, 4, 1), 602 603 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 604 MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2), 605 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 606 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 607 608 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 609 MUX(0, "mout_aclk333_432_isp", mout_group4_p, 610 SRC_TOP1, 4, 2), 611 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 612 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 613 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 614 615 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 616 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 617 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 618 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 619 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 620 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 621 622 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 623 mout_group5_5800_p, SRC_TOP7, 16, 2), 624 MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2, 625 CLK_SET_RATE_PARENT, 0), 626 627 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 628 }; 629 630 static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 631 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 632 "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 633 }; 634 635 static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { 636 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 637 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 638 }; 639 640 static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 641 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 642 SRC_TOP7, 4, 1), 643 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 644 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 645 646 MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 647 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 648 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 649 MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 650 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 651 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 652 653 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 654 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 655 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 656 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 657 658 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 659 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 660 661 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 662 663 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 664 SRC_TOP3, 0, 1), 665 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 666 SRC_TOP3, 4, 1), 667 MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 668 mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 669 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 670 SRC_TOP3, 12, 1), 671 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 672 SRC_TOP3, 16, 1), 673 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 674 SRC_TOP3, 20, 1), 675 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 676 SRC_TOP3, 24, 1), 677 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 678 SRC_TOP3, 28, 1), 679 680 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 681 SRC_TOP4, 0, 1), 682 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 683 SRC_TOP4, 4, 1), 684 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 685 SRC_TOP4, 8, 1), 686 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 687 SRC_TOP4, 12, 1), 688 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 689 SRC_TOP4, 16, 1), 690 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 691 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 692 MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 693 SRC_TOP4, 28, 1), 694 695 MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 696 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 697 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 698 SRC_TOP5, 4, 1), 699 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 700 SRC_TOP5, 8, 1), 701 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 702 SRC_TOP5, 12, 1), 703 MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 704 SRC_TOP5, 16, 1), 705 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 706 SRC_TOP5, 20, 1), 707 MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 708 mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 709 MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 710 mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 711 712 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 713 MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 714 MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 715 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 716 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 717 MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, 718 CLK_SET_RATE_PARENT, 0), 719 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 720 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 721 722 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 723 SRC_TOP10, 0, 1), 724 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 725 SRC_TOP10, 4, 1), 726 MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 727 SRC_TOP10, 8, 1), 728 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 729 SRC_TOP10, 12, 1), 730 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 731 SRC_TOP10, 16, 1), 732 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 733 SRC_TOP10, 20, 1), 734 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 735 SRC_TOP10, 24, 1), 736 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 737 SRC_TOP10, 28, 1), 738 739 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 740 SRC_TOP11, 0, 1), 741 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 742 SRC_TOP11, 4, 1), 743 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 744 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 745 SRC_TOP11, 12, 1), 746 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 747 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 748 MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 749 SRC_TOP11, 28, 1), 750 751 MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 752 mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 753 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 754 SRC_TOP12, 8, 1), 755 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 756 SRC_TOP12, 12, 1), 757 MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 758 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 759 SRC_TOP12, 20, 1), 760 MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 761 mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 762 MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 763 mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 764 765 /* DISP1 Block */ 766 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 767 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 768 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 769 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 770 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 771 772 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 773 774 /* CDREX block */ 775 MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p, 776 SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0), 777 MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1, 778 CLK_SET_RATE_PARENT, 0), 779 780 /* MAU Block */ 781 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 782 783 /* FSYS Block */ 784 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 785 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 786 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 787 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 788 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 789 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 790 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 791 792 /* PERIC Block */ 793 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 794 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 795 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 796 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 797 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 798 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 799 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 800 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 801 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 802 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 803 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 804 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 805 806 /* ISP Block */ 807 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 808 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 809 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 810 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 811 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 812 }; 813 814 static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 815 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 816 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 817 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 818 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 819 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 820 821 DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 822 DIV_TOP0, 0, 3), 823 DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 824 DIV_TOP0, 4, 3), 825 DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 826 DIV_TOP0, 8, 3), 827 DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 828 DIV_TOP0, 12, 3), 829 DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 830 DIV_TOP0, 20, 3), 831 DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 832 DIV_TOP0, 24, 3), 833 DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 834 DIV_TOP0, 28, 3), 835 DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 836 "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 837 DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 838 "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 839 DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 840 DIV_TOP1, 8, 6), 841 DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 842 "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 843 DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 844 DIV_TOP1, 20, 3), 845 DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 846 DIV_TOP1, 24, 3), 847 DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 848 DIV_TOP1, 28, 3), 849 850 DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 851 DIV_TOP2, 8, 3), 852 DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 853 DIV_TOP2, 12, 3), 854 DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 855 16, 3), 856 DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 857 DIV_TOP2, 20, 3), 858 DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 859 "mout_aclk300_disp1", DIV_TOP2, 24, 3), 860 DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 861 DIV_TOP2, 28, 3), 862 863 /* DISP1 Block */ 864 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 865 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 866 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 867 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 868 DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 869 "mout_aclk400_disp1", DIV_TOP2, 4, 3), 870 871 /* CDREX Block */ 872 DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", 873 DIV_CDREX0, 28, 3), 874 DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", 875 DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), 876 DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", 877 DIV_CDREX0, 16, 3), 878 DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", 879 DIV_CDREX0, 8, 3), 880 DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", 881 DIV_CDREX0, 3, 5), 882 883 DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", 884 DIV_CDREX1, 8, 3), 885 886 /* Audio Block */ 887 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 888 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 889 890 /* USB3.0 */ 891 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 892 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 893 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 894 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 895 896 /* MMC */ 897 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 898 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 899 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 900 901 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 902 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 903 904 /* UART and PWM */ 905 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 906 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 907 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 908 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 909 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 910 911 /* SPI */ 912 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 913 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 914 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 915 916 917 /* PCM */ 918 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 919 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 920 921 /* Audio - I2S */ 922 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 923 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 924 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 925 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 926 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 927 928 /* SPI Pre-Ratio */ 929 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 930 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 931 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 932 933 /* GSCL Block */ 934 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 935 936 /* MSCL Block */ 937 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 938 939 /* PSGEN */ 940 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 941 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 942 943 /* ISP Block */ 944 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 945 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 946 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 947 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 948 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 949 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 950 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 951 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 952 CLK_SET_RATE_PARENT, 0), 953 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 954 CLK_SET_RATE_PARENT, 0), 955 }; 956 957 static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 958 /* G2D */ 959 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 960 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 961 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 962 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 963 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 964 965 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 966 GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), 967 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 968 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 969 970 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 971 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 972 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 973 GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), 974 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 975 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 976 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 977 GATE_BUS_TOP, 5, 0, 0), 978 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 979 GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), 980 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 981 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 982 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 983 GATE_BUS_TOP, 8, 0, 0), 984 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 985 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 986 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 987 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 988 GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 989 GATE_BUS_TOP, 13, 0, 0), 990 GATE(0, "aclk166", "mout_user_aclk166", 991 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 992 GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", 993 GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), 994 GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 995 GATE_BUS_TOP, 16, 0, 0), 996 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 997 GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), 998 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 999 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), 1000 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 1001 GATE_BUS_TOP, 28, 0, 0), 1002 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 1003 GATE_BUS_TOP, 29, 0, 0), 1004 1005 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 1006 SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), 1007 1008 /* sclk */ 1009 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 1010 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 1011 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 1012 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 1013 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 1014 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 1015 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 1016 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 1017 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 1018 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 1019 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 1020 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 1021 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 1022 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 1023 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 1024 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 1025 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 1026 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1027 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 1028 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 1029 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 1030 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 1031 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 1032 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 1033 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 1034 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 1035 1036 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 1037 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 1038 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 1039 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 1040 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 1041 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 1042 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 1043 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 1044 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 1045 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 1046 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 1047 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 1048 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 1049 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 1050 1051 /* Display */ 1052 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 1053 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 1054 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 1055 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 1056 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 1057 GATE_TOP_SCLK_DISP1, 9, 0, 0), 1058 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 1059 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 1060 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 1061 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 1062 1063 /* Maudio Block */ 1064 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 1065 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1066 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 1067 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 1068 1069 /* FSYS Block */ 1070 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1071 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1072 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1073 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 1074 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 1075 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 1076 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 1077 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1078 GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 1079 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 1080 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 1081 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 1082 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 1083 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 1084 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 1085 1086 /* PERIC Block */ 1087 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 1088 GATE_IP_PERIC, 0, 0, 0), 1089 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 1090 GATE_IP_PERIC, 1, 0, 0), 1091 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 1092 GATE_IP_PERIC, 2, 0, 0), 1093 GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 1094 GATE_IP_PERIC, 3, 0, 0), 1095 GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 1096 GATE_IP_PERIC, 6, 0, 0), 1097 GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 1098 GATE_IP_PERIC, 7, 0, 0), 1099 GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 1100 GATE_IP_PERIC, 8, 0, 0), 1101 GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 1102 GATE_IP_PERIC, 9, 0, 0), 1103 GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 1104 GATE_IP_PERIC, 10, 0, 0), 1105 GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 1106 GATE_IP_PERIC, 11, 0, 0), 1107 GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 1108 GATE_IP_PERIC, 12, 0, 0), 1109 GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 1110 GATE_IP_PERIC, 13, 0, 0), 1111 GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 1112 GATE_IP_PERIC, 14, 0, 0), 1113 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 1114 GATE_IP_PERIC, 15, 0, 0), 1115 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 1116 GATE_IP_PERIC, 16, 0, 0), 1117 GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 1118 GATE_IP_PERIC, 17, 0, 0), 1119 GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 1120 GATE_IP_PERIC, 18, 0, 0), 1121 GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 1122 GATE_IP_PERIC, 20, 0, 0), 1123 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 1124 GATE_IP_PERIC, 21, 0, 0), 1125 GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 1126 GATE_IP_PERIC, 22, 0, 0), 1127 GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 1128 GATE_IP_PERIC, 23, 0, 0), 1129 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 1130 GATE_IP_PERIC, 24, 0, 0), 1131 GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 1132 GATE_IP_PERIC, 26, 0, 0), 1133 GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 1134 GATE_IP_PERIC, 28, 0, 0), 1135 GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 1136 GATE_IP_PERIC, 30, 0, 0), 1137 GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 1138 GATE_IP_PERIC, 31, 0, 0), 1139 1140 GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 1141 GATE_BUS_PERIC, 22, 0, 0), 1142 1143 /* PERIS Block */ 1144 GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 1145 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1146 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 1147 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1148 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 1149 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 1150 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 1151 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 1152 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 1153 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 1154 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 1155 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 1156 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 1157 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 1158 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 1159 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 1160 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 1161 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 1162 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 1163 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 1164 1165 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 1166 1167 /* GEN Block */ 1168 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 1169 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 1170 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 1171 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 1172 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 1173 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 1174 GATE_IP_GEN, 6, 0, 0), 1175 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 1176 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 1177 GATE_IP_GEN, 9, 0, 0), 1178 1179 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 1180 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 1181 GATE_BUS_GEN, 28, 0, 0), 1182 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 1183 1184 /* GSCL Block */ 1185 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 1186 GATE_TOP_SCLK_GSCL, 6, 0, 0), 1187 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 1188 GATE_TOP_SCLK_GSCL, 7, 0, 0), 1189 1190 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 1191 GATE_IP_GSCL0, 4, 0, 0), 1192 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 1193 GATE_IP_GSCL0, 5, 0, 0), 1194 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 1195 GATE_IP_GSCL0, 6, 0, 0), 1196 1197 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 1198 GATE_IP_GSCL1, 2, 0, 0), 1199 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 1200 GATE_IP_GSCL1, 3, 0, 0), 1201 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 1202 GATE_IP_GSCL1, 4, 0, 0), 1203 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 1204 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 1205 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 1206 GATE_IP_GSCL1, 16, 0, 0), 1207 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 1208 GATE_IP_GSCL1, 17, 0, 0), 1209 1210 /* MSCL Block */ 1211 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 1212 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 1213 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 1214 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 1215 GATE_IP_MSCL, 8, 0, 0), 1216 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 1217 GATE_IP_MSCL, 9, 0, 0), 1218 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 1219 GATE_IP_MSCL, 10, 0, 0), 1220 1221 /* ISP */ 1222 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 1223 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 1224 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 1225 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 1226 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 1227 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 1228 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 1229 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 1230 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 1231 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 1232 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 1233 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 1234 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 1235 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 1236 1237 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 1238 }; 1239 1240 static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { 1241 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 1242 }; 1243 1244 static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { 1245 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1246 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1247 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1248 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1249 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1250 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1251 GATE_IP_DISP1, 7, 0, 0), 1252 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1253 GATE_IP_DISP1, 8, 0, 0), 1254 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1255 GATE_IP_DISP1, 9, 0, 0), 1256 }; 1257 1258 static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = { 1259 { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ 1260 { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ 1261 { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ 1262 { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ 1263 { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ 1264 }; 1265 1266 static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { 1267 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 1268 DIV2_RATIO0, 4, 2), 1269 }; 1270 1271 static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { 1272 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1273 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1274 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 1275 GATE_IP_GSCL1, 6, 0, 0), 1276 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 1277 GATE_IP_GSCL1, 7, 0, 0), 1278 }; 1279 1280 static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { 1281 { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ 1282 { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ 1283 { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ 1284 { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ 1285 }; 1286 1287 static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { 1288 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 1289 }; 1290 1291 static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { 1292 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 1293 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 1294 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 1295 }; 1296 1297 static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { 1298 { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ 1299 { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ 1300 { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ 1301 }; 1302 1303 static const struct exynos5_subcmu_info exynos5x_subcmus[] = { 1304 { 1305 .div_clks = exynos5x_disp_div_clks, 1306 .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), 1307 .gate_clks = exynos5x_disp_gate_clks, 1308 .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), 1309 .suspend_regs = exynos5x_disp_suspend_regs, 1310 .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), 1311 .pd_name = "DISP", 1312 }, { 1313 .div_clks = exynos5x_gsc_div_clks, 1314 .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), 1315 .gate_clks = exynos5x_gsc_gate_clks, 1316 .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), 1317 .suspend_regs = exynos5x_gsc_suspend_regs, 1318 .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), 1319 .pd_name = "GSC", 1320 }, { 1321 .div_clks = exynos5x_mfc_div_clks, 1322 .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), 1323 .gate_clks = exynos5x_mfc_gate_clks, 1324 .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), 1325 .suspend_regs = exynos5x_mfc_suspend_regs, 1326 .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), 1327 .pd_name = "MFC", 1328 }, 1329 }; 1330 1331 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { 1332 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0), 1333 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0), 1334 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0), 1335 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), 1336 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 1337 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 1338 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 1339 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 1340 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1), 1341 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), 1342 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), 1343 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1), 1344 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), 1345 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 1346 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2), 1347 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), 1348 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), 1349 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3), 1350 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), 1351 }; 1352 1353 static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 1354 PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), 1355 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), 1356 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), 1357 PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671), 1358 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0), 1359 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), 1360 PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671), 1361 PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719), 1362 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0), 1363 PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923), 1364 PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762), 1365 PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719), 1366 PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690), 1367 PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762), 1368 PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), 1369 }; 1370 1371 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1372 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1373 APLL_CON0, NULL), 1374 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1375 CPLL_CON0, NULL), 1376 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 1377 DPLL_CON0, NULL), 1378 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 1379 EPLL_CON0, NULL), 1380 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 1381 RPLL_CON0, NULL), 1382 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 1383 IPLL_CON0, NULL), 1384 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 1385 SPLL_CON0, NULL), 1386 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 1387 VPLL_CON0, NULL), 1388 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 1389 MPLL_CON0, NULL), 1390 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 1391 BPLL_CON0, NULL), 1392 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 1393 KPLL_CON0, NULL), 1394 }; 1395 1396 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1397 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1398 ((cpud) << 4))) 1399 1400 static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1401 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1402 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1403 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1404 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1405 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1406 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1407 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1408 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1409 { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1410 { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1411 { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1412 { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1413 { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1414 { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1415 { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1416 { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1417 { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1418 { 0 }, 1419 }; 1420 1421 static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 1422 { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1423 { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1424 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1425 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1426 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1427 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1428 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1429 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1430 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1431 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1432 { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 1433 { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 1434 { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 1435 { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 1436 { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 1437 { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1438 { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1439 { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1440 { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1441 { 0 }, 1442 }; 1443 1444 #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1445 ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1446 1447 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 1448 { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1449 { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1450 { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1451 { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1452 { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1453 { 900000, E5420_KFC_DIV(3, 5, 2), }, 1454 { 800000, E5420_KFC_DIV(3, 5, 2), }, 1455 { 700000, E5420_KFC_DIV(3, 4, 2), }, 1456 { 600000, E5420_KFC_DIV(3, 4, 2), }, 1457 { 500000, E5420_KFC_DIV(3, 4, 2), }, 1458 { 400000, E5420_KFC_DIV(3, 3, 2), }, 1459 { 300000, E5420_KFC_DIV(3, 3, 2), }, 1460 { 200000, E5420_KFC_DIV(3, 3, 2), }, 1461 { 0 }, 1462 }; 1463 1464 static const struct of_device_id ext_clk_match[] __initconst = { 1465 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 1466 { }, 1467 }; 1468 1469 /* register exynos5420 clocks */ 1470 static void __init exynos5x_clk_init(struct device_node *np, 1471 enum exynos5x_soc soc) 1472 { 1473 struct samsung_clk_provider *ctx; 1474 1475 if (np) { 1476 reg_base = of_iomap(np, 0); 1477 if (!reg_base) 1478 panic("%s: failed to map registers\n", __func__); 1479 } else { 1480 panic("%s: unable to determine soc\n", __func__); 1481 } 1482 1483 exynos5x_soc = soc; 1484 1485 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1486 1487 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 1488 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 1489 ext_clk_match); 1490 1491 if (_get_rate("fin_pll") == 24 * MHZ) { 1492 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1493 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; 1494 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1495 exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1496 } 1497 1498 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1499 reg_base); 1500 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 1501 ARRAY_SIZE(exynos5x_fixed_rate_clks)); 1502 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 1503 ARRAY_SIZE(exynos5x_fixed_factor_clks)); 1504 samsung_clk_register_mux(ctx, exynos5x_mux_clks, 1505 ARRAY_SIZE(exynos5x_mux_clks)); 1506 samsung_clk_register_div(ctx, exynos5x_div_clks, 1507 ARRAY_SIZE(exynos5x_div_clks)); 1508 samsung_clk_register_gate(ctx, exynos5x_gate_clks, 1509 ARRAY_SIZE(exynos5x_gate_clks)); 1510 1511 if (soc == EXYNOS5420) { 1512 samsung_clk_register_mux(ctx, exynos5420_mux_clks, 1513 ARRAY_SIZE(exynos5420_mux_clks)); 1514 samsung_clk_register_div(ctx, exynos5420_div_clks, 1515 ARRAY_SIZE(exynos5420_div_clks)); 1516 samsung_clk_register_gate(ctx, exynos5420_gate_clks, 1517 ARRAY_SIZE(exynos5420_gate_clks)); 1518 } else { 1519 samsung_clk_register_fixed_factor( 1520 ctx, exynos5800_fixed_factor_clks, 1521 ARRAY_SIZE(exynos5800_fixed_factor_clks)); 1522 samsung_clk_register_mux(ctx, exynos5800_mux_clks, 1523 ARRAY_SIZE(exynos5800_mux_clks)); 1524 samsung_clk_register_div(ctx, exynos5800_div_clks, 1525 ARRAY_SIZE(exynos5800_div_clks)); 1526 samsung_clk_register_gate(ctx, exynos5800_gate_clks, 1527 ARRAY_SIZE(exynos5800_gate_clks)); 1528 } 1529 1530 if (soc == EXYNOS5420) { 1531 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1532 mout_cpu_p[0], mout_cpu_p[1], 0x200, 1533 exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); 1534 } else { 1535 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1536 mout_cpu_p[0], mout_cpu_p[1], 0x200, 1537 exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); 1538 } 1539 exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", 1540 mout_kfc_p[0], mout_kfc_p[1], 0x28200, 1541 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); 1542 1543 exynos5420_clk_sleep_init(); 1544 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), 1545 exynos5x_subcmus); 1546 1547 samsung_clk_of_add_provider(np, ctx); 1548 } 1549 1550 static void __init exynos5420_clk_init(struct device_node *np) 1551 { 1552 exynos5x_clk_init(np, EXYNOS5420); 1553 } 1554 CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", 1555 exynos5420_clk_init); 1556 1557 static void __init exynos5800_clk_init(struct device_node *np) 1558 { 1559 exynos5x_clk_init(np, EXYNOS5800); 1560 } 1561 CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", 1562 exynos5800_clk_init); 1563