1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Authors: Thomas Abraham <thomas.ab@samsung.com> 4 * Chander Kashyap <k.chander@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for Exynos5420 SoC. 11 */ 12 13 #include <dt-bindings/clock/exynos5420.h> 14 #include <linux/slab.h> 15 #include <linux/clk-provider.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/syscore_ops.h> 19 20 #include "clk.h" 21 #include "clk-cpu.h" 22 23 #define APLL_LOCK 0x0 24 #define APLL_CON0 0x100 25 #define SRC_CPU 0x200 26 #define DIV_CPU0 0x500 27 #define DIV_CPU1 0x504 28 #define GATE_BUS_CPU 0x700 29 #define GATE_SCLK_CPU 0x800 30 #define CLKOUT_CMU_CPU 0xa00 31 #define SRC_MASK_CPERI 0x4300 32 #define GATE_IP_G2D 0x8800 33 #define CPLL_LOCK 0x10020 34 #define DPLL_LOCK 0x10030 35 #define EPLL_LOCK 0x10040 36 #define RPLL_LOCK 0x10050 37 #define IPLL_LOCK 0x10060 38 #define SPLL_LOCK 0x10070 39 #define VPLL_LOCK 0x10080 40 #define MPLL_LOCK 0x10090 41 #define CPLL_CON0 0x10120 42 #define DPLL_CON0 0x10128 43 #define EPLL_CON0 0x10130 44 #define EPLL_CON1 0x10134 45 #define EPLL_CON2 0x10138 46 #define RPLL_CON0 0x10140 47 #define RPLL_CON1 0x10144 48 #define RPLL_CON2 0x10148 49 #define IPLL_CON0 0x10150 50 #define SPLL_CON0 0x10160 51 #define VPLL_CON0 0x10170 52 #define MPLL_CON0 0x10180 53 #define SRC_TOP0 0x10200 54 #define SRC_TOP1 0x10204 55 #define SRC_TOP2 0x10208 56 #define SRC_TOP3 0x1020c 57 #define SRC_TOP4 0x10210 58 #define SRC_TOP5 0x10214 59 #define SRC_TOP6 0x10218 60 #define SRC_TOP7 0x1021c 61 #define SRC_TOP8 0x10220 /* 5800 specific */ 62 #define SRC_TOP9 0x10224 /* 5800 specific */ 63 #define SRC_DISP10 0x1022c 64 #define SRC_MAU 0x10240 65 #define SRC_FSYS 0x10244 66 #define SRC_PERIC0 0x10250 67 #define SRC_PERIC1 0x10254 68 #define SRC_ISP 0x10270 69 #define SRC_CAM 0x10274 /* 5800 specific */ 70 #define SRC_TOP10 0x10280 71 #define SRC_TOP11 0x10284 72 #define SRC_TOP12 0x10288 73 #define SRC_TOP13 0x1028c /* 5800 specific */ 74 #define SRC_MASK_TOP0 0x10300 75 #define SRC_MASK_TOP1 0x10304 76 #define SRC_MASK_TOP2 0x10308 77 #define SRC_MASK_TOP7 0x1031c 78 #define SRC_MASK_DISP10 0x1032c 79 #define SRC_MASK_MAU 0x10334 80 #define SRC_MASK_FSYS 0x10340 81 #define SRC_MASK_PERIC0 0x10350 82 #define SRC_MASK_PERIC1 0x10354 83 #define SRC_MASK_ISP 0x10370 84 #define DIV_TOP0 0x10500 85 #define DIV_TOP1 0x10504 86 #define DIV_TOP2 0x10508 87 #define DIV_TOP8 0x10520 /* 5800 specific */ 88 #define DIV_TOP9 0x10524 /* 5800 specific */ 89 #define DIV_DISP10 0x1052c 90 #define DIV_MAU 0x10544 91 #define DIV_FSYS0 0x10548 92 #define DIV_FSYS1 0x1054c 93 #define DIV_FSYS2 0x10550 94 #define DIV_PERIC0 0x10558 95 #define DIV_PERIC1 0x1055c 96 #define DIV_PERIC2 0x10560 97 #define DIV_PERIC3 0x10564 98 #define DIV_PERIC4 0x10568 99 #define DIV_CAM 0x10574 /* 5800 specific */ 100 #define SCLK_DIV_ISP0 0x10580 101 #define SCLK_DIV_ISP1 0x10584 102 #define DIV2_RATIO0 0x10590 103 #define DIV4_RATIO 0x105a0 104 #define GATE_BUS_TOP 0x10700 105 #define GATE_BUS_DISP1 0x10728 106 #define GATE_BUS_GEN 0x1073c 107 #define GATE_BUS_FSYS0 0x10740 108 #define GATE_BUS_FSYS2 0x10748 109 #define GATE_BUS_PERIC 0x10750 110 #define GATE_BUS_PERIC1 0x10754 111 #define GATE_BUS_PERIS0 0x10760 112 #define GATE_BUS_PERIS1 0x10764 113 #define GATE_BUS_NOC 0x10770 114 #define GATE_TOP_SCLK_ISP 0x10870 115 #define GATE_IP_GSCL0 0x10910 116 #define GATE_IP_GSCL1 0x10920 117 #define GATE_IP_CAM 0x10924 /* 5800 specific */ 118 #define GATE_IP_MFC 0x1092c 119 #define GATE_IP_DISP1 0x10928 120 #define GATE_IP_G3D 0x10930 121 #define GATE_IP_GEN 0x10934 122 #define GATE_IP_FSYS 0x10944 123 #define GATE_IP_PERIC 0x10950 124 #define GATE_IP_PERIS 0x10960 125 #define GATE_IP_MSCL 0x10970 126 #define GATE_TOP_SCLK_GSCL 0x10820 127 #define GATE_TOP_SCLK_DISP1 0x10828 128 #define GATE_TOP_SCLK_MAU 0x1083c 129 #define GATE_TOP_SCLK_FSYS 0x10840 130 #define GATE_TOP_SCLK_PERIC 0x10850 131 #define TOP_SPARE2 0x10b08 132 #define BPLL_LOCK 0x20010 133 #define BPLL_CON0 0x20110 134 #define KPLL_LOCK 0x28000 135 #define KPLL_CON0 0x28100 136 #define SRC_KFC 0x28200 137 #define DIV_KFC0 0x28500 138 139 /* Exynos5x SoC type */ 140 enum exynos5x_soc { 141 EXYNOS5420, 142 EXYNOS5800, 143 }; 144 145 /* list of PLLs */ 146 enum exynos5x_plls { 147 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 148 bpll, kpll, 149 nr_plls /* number of PLLs */ 150 }; 151 152 static void __iomem *reg_base; 153 static enum exynos5x_soc exynos5x_soc; 154 155 #ifdef CONFIG_PM_SLEEP 156 static struct samsung_clk_reg_dump *exynos5x_save; 157 static struct samsung_clk_reg_dump *exynos5800_save; 158 159 /* 160 * list of controller registers to be saved and restored during a 161 * suspend/resume cycle. 162 */ 163 static unsigned long exynos5x_clk_regs[] __initdata = { 164 SRC_CPU, 165 DIV_CPU0, 166 DIV_CPU1, 167 GATE_BUS_CPU, 168 GATE_SCLK_CPU, 169 CLKOUT_CMU_CPU, 170 EPLL_CON0, 171 EPLL_CON1, 172 EPLL_CON2, 173 RPLL_CON0, 174 RPLL_CON1, 175 RPLL_CON2, 176 SRC_TOP0, 177 SRC_TOP1, 178 SRC_TOP2, 179 SRC_TOP3, 180 SRC_TOP4, 181 SRC_TOP5, 182 SRC_TOP6, 183 SRC_TOP7, 184 SRC_DISP10, 185 SRC_MAU, 186 SRC_FSYS, 187 SRC_PERIC0, 188 SRC_PERIC1, 189 SRC_TOP10, 190 SRC_TOP11, 191 SRC_TOP12, 192 SRC_MASK_TOP2, 193 SRC_MASK_TOP7, 194 SRC_MASK_DISP10, 195 SRC_MASK_FSYS, 196 SRC_MASK_PERIC0, 197 SRC_MASK_PERIC1, 198 SRC_MASK_TOP0, 199 SRC_MASK_TOP1, 200 SRC_MASK_MAU, 201 SRC_MASK_ISP, 202 SRC_ISP, 203 DIV_TOP0, 204 DIV_TOP1, 205 DIV_TOP2, 206 DIV_DISP10, 207 DIV_MAU, 208 DIV_FSYS0, 209 DIV_FSYS1, 210 DIV_FSYS2, 211 DIV_PERIC0, 212 DIV_PERIC1, 213 DIV_PERIC2, 214 DIV_PERIC3, 215 DIV_PERIC4, 216 SCLK_DIV_ISP0, 217 SCLK_DIV_ISP1, 218 DIV2_RATIO0, 219 DIV4_RATIO, 220 GATE_BUS_DISP1, 221 GATE_BUS_TOP, 222 GATE_BUS_GEN, 223 GATE_BUS_FSYS0, 224 GATE_BUS_FSYS2, 225 GATE_BUS_PERIC, 226 GATE_BUS_PERIC1, 227 GATE_BUS_PERIS0, 228 GATE_BUS_PERIS1, 229 GATE_BUS_NOC, 230 GATE_TOP_SCLK_ISP, 231 GATE_IP_GSCL0, 232 GATE_IP_GSCL1, 233 GATE_IP_MFC, 234 GATE_IP_DISP1, 235 GATE_IP_G3D, 236 GATE_IP_GEN, 237 GATE_IP_FSYS, 238 GATE_IP_PERIC, 239 GATE_IP_PERIS, 240 GATE_IP_MSCL, 241 GATE_TOP_SCLK_GSCL, 242 GATE_TOP_SCLK_DISP1, 243 GATE_TOP_SCLK_MAU, 244 GATE_TOP_SCLK_FSYS, 245 GATE_TOP_SCLK_PERIC, 246 TOP_SPARE2, 247 SRC_KFC, 248 DIV_KFC0, 249 }; 250 251 static unsigned long exynos5800_clk_regs[] __initdata = { 252 SRC_TOP8, 253 SRC_TOP9, 254 SRC_CAM, 255 SRC_TOP1, 256 DIV_TOP8, 257 DIV_TOP9, 258 DIV_CAM, 259 GATE_IP_CAM, 260 }; 261 262 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 263 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 264 { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 265 { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 266 { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 267 { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 268 { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 269 { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 270 { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 271 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 272 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 273 { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 274 { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 275 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 276 { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 277 }; 278 279 static int exynos5420_clk_suspend(void) 280 { 281 samsung_clk_save(reg_base, exynos5x_save, 282 ARRAY_SIZE(exynos5x_clk_regs)); 283 284 if (exynos5x_soc == EXYNOS5800) 285 samsung_clk_save(reg_base, exynos5800_save, 286 ARRAY_SIZE(exynos5800_clk_regs)); 287 288 samsung_clk_restore(reg_base, exynos5420_set_clksrc, 289 ARRAY_SIZE(exynos5420_set_clksrc)); 290 291 return 0; 292 } 293 294 static void exynos5420_clk_resume(void) 295 { 296 samsung_clk_restore(reg_base, exynos5x_save, 297 ARRAY_SIZE(exynos5x_clk_regs)); 298 299 if (exynos5x_soc == EXYNOS5800) 300 samsung_clk_restore(reg_base, exynos5800_save, 301 ARRAY_SIZE(exynos5800_clk_regs)); 302 } 303 304 static struct syscore_ops exynos5420_clk_syscore_ops = { 305 .suspend = exynos5420_clk_suspend, 306 .resume = exynos5420_clk_resume, 307 }; 308 309 static void exynos5420_clk_sleep_init(void) 310 { 311 exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs, 312 ARRAY_SIZE(exynos5x_clk_regs)); 313 if (!exynos5x_save) { 314 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 315 __func__); 316 return; 317 } 318 319 if (exynos5x_soc == EXYNOS5800) { 320 exynos5800_save = 321 samsung_clk_alloc_reg_dump(exynos5800_clk_regs, 322 ARRAY_SIZE(exynos5800_clk_regs)); 323 if (!exynos5800_save) 324 goto err_soc; 325 } 326 327 register_syscore_ops(&exynos5420_clk_syscore_ops); 328 return; 329 err_soc: 330 kfree(exynos5x_save); 331 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 332 __func__); 333 return; 334 } 335 #else 336 static void exynos5420_clk_sleep_init(void) {} 337 #endif 338 339 /* list of all parent clocks */ 340 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 341 "mout_sclk_mpll", "mout_sclk_spll"}; 342 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 343 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 344 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 345 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 346 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 347 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 348 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 349 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 350 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 351 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 352 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 353 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 354 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 355 356 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 357 "mout_sclk_mpll"}; 358 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 359 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 360 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 361 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 362 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 363 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 364 365 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 366 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 367 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 368 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 369 370 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 371 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 372 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 373 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 374 375 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 376 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 377 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 378 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 379 380 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 381 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 382 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 383 384 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 385 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 386 387 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 388 "mout_sclk_spll"}; 389 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 390 391 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 392 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 393 394 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 395 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 396 397 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 398 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 399 400 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 401 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 402 403 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 404 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 405 406 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 407 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 408 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 409 410 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 411 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 412 413 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 414 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 415 416 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 417 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 418 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 419 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 420 421 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 422 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 423 424 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 425 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 426 427 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 428 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 429 430 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 431 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 432 433 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 434 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 435 "mout_sclk_epll", "mout_sclk_rpll"}; 436 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 437 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 438 "mout_sclk_epll", "mout_sclk_rpll"}; 439 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 440 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 441 "mout_sclk_epll", "mout_sclk_rpll"}; 442 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 443 "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 444 "mout_sclk_epll", "mout_sclk_rpll"}; 445 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 446 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 447 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 448 "mout_sclk_epll", "mout_sclk_rpll"}; 449 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 450 "mout_sclk_mpll", "mout_sclk_spll"}; 451 /* List of parents specific to exynos5800 */ 452 PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 453 PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 454 "mout_sclk_mpll", "ff_dout_spll2" }; 455 PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 456 "mout_sclk_mpll", "ff_dout_spll2", 457 "mout_epll2", "mout_sclk_ipll" }; 458 PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 459 "mout_sclk_mpll", "ff_dout_spll2", 460 "mout_epll2" }; 461 PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 462 "mout_sclk_mpll", "mout_sclk_spll" }; 463 PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 464 "mout_sclk_mpll", "ff_dout_spll2" }; 465 PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 466 "mout_sclk_mpll", "mout_sclk_spll", 467 "mout_epll2", "mout_sclk_ipll" }; 468 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 469 "mout_sclk_mpll", 470 "ff_dout_spll2" }; 471 PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 472 PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 473 PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 474 PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 475 PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 476 PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 477 PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 478 PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 479 480 /* fixed rate clocks generated outside the soc */ 481 static struct samsung_fixed_rate_clock 482 exynos5x_fixed_rate_ext_clks[] __initdata = { 483 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 484 }; 485 486 /* fixed rate clocks generated inside the soc */ 487 static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = { 488 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 489 FRATE(0, "sclk_pwi", NULL, 0, 24000000), 490 FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 491 FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 492 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 493 }; 494 495 static struct samsung_fixed_factor_clock 496 exynos5x_fixed_factor_clks[] __initdata = { 497 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 498 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 499 }; 500 501 static struct samsung_fixed_factor_clock 502 exynos5800_fixed_factor_clks[] __initdata = { 503 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 504 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 505 }; 506 507 static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { 508 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 509 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 510 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 511 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 512 513 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 514 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 515 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 516 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 517 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 518 519 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 520 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 521 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 522 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 523 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 524 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 525 526 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7, 527 20, 2), 528 MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 529 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 530 531 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 532 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 533 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 534 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 535 536 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 537 SRC_TOP9, 16, 1), 538 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 539 SRC_TOP9, 20, 1), 540 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 541 SRC_TOP9, 24, 1), 542 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 543 SRC_TOP9, 28, 1), 544 545 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 546 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 547 SRC_TOP13, 20, 1), 548 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 549 SRC_TOP13, 24, 1), 550 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 551 SRC_TOP13, 28, 1), 552 553 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 554 }; 555 556 static struct samsung_div_clock exynos5800_div_clks[] __initdata = { 557 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 558 "mout_aclk400_wcore", DIV_TOP0, 16, 3), 559 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 560 DIV_TOP8, 16, 3), 561 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 562 DIV_TOP8, 20, 3), 563 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 564 DIV_TOP8, 24, 3), 565 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 566 DIV_TOP8, 28, 3), 567 568 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 569 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 570 }; 571 572 static struct samsung_gate_clock exynos5800_gate_clks[] __initdata = { 573 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 574 GATE_BUS_TOP, 24, 0, 0), 575 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 576 GATE_BUS_TOP, 27, 0, 0), 577 }; 578 579 static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 580 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 581 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 582 TOP_SPARE2, 4, 1), 583 584 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 585 MUX_A(0, "mout_aclk400_mscl", mout_group1_p, 586 SRC_TOP0, 4, 2, "aclk400_mscl"), 587 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 588 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 589 590 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 591 MUX(0, "mout_aclk333_432_isp", mout_group4_p, 592 SRC_TOP1, 4, 2), 593 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 594 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 595 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 596 597 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 598 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 599 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 600 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 601 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 602 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 603 604 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2), 605 606 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 607 }; 608 609 static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 610 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 611 "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 612 }; 613 614 static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 615 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 616 SRC_TOP7, 4, 1), 617 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 618 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 619 620 MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 621 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 622 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 623 MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 624 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 625 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 626 627 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 628 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 629 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 630 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 631 632 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 633 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 634 635 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 636 637 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 638 SRC_TOP3, 0, 1), 639 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 640 SRC_TOP3, 4, 1), 641 MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 642 mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 643 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 644 SRC_TOP3, 12, 1), 645 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 646 SRC_TOP3, 16, 1), 647 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 648 SRC_TOP3, 20, 1), 649 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 650 SRC_TOP3, 24, 1), 651 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 652 SRC_TOP3, 28, 1), 653 654 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 655 SRC_TOP4, 0, 1), 656 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 657 SRC_TOP4, 4, 1), 658 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 659 SRC_TOP4, 8, 1), 660 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 661 SRC_TOP4, 12, 1), 662 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 663 SRC_TOP4, 16, 1), 664 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 665 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 666 MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 667 SRC_TOP4, 28, 1), 668 669 MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 670 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 671 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 672 SRC_TOP5, 4, 1), 673 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 674 SRC_TOP5, 8, 1), 675 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 676 SRC_TOP5, 12, 1), 677 MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 678 SRC_TOP5, 16, 1), 679 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 680 SRC_TOP5, 20, 1), 681 MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 682 mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 683 MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 684 mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 685 686 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 687 MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 688 MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 689 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 690 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 691 MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1), 692 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 693 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 694 695 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 696 SRC_TOP10, 0, 1), 697 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 698 SRC_TOP10, 4, 1), 699 MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 700 SRC_TOP10, 8, 1), 701 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 702 SRC_TOP10, 12, 1), 703 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 704 SRC_TOP10, 16, 1), 705 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 706 SRC_TOP10, 20, 1), 707 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 708 SRC_TOP10, 24, 1), 709 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 710 SRC_TOP10, 28, 1), 711 712 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 713 SRC_TOP11, 0, 1), 714 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 715 SRC_TOP11, 4, 1), 716 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 717 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 718 SRC_TOP11, 12, 1), 719 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 720 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 721 MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 722 SRC_TOP11, 28, 1), 723 724 MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 725 mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 726 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 727 SRC_TOP12, 8, 1), 728 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 729 SRC_TOP12, 12, 1), 730 MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 731 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 732 SRC_TOP12, 20, 1), 733 MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 734 mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 735 MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 736 mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 737 738 /* DISP1 Block */ 739 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 740 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 741 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 742 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 743 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 744 745 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 746 747 /* MAU Block */ 748 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 749 750 /* FSYS Block */ 751 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 752 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 753 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 754 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 755 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 756 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 757 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 758 759 /* PERIC Block */ 760 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 761 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 762 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 763 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 764 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 765 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 766 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 767 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 768 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 769 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 770 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 771 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 772 773 /* ISP Block */ 774 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 775 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 776 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 777 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 778 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 779 }; 780 781 static struct samsung_div_clock exynos5x_div_clks[] __initdata = { 782 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 783 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 784 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 785 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 786 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 787 788 DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 789 DIV_TOP0, 0, 3), 790 DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 791 DIV_TOP0, 4, 3), 792 DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 793 DIV_TOP0, 8, 3), 794 DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 795 DIV_TOP0, 12, 3), 796 DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 797 DIV_TOP0, 20, 3), 798 DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 799 DIV_TOP0, 24, 3), 800 DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 801 DIV_TOP0, 28, 3), 802 DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 803 "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 804 DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 805 "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 806 DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 807 DIV_TOP1, 8, 6), 808 DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 809 "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 810 DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 811 DIV_TOP1, 20, 3), 812 DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 813 DIV_TOP1, 24, 3), 814 DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 815 DIV_TOP1, 28, 3), 816 817 DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 818 DIV_TOP2, 8, 3), 819 DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 820 DIV_TOP2, 12, 3), 821 DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 822 16, 3), 823 DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 824 DIV_TOP2, 20, 3), 825 DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 826 "mout_aclk300_disp1", DIV_TOP2, 24, 3), 827 DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 828 DIV_TOP2, 28, 3), 829 830 /* DISP1 Block */ 831 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 832 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 833 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 834 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 835 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 836 DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 837 "mout_aclk400_disp1", DIV_TOP2, 4, 3), 838 839 /* Audio Block */ 840 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 841 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 842 843 /* USB3.0 */ 844 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 845 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 846 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 847 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 848 849 /* MMC */ 850 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 851 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 852 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 853 854 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 855 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 856 857 /* UART and PWM */ 858 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 859 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 860 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 861 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 862 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 863 864 /* SPI */ 865 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 866 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 867 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 868 869 /* Mfc Block */ 870 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 871 872 /* PCM */ 873 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 874 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 875 876 /* Audio - I2S */ 877 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 878 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 879 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 880 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 881 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 882 883 /* SPI Pre-Ratio */ 884 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 885 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 886 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 887 888 /* GSCL Block */ 889 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 890 DIV2_RATIO0, 4, 2), 891 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 892 893 /* MSCL Block */ 894 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 895 896 /* PSGEN */ 897 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 898 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 899 900 /* ISP Block */ 901 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 902 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 903 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 904 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 905 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 906 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 907 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 908 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 909 CLK_SET_RATE_PARENT, 0), 910 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 911 CLK_SET_RATE_PARENT, 0), 912 }; 913 914 static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = { 915 /* G2D */ 916 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 917 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 918 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 919 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 920 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 921 922 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 923 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 924 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 925 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 926 927 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 928 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 929 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 930 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), 931 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 932 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 933 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 934 GATE_BUS_TOP, 5, 0, 0), 935 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 936 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), 937 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 938 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 939 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 940 GATE_BUS_TOP, 8, 0, 0), 941 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 942 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 943 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 944 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 945 GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 946 GATE_BUS_TOP, 13, 0, 0), 947 GATE(0, "aclk166", "mout_user_aclk166", 948 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 949 GATE(0, "aclk333", "mout_user_aclk333", 950 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 951 GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 952 GATE_BUS_TOP, 16, 0, 0), 953 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 954 GATE_BUS_TOP, 17, 0, 0), 955 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 956 GATE_BUS_TOP, 18, 0, 0), 957 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 958 GATE_BUS_TOP, 28, 0, 0), 959 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 960 GATE_BUS_TOP, 29, 0, 0), 961 962 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 963 SRC_MASK_TOP2, 24, 0, 0), 964 965 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 966 SRC_MASK_TOP7, 20, 0, 0), 967 968 /* sclk */ 969 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 970 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 971 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 972 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 973 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 974 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 975 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 976 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 977 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 978 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 979 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 980 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 981 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 982 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 983 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 984 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 985 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 986 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 987 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 988 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 989 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 990 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 991 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 992 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 993 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 994 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 995 996 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 997 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 998 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 999 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 1000 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 1001 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 1002 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 1003 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 1004 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 1005 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 1006 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 1007 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 1008 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 1009 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 1010 1011 /* Display */ 1012 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 1013 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 1014 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 1015 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 1016 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 1017 GATE_TOP_SCLK_DISP1, 9, 0, 0), 1018 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 1019 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 1020 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 1021 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 1022 1023 /* Maudio Block */ 1024 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 1025 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1026 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 1027 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 1028 1029 /* FSYS Block */ 1030 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1031 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1032 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1033 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 1034 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 1035 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 1036 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 1037 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1038 GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 1039 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 1040 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 1041 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 1042 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 1043 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 1044 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 1045 1046 /* PERIC Block */ 1047 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 1048 GATE_IP_PERIC, 0, 0, 0), 1049 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 1050 GATE_IP_PERIC, 1, 0, 0), 1051 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 1052 GATE_IP_PERIC, 2, 0, 0), 1053 GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 1054 GATE_IP_PERIC, 3, 0, 0), 1055 GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 1056 GATE_IP_PERIC, 6, 0, 0), 1057 GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 1058 GATE_IP_PERIC, 7, 0, 0), 1059 GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 1060 GATE_IP_PERIC, 8, 0, 0), 1061 GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 1062 GATE_IP_PERIC, 9, 0, 0), 1063 GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 1064 GATE_IP_PERIC, 10, 0, 0), 1065 GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 1066 GATE_IP_PERIC, 11, 0, 0), 1067 GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 1068 GATE_IP_PERIC, 12, 0, 0), 1069 GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 1070 GATE_IP_PERIC, 13, 0, 0), 1071 GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 1072 GATE_IP_PERIC, 14, 0, 0), 1073 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 1074 GATE_IP_PERIC, 15, 0, 0), 1075 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 1076 GATE_IP_PERIC, 16, 0, 0), 1077 GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 1078 GATE_IP_PERIC, 17, 0, 0), 1079 GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 1080 GATE_IP_PERIC, 18, 0, 0), 1081 GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 1082 GATE_IP_PERIC, 20, 0, 0), 1083 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 1084 GATE_IP_PERIC, 21, 0, 0), 1085 GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 1086 GATE_IP_PERIC, 22, 0, 0), 1087 GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 1088 GATE_IP_PERIC, 23, 0, 0), 1089 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 1090 GATE_IP_PERIC, 24, 0, 0), 1091 GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 1092 GATE_IP_PERIC, 26, 0, 0), 1093 GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 1094 GATE_IP_PERIC, 28, 0, 0), 1095 GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 1096 GATE_IP_PERIC, 30, 0, 0), 1097 GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 1098 GATE_IP_PERIC, 31, 0, 0), 1099 1100 GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 1101 GATE_BUS_PERIC, 22, 0, 0), 1102 1103 /* PERIS Block */ 1104 GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 1105 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1106 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 1107 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1108 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 1109 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 1110 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 1111 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 1112 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 1113 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 1114 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 1115 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 1116 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 1117 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 1118 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 1119 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 1120 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 1121 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 1122 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 1123 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 1124 1125 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 1126 1127 /* GEN Block */ 1128 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 1129 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 1130 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 1131 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 1132 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 1133 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 1134 GATE_IP_GEN, 6, 0, 0), 1135 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 1136 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 1137 GATE_IP_GEN, 9, 0, 0), 1138 1139 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 1140 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 1141 GATE_BUS_GEN, 28, 0, 0), 1142 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 1143 1144 /* GSCL Block */ 1145 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 1146 GATE_TOP_SCLK_GSCL, 6, 0, 0), 1147 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 1148 GATE_TOP_SCLK_GSCL, 7, 0, 0), 1149 1150 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1151 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1152 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 1153 GATE_IP_GSCL0, 4, 0, 0), 1154 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 1155 GATE_IP_GSCL0, 5, 0, 0), 1156 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 1157 GATE_IP_GSCL0, 6, 0, 0), 1158 1159 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 1160 GATE_IP_GSCL1, 2, 0, 0), 1161 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 1162 GATE_IP_GSCL1, 3, 0, 0), 1163 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 1164 GATE_IP_GSCL1, 4, 0, 0), 1165 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 1166 GATE_IP_GSCL1, 6, 0, 0), 1167 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 1168 GATE_IP_GSCL1, 7, 0, 0), 1169 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 1170 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 1171 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 1172 GATE_IP_GSCL1, 16, 0, 0), 1173 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 1174 GATE_IP_GSCL1, 17, 0, 0), 1175 1176 /* MSCL Block */ 1177 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 1178 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 1179 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 1180 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 1181 GATE_IP_MSCL, 8, 0, 0), 1182 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 1183 GATE_IP_MSCL, 9, 0, 0), 1184 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 1185 GATE_IP_MSCL, 10, 0, 0), 1186 1187 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1188 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1189 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1190 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1191 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1192 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1193 GATE_IP_DISP1, 7, 0, 0), 1194 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1195 GATE_IP_DISP1, 8, 0, 0), 1196 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1197 GATE_IP_DISP1, 9, 0, 0), 1198 1199 /* ISP */ 1200 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 1201 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 1202 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 1203 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 1204 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 1205 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 1206 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 1207 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 1208 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 1209 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 1210 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 1211 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 1212 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 1213 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 1214 1215 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 1216 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 1217 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 1218 1219 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 1220 }; 1221 1222 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = { 1223 PLL_35XX_RATE(2000000000, 250, 3, 0), 1224 PLL_35XX_RATE(1900000000, 475, 6, 0), 1225 PLL_35XX_RATE(1800000000, 225, 3, 0), 1226 PLL_35XX_RATE(1700000000, 425, 6, 0), 1227 PLL_35XX_RATE(1600000000, 200, 3, 0), 1228 PLL_35XX_RATE(1500000000, 250, 4, 0), 1229 PLL_35XX_RATE(1400000000, 175, 3, 0), 1230 PLL_35XX_RATE(1300000000, 325, 6, 0), 1231 PLL_35XX_RATE(1200000000, 200, 2, 1), 1232 PLL_35XX_RATE(1100000000, 275, 3, 1), 1233 PLL_35XX_RATE(1000000000, 250, 3, 1), 1234 PLL_35XX_RATE(900000000, 150, 2, 1), 1235 PLL_35XX_RATE(800000000, 200, 3, 1), 1236 PLL_35XX_RATE(700000000, 175, 3, 1), 1237 PLL_35XX_RATE(600000000, 200, 2, 2), 1238 PLL_35XX_RATE(500000000, 250, 3, 2), 1239 PLL_35XX_RATE(400000000, 200, 3, 2), 1240 PLL_35XX_RATE(300000000, 200, 2, 3), 1241 PLL_35XX_RATE(200000000, 200, 3, 3), 1242 }; 1243 1244 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1245 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1246 APLL_CON0, NULL), 1247 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1248 CPLL_CON0, NULL), 1249 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 1250 DPLL_CON0, NULL), 1251 [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 1252 EPLL_CON0, NULL), 1253 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 1254 RPLL_CON0, NULL), 1255 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 1256 IPLL_CON0, NULL), 1257 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 1258 SPLL_CON0, NULL), 1259 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 1260 VPLL_CON0, NULL), 1261 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 1262 MPLL_CON0, NULL), 1263 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 1264 BPLL_CON0, NULL), 1265 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 1266 KPLL_CON0, NULL), 1267 }; 1268 1269 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1270 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1271 ((cpud) << 4))) 1272 1273 static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1274 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1275 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1276 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1277 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1278 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1279 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1280 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1281 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1282 { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1283 { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1284 { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1285 { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1286 { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1287 { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1288 { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1289 { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1290 { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1291 { 0 }, 1292 }; 1293 1294 static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 1295 { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1296 { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1297 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1298 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1299 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1300 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1301 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1302 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1303 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1304 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1305 { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 1306 { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 1307 { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 1308 { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 1309 { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 1310 { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1311 { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1312 { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1313 { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1314 { 0 }, 1315 }; 1316 1317 #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1318 ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1319 1320 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 1321 { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1322 { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1323 { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1324 { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1325 { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1326 { 900000, E5420_KFC_DIV(3, 5, 2), }, 1327 { 800000, E5420_KFC_DIV(3, 5, 2), }, 1328 { 700000, E5420_KFC_DIV(3, 4, 2), }, 1329 { 600000, E5420_KFC_DIV(3, 4, 2), }, 1330 { 500000, E5420_KFC_DIV(3, 4, 2), }, 1331 { 400000, E5420_KFC_DIV(3, 3, 2), }, 1332 { 300000, E5420_KFC_DIV(3, 3, 2), }, 1333 { 200000, E5420_KFC_DIV(3, 3, 2), }, 1334 { 0 }, 1335 }; 1336 1337 static const struct of_device_id ext_clk_match[] __initconst = { 1338 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 1339 { }, 1340 }; 1341 1342 /* register exynos5420 clocks */ 1343 static void __init exynos5x_clk_init(struct device_node *np, 1344 enum exynos5x_soc soc) 1345 { 1346 struct samsung_clk_provider *ctx; 1347 1348 if (np) { 1349 reg_base = of_iomap(np, 0); 1350 if (!reg_base) 1351 panic("%s: failed to map registers\n", __func__); 1352 } else { 1353 panic("%s: unable to determine soc\n", __func__); 1354 } 1355 1356 exynos5x_soc = soc; 1357 1358 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1359 if (!ctx) 1360 panic("%s: unable to allocate context.\n", __func__); 1361 1362 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 1363 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 1364 ext_clk_match); 1365 1366 if (_get_rate("fin_pll") == 24 * MHZ) { 1367 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1368 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1369 } 1370 1371 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1372 reg_base); 1373 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 1374 ARRAY_SIZE(exynos5x_fixed_rate_clks)); 1375 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 1376 ARRAY_SIZE(exynos5x_fixed_factor_clks)); 1377 samsung_clk_register_mux(ctx, exynos5x_mux_clks, 1378 ARRAY_SIZE(exynos5x_mux_clks)); 1379 samsung_clk_register_div(ctx, exynos5x_div_clks, 1380 ARRAY_SIZE(exynos5x_div_clks)); 1381 samsung_clk_register_gate(ctx, exynos5x_gate_clks, 1382 ARRAY_SIZE(exynos5x_gate_clks)); 1383 1384 if (soc == EXYNOS5420) { 1385 samsung_clk_register_mux(ctx, exynos5420_mux_clks, 1386 ARRAY_SIZE(exynos5420_mux_clks)); 1387 samsung_clk_register_div(ctx, exynos5420_div_clks, 1388 ARRAY_SIZE(exynos5420_div_clks)); 1389 } else { 1390 samsung_clk_register_fixed_factor( 1391 ctx, exynos5800_fixed_factor_clks, 1392 ARRAY_SIZE(exynos5800_fixed_factor_clks)); 1393 samsung_clk_register_mux(ctx, exynos5800_mux_clks, 1394 ARRAY_SIZE(exynos5800_mux_clks)); 1395 samsung_clk_register_div(ctx, exynos5800_div_clks, 1396 ARRAY_SIZE(exynos5800_div_clks)); 1397 samsung_clk_register_gate(ctx, exynos5800_gate_clks, 1398 ARRAY_SIZE(exynos5800_gate_clks)); 1399 } 1400 1401 if (soc == EXYNOS5420) { 1402 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1403 mout_cpu_p[0], mout_cpu_p[1], 0x200, 1404 exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); 1405 } else { 1406 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1407 mout_cpu_p[0], mout_cpu_p[1], 0x200, 1408 exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); 1409 } 1410 exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", 1411 mout_kfc_p[0], mout_kfc_p[1], 0x28200, 1412 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); 1413 1414 exynos5420_clk_sleep_init(); 1415 1416 samsung_clk_of_add_provider(np, ctx); 1417 } 1418 1419 static void __init exynos5420_clk_init(struct device_node *np) 1420 { 1421 exynos5x_clk_init(np, EXYNOS5420); 1422 } 1423 CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 1424 1425 static void __init exynos5800_clk_init(struct device_node *np) 1426 { 1427 exynos5x_clk_init(np, EXYNOS5800); 1428 } 1429 CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init); 1430