1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Authors: Thomas Abraham <thomas.ab@samsung.com> 5 * Chander Kashyap <k.chander@samsung.com> 6 * 7 * Common Clock Framework support for Exynos5420 SoC. 8 */ 9 10 #include <dt-bindings/clock/exynos5420.h> 11 #include <linux/slab.h> 12 #include <linux/clk-provider.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 16 #include "clk.h" 17 #include "clk-cpu.h" 18 #include "clk-exynos5-subcmu.h" 19 20 #define APLL_LOCK 0x0 21 #define APLL_CON0 0x100 22 #define SRC_CPU 0x200 23 #define DIV_CPU0 0x500 24 #define DIV_CPU1 0x504 25 #define GATE_BUS_CPU 0x700 26 #define GATE_SCLK_CPU 0x800 27 #define CLKOUT_CMU_CPU 0xa00 28 #define SRC_MASK_CPERI 0x4300 29 #define GATE_IP_G2D 0x8800 30 #define CPLL_LOCK 0x10020 31 #define DPLL_LOCK 0x10030 32 #define EPLL_LOCK 0x10040 33 #define RPLL_LOCK 0x10050 34 #define IPLL_LOCK 0x10060 35 #define SPLL_LOCK 0x10070 36 #define VPLL_LOCK 0x10080 37 #define MPLL_LOCK 0x10090 38 #define CPLL_CON0 0x10120 39 #define DPLL_CON0 0x10128 40 #define EPLL_CON0 0x10130 41 #define EPLL_CON1 0x10134 42 #define EPLL_CON2 0x10138 43 #define RPLL_CON0 0x10140 44 #define RPLL_CON1 0x10144 45 #define RPLL_CON2 0x10148 46 #define IPLL_CON0 0x10150 47 #define SPLL_CON0 0x10160 48 #define VPLL_CON0 0x10170 49 #define MPLL_CON0 0x10180 50 #define SRC_TOP0 0x10200 51 #define SRC_TOP1 0x10204 52 #define SRC_TOP2 0x10208 53 #define SRC_TOP3 0x1020c 54 #define SRC_TOP4 0x10210 55 #define SRC_TOP5 0x10214 56 #define SRC_TOP6 0x10218 57 #define SRC_TOP7 0x1021c 58 #define SRC_TOP8 0x10220 /* 5800 specific */ 59 #define SRC_TOP9 0x10224 /* 5800 specific */ 60 #define SRC_DISP10 0x1022c 61 #define SRC_MAU 0x10240 62 #define SRC_FSYS 0x10244 63 #define SRC_PERIC0 0x10250 64 #define SRC_PERIC1 0x10254 65 #define SRC_ISP 0x10270 66 #define SRC_CAM 0x10274 /* 5800 specific */ 67 #define SRC_TOP10 0x10280 68 #define SRC_TOP11 0x10284 69 #define SRC_TOP12 0x10288 70 #define SRC_TOP13 0x1028c /* 5800 specific */ 71 #define SRC_MASK_TOP0 0x10300 72 #define SRC_MASK_TOP1 0x10304 73 #define SRC_MASK_TOP2 0x10308 74 #define SRC_MASK_TOP7 0x1031c 75 #define SRC_MASK_DISP10 0x1032c 76 #define SRC_MASK_MAU 0x10334 77 #define SRC_MASK_FSYS 0x10340 78 #define SRC_MASK_PERIC0 0x10350 79 #define SRC_MASK_PERIC1 0x10354 80 #define SRC_MASK_ISP 0x10370 81 #define DIV_TOP0 0x10500 82 #define DIV_TOP1 0x10504 83 #define DIV_TOP2 0x10508 84 #define DIV_TOP8 0x10520 /* 5800 specific */ 85 #define DIV_TOP9 0x10524 /* 5800 specific */ 86 #define DIV_DISP10 0x1052c 87 #define DIV_MAU 0x10544 88 #define DIV_FSYS0 0x10548 89 #define DIV_FSYS1 0x1054c 90 #define DIV_FSYS2 0x10550 91 #define DIV_PERIC0 0x10558 92 #define DIV_PERIC1 0x1055c 93 #define DIV_PERIC2 0x10560 94 #define DIV_PERIC3 0x10564 95 #define DIV_PERIC4 0x10568 96 #define DIV_CAM 0x10574 /* 5800 specific */ 97 #define SCLK_DIV_ISP0 0x10580 98 #define SCLK_DIV_ISP1 0x10584 99 #define DIV2_RATIO0 0x10590 100 #define DIV4_RATIO 0x105a0 101 #define GATE_BUS_TOP 0x10700 102 #define GATE_BUS_DISP1 0x10728 103 #define GATE_BUS_GEN 0x1073c 104 #define GATE_BUS_FSYS0 0x10740 105 #define GATE_BUS_FSYS2 0x10748 106 #define GATE_BUS_PERIC 0x10750 107 #define GATE_BUS_PERIC1 0x10754 108 #define GATE_BUS_PERIS0 0x10760 109 #define GATE_BUS_PERIS1 0x10764 110 #define GATE_BUS_NOC 0x10770 111 #define GATE_TOP_SCLK_ISP 0x10870 112 #define GATE_IP_GSCL0 0x10910 113 #define GATE_IP_GSCL1 0x10920 114 #define GATE_IP_CAM 0x10924 /* 5800 specific */ 115 #define GATE_IP_MFC 0x1092c 116 #define GATE_IP_DISP1 0x10928 117 #define GATE_IP_G3D 0x10930 118 #define GATE_IP_GEN 0x10934 119 #define GATE_IP_FSYS 0x10944 120 #define GATE_IP_PERIC 0x10950 121 #define GATE_IP_PERIS 0x10960 122 #define GATE_IP_MSCL 0x10970 123 #define GATE_TOP_SCLK_GSCL 0x10820 124 #define GATE_TOP_SCLK_DISP1 0x10828 125 #define GATE_TOP_SCLK_MAU 0x1083c 126 #define GATE_TOP_SCLK_FSYS 0x10840 127 #define GATE_TOP_SCLK_PERIC 0x10850 128 #define TOP_SPARE2 0x10b08 129 #define BPLL_LOCK 0x20010 130 #define BPLL_CON0 0x20110 131 #define SRC_CDREX 0x20200 132 #define DIV_CDREX0 0x20500 133 #define DIV_CDREX1 0x20504 134 #define KPLL_LOCK 0x28000 135 #define KPLL_CON0 0x28100 136 #define SRC_KFC 0x28200 137 #define DIV_KFC0 0x28500 138 139 /* Exynos5x SoC type */ 140 enum exynos5x_soc { 141 EXYNOS5420, 142 EXYNOS5800, 143 }; 144 145 /* list of PLLs */ 146 enum exynos5x_plls { 147 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 148 bpll, kpll, 149 nr_plls /* number of PLLs */ 150 }; 151 152 static void __iomem *reg_base; 153 static enum exynos5x_soc exynos5x_soc; 154 155 /* 156 * list of controller registers to be saved and restored during a 157 * suspend/resume cycle. 158 */ 159 static const unsigned long exynos5x_clk_regs[] __initconst = { 160 SRC_CPU, 161 DIV_CPU0, 162 DIV_CPU1, 163 GATE_BUS_CPU, 164 GATE_SCLK_CPU, 165 CLKOUT_CMU_CPU, 166 EPLL_CON0, 167 EPLL_CON1, 168 EPLL_CON2, 169 RPLL_CON0, 170 RPLL_CON1, 171 RPLL_CON2, 172 SRC_TOP0, 173 SRC_TOP1, 174 SRC_TOP2, 175 SRC_TOP3, 176 SRC_TOP4, 177 SRC_TOP5, 178 SRC_TOP6, 179 SRC_TOP7, 180 SRC_DISP10, 181 SRC_MAU, 182 SRC_FSYS, 183 SRC_PERIC0, 184 SRC_PERIC1, 185 SRC_TOP10, 186 SRC_TOP11, 187 SRC_TOP12, 188 SRC_MASK_TOP2, 189 SRC_MASK_TOP7, 190 SRC_MASK_DISP10, 191 SRC_MASK_FSYS, 192 SRC_MASK_PERIC0, 193 SRC_MASK_PERIC1, 194 SRC_MASK_TOP0, 195 SRC_MASK_TOP1, 196 SRC_MASK_MAU, 197 SRC_MASK_ISP, 198 SRC_ISP, 199 DIV_TOP0, 200 DIV_TOP1, 201 DIV_TOP2, 202 DIV_DISP10, 203 DIV_MAU, 204 DIV_FSYS0, 205 DIV_FSYS1, 206 DIV_FSYS2, 207 DIV_PERIC0, 208 DIV_PERIC1, 209 DIV_PERIC2, 210 DIV_PERIC3, 211 DIV_PERIC4, 212 SCLK_DIV_ISP0, 213 SCLK_DIV_ISP1, 214 DIV2_RATIO0, 215 DIV4_RATIO, 216 GATE_BUS_DISP1, 217 GATE_BUS_TOP, 218 GATE_BUS_GEN, 219 GATE_BUS_FSYS0, 220 GATE_BUS_FSYS2, 221 GATE_BUS_PERIC, 222 GATE_BUS_PERIC1, 223 GATE_BUS_PERIS0, 224 GATE_BUS_PERIS1, 225 GATE_BUS_NOC, 226 GATE_TOP_SCLK_ISP, 227 GATE_IP_GSCL0, 228 GATE_IP_GSCL1, 229 GATE_IP_MFC, 230 GATE_IP_DISP1, 231 GATE_IP_G3D, 232 GATE_IP_GEN, 233 GATE_IP_FSYS, 234 GATE_IP_PERIC, 235 GATE_IP_PERIS, 236 GATE_IP_MSCL, 237 GATE_TOP_SCLK_GSCL, 238 GATE_TOP_SCLK_DISP1, 239 GATE_TOP_SCLK_MAU, 240 GATE_TOP_SCLK_FSYS, 241 GATE_TOP_SCLK_PERIC, 242 TOP_SPARE2, 243 SRC_CDREX, 244 DIV_CDREX0, 245 DIV_CDREX1, 246 SRC_KFC, 247 DIV_KFC0, 248 }; 249 250 static const unsigned long exynos5800_clk_regs[] __initconst = { 251 SRC_TOP8, 252 SRC_TOP9, 253 SRC_CAM, 254 SRC_TOP1, 255 DIV_TOP8, 256 DIV_TOP9, 257 DIV_CAM, 258 GATE_IP_CAM, 259 }; 260 261 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 262 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 263 { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 264 { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 265 { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 266 { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 267 { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 268 { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 269 { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 270 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 271 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 272 { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 273 { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 274 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 275 { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 276 { .offset = GATE_IP_PERIS, .value = 0xffffffff, }, 277 }; 278 279 /* list of all parent clocks */ 280 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 281 "mout_sclk_mpll", "mout_sclk_spll"}; 282 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 283 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 284 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 285 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 286 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 287 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 288 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 289 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 290 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 291 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 292 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 293 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 294 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 295 296 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 297 "mout_sclk_mpll"}; 298 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 299 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 300 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 301 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 302 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 303 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 304 305 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 306 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 307 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 308 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 309 310 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 311 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 312 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 313 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 314 315 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 316 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 317 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 318 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 319 320 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 321 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 322 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 323 324 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 325 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 326 327 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 328 "mout_sclk_spll"}; 329 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 330 331 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 332 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 333 334 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 335 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 336 337 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 338 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 339 340 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 341 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 342 343 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 344 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 345 346 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 347 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 348 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 349 350 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 351 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 352 353 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 354 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 355 356 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 357 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 358 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 359 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 360 361 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 362 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 363 364 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 365 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 366 367 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 368 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 369 370 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 371 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 372 373 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 374 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 375 "mout_sclk_epll", "mout_sclk_rpll"}; 376 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 377 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 378 "mout_sclk_epll", "mout_sclk_rpll"}; 379 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 380 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 381 "mout_sclk_epll", "mout_sclk_rpll"}; 382 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 383 "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 384 "mout_sclk_epll", "mout_sclk_rpll"}; 385 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 386 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 387 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 388 "mout_sclk_epll", "mout_sclk_rpll"}; 389 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 390 "mout_sclk_mpll", "mout_sclk_spll"}; 391 PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"}; 392 393 /* List of parents specific to exynos5800 */ 394 PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 395 PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 396 "mout_sclk_mpll", "ff_dout_spll2" }; 397 PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 398 "mout_sclk_mpll", "ff_dout_spll2", 399 "mout_epll2", "mout_sclk_ipll" }; 400 PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 401 "mout_sclk_mpll", "ff_dout_spll2", 402 "mout_epll2" }; 403 PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 404 "mout_sclk_mpll", "mout_sclk_spll" }; 405 PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 406 "mout_sclk_mpll", "ff_dout_spll2" }; 407 PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 408 "mout_sclk_mpll", "mout_sclk_spll", 409 "mout_epll2", "mout_sclk_ipll" }; 410 PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll", 411 "mout_sclk_mpll", "ff_dout_spll2", 412 "mout_sclk_spll", "mout_sclk_epll"}; 413 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 414 "mout_sclk_mpll", 415 "ff_dout_spll2" }; 416 PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 417 PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 418 PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 419 PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 420 PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 421 PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 422 PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 423 PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 424 PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; 425 426 /* fixed rate clocks generated outside the soc */ 427 static struct samsung_fixed_rate_clock 428 exynos5x_fixed_rate_ext_clks[] __initdata = { 429 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 430 }; 431 432 /* fixed rate clocks generated inside the soc */ 433 static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { 434 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 435 FRATE(0, "sclk_pwi", NULL, 0, 24000000), 436 FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 437 FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 438 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 439 }; 440 441 static const struct samsung_fixed_factor_clock 442 exynos5x_fixed_factor_clks[] __initconst = { 443 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 444 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 445 }; 446 447 static const struct samsung_fixed_factor_clock 448 exynos5800_fixed_factor_clks[] __initconst = { 449 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 450 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 451 }; 452 453 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 454 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 455 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 456 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 457 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 458 459 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 460 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 461 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 462 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 463 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 464 465 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 466 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 467 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 468 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 469 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 470 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 471 472 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 473 mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), 474 MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, 475 SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), 476 MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 477 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 478 479 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 480 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 481 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 482 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 483 484 MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, 485 SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0), 486 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 487 SRC_TOP9, 16, 1), 488 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 489 SRC_TOP9, 20, 1), 490 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 491 SRC_TOP9, 24, 1), 492 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 493 SRC_TOP9, 28, 1), 494 495 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 496 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 497 SRC_TOP13, 20, 1), 498 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 499 SRC_TOP13, 24, 1), 500 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 501 SRC_TOP13, 28, 1), 502 503 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 504 }; 505 506 static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { 507 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 508 "mout_aclk400_wcore", DIV_TOP0, 16, 3), 509 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 510 DIV_TOP8, 16, 3), 511 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 512 DIV_TOP8, 20, 3), 513 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 514 DIV_TOP8, 24, 3), 515 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 516 DIV_TOP8, 28, 3), 517 518 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 519 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 520 }; 521 522 static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 523 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 524 GATE_BUS_TOP, 24, 0, 0), 525 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 526 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), 527 GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", 528 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 529 }; 530 531 static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 532 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 533 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 534 TOP_SPARE2, 4, 1), 535 536 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 537 MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2), 538 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 539 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 540 541 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 542 MUX(0, "mout_aclk333_432_isp", mout_group4_p, 543 SRC_TOP1, 4, 2), 544 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 545 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 546 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 547 548 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 549 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 550 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 551 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 552 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 553 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 554 555 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 556 mout_group5_5800_p, SRC_TOP7, 16, 2), 557 MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2, 558 CLK_SET_RATE_PARENT, 0), 559 560 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 561 }; 562 563 static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 564 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 565 "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 566 }; 567 568 static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { 569 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 570 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 571 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 572 }; 573 574 static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 575 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 576 SRC_TOP7, 4, 1), 577 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 578 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 579 580 MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 581 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 582 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 583 MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 584 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 585 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 586 587 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 588 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 589 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 590 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 591 592 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 593 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 594 595 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 596 597 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 598 SRC_TOP3, 0, 1), 599 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 600 SRC_TOP3, 4, 1), 601 MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 602 mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 603 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 604 SRC_TOP3, 12, 1), 605 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 606 SRC_TOP3, 16, 1), 607 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 608 SRC_TOP3, 20, 1), 609 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 610 SRC_TOP3, 24, 1), 611 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 612 SRC_TOP3, 28, 1), 613 614 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 615 SRC_TOP4, 0, 1), 616 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 617 SRC_TOP4, 4, 1), 618 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 619 SRC_TOP4, 8, 1), 620 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 621 SRC_TOP4, 12, 1), 622 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 623 SRC_TOP4, 16, 1), 624 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 625 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 626 MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 627 SRC_TOP4, 28, 1), 628 629 MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 630 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 631 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 632 SRC_TOP5, 4, 1), 633 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 634 SRC_TOP5, 8, 1), 635 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 636 SRC_TOP5, 12, 1), 637 MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 638 SRC_TOP5, 16, 1), 639 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 640 SRC_TOP5, 20, 1), 641 MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 642 mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 643 MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 644 mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 645 646 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 647 MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 648 MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 649 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 650 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 651 MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, 652 CLK_SET_RATE_PARENT, 0), 653 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 654 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 655 656 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 657 SRC_TOP10, 0, 1), 658 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 659 SRC_TOP10, 4, 1), 660 MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 661 SRC_TOP10, 8, 1), 662 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 663 SRC_TOP10, 12, 1), 664 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 665 SRC_TOP10, 16, 1), 666 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 667 SRC_TOP10, 20, 1), 668 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 669 SRC_TOP10, 24, 1), 670 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 671 SRC_TOP10, 28, 1), 672 673 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 674 SRC_TOP11, 0, 1), 675 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 676 SRC_TOP11, 4, 1), 677 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 678 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 679 SRC_TOP11, 12, 1), 680 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 681 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 682 MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 683 SRC_TOP11, 28, 1), 684 685 MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 686 mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 687 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 688 SRC_TOP12, 8, 1), 689 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 690 SRC_TOP12, 12, 1), 691 MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 692 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 693 SRC_TOP12, 20, 1), 694 MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 695 mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 696 MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 697 mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 698 699 /* DISP1 Block */ 700 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 701 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 702 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 703 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 704 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 705 706 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 707 708 /* CDREX block */ 709 MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p, 710 SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0), 711 MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1, 712 CLK_SET_RATE_PARENT, 0), 713 714 /* MAU Block */ 715 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 716 717 /* FSYS Block */ 718 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 719 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 720 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 721 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 722 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 723 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 724 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 725 726 /* PERIC Block */ 727 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 728 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 729 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 730 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 731 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 732 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 733 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 734 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 735 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 736 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 737 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 738 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 739 740 /* ISP Block */ 741 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 742 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 743 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 744 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 745 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 746 }; 747 748 static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 749 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 750 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 751 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 752 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 753 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 754 755 DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 756 DIV_TOP0, 0, 3), 757 DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 758 DIV_TOP0, 4, 3), 759 DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 760 DIV_TOP0, 8, 3), 761 DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 762 DIV_TOP0, 12, 3), 763 DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 764 DIV_TOP0, 20, 3), 765 DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 766 DIV_TOP0, 24, 3), 767 DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 768 DIV_TOP0, 28, 3), 769 DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 770 "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 771 DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 772 "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 773 DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 774 DIV_TOP1, 8, 6), 775 DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 776 "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 777 DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 778 DIV_TOP1, 20, 3), 779 DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 780 DIV_TOP1, 24, 3), 781 DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 782 DIV_TOP1, 28, 3), 783 784 DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 785 DIV_TOP2, 8, 3), 786 DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 787 DIV_TOP2, 12, 3), 788 DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 789 16, 3), 790 DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 791 DIV_TOP2, 20, 3), 792 DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 793 "mout_aclk300_disp1", DIV_TOP2, 24, 3), 794 DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 795 DIV_TOP2, 28, 3), 796 797 /* DISP1 Block */ 798 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 799 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 800 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 801 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 802 DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 803 "mout_aclk400_disp1", DIV_TOP2, 4, 3), 804 805 /* CDREX Block */ 806 DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", 807 DIV_CDREX0, 28, 3), 808 DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", 809 DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), 810 DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", 811 DIV_CDREX0, 16, 3), 812 DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", 813 DIV_CDREX0, 8, 3), 814 DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", 815 DIV_CDREX0, 3, 5), 816 817 DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", 818 DIV_CDREX1, 8, 3), 819 820 /* Audio Block */ 821 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 822 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 823 824 /* USB3.0 */ 825 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 826 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 827 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 828 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 829 830 /* MMC */ 831 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 832 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 833 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 834 835 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 836 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 837 838 /* UART and PWM */ 839 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 840 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 841 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 842 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 843 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 844 845 /* SPI */ 846 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 847 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 848 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 849 850 851 /* PCM */ 852 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 853 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 854 855 /* Audio - I2S */ 856 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 857 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 858 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 859 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 860 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 861 862 /* SPI Pre-Ratio */ 863 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 864 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 865 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 866 867 /* GSCL Block */ 868 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 869 870 /* MSCL Block */ 871 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 872 873 /* PSGEN */ 874 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 875 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 876 877 /* ISP Block */ 878 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 879 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 880 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 881 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 882 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 883 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 884 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 885 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 886 CLK_SET_RATE_PARENT, 0), 887 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 888 CLK_SET_RATE_PARENT, 0), 889 }; 890 891 static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 892 /* G2D */ 893 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 894 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 895 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 896 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 897 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 898 899 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 900 GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), 901 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 902 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 903 904 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 905 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 906 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 907 GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), 908 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 909 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 910 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 911 GATE_BUS_TOP, 5, 0, 0), 912 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 913 GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), 914 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 915 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 916 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 917 GATE_BUS_TOP, 8, 0, 0), 918 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 919 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 920 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 921 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 922 GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 923 GATE_BUS_TOP, 13, 0, 0), 924 GATE(0, "aclk166", "mout_user_aclk166", 925 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 926 GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", 927 GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), 928 GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 929 GATE_BUS_TOP, 16, 0, 0), 930 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 931 GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), 932 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 933 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), 934 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 935 GATE_BUS_TOP, 28, 0, 0), 936 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 937 GATE_BUS_TOP, 29, 0, 0), 938 939 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 940 SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), 941 942 /* sclk */ 943 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 944 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 945 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 946 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 947 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 948 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 949 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 950 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 951 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 952 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 953 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 954 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 955 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 956 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 957 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 958 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 959 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 960 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 961 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 962 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 963 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 964 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 965 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 966 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 967 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 968 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 969 970 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 971 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 972 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 973 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 974 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 975 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 976 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 977 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 978 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 979 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 980 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 981 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 982 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 983 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 984 985 /* Display */ 986 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 987 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 988 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 989 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 990 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 991 GATE_TOP_SCLK_DISP1, 9, 0, 0), 992 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 993 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 994 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 995 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 996 997 /* Maudio Block */ 998 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 999 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1000 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 1001 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 1002 1003 /* FSYS Block */ 1004 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1005 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1006 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1007 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 1008 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 1009 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 1010 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 1011 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1012 GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 1013 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 1014 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 1015 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 1016 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 1017 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 1018 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 1019 1020 /* PERIC Block */ 1021 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 1022 GATE_IP_PERIC, 0, 0, 0), 1023 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 1024 GATE_IP_PERIC, 1, 0, 0), 1025 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 1026 GATE_IP_PERIC, 2, 0, 0), 1027 GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 1028 GATE_IP_PERIC, 3, 0, 0), 1029 GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 1030 GATE_IP_PERIC, 6, 0, 0), 1031 GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 1032 GATE_IP_PERIC, 7, 0, 0), 1033 GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 1034 GATE_IP_PERIC, 8, 0, 0), 1035 GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 1036 GATE_IP_PERIC, 9, 0, 0), 1037 GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 1038 GATE_IP_PERIC, 10, 0, 0), 1039 GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 1040 GATE_IP_PERIC, 11, 0, 0), 1041 GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 1042 GATE_IP_PERIC, 12, 0, 0), 1043 GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 1044 GATE_IP_PERIC, 13, 0, 0), 1045 GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 1046 GATE_IP_PERIC, 14, 0, 0), 1047 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 1048 GATE_IP_PERIC, 15, 0, 0), 1049 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 1050 GATE_IP_PERIC, 16, 0, 0), 1051 GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 1052 GATE_IP_PERIC, 17, 0, 0), 1053 GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 1054 GATE_IP_PERIC, 18, 0, 0), 1055 GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 1056 GATE_IP_PERIC, 20, 0, 0), 1057 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 1058 GATE_IP_PERIC, 21, 0, 0), 1059 GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 1060 GATE_IP_PERIC, 22, 0, 0), 1061 GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 1062 GATE_IP_PERIC, 23, 0, 0), 1063 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 1064 GATE_IP_PERIC, 24, 0, 0), 1065 GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 1066 GATE_IP_PERIC, 26, 0, 0), 1067 GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 1068 GATE_IP_PERIC, 28, 0, 0), 1069 GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 1070 GATE_IP_PERIC, 30, 0, 0), 1071 GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 1072 GATE_IP_PERIC, 31, 0, 0), 1073 1074 GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 1075 GATE_BUS_PERIC, 22, 0, 0), 1076 1077 /* PERIS Block */ 1078 GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 1079 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1080 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 1081 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1082 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 1083 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 1084 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 1085 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 1086 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 1087 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 1088 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 1089 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 1090 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 1091 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 1092 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 1093 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 1094 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 1095 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 1096 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 1097 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 1098 1099 /* GEN Block */ 1100 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 1101 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 1102 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 1103 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 1104 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 1105 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 1106 GATE_IP_GEN, 6, 0, 0), 1107 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 1108 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 1109 GATE_IP_GEN, 9, 0, 0), 1110 1111 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 1112 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 1113 GATE_BUS_GEN, 28, 0, 0), 1114 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 1115 1116 /* GSCL Block */ 1117 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 1118 GATE_TOP_SCLK_GSCL, 6, 0, 0), 1119 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 1120 GATE_TOP_SCLK_GSCL, 7, 0, 0), 1121 1122 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 1123 GATE_IP_GSCL0, 4, 0, 0), 1124 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 1125 GATE_IP_GSCL0, 5, 0, 0), 1126 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 1127 GATE_IP_GSCL0, 6, 0, 0), 1128 1129 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 1130 GATE_IP_GSCL1, 2, 0, 0), 1131 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 1132 GATE_IP_GSCL1, 3, 0, 0), 1133 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 1134 GATE_IP_GSCL1, 4, 0, 0), 1135 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 1136 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 1137 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 1138 GATE_IP_GSCL1, 16, 0, 0), 1139 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 1140 GATE_IP_GSCL1, 17, 0, 0), 1141 1142 /* MSCL Block */ 1143 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 1144 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 1145 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 1146 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 1147 GATE_IP_MSCL, 8, 0, 0), 1148 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 1149 GATE_IP_MSCL, 9, 0, 0), 1150 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 1151 GATE_IP_MSCL, 10, 0, 0), 1152 1153 /* ISP */ 1154 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 1155 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 1156 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 1157 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 1158 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 1159 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 1160 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 1161 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 1162 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 1163 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 1164 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 1165 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 1166 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 1167 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 1168 1169 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 1170 }; 1171 1172 static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { 1173 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 1174 }; 1175 1176 static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { 1177 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1178 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1179 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1180 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1181 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1182 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1183 GATE_IP_DISP1, 7, 0, 0), 1184 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1185 GATE_IP_DISP1, 8, 0, 0), 1186 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1187 GATE_IP_DISP1, 9, 0, 0), 1188 }; 1189 1190 static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = { 1191 { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ 1192 { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ 1193 { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ 1194 { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ 1195 { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ 1196 }; 1197 1198 static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { 1199 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 1200 DIV2_RATIO0, 4, 2), 1201 }; 1202 1203 static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { 1204 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1205 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1206 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 1207 GATE_IP_GSCL1, 6, 0, 0), 1208 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 1209 GATE_IP_GSCL1, 7, 0, 0), 1210 }; 1211 1212 static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { 1213 { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ 1214 { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ 1215 { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ 1216 { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ 1217 }; 1218 1219 static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { 1220 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 1221 }; 1222 1223 static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { 1224 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 1225 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 1226 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 1227 }; 1228 1229 static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { 1230 { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ 1231 { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ 1232 { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ 1233 }; 1234 1235 static const struct exynos5_subcmu_info exynos5x_subcmus[] = { 1236 { 1237 .div_clks = exynos5x_disp_div_clks, 1238 .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), 1239 .gate_clks = exynos5x_disp_gate_clks, 1240 .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), 1241 .suspend_regs = exynos5x_disp_suspend_regs, 1242 .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), 1243 .pd_name = "DISP", 1244 }, { 1245 .div_clks = exynos5x_gsc_div_clks, 1246 .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), 1247 .gate_clks = exynos5x_gsc_gate_clks, 1248 .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), 1249 .suspend_regs = exynos5x_gsc_suspend_regs, 1250 .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), 1251 .pd_name = "GSC", 1252 }, { 1253 .div_clks = exynos5x_mfc_div_clks, 1254 .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), 1255 .gate_clks = exynos5x_mfc_gate_clks, 1256 .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), 1257 .suspend_regs = exynos5x_mfc_suspend_regs, 1258 .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), 1259 .pd_name = "MFC", 1260 }, 1261 }; 1262 1263 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { 1264 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0), 1265 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0), 1266 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0), 1267 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), 1268 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 1269 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 1270 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 1271 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 1272 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1), 1273 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), 1274 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), 1275 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1), 1276 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), 1277 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 1278 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2), 1279 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), 1280 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), 1281 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3), 1282 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), 1283 }; 1284 1285 static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 1286 PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), 1287 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), 1288 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), 1289 PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671), 1290 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0), 1291 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), 1292 PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671), 1293 PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719), 1294 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0), 1295 PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923), 1296 PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762), 1297 PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719), 1298 PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690), 1299 PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762), 1300 PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), 1301 }; 1302 1303 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1304 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1305 APLL_CON0, NULL), 1306 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1307 CPLL_CON0, NULL), 1308 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 1309 DPLL_CON0, NULL), 1310 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 1311 EPLL_CON0, NULL), 1312 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 1313 RPLL_CON0, NULL), 1314 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 1315 IPLL_CON0, NULL), 1316 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 1317 SPLL_CON0, NULL), 1318 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 1319 VPLL_CON0, NULL), 1320 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 1321 MPLL_CON0, NULL), 1322 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 1323 BPLL_CON0, NULL), 1324 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 1325 KPLL_CON0, NULL), 1326 }; 1327 1328 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1329 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1330 ((cpud) << 4))) 1331 1332 static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1333 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1334 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1335 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1336 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1337 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1338 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1339 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1340 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1341 { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1342 { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1343 { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1344 { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1345 { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1346 { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1347 { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1348 { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1349 { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1350 { 0 }, 1351 }; 1352 1353 static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 1354 { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1355 { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1356 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1357 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1358 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1359 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1360 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1361 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1362 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1363 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1364 { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 1365 { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 1366 { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 1367 { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 1368 { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 1369 { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1370 { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1371 { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1372 { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1373 { 0 }, 1374 }; 1375 1376 #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1377 ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1378 1379 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 1380 { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1381 { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1382 { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1383 { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1384 { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1385 { 900000, E5420_KFC_DIV(3, 5, 2), }, 1386 { 800000, E5420_KFC_DIV(3, 5, 2), }, 1387 { 700000, E5420_KFC_DIV(3, 4, 2), }, 1388 { 600000, E5420_KFC_DIV(3, 4, 2), }, 1389 { 500000, E5420_KFC_DIV(3, 4, 2), }, 1390 { 400000, E5420_KFC_DIV(3, 3, 2), }, 1391 { 300000, E5420_KFC_DIV(3, 3, 2), }, 1392 { 200000, E5420_KFC_DIV(3, 3, 2), }, 1393 { 0 }, 1394 }; 1395 1396 static const struct of_device_id ext_clk_match[] __initconst = { 1397 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 1398 { }, 1399 }; 1400 1401 /* register exynos5420 clocks */ 1402 static void __init exynos5x_clk_init(struct device_node *np, 1403 enum exynos5x_soc soc) 1404 { 1405 struct samsung_clk_provider *ctx; 1406 1407 if (np) { 1408 reg_base = of_iomap(np, 0); 1409 if (!reg_base) 1410 panic("%s: failed to map registers\n", __func__); 1411 } else { 1412 panic("%s: unable to determine soc\n", __func__); 1413 } 1414 1415 exynos5x_soc = soc; 1416 1417 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1418 1419 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 1420 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 1421 ext_clk_match); 1422 1423 if (_get_rate("fin_pll") == 24 * MHZ) { 1424 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1425 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; 1426 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1427 exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1428 } 1429 1430 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1431 reg_base); 1432 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 1433 ARRAY_SIZE(exynos5x_fixed_rate_clks)); 1434 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 1435 ARRAY_SIZE(exynos5x_fixed_factor_clks)); 1436 samsung_clk_register_mux(ctx, exynos5x_mux_clks, 1437 ARRAY_SIZE(exynos5x_mux_clks)); 1438 samsung_clk_register_div(ctx, exynos5x_div_clks, 1439 ARRAY_SIZE(exynos5x_div_clks)); 1440 samsung_clk_register_gate(ctx, exynos5x_gate_clks, 1441 ARRAY_SIZE(exynos5x_gate_clks)); 1442 1443 if (soc == EXYNOS5420) { 1444 samsung_clk_register_mux(ctx, exynos5420_mux_clks, 1445 ARRAY_SIZE(exynos5420_mux_clks)); 1446 samsung_clk_register_div(ctx, exynos5420_div_clks, 1447 ARRAY_SIZE(exynos5420_div_clks)); 1448 samsung_clk_register_gate(ctx, exynos5420_gate_clks, 1449 ARRAY_SIZE(exynos5420_gate_clks)); 1450 } else { 1451 samsung_clk_register_fixed_factor( 1452 ctx, exynos5800_fixed_factor_clks, 1453 ARRAY_SIZE(exynos5800_fixed_factor_clks)); 1454 samsung_clk_register_mux(ctx, exynos5800_mux_clks, 1455 ARRAY_SIZE(exynos5800_mux_clks)); 1456 samsung_clk_register_div(ctx, exynos5800_div_clks, 1457 ARRAY_SIZE(exynos5800_div_clks)); 1458 samsung_clk_register_gate(ctx, exynos5800_gate_clks, 1459 ARRAY_SIZE(exynos5800_gate_clks)); 1460 } 1461 1462 if (soc == EXYNOS5420) { 1463 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1464 mout_cpu_p[0], mout_cpu_p[1], 0x200, 1465 exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); 1466 } else { 1467 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1468 mout_cpu_p[0], mout_cpu_p[1], 0x200, 1469 exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); 1470 } 1471 exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", 1472 mout_kfc_p[0], mout_kfc_p[1], 0x28200, 1473 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); 1474 1475 samsung_clk_extended_sleep_init(reg_base, 1476 exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs), 1477 exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); 1478 if (soc == EXYNOS5800) 1479 samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, 1480 ARRAY_SIZE(exynos5800_clk_regs)); 1481 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), 1482 exynos5x_subcmus); 1483 1484 samsung_clk_of_add_provider(np, ctx); 1485 } 1486 1487 static void __init exynos5420_clk_init(struct device_node *np) 1488 { 1489 exynos5x_clk_init(np, EXYNOS5420); 1490 } 1491 CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", 1492 exynos5420_clk_init); 1493 1494 static void __init exynos5800_clk_init(struct device_node *np) 1495 { 1496 exynos5x_clk_init(np, EXYNOS5800); 1497 } 1498 CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", 1499 exynos5800_clk_init); 1500