1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 21609027fSChander Kashyap /* 31609027fSChander Kashyap * Copyright (c) 2013 Samsung Electronics Co., Ltd. 41609027fSChander Kashyap * Authors: Thomas Abraham <thomas.ab@samsung.com> 51609027fSChander Kashyap * Chander Kashyap <k.chander@samsung.com> 61609027fSChander Kashyap * 71609027fSChander Kashyap * Common Clock Framework support for Exynos5420 SoC. 81609027fSChander Kashyap */ 91609027fSChander Kashyap 10cba9d2faSAndrzej Hajda #include <dt-bindings/clock/exynos5420.h> 116f1ed07aSStephen Boyd #include <linux/slab.h> 121609027fSChander Kashyap #include <linux/clk-provider.h> 131609027fSChander Kashyap #include <linux/of.h> 141609027fSChander Kashyap #include <linux/of_address.h> 151609027fSChander Kashyap 161609027fSChander Kashyap #include "clk.h" 17bee4f87fSThomas Abraham #include "clk-cpu.h" 18ec4016ffSMarek Szyprowski #include "clk-exynos5-subcmu.h" 191609027fSChander Kashyap 20c898c6b7SYadwinder Singh Brar #define APLL_LOCK 0x0 21c898c6b7SYadwinder Singh Brar #define APLL_CON0 0x100 221609027fSChander Kashyap #define SRC_CPU 0x200 231609027fSChander Kashyap #define DIV_CPU0 0x500 241609027fSChander Kashyap #define DIV_CPU1 0x504 251609027fSChander Kashyap #define GATE_BUS_CPU 0x700 261609027fSChander Kashyap #define GATE_SCLK_CPU 0x800 2777342432SShaik Ameer Basha #define CLKOUT_CMU_CPU 0xa00 28e9d52956SVikas Sajjan #define SRC_MASK_CPERI 0x4300 295b73721bSNaveen Krishna Chatradhi #define GATE_IP_G2D 0x8800 30c898c6b7SYadwinder Singh Brar #define CPLL_LOCK 0x10020 31c898c6b7SYadwinder Singh Brar #define DPLL_LOCK 0x10030 32c898c6b7SYadwinder Singh Brar #define EPLL_LOCK 0x10040 33c898c6b7SYadwinder Singh Brar #define RPLL_LOCK 0x10050 34c898c6b7SYadwinder Singh Brar #define IPLL_LOCK 0x10060 35c898c6b7SYadwinder Singh Brar #define SPLL_LOCK 0x10070 3653cb6342SSachin Kamat #define VPLL_LOCK 0x10080 37c898c6b7SYadwinder Singh Brar #define MPLL_LOCK 0x10090 38c898c6b7SYadwinder Singh Brar #define CPLL_CON0 0x10120 39c898c6b7SYadwinder Singh Brar #define DPLL_CON0 0x10128 40c898c6b7SYadwinder Singh Brar #define EPLL_CON0 0x10130 4177342432SShaik Ameer Basha #define EPLL_CON1 0x10134 4277342432SShaik Ameer Basha #define EPLL_CON2 0x10138 43c898c6b7SYadwinder Singh Brar #define RPLL_CON0 0x10140 4477342432SShaik Ameer Basha #define RPLL_CON1 0x10144 4577342432SShaik Ameer Basha #define RPLL_CON2 0x10148 46c898c6b7SYadwinder Singh Brar #define IPLL_CON0 0x10150 47c898c6b7SYadwinder Singh Brar #define SPLL_CON0 0x10160 48c898c6b7SYadwinder Singh Brar #define VPLL_CON0 0x10170 49c898c6b7SYadwinder Singh Brar #define MPLL_CON0 0x10180 501609027fSChander Kashyap #define SRC_TOP0 0x10200 511609027fSChander Kashyap #define SRC_TOP1 0x10204 521609027fSChander Kashyap #define SRC_TOP2 0x10208 531609027fSChander Kashyap #define SRC_TOP3 0x1020c 541609027fSChander Kashyap #define SRC_TOP4 0x10210 551609027fSChander Kashyap #define SRC_TOP5 0x10214 561609027fSChander Kashyap #define SRC_TOP6 0x10218 571609027fSChander Kashyap #define SRC_TOP7 0x1021c 586520e968SAlim Akhtar #define SRC_TOP8 0x10220 /* 5800 specific */ 596520e968SAlim Akhtar #define SRC_TOP9 0x10224 /* 5800 specific */ 601609027fSChander Kashyap #define SRC_DISP10 0x1022c 611609027fSChander Kashyap #define SRC_MAU 0x10240 621609027fSChander Kashyap #define SRC_FSYS 0x10244 631609027fSChander Kashyap #define SRC_PERIC0 0x10250 641609027fSChander Kashyap #define SRC_PERIC1 0x10254 653a767b35SShaik Ameer Basha #define SRC_ISP 0x10270 666520e968SAlim Akhtar #define SRC_CAM 0x10274 /* 5800 specific */ 671609027fSChander Kashyap #define SRC_TOP10 0x10280 681609027fSChander Kashyap #define SRC_TOP11 0x10284 691609027fSChander Kashyap #define SRC_TOP12 0x10288 706520e968SAlim Akhtar #define SRC_TOP13 0x1028c /* 5800 specific */ 71e9d52956SVikas Sajjan #define SRC_MASK_TOP0 0x10300 72e9d52956SVikas Sajjan #define SRC_MASK_TOP1 0x10304 73424b673aSShaik Ameer Basha #define SRC_MASK_TOP2 0x10308 7431116a64SShaik Ameer Basha #define SRC_MASK_TOP7 0x1031c 751609027fSChander Kashyap #define SRC_MASK_DISP10 0x1032c 7631116a64SShaik Ameer Basha #define SRC_MASK_MAU 0x10334 771609027fSChander Kashyap #define SRC_MASK_FSYS 0x10340 781609027fSChander Kashyap #define SRC_MASK_PERIC0 0x10350 791609027fSChander Kashyap #define SRC_MASK_PERIC1 0x10354 80e9d52956SVikas Sajjan #define SRC_MASK_ISP 0x10370 811609027fSChander Kashyap #define DIV_TOP0 0x10500 821609027fSChander Kashyap #define DIV_TOP1 0x10504 831609027fSChander Kashyap #define DIV_TOP2 0x10508 846520e968SAlim Akhtar #define DIV_TOP8 0x10520 /* 5800 specific */ 856520e968SAlim Akhtar #define DIV_TOP9 0x10524 /* 5800 specific */ 861609027fSChander Kashyap #define DIV_DISP10 0x1052c 871609027fSChander Kashyap #define DIV_MAU 0x10544 881609027fSChander Kashyap #define DIV_FSYS0 0x10548 891609027fSChander Kashyap #define DIV_FSYS1 0x1054c 901609027fSChander Kashyap #define DIV_FSYS2 0x10550 911609027fSChander Kashyap #define DIV_PERIC0 0x10558 921609027fSChander Kashyap #define DIV_PERIC1 0x1055c 931609027fSChander Kashyap #define DIV_PERIC2 0x10560 941609027fSChander Kashyap #define DIV_PERIC3 0x10564 951609027fSChander Kashyap #define DIV_PERIC4 0x10568 966520e968SAlim Akhtar #define DIV_CAM 0x10574 /* 5800 specific */ 973a767b35SShaik Ameer Basha #define SCLK_DIV_ISP0 0x10580 983a767b35SShaik Ameer Basha #define SCLK_DIV_ISP1 0x10584 9902932381SShaik Ameer Basha #define DIV2_RATIO0 0x10590 1001d87db4dSShaik Ameer Basha #define DIV4_RATIO 0x105a0 1011609027fSChander Kashyap #define GATE_BUS_TOP 0x10700 102e9d52956SVikas Sajjan #define GATE_BUS_DISP1 0x10728 1030a22c306SShaik Ameer Basha #define GATE_BUS_GEN 0x1073c 1041609027fSChander Kashyap #define GATE_BUS_FSYS0 0x10740 1056b5ae463SShaik Ameer Basha #define GATE_BUS_FSYS2 0x10748 1061609027fSChander Kashyap #define GATE_BUS_PERIC 0x10750 1071609027fSChander Kashyap #define GATE_BUS_PERIC1 0x10754 1081609027fSChander Kashyap #define GATE_BUS_PERIS0 0x10760 1091609027fSChander Kashyap #define GATE_BUS_PERIS1 0x10764 1106575fa76SShaik Ameer Basha #define GATE_BUS_NOC 0x10770 1113a767b35SShaik Ameer Basha #define GATE_TOP_SCLK_ISP 0x10870 1121609027fSChander Kashyap #define GATE_IP_GSCL0 0x10910 1131609027fSChander Kashyap #define GATE_IP_GSCL1 0x10920 1146520e968SAlim Akhtar #define GATE_IP_CAM 0x10924 /* 5800 specific */ 1151609027fSChander Kashyap #define GATE_IP_MFC 0x1092c 1161609027fSChander Kashyap #define GATE_IP_DISP1 0x10928 1171609027fSChander Kashyap #define GATE_IP_G3D 0x10930 1181609027fSChander Kashyap #define GATE_IP_GEN 0x10934 1196b5ae463SShaik Ameer Basha #define GATE_IP_FSYS 0x10944 120faec151bSShaik Ameer Basha #define GATE_IP_PERIC 0x10950 1210a22c306SShaik Ameer Basha #define GATE_IP_PERIS 0x10960 1221609027fSChander Kashyap #define GATE_IP_MSCL 0x10970 1231609027fSChander Kashyap #define GATE_TOP_SCLK_GSCL 0x10820 1241609027fSChander Kashyap #define GATE_TOP_SCLK_DISP1 0x10828 1251609027fSChander Kashyap #define GATE_TOP_SCLK_MAU 0x1083c 1261609027fSChander Kashyap #define GATE_TOP_SCLK_FSYS 0x10840 1271609027fSChander Kashyap #define GATE_TOP_SCLK_PERIC 0x10850 128424b673aSShaik Ameer Basha #define TOP_SPARE2 0x10b08 129c898c6b7SYadwinder Singh Brar #define BPLL_LOCK 0x20010 130c898c6b7SYadwinder Singh Brar #define BPLL_CON0 0x20110 131e867e8faSChanwoo Choi #define SRC_CDREX 0x20200 132e867e8faSChanwoo Choi #define DIV_CDREX0 0x20500 133e867e8faSChanwoo Choi #define DIV_CDREX1 0x20504 1342f57b95cSLukasz Luba #define GATE_BUS_CDREX0 0x20700 1352f57b95cSLukasz Luba #define GATE_BUS_CDREX1 0x20704 136c898c6b7SYadwinder Singh Brar #define KPLL_LOCK 0x28000 137c898c6b7SYadwinder Singh Brar #define KPLL_CON0 0x28100 1381609027fSChander Kashyap #define SRC_KFC 0x28200 1391609027fSChander Kashyap #define DIV_KFC0 0x28500 1401609027fSChander Kashyap 1416520e968SAlim Akhtar /* Exynos5x SoC type */ 1426520e968SAlim Akhtar enum exynos5x_soc { 1436520e968SAlim Akhtar EXYNOS5420, 1446520e968SAlim Akhtar EXYNOS5800, 1456520e968SAlim Akhtar }; 1466520e968SAlim Akhtar 147c898c6b7SYadwinder Singh Brar /* list of PLLs */ 1486520e968SAlim Akhtar enum exynos5x_plls { 149c898c6b7SYadwinder Singh Brar apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 150c898c6b7SYadwinder Singh Brar bpll, kpll, 151c898c6b7SYadwinder Singh Brar nr_plls /* number of PLLs */ 152c898c6b7SYadwinder Singh Brar }; 153c898c6b7SYadwinder Singh Brar 154388c7885STomasz Figa static void __iomem *reg_base; 1556520e968SAlim Akhtar static enum exynos5x_soc exynos5x_soc; 156388c7885STomasz Figa 1571609027fSChander Kashyap /* 1581609027fSChander Kashyap * list of controller registers to be saved and restored during a 1591609027fSChander Kashyap * suspend/resume cycle. 1601609027fSChander Kashyap */ 161ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5x_clk_regs[] __initconst = { 1621609027fSChander Kashyap SRC_CPU, 1631609027fSChander Kashyap DIV_CPU0, 1641609027fSChander Kashyap DIV_CPU1, 1651609027fSChander Kashyap GATE_BUS_CPU, 1661609027fSChander Kashyap GATE_SCLK_CPU, 16777342432SShaik Ameer Basha CLKOUT_CMU_CPU, 168e9323b66SMarek Szyprowski CPLL_CON0, 169e9323b66SMarek Szyprowski DPLL_CON0, 17077342432SShaik Ameer Basha EPLL_CON0, 17177342432SShaik Ameer Basha EPLL_CON1, 17277342432SShaik Ameer Basha EPLL_CON2, 17377342432SShaik Ameer Basha RPLL_CON0, 17477342432SShaik Ameer Basha RPLL_CON1, 17577342432SShaik Ameer Basha RPLL_CON2, 176e9323b66SMarek Szyprowski IPLL_CON0, 177e9323b66SMarek Szyprowski SPLL_CON0, 178e9323b66SMarek Szyprowski VPLL_CON0, 179e9323b66SMarek Szyprowski MPLL_CON0, 1801609027fSChander Kashyap SRC_TOP0, 1811609027fSChander Kashyap SRC_TOP1, 1821609027fSChander Kashyap SRC_TOP2, 1831609027fSChander Kashyap SRC_TOP3, 1841609027fSChander Kashyap SRC_TOP4, 1851609027fSChander Kashyap SRC_TOP5, 1861609027fSChander Kashyap SRC_TOP6, 1871609027fSChander Kashyap SRC_TOP7, 1881609027fSChander Kashyap SRC_DISP10, 1891609027fSChander Kashyap SRC_MAU, 1901609027fSChander Kashyap SRC_FSYS, 1911609027fSChander Kashyap SRC_PERIC0, 1921609027fSChander Kashyap SRC_PERIC1, 1931609027fSChander Kashyap SRC_TOP10, 1941609027fSChander Kashyap SRC_TOP11, 1951609027fSChander Kashyap SRC_TOP12, 196424b673aSShaik Ameer Basha SRC_MASK_TOP2, 19731116a64SShaik Ameer Basha SRC_MASK_TOP7, 1981609027fSChander Kashyap SRC_MASK_DISP10, 1991609027fSChander Kashyap SRC_MASK_FSYS, 2001609027fSChander Kashyap SRC_MASK_PERIC0, 2011609027fSChander Kashyap SRC_MASK_PERIC1, 202e9d52956SVikas Sajjan SRC_MASK_TOP0, 203e9d52956SVikas Sajjan SRC_MASK_TOP1, 204e9d52956SVikas Sajjan SRC_MASK_MAU, 205e9d52956SVikas Sajjan SRC_MASK_ISP, 2063a767b35SShaik Ameer Basha SRC_ISP, 2071609027fSChander Kashyap DIV_TOP0, 2081609027fSChander Kashyap DIV_TOP1, 2091609027fSChander Kashyap DIV_TOP2, 2101609027fSChander Kashyap DIV_DISP10, 2111609027fSChander Kashyap DIV_MAU, 2121609027fSChander Kashyap DIV_FSYS0, 2131609027fSChander Kashyap DIV_FSYS1, 2141609027fSChander Kashyap DIV_FSYS2, 2151609027fSChander Kashyap DIV_PERIC0, 2161609027fSChander Kashyap DIV_PERIC1, 2171609027fSChander Kashyap DIV_PERIC2, 2181609027fSChander Kashyap DIV_PERIC3, 2191609027fSChander Kashyap DIV_PERIC4, 2203a767b35SShaik Ameer Basha SCLK_DIV_ISP0, 2213a767b35SShaik Ameer Basha SCLK_DIV_ISP1, 22202932381SShaik Ameer Basha DIV2_RATIO0, 2231d87db4dSShaik Ameer Basha DIV4_RATIO, 224e9d52956SVikas Sajjan GATE_BUS_DISP1, 2251609027fSChander Kashyap GATE_BUS_TOP, 2260a22c306SShaik Ameer Basha GATE_BUS_GEN, 2271609027fSChander Kashyap GATE_BUS_FSYS0, 2286b5ae463SShaik Ameer Basha GATE_BUS_FSYS2, 2291609027fSChander Kashyap GATE_BUS_PERIC, 2301609027fSChander Kashyap GATE_BUS_PERIC1, 2311609027fSChander Kashyap GATE_BUS_PERIS0, 2321609027fSChander Kashyap GATE_BUS_PERIS1, 2336575fa76SShaik Ameer Basha GATE_BUS_NOC, 2343a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2351609027fSChander Kashyap GATE_IP_GSCL0, 2361609027fSChander Kashyap GATE_IP_GSCL1, 2371609027fSChander Kashyap GATE_IP_MFC, 2381609027fSChander Kashyap GATE_IP_DISP1, 2391609027fSChander Kashyap GATE_IP_G3D, 2401609027fSChander Kashyap GATE_IP_GEN, 2416b5ae463SShaik Ameer Basha GATE_IP_FSYS, 242faec151bSShaik Ameer Basha GATE_IP_PERIC, 2430a22c306SShaik Ameer Basha GATE_IP_PERIS, 2441609027fSChander Kashyap GATE_IP_MSCL, 2451609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 2461609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 2471609027fSChander Kashyap GATE_TOP_SCLK_MAU, 2481609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2491609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 250424b673aSShaik Ameer Basha TOP_SPARE2, 251e867e8faSChanwoo Choi SRC_CDREX, 252e867e8faSChanwoo Choi DIV_CDREX0, 253e867e8faSChanwoo Choi DIV_CDREX1, 2541609027fSChander Kashyap SRC_KFC, 2551609027fSChander Kashyap DIV_KFC0, 2562f57b95cSLukasz Luba GATE_BUS_CDREX0, 2572f57b95cSLukasz Luba GATE_BUS_CDREX1, 2581609027fSChander Kashyap }; 2591609027fSChander Kashyap 260ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5800_clk_regs[] __initconst = { 2616520e968SAlim Akhtar SRC_TOP8, 2626520e968SAlim Akhtar SRC_TOP9, 2636520e968SAlim Akhtar SRC_CAM, 2646520e968SAlim Akhtar SRC_TOP1, 2656520e968SAlim Akhtar DIV_TOP8, 2666520e968SAlim Akhtar DIV_TOP9, 2676520e968SAlim Akhtar DIV_CAM, 2686520e968SAlim Akhtar GATE_IP_CAM, 2696520e968SAlim Akhtar }; 2706520e968SAlim Akhtar 271e9d52956SVikas Sajjan static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 272e9d52956SVikas Sajjan { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 273e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 274e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 275e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 276e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 277e9d52956SVikas Sajjan { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 278e9d52956SVikas Sajjan { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 279e9d52956SVikas Sajjan { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 280e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 281e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 282e9d52956SVikas Sajjan { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 28397372e5aSJavier Martinez Canillas { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 284e9d52956SVikas Sajjan { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 285e9d52956SVikas Sajjan { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 286b3322802SMarek Szyprowski { .offset = GATE_IP_PERIS, .value = 0xffffffff, }, 287e9d52956SVikas Sajjan }; 288e9d52956SVikas Sajjan 2891609027fSChander Kashyap /* list of all parent clocks */ 290dbd713bbSShaik Ameer Basha PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 291dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 292dbd713bbSShaik Ameer Basha PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 293dbd713bbSShaik Ameer Basha PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 294dbd713bbSShaik Ameer Basha PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 295dbd713bbSShaik Ameer Basha PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 296dbd713bbSShaik Ameer Basha PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 297dbd713bbSShaik Ameer Basha PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 298dbd713bbSShaik Ameer Basha PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 299dbd713bbSShaik Ameer Basha PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 300dbd713bbSShaik Ameer Basha PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 301dbd713bbSShaik Ameer Basha PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 302dbd713bbSShaik Ameer Basha PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 303dbd713bbSShaik Ameer Basha PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 304dbd713bbSShaik Ameer Basha PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 3051609027fSChander Kashyap 306dbd713bbSShaik Ameer Basha PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 307dbd713bbSShaik Ameer Basha "mout_sclk_mpll"}; 308dbd713bbSShaik Ameer Basha PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 309dbd713bbSShaik Ameer Basha "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 310dbd713bbSShaik Ameer Basha "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 311dbd713bbSShaik Ameer Basha PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 312dbd713bbSShaik Ameer Basha PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 313dbd713bbSShaik Ameer Basha PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 3141609027fSChander Kashyap 315424b673aSShaik Ameer Basha PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 316dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 317faec151bSShaik Ameer Basha PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 318b31ca2a0SShaik Ameer Basha PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 3191609027fSChander Kashyap 320dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 3216b5ae463SShaik Ameer Basha PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 3226b5ae463SShaik Ameer Basha PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 323dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 3241609027fSChander Kashyap 325dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 326dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 3276575fa76SShaik Ameer Basha PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 3286575fa76SShaik Ameer Basha PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 3296575fa76SShaik Ameer Basha 3306575fa76SShaik Ameer Basha PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 3316575fa76SShaik Ameer Basha PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 3326575fa76SShaik Ameer Basha PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 3336575fa76SShaik Ameer Basha 3343a767b35SShaik Ameer Basha PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 3353a767b35SShaik Ameer Basha PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 3363a767b35SShaik Ameer Basha 3373a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 3383a767b35SShaik Ameer Basha "mout_sclk_spll"}; 3393a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 3403a767b35SShaik Ameer Basha 3413a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 3423a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 3431609027fSChander Kashyap 344dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 345424b673aSShaik Ameer Basha PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 3461609027fSChander Kashyap 347dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 348dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 3491609027fSChander Kashyap 350dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 351dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 3521609027fSChander Kashyap 353dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 354dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 3551609027fSChander Kashyap 356dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 357dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 3583a767b35SShaik Ameer Basha PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 3591609027fSChander Kashyap 360dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 361dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 3621609027fSChander Kashyap 363dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 364dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 3651609027fSChander Kashyap 366dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 367424b673aSShaik Ameer Basha PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 368dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 369424b673aSShaik Ameer Basha PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 3701609027fSChander Kashyap 371dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 372dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 3731609027fSChander Kashyap 374dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 375dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 3761609027fSChander Kashyap 377dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 378dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 3791609027fSChander Kashyap 380dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 381dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 3821609027fSChander Kashyap 383dbd713bbSShaik Ameer Basha PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 384dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 385dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 386dbd713bbSShaik Ameer Basha PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 387dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 388dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 389dbd713bbSShaik Ameer Basha PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 390dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 391dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 392dbd713bbSShaik Ameer Basha PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 393dbd713bbSShaik Ameer Basha "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 394dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 395dbd713bbSShaik Ameer Basha PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 396dbd713bbSShaik Ameer Basha PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 397dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 398dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 39931116a64SShaik Ameer Basha PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 40031116a64SShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 401e867e8faSChanwoo Choi PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"}; 402e867e8faSChanwoo Choi 4036520e968SAlim Akhtar /* List of parents specific to exynos5800 */ 4046520e968SAlim Akhtar PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 4056520e968SAlim Akhtar PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4066520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4076520e968SAlim Akhtar PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4086520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4096520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 4106520e968SAlim Akhtar PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4116520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4126520e968SAlim Akhtar "mout_epll2" }; 4136520e968SAlim Akhtar PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4146520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll" }; 4156520e968SAlim Akhtar PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 4166520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4176520e968SAlim Akhtar PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4186520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll", 4196520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 420e867e8faSChanwoo Choi PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll", 421e867e8faSChanwoo Choi "mout_sclk_mpll", "ff_dout_spll2", 422e867e8faSChanwoo Choi "mout_sclk_spll", "mout_sclk_epll"}; 4236520e968SAlim Akhtar PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 4246520e968SAlim Akhtar "mout_sclk_mpll", 4256520e968SAlim Akhtar "ff_dout_spll2" }; 4266520e968SAlim Akhtar PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 4276520e968SAlim Akhtar PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 4286520e968SAlim Akhtar PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 4296520e968SAlim Akhtar PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 4306520e968SAlim Akhtar PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 4316520e968SAlim Akhtar PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 4326520e968SAlim Akhtar PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 4336520e968SAlim Akhtar PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 4348a9cf26eSSylwester Nawrocki PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; 4352f57b95cSLukasz Luba PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll", 4362f57b95cSLukasz Luba "mout_sclk_mpll", "ff_dout_spll2", 4372f57b95cSLukasz Luba "mout_sclk_spll", "mout_sclk_epll"}; 4381609027fSChander Kashyap 4391609027fSChander Kashyap /* fixed rate clocks generated outside the soc */ 4406520e968SAlim Akhtar static struct samsung_fixed_rate_clock 4416520e968SAlim Akhtar exynos5x_fixed_rate_ext_clks[] __initdata = { 442728f288dSStephen Boyd FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 4431609027fSChander Kashyap }; 4441609027fSChander Kashyap 4451609027fSChander Kashyap /* fixed rate clocks generated inside the soc */ 446ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { 447728f288dSStephen Boyd FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 448728f288dSStephen Boyd FRATE(0, "sclk_pwi", NULL, 0, 24000000), 449728f288dSStephen Boyd FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 450728f288dSStephen Boyd FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 451728f288dSStephen Boyd FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 4521609027fSChander Kashyap }; 4531609027fSChander Kashyap 454ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 455ad98c64fSKrzysztof Kozlowski exynos5x_fixed_factor_clks[] __initconst = { 456b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 457b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 4581609027fSChander Kashyap }; 4591609027fSChander Kashyap 460ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 461ad98c64fSKrzysztof Kozlowski exynos5800_fixed_factor_clks[] __initconst = { 4626520e968SAlim Akhtar FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 4632f57b95cSLukasz Luba FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 4646520e968SAlim Akhtar }; 4656520e968SAlim Akhtar 466ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 4676520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 4686520e968SAlim Akhtar MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 4696520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 4706520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 4716520e968SAlim Akhtar 4726520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 4736520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 4746520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 4756520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 4766520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 4776520e968SAlim Akhtar 4786520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 4796520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 4806520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 4816520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 4826520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 4836520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 4846520e968SAlim Akhtar 4852f57b95cSLukasz Luba MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy", 4862f57b95cSLukasz Luba mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3), 4872f57b95cSLukasz Luba 488e867e8faSChanwoo Choi MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 4892f57b95cSLukasz Luba mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3), 490599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, 491599cebeaSSylwester Nawrocki SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), 4922f57b95cSLukasz Luba MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 4936520e968SAlim Akhtar MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 4946520e968SAlim Akhtar 4956520e968SAlim Akhtar MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 4966520e968SAlim Akhtar MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 4976520e968SAlim Akhtar MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 4986520e968SAlim Akhtar MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 4996520e968SAlim Akhtar 500599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, 501599cebeaSSylwester Nawrocki SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0), 5026520e968SAlim Akhtar MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 5036520e968SAlim Akhtar SRC_TOP9, 16, 1), 5046520e968SAlim Akhtar MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 5056520e968SAlim Akhtar SRC_TOP9, 20, 1), 5066520e968SAlim Akhtar MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 5076520e968SAlim Akhtar SRC_TOP9, 24, 1), 5086520e968SAlim Akhtar MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 5096520e968SAlim Akhtar SRC_TOP9, 28, 1), 5106520e968SAlim Akhtar 5116520e968SAlim Akhtar MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 5126520e968SAlim Akhtar MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 5136520e968SAlim Akhtar SRC_TOP13, 20, 1), 5146520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 5156520e968SAlim Akhtar SRC_TOP13, 24, 1), 5166520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 5176520e968SAlim Akhtar SRC_TOP13, 28, 1), 5186520e968SAlim Akhtar 5196520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 5206520e968SAlim Akhtar }; 5216520e968SAlim Akhtar 522ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { 52381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 52481fed6e3SChanwoo Choi "mout_aclk400_wcore", DIV_TOP0, 16, 3), 5256520e968SAlim Akhtar DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 5266520e968SAlim Akhtar DIV_TOP8, 16, 3), 5276520e968SAlim Akhtar DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 5286520e968SAlim Akhtar DIV_TOP8, 20, 3), 5296520e968SAlim Akhtar DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 5306520e968SAlim Akhtar DIV_TOP8, 24, 3), 5316520e968SAlim Akhtar DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 5326520e968SAlim Akhtar DIV_TOP8, 28, 3), 5336520e968SAlim Akhtar 5346520e968SAlim Akhtar DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 5356520e968SAlim Akhtar DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 5366520e968SAlim Akhtar }; 5376520e968SAlim Akhtar 538ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 5396520e968SAlim Akhtar GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 5406520e968SAlim Akhtar GATE_BUS_TOP, 24, 0, 0), 5416520e968SAlim Akhtar GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 542318fa46cSMarek Szyprowski GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), 5436520e968SAlim Akhtar }; 5446520e968SAlim Akhtar 545ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 5466520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 5476520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 5486520e968SAlim Akhtar TOP_SPARE2, 4, 1), 5496520e968SAlim Akhtar 5506520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 55136ba4824SMarek Szyprowski MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2), 5526520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 5536520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 5546520e968SAlim Akhtar 5556520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 5566520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group4_p, 5576520e968SAlim Akhtar SRC_TOP1, 4, 2), 5586520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 5596520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 5606520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 5616520e968SAlim Akhtar 5626520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 5636520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 5646520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 5656520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 5666520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 5676520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 5686520e968SAlim Akhtar 569e867e8faSChanwoo Choi MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 570e867e8faSChanwoo Choi mout_group5_5800_p, SRC_TOP7, 16, 2), 57106255a92SSylwester Nawrocki MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2, 57206255a92SSylwester Nawrocki CLK_SET_RATE_PARENT, 0), 5736520e968SAlim Akhtar 5746520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 5756520e968SAlim Akhtar }; 5766520e968SAlim Akhtar 577ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 57881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 57981fed6e3SChanwoo Choi "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 5806520e968SAlim Akhtar }; 5816520e968SAlim Akhtar 58241097f25SSylwester Nawrocki static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { 583d32dd2a1SJoonyoung Shim GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 584b6adeb6bSSylwester Nawrocki /* Maudio Block */ 58541097f25SSylwester Nawrocki GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 586599cebeaSSylwester Nawrocki SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 587b6adeb6bSSylwester Nawrocki GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 588b6adeb6bSSylwester Nawrocki GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 589b6adeb6bSSylwester Nawrocki GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 590b6adeb6bSSylwester Nawrocki GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 59141097f25SSylwester Nawrocki }; 59241097f25SSylwester Nawrocki 593ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 594b31ca2a0SShaik Ameer Basha MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 595b31ca2a0SShaik Ameer Basha SRC_TOP7, 4, 1), 596dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 597dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 59831116a64SShaik Ameer Basha 599bee4f87fSThomas Abraham MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 600bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 601dbd713bbSShaik Ameer Basha MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 602bee4f87fSThomas Abraham MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 603bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 604dbd713bbSShaik Ameer Basha MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 6051609027fSChander Kashyap 606dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 607dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 6086b5ae463SShaik Ameer Basha MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 609dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 6101609027fSChander Kashyap 611dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 612dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 6131609027fSChander Kashyap 614dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 6151609027fSChander Kashyap 6163a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 6173a767b35SShaik Ameer Basha SRC_TOP3, 0, 1), 618dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 6191609027fSChander Kashyap SRC_TOP3, 4, 1), 62088560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 62188560100SJavier Martinez Canillas mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 622dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 6231609027fSChander Kashyap SRC_TOP3, 12, 1), 6246575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 6256575fa76SShaik Ameer Basha SRC_TOP3, 16, 1), 6266575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 6276575fa76SShaik Ameer Basha SRC_TOP3, 20, 1), 6286b5ae463SShaik Ameer Basha MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 6296b5ae463SShaik Ameer Basha SRC_TOP3, 24, 1), 630dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 6311609027fSChander Kashyap SRC_TOP3, 28, 1), 6321609027fSChander Kashyap 633dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 6341609027fSChander Kashyap SRC_TOP4, 0, 1), 6353a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 6363a767b35SShaik Ameer Basha SRC_TOP4, 4, 1), 637faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 638faec151bSShaik Ameer Basha SRC_TOP4, 8, 1), 6393a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 6403a767b35SShaik Ameer Basha SRC_TOP4, 12, 1), 6413a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 6423a767b35SShaik Ameer Basha SRC_TOP4, 16, 1), 643dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 644dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 645c0fb262bSArun Kumar K MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 646c0fb262bSArun Kumar K SRC_TOP4, 28, 1), 6471609027fSChander Kashyap 64888560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 64988560100SJavier Martinez Canillas mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 650faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 651faec151bSShaik Ameer Basha SRC_TOP5, 4, 1), 6523fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 6533fac5941SShaik Ameer Basha SRC_TOP5, 8, 1), 6543fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 6553fac5941SShaik Ameer Basha SRC_TOP5, 12, 1), 6563fac5941SShaik Ameer Basha MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 6573fac5941SShaik Ameer Basha SRC_TOP5, 16, 1), 658dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 6591609027fSChander Kashyap SRC_TOP5, 20, 1), 66088560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 66188560100SJavier Martinez Canillas mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 662c0feb268SMarek Szyprowski MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 663c0feb268SMarek Szyprowski mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 6641609027fSChander Kashyap 665dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 666dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 6672f57b95cSLukasz Luba MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 668dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 669dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 670599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, 671599cebeaSSylwester Nawrocki CLK_SET_RATE_PARENT, 0), 672dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 673dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 6741609027fSChander Kashyap 6753a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 6763a767b35SShaik Ameer Basha SRC_TOP10, 0, 1), 677dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 678dbd713bbSShaik Ameer Basha SRC_TOP10, 4, 1), 67988560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 68088560100SJavier Martinez Canillas SRC_TOP10, 8, 1), 681dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 6821609027fSChander Kashyap SRC_TOP10, 12, 1), 6836575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 6846575fa76SShaik Ameer Basha SRC_TOP10, 16, 1), 6856575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 6866575fa76SShaik Ameer Basha SRC_TOP10, 20, 1), 6876b5ae463SShaik Ameer Basha MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 6886b5ae463SShaik Ameer Basha SRC_TOP10, 24, 1), 689dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 690dbd713bbSShaik Ameer Basha SRC_TOP10, 28, 1), 6913a767b35SShaik Ameer Basha 692dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 6931609027fSChander Kashyap SRC_TOP11, 0, 1), 6943a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 6953a767b35SShaik Ameer Basha SRC_TOP11, 4, 1), 696dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 6973a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 6983a767b35SShaik Ameer Basha SRC_TOP11, 12, 1), 699dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 700dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 701c0fb262bSArun Kumar K MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 702c0fb262bSArun Kumar K SRC_TOP11, 28, 1), 7031609027fSChander Kashyap 70488560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 70588560100SJavier Martinez Canillas mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 706dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 707dbd713bbSShaik Ameer Basha SRC_TOP12, 8, 1), 708dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 709dbd713bbSShaik Ameer Basha SRC_TOP12, 12, 1), 710dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 711dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 712dbd713bbSShaik Ameer Basha SRC_TOP12, 20, 1), 71388560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 71488560100SJavier Martinez Canillas mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 715c0feb268SMarek Szyprowski MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 716c0feb268SMarek Szyprowski mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 7171609027fSChander Kashyap 7181609027fSChander Kashyap /* DISP1 Block */ 719dbd713bbSShaik Ameer Basha MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 720dbd713bbSShaik Ameer Basha MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 721dbd713bbSShaik Ameer Basha MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 722dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 723424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 7246575fa76SShaik Ameer Basha 725424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 7261609027fSChander Kashyap 727e867e8faSChanwoo Choi /* CDREX block */ 728e867e8faSChanwoo Choi MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p, 729e867e8faSChanwoo Choi SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0), 730e867e8faSChanwoo Choi MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1, 731e867e8faSChanwoo Choi CLK_SET_RATE_PARENT, 0), 732e867e8faSChanwoo Choi 7331609027fSChander Kashyap /* MAU Block */ 73431116a64SShaik Ameer Basha MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 7351609027fSChander Kashyap 7361609027fSChander Kashyap /* FSYS Block */ 737dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 738dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 739dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 740dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 741dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 742dbd713bbSShaik Ameer Basha MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 7436b5ae463SShaik Ameer Basha MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 7441609027fSChander Kashyap 7451609027fSChander Kashyap /* PERIC Block */ 746dbd713bbSShaik Ameer Basha MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 747dbd713bbSShaik Ameer Basha MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 748dbd713bbSShaik Ameer Basha MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 749dbd713bbSShaik Ameer Basha MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 750dbd713bbSShaik Ameer Basha MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 751dbd713bbSShaik Ameer Basha MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 752dbd713bbSShaik Ameer Basha MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 753dbd713bbSShaik Ameer Basha MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 754dbd713bbSShaik Ameer Basha MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 755dbd713bbSShaik Ameer Basha MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 756dbd713bbSShaik Ameer Basha MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 757dbd713bbSShaik Ameer Basha MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 7583a767b35SShaik Ameer Basha 7593a767b35SShaik Ameer Basha /* ISP Block */ 7603a767b35SShaik Ameer Basha MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 7613a767b35SShaik Ameer Basha MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 7623a767b35SShaik Ameer Basha MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 7633a767b35SShaik Ameer Basha MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 7643a767b35SShaik Ameer Basha MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 7651609027fSChander Kashyap }; 7661609027fSChander Kashyap 767ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 768cba9d2faSAndrzej Hajda DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 769cba9d2faSAndrzej Hajda DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 770cba9d2faSAndrzej Hajda DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 771dbd713bbSShaik Ameer Basha DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 772cba9d2faSAndrzej Hajda DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 7731609027fSChander Kashyap 77481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 77581fed6e3SChanwoo Choi DIV_TOP0, 0, 3), 77681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 77781fed6e3SChanwoo Choi DIV_TOP0, 4, 3), 77881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 77981fed6e3SChanwoo Choi DIV_TOP0, 8, 3), 78081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 78181fed6e3SChanwoo Choi DIV_TOP0, 12, 3), 78281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 78381fed6e3SChanwoo Choi DIV_TOP0, 20, 3), 78481fed6e3SChanwoo Choi DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 78581fed6e3SChanwoo Choi DIV_TOP0, 24, 3), 78681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 78781fed6e3SChanwoo Choi DIV_TOP0, 28, 3), 78881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 78981fed6e3SChanwoo Choi "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 79081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 79181fed6e3SChanwoo Choi "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 79281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 79381fed6e3SChanwoo Choi DIV_TOP1, 8, 6), 79481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 79581fed6e3SChanwoo Choi "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 79681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 79781fed6e3SChanwoo Choi DIV_TOP1, 20, 3), 79881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 79981fed6e3SChanwoo Choi DIV_TOP1, 24, 3), 80081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 80181fed6e3SChanwoo Choi DIV_TOP1, 28, 3), 8021609027fSChander Kashyap 80381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 80481fed6e3SChanwoo Choi DIV_TOP2, 8, 3), 80581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 80681fed6e3SChanwoo Choi DIV_TOP2, 12, 3), 80781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 80881fed6e3SChanwoo Choi 16, 3), 80981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 81081fed6e3SChanwoo Choi DIV_TOP2, 20, 3), 81181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 81281fed6e3SChanwoo Choi "mout_aclk300_disp1", DIV_TOP2, 24, 3), 81381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 81481fed6e3SChanwoo Choi DIV_TOP2, 28, 3), 8151609027fSChander Kashyap 8161609027fSChander Kashyap /* DISP1 Block */ 817424b673aSShaik Ameer Basha DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 818cba9d2faSAndrzej Hajda DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 819cba9d2faSAndrzej Hajda DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 820cba9d2faSAndrzej Hajda DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 82181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 82281fed6e3SChanwoo Choi "mout_aclk400_disp1", DIV_TOP2, 4, 3), 8231609027fSChander Kashyap 824e867e8faSChanwoo Choi /* CDREX Block */ 8252f57b95cSLukasz Luba /* 8262f57b95cSLukasz Luba * The three clocks below are controlled using the same register and 8272f57b95cSLukasz Luba * bits. They are put into one because there is a need of 8282f57b95cSLukasz Luba * synchronization between the BUS and DREXs (two external memory 8292f57b95cSLukasz Luba * interfaces). 8302f57b95cSLukasz Luba * They are put here to show this HW assumption and for clock 8312f57b95cSLukasz Luba * information summary completeness. 8322f57b95cSLukasz Luba */ 8332f57b95cSLukasz Luba DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", 8342f57b95cSLukasz Luba DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 8352f57b95cSLukasz Luba DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0", 8362f57b95cSLukasz Luba DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 8372f57b95cSLukasz Luba DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0", 8382f57b95cSLukasz Luba DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 8392f57b95cSLukasz Luba 840e867e8faSChanwoo Choi DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", 841e867e8faSChanwoo Choi DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), 842e867e8faSChanwoo Choi DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", 843e867e8faSChanwoo Choi DIV_CDREX0, 16, 3), 844e867e8faSChanwoo Choi DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", 845e867e8faSChanwoo Choi DIV_CDREX0, 8, 3), 846e867e8faSChanwoo Choi DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", 847e867e8faSChanwoo Choi DIV_CDREX0, 3, 5), 848e867e8faSChanwoo Choi 849e867e8faSChanwoo Choi DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", 850e867e8faSChanwoo Choi DIV_CDREX1, 8, 3), 851e867e8faSChanwoo Choi 8521609027fSChander Kashyap /* Audio Block */ 853cba9d2faSAndrzej Hajda DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 854cba9d2faSAndrzej Hajda DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 8551609027fSChander Kashyap 8561609027fSChander Kashyap /* USB3.0 */ 857cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 858cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 859cba9d2faSAndrzej Hajda DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 860cba9d2faSAndrzej Hajda DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 8611609027fSChander Kashyap 8621609027fSChander Kashyap /* MMC */ 863cba9d2faSAndrzej Hajda DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 864cba9d2faSAndrzej Hajda DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 865cba9d2faSAndrzej Hajda DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 8661609027fSChander Kashyap 867cba9d2faSAndrzej Hajda DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 8686b5ae463SShaik Ameer Basha DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 8691609027fSChander Kashyap 8701609027fSChander Kashyap /* UART and PWM */ 871cba9d2faSAndrzej Hajda DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 872cba9d2faSAndrzej Hajda DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 873cba9d2faSAndrzej Hajda DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 874cba9d2faSAndrzej Hajda DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 875cba9d2faSAndrzej Hajda DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 8761609027fSChander Kashyap 8771609027fSChander Kashyap /* SPI */ 878cba9d2faSAndrzej Hajda DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 879cba9d2faSAndrzej Hajda DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 880cba9d2faSAndrzej Hajda DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 8811609027fSChander Kashyap 8821d87db4dSShaik Ameer Basha 8831609027fSChander Kashyap /* PCM */ 884cba9d2faSAndrzej Hajda DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 885cba9d2faSAndrzej Hajda DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 8861609027fSChander Kashyap 8871609027fSChander Kashyap /* Audio - I2S */ 888cba9d2faSAndrzej Hajda DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 889cba9d2faSAndrzej Hajda DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 890cba9d2faSAndrzej Hajda DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 891cba9d2faSAndrzej Hajda DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 892cba9d2faSAndrzej Hajda DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 8931609027fSChander Kashyap 8941609027fSChander Kashyap /* SPI Pre-Ratio */ 895faec151bSShaik Ameer Basha DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 896faec151bSShaik Ameer Basha DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 897faec151bSShaik Ameer Basha DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 8983a767b35SShaik Ameer Basha 89902932381SShaik Ameer Basha /* GSCL Block */ 90002932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 90102932381SShaik Ameer Basha 9020a22c306SShaik Ameer Basha /* PSGEN */ 9030a22c306SShaik Ameer Basha DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 9040a22c306SShaik Ameer Basha DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 9050a22c306SShaik Ameer Basha 9063a767b35SShaik Ameer Basha /* ISP Block */ 9073a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 9083a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 9093a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 9103a767b35SShaik Ameer Basha DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 9113a767b35SShaik Ameer Basha DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 9123a767b35SShaik Ameer Basha DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 9133a767b35SShaik Ameer Basha DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 9143a767b35SShaik Ameer Basha DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 9153a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 9163a767b35SShaik Ameer Basha DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 9173a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 9181609027fSChander Kashyap }; 9191609027fSChander Kashyap 920ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 9215b73721bSNaveen Krishna Chatradhi /* G2D */ 9223fac5941SShaik Ameer Basha GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 9235b73721bSNaveen Krishna Chatradhi GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 9243fac5941SShaik Ameer Basha GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 9253fac5941SShaik Ameer Basha GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 9263fac5941SShaik Ameer Basha GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 9275b73721bSNaveen Krishna Chatradhi 9281609027fSChander Kashyap GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 929318fa46cSMarek Szyprowski GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), 9301609027fSChander Kashyap GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 9311609027fSChander Kashyap GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 9321609027fSChander Kashyap 9331609027fSChander Kashyap GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 9341609027fSChander Kashyap GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 9351609027fSChander Kashyap GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 936318fa46cSMarek Szyprowski GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), 9371609027fSChander Kashyap GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 9381609027fSChander Kashyap GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 9393a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 9403a767b35SShaik Ameer Basha GATE_BUS_TOP, 5, 0, 0), 9411609027fSChander Kashyap GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 942318fa46cSMarek Szyprowski GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), 9431609027fSChander Kashyap GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 9441609027fSChander Kashyap GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 9453a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 9463a767b35SShaik Ameer Basha GATE_BUS_TOP, 8, 0, 0), 947b31ca2a0SShaik Ameer Basha GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 9481609027fSChander Kashyap GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 949faec151bSShaik Ameer Basha GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 9501609027fSChander Kashyap GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 9513a767b35SShaik Ameer Basha GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 9523a767b35SShaik Ameer Basha GATE_BUS_TOP, 13, 0, 0), 9531609027fSChander Kashyap GATE(0, "aclk166", "mout_user_aclk166", 9541609027fSChander Kashyap GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 95534cba900SJavier Martinez Canillas GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", 956318fa46cSMarek Szyprowski GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), 9573a767b35SShaik Ameer Basha GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 9583a767b35SShaik Ameer Basha GATE_BUS_TOP, 16, 0, 0), 95902932381SShaik Ameer Basha GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 960c07c1a0fSAndrzej Pietrasiewicz GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), 961424b673aSShaik Ameer Basha GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 962318fa46cSMarek Szyprowski GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), 963b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 964b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 28, 0, 0), 965b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 966b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 29, 0, 0), 967424b673aSShaik Ameer Basha 968424b673aSShaik Ameer Basha GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 969318fa46cSMarek Szyprowski SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), 9701609027fSChander Kashyap 9711609027fSChander Kashyap /* sclk */ 972cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 9731609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 974cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 9751609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 976cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 9771609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 978cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 9791609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 980faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 9811609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 982faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 9831609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 984faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 9851609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 986cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 9871609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 988cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 9891609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 990cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 9911609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 992cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 9931609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 994cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 9951609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 996cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 9971609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 9981609027fSChander Kashyap 999cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 10001609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 1001cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 10021609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 1003cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 10041609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 1005cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 10061609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 1007cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 10081609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 1009cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 10101609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 1011cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 10121609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 10131609027fSChander Kashyap 10141609027fSChander Kashyap /* Display */ 1015cba9d2faSAndrzej Hajda GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 10161609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 1017cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 10181609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 1019cba9d2faSAndrzej Hajda GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 1020424b673aSShaik Ameer Basha GATE_TOP_SCLK_DISP1, 9, 0, 0), 1021cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 10221609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 1023cba9d2faSAndrzej Hajda GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 10241609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 10251609027fSChander Kashyap 10266b5ae463SShaik Ameer Basha /* FSYS Block */ 1027cba9d2faSAndrzej Hajda GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1028cba9d2faSAndrzej Hajda GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1029cba9d2faSAndrzej Hajda GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1030cba9d2faSAndrzej Hajda GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 10316b5ae463SShaik Ameer Basha GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 10326b5ae463SShaik Ameer Basha GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 10336b5ae463SShaik Ameer Basha GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 10346b5ae463SShaik Ameer Basha GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1035cba9d2faSAndrzej Hajda GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 10366b5ae463SShaik Ameer Basha GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 10376b5ae463SShaik Ameer Basha GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 10386b5ae463SShaik Ameer Basha GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 10396b5ae463SShaik Ameer Basha GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 10406b5ae463SShaik Ameer Basha GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 10416b5ae463SShaik Ameer Basha SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 10421609027fSChander Kashyap 1043faec151bSShaik Ameer Basha /* PERIC Block */ 104444ff0254SDoug Anderson GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 104544ff0254SDoug Anderson GATE_IP_PERIC, 0, 0, 0), 104644ff0254SDoug Anderson GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 104744ff0254SDoug Anderson GATE_IP_PERIC, 1, 0, 0), 104844ff0254SDoug Anderson GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 104944ff0254SDoug Anderson GATE_IP_PERIC, 2, 0, 0), 105044ff0254SDoug Anderson GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 105144ff0254SDoug Anderson GATE_IP_PERIC, 3, 0, 0), 105244ff0254SDoug Anderson GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 105344ff0254SDoug Anderson GATE_IP_PERIC, 6, 0, 0), 105444ff0254SDoug Anderson GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 105544ff0254SDoug Anderson GATE_IP_PERIC, 7, 0, 0), 105644ff0254SDoug Anderson GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 105744ff0254SDoug Anderson GATE_IP_PERIC, 8, 0, 0), 105844ff0254SDoug Anderson GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 105944ff0254SDoug Anderson GATE_IP_PERIC, 9, 0, 0), 106044ff0254SDoug Anderson GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 106144ff0254SDoug Anderson GATE_IP_PERIC, 10, 0, 0), 106244ff0254SDoug Anderson GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 106344ff0254SDoug Anderson GATE_IP_PERIC, 11, 0, 0), 106444ff0254SDoug Anderson GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 106544ff0254SDoug Anderson GATE_IP_PERIC, 12, 0, 0), 106644ff0254SDoug Anderson GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 106744ff0254SDoug Anderson GATE_IP_PERIC, 13, 0, 0), 106844ff0254SDoug Anderson GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 106944ff0254SDoug Anderson GATE_IP_PERIC, 14, 0, 0), 107044ff0254SDoug Anderson GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 107144ff0254SDoug Anderson GATE_IP_PERIC, 15, 0, 0), 107244ff0254SDoug Anderson GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 107344ff0254SDoug Anderson GATE_IP_PERIC, 16, 0, 0), 107444ff0254SDoug Anderson GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 107544ff0254SDoug Anderson GATE_IP_PERIC, 17, 0, 0), 107644ff0254SDoug Anderson GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 107744ff0254SDoug Anderson GATE_IP_PERIC, 18, 0, 0), 107844ff0254SDoug Anderson GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 107944ff0254SDoug Anderson GATE_IP_PERIC, 20, 0, 0), 108044ff0254SDoug Anderson GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 108144ff0254SDoug Anderson GATE_IP_PERIC, 21, 0, 0), 108244ff0254SDoug Anderson GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 108344ff0254SDoug Anderson GATE_IP_PERIC, 22, 0, 0), 108444ff0254SDoug Anderson GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 108544ff0254SDoug Anderson GATE_IP_PERIC, 23, 0, 0), 108644ff0254SDoug Anderson GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 108744ff0254SDoug Anderson GATE_IP_PERIC, 24, 0, 0), 108844ff0254SDoug Anderson GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 108944ff0254SDoug Anderson GATE_IP_PERIC, 26, 0, 0), 109044ff0254SDoug Anderson GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 109144ff0254SDoug Anderson GATE_IP_PERIC, 28, 0, 0), 109244ff0254SDoug Anderson GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 109344ff0254SDoug Anderson GATE_IP_PERIC, 30, 0, 0), 109444ff0254SDoug Anderson GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 109544ff0254SDoug Anderson GATE_IP_PERIC, 31, 0, 0), 10961609027fSChander Kashyap 109744ff0254SDoug Anderson GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 109844ff0254SDoug Anderson GATE_BUS_PERIC, 22, 0, 0), 10991609027fSChander Kashyap 11000a22c306SShaik Ameer Basha /* PERIS Block */ 1101cba9d2faSAndrzej Hajda GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 11020a22c306SShaik Ameer Basha GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1103cba9d2faSAndrzej Hajda GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 11040a22c306SShaik Ameer Basha GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 11050a22c306SShaik Ameer Basha GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 11060a22c306SShaik Ameer Basha GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 11070a22c306SShaik Ameer Basha GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 11080a22c306SShaik Ameer Basha GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 11090a22c306SShaik Ameer Basha GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 11100a22c306SShaik Ameer Basha GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 11110a22c306SShaik Ameer Basha GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 11120a22c306SShaik Ameer Basha GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 11130a22c306SShaik Ameer Basha GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 11140a22c306SShaik Ameer Basha GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 11150a22c306SShaik Ameer Basha GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 11160a22c306SShaik Ameer Basha GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 11170a22c306SShaik Ameer Basha GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 11180a22c306SShaik Ameer Basha GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 11190a22c306SShaik Ameer Basha GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 11200a22c306SShaik Ameer Basha GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 11211609027fSChander Kashyap 11220a22c306SShaik Ameer Basha /* GEN Block */ 11230a22c306SShaik Ameer Basha GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 11240a22c306SShaik Ameer Basha GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 11250a22c306SShaik Ameer Basha GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 11260a22c306SShaik Ameer Basha GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 11270a22c306SShaik Ameer Basha GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 11280a22c306SShaik Ameer Basha GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 11290a22c306SShaik Ameer Basha GATE_IP_GEN, 6, 0, 0), 11300a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 11310a22c306SShaik Ameer Basha GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 11320a22c306SShaik Ameer Basha GATE_IP_GEN, 9, 0, 0), 11330a22c306SShaik Ameer Basha 11340a22c306SShaik Ameer Basha /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 11350a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 11360a22c306SShaik Ameer Basha GATE_BUS_GEN, 28, 0, 0), 11370a22c306SShaik Ameer Basha GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 11381609027fSChander Kashyap 113902932381SShaik Ameer Basha /* GSCL Block */ 114002932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 114102932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 6, 0, 0), 114202932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 114302932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 7, 0, 0), 114402932381SShaik Ameer Basha 114502932381SShaik Ameer Basha GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 114602932381SShaik Ameer Basha GATE_IP_GSCL0, 4, 0, 0), 114702932381SShaik Ameer Basha GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 114802932381SShaik Ameer Basha GATE_IP_GSCL0, 5, 0, 0), 114902932381SShaik Ameer Basha GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 115002932381SShaik Ameer Basha GATE_IP_GSCL0, 6, 0, 0), 11511609027fSChander Kashyap 115202932381SShaik Ameer Basha GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 115302932381SShaik Ameer Basha GATE_IP_GSCL1, 2, 0, 0), 115402932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 11551609027fSChander Kashyap GATE_IP_GSCL1, 3, 0, 0), 115602932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 11571609027fSChander Kashyap GATE_IP_GSCL1, 4, 0, 0), 115802932381SShaik Ameer Basha GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 115902932381SShaik Ameer Basha GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 116002932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 11611609027fSChander Kashyap GATE_IP_GSCL1, 16, 0, 0), 1162cba9d2faSAndrzej Hajda GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 11631609027fSChander Kashyap GATE_IP_GSCL1, 17, 0, 0), 11641609027fSChander Kashyap 11653a767b35SShaik Ameer Basha /* ISP */ 11663a767b35SShaik Ameer Basha GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 11673a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 11683a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 11693a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 11703a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 11713a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 11723a767b35SShaik Ameer Basha GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 11733a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 11743a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 11753a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 11763a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 11773a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 11783a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 11793a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 11803a767b35SShaik Ameer Basha 11812f57b95cSLukasz Luba /* CDREX */ 11822f57b95cSLukasz Luba GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", 11832f57b95cSLukasz Luba GATE_BUS_CDREX0, 0, 0, 0), 11842f57b95cSLukasz Luba GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex", 11852f57b95cSLukasz Luba GATE_BUS_CDREX0, 1, 0, 0), 11862f57b95cSLukasz Luba GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy", 11872f57b95cSLukasz Luba SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0), 11882f57b95cSLukasz Luba 11892f57b95cSLukasz Luba GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1", 11902f57b95cSLukasz Luba GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0), 11912f57b95cSLukasz Luba GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1", 11922f57b95cSLukasz Luba GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0), 11932f57b95cSLukasz Luba GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1", 11942f57b95cSLukasz Luba GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0), 11952f57b95cSLukasz Luba GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1", 11962f57b95cSLukasz Luba GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0), 11972f57b95cSLukasz Luba 11982f57b95cSLukasz Luba GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex", 11992f57b95cSLukasz Luba GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0), 12002f57b95cSLukasz Luba GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex", 12012f57b95cSLukasz Luba GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0), 12022f57b95cSLukasz Luba GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex", 12032f57b95cSLukasz Luba GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0), 12042f57b95cSLukasz Luba GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex", 12052f57b95cSLukasz Luba GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0), 1206ec4016ffSMarek Szyprowski }; 1207ec4016ffSMarek Szyprowski 1208ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { 1209ec4016ffSMarek Szyprowski DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 1210ec4016ffSMarek Szyprowski }; 1211ec4016ffSMarek Szyprowski 1212ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { 1213ec4016ffSMarek Szyprowski GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1214ec4016ffSMarek Szyprowski GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1215ec4016ffSMarek Szyprowski GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1216ec4016ffSMarek Szyprowski GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1217ec4016ffSMarek Szyprowski GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1218ec4016ffSMarek Szyprowski GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1219ec4016ffSMarek Szyprowski GATE_IP_DISP1, 7, 0, 0), 1220ec4016ffSMarek Szyprowski GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1221ec4016ffSMarek Szyprowski GATE_IP_DISP1, 8, 0, 0), 1222ec4016ffSMarek Szyprowski GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1223ec4016ffSMarek Szyprowski GATE_IP_DISP1, 9, 0, 0), 1224ec4016ffSMarek Szyprowski }; 1225ec4016ffSMarek Szyprowski 1226ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = { 1227ec4016ffSMarek Szyprowski { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ 1228ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ 1229ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ 1230ec4016ffSMarek Szyprowski { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ 1231ec4016ffSMarek Szyprowski { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ 1232ec4016ffSMarek Szyprowski }; 1233ec4016ffSMarek Szyprowski 1234ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { 1235ec4016ffSMarek Szyprowski DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 1236ec4016ffSMarek Szyprowski DIV2_RATIO0, 4, 2), 1237ec4016ffSMarek Szyprowski }; 1238ec4016ffSMarek Szyprowski 1239ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { 1240ec4016ffSMarek Szyprowski GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1241ec4016ffSMarek Szyprowski GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1242ec4016ffSMarek Szyprowski GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 1243ec4016ffSMarek Szyprowski GATE_IP_GSCL1, 6, 0, 0), 1244ec4016ffSMarek Szyprowski GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 1245ec4016ffSMarek Szyprowski GATE_IP_GSCL1, 7, 0, 0), 1246ec4016ffSMarek Szyprowski }; 1247ec4016ffSMarek Szyprowski 1248ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { 1249ec4016ffSMarek Szyprowski { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ 1250ec4016ffSMarek Szyprowski { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ 1251ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ 1252ec4016ffSMarek Szyprowski { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ 1253ec4016ffSMarek Szyprowski }; 1254ec4016ffSMarek Szyprowski 1255c9f7567aSMarek Szyprowski static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = { 1256c9f7567aSMarek Szyprowski GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 1257c9f7567aSMarek Szyprowski }; 1258c9f7567aSMarek Szyprowski 1259c9f7567aSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = { 1260c9f7567aSMarek Szyprowski { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */ 1261c9f7567aSMarek Szyprowski { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */ 1262c9f7567aSMarek Szyprowski }; 1263c9f7567aSMarek Szyprowski 1264ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { 1265ec4016ffSMarek Szyprowski DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 1266ec4016ffSMarek Szyprowski }; 1267ec4016ffSMarek Szyprowski 1268ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { 1269cba9d2faSAndrzej Hajda GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 12701d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 12711d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 1272ec4016ffSMarek Szyprowski }; 12731609027fSChander Kashyap 1274ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { 1275ec4016ffSMarek Szyprowski { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ 1276ec4016ffSMarek Szyprowski { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ 1277ec4016ffSMarek Szyprowski { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ 1278ec4016ffSMarek Szyprowski }; 1279ec4016ffSMarek Szyprowski 1280baf7b79eSMarek Szyprowski static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = { 1281baf7b79eSMarek Szyprowski /* MSCL Block */ 1282baf7b79eSMarek Szyprowski GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 1283baf7b79eSMarek Szyprowski GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 1284baf7b79eSMarek Szyprowski GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 1285baf7b79eSMarek Szyprowski GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 1286baf7b79eSMarek Szyprowski GATE_IP_MSCL, 8, 0, 0), 1287baf7b79eSMarek Szyprowski GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 1288baf7b79eSMarek Szyprowski GATE_IP_MSCL, 9, 0, 0), 1289baf7b79eSMarek Szyprowski GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 1290baf7b79eSMarek Szyprowski GATE_IP_MSCL, 10, 0, 0), 1291baf7b79eSMarek Szyprowski }; 1292baf7b79eSMarek Szyprowski 1293baf7b79eSMarek Szyprowski static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = { 1294baf7b79eSMarek Szyprowski DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 1295baf7b79eSMarek Szyprowski }; 1296baf7b79eSMarek Szyprowski 1297baf7b79eSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = { 1298baf7b79eSMarek Szyprowski { GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */ 1299baf7b79eSMarek Szyprowski { SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */ 1300baf7b79eSMarek Szyprowski { DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */ 1301baf7b79eSMarek Szyprowski }; 1302b6adeb6bSSylwester Nawrocki 1303b6adeb6bSSylwester Nawrocki static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = { 1304b6adeb6bSSylwester Nawrocki GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", 1305b6adeb6bSSylwester Nawrocki SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 1306b6adeb6bSSylwester Nawrocki GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 1307b6adeb6bSSylwester Nawrocki GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1308b6adeb6bSSylwester Nawrocki GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 1309b6adeb6bSSylwester Nawrocki GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 1310b6adeb6bSSylwester Nawrocki }; 1311b6adeb6bSSylwester Nawrocki 1312b6adeb6bSSylwester Nawrocki static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = { 1313b6adeb6bSSylwester Nawrocki { SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */ 1314b6adeb6bSSylwester Nawrocki }; 1315b6adeb6bSSylwester Nawrocki 1316bf32e7dbSSylwester Nawrocki static const struct exynos5_subcmu_info exynos5x_disp_subcmu = { 1317ec4016ffSMarek Szyprowski .div_clks = exynos5x_disp_div_clks, 1318ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), 1319ec4016ffSMarek Szyprowski .gate_clks = exynos5x_disp_gate_clks, 1320ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), 1321ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_disp_suspend_regs, 1322ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), 1323ec4016ffSMarek Szyprowski .pd_name = "DISP", 1324bf32e7dbSSylwester Nawrocki }; 1325bf32e7dbSSylwester Nawrocki 1326bf32e7dbSSylwester Nawrocki static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = { 1327ec4016ffSMarek Szyprowski .div_clks = exynos5x_gsc_div_clks, 1328ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), 1329ec4016ffSMarek Szyprowski .gate_clks = exynos5x_gsc_gate_clks, 1330ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), 1331ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_gsc_suspend_regs, 1332ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), 1333ec4016ffSMarek Szyprowski .pd_name = "GSC", 1334bf32e7dbSSylwester Nawrocki }; 1335bf32e7dbSSylwester Nawrocki 1336c9f7567aSMarek Szyprowski static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = { 1337c9f7567aSMarek Szyprowski .gate_clks = exynos5x_g3d_gate_clks, 1338c9f7567aSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks), 1339c9f7567aSMarek Szyprowski .suspend_regs = exynos5x_g3d_suspend_regs, 1340c9f7567aSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs), 1341c9f7567aSMarek Szyprowski .pd_name = "G3D", 1342c9f7567aSMarek Szyprowski }; 1343c9f7567aSMarek Szyprowski 1344bf32e7dbSSylwester Nawrocki static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = { 1345ec4016ffSMarek Szyprowski .div_clks = exynos5x_mfc_div_clks, 1346ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), 1347ec4016ffSMarek Szyprowski .gate_clks = exynos5x_mfc_gate_clks, 1348ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), 1349ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_mfc_suspend_regs, 1350ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), 1351ec4016ffSMarek Szyprowski .pd_name = "MFC", 1352bf32e7dbSSylwester Nawrocki }; 1353bf32e7dbSSylwester Nawrocki 1354baf7b79eSMarek Szyprowski static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = { 1355baf7b79eSMarek Szyprowski .div_clks = exynos5x_mscl_div_clks, 1356baf7b79eSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_mscl_div_clks), 1357baf7b79eSMarek Szyprowski .gate_clks = exynos5x_mscl_gate_clks, 1358baf7b79eSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_mscl_gate_clks), 1359baf7b79eSMarek Szyprowski .suspend_regs = exynos5x_mscl_suspend_regs, 1360baf7b79eSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_mscl_suspend_regs), 1361baf7b79eSMarek Szyprowski .pd_name = "MSC", 1362baf7b79eSMarek Szyprowski }; 1363baf7b79eSMarek Szyprowski 1364b6adeb6bSSylwester Nawrocki static const struct exynos5_subcmu_info exynos5800_mau_subcmu = { 1365b6adeb6bSSylwester Nawrocki .gate_clks = exynos5800_mau_gate_clks, 1366b6adeb6bSSylwester Nawrocki .nr_gate_clks = ARRAY_SIZE(exynos5800_mau_gate_clks), 1367b6adeb6bSSylwester Nawrocki .suspend_regs = exynos5800_mau_suspend_regs, 1368b6adeb6bSSylwester Nawrocki .nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs), 1369b6adeb6bSSylwester Nawrocki .pd_name = "MAU", 1370b6adeb6bSSylwester Nawrocki }; 1371b6adeb6bSSylwester Nawrocki 1372bf32e7dbSSylwester Nawrocki static const struct exynos5_subcmu_info *exynos5x_subcmus[] = { 1373bf32e7dbSSylwester Nawrocki &exynos5x_disp_subcmu, 1374bf32e7dbSSylwester Nawrocki &exynos5x_gsc_subcmu, 1375c9f7567aSMarek Szyprowski &exynos5x_g3d_subcmu, 1376bf32e7dbSSylwester Nawrocki &exynos5x_mfc_subcmu, 1377baf7b79eSMarek Szyprowski &exynos5x_mscl_subcmu, 13781609027fSChander Kashyap }; 13791609027fSChander Kashyap 1380b6adeb6bSSylwester Nawrocki static const struct exynos5_subcmu_info *exynos5800_subcmus[] = { 1381b6adeb6bSSylwester Nawrocki &exynos5x_disp_subcmu, 1382b6adeb6bSSylwester Nawrocki &exynos5x_gsc_subcmu, 1383c9f7567aSMarek Szyprowski &exynos5x_g3d_subcmu, 1384b6adeb6bSSylwester Nawrocki &exynos5x_mfc_subcmu, 1385baf7b79eSMarek Szyprowski &exynos5x_mscl_subcmu, 1386b6adeb6bSSylwester Nawrocki &exynos5800_mau_subcmu, 1387b6adeb6bSSylwester Nawrocki }; 1388b6adeb6bSSylwester Nawrocki 1389ebd217e1SKrzysztof Kozlowski static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { 13901d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0), 13911d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0), 13921d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0), 13931d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), 13941d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 13951d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 13961d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 13971d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 13981d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1), 13991d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), 14001d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), 14011d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1), 14021d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), 14031d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 14041d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2), 14051d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), 14061d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), 14071d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3), 14081d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), 1409ca5b4029SThomas Abraham }; 1410ca5b4029SThomas Abraham 14118b4a7acfSLukasz Luba static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { 14128b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), 14138b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), 14148b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), 14158b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), 14168b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), 14178b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), 14188b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), 14198b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), 14208b4a7acfSLukasz Luba }; 14218b4a7acfSLukasz Luba 14229842452aSSylwester Nawrocki static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 14231d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), 14241d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), 14251d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), 14261d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671), 14271d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0), 14281d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), 14291d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671), 14301d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719), 14311d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0), 1432948e0684SSylwester Nawrocki PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923), 1433948e0684SSylwester Nawrocki PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762), 14341d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719), 14351d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690), 1436948e0684SSylwester Nawrocki PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762), 14371d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), 14389842452aSSylwester Nawrocki }; 14399842452aSSylwester Nawrocki 14406520e968SAlim Akhtar static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1441cba9d2faSAndrzej Hajda [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 14423ff6e0d8SYadwinder Singh Brar APLL_CON0, NULL), 1443cba9d2faSAndrzej Hajda [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1444cdf64eeeSChander Kashyap CPLL_CON0, NULL), 1445cba9d2faSAndrzej Hajda [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 14463ff6e0d8SYadwinder Singh Brar DPLL_CON0, NULL), 14479842452aSSylwester Nawrocki [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 14483ff6e0d8SYadwinder Singh Brar EPLL_CON0, NULL), 1449cba9d2faSAndrzej Hajda [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 14503ff6e0d8SYadwinder Singh Brar RPLL_CON0, NULL), 1451cba9d2faSAndrzej Hajda [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 14523ff6e0d8SYadwinder Singh Brar IPLL_CON0, NULL), 1453cba9d2faSAndrzej Hajda [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 14543ff6e0d8SYadwinder Singh Brar SPLL_CON0, NULL), 1455cba9d2faSAndrzej Hajda [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 14563ff6e0d8SYadwinder Singh Brar VPLL_CON0, NULL), 1457cba9d2faSAndrzej Hajda [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 14583ff6e0d8SYadwinder Singh Brar MPLL_CON0, NULL), 1459cba9d2faSAndrzej Hajda [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 14603ff6e0d8SYadwinder Singh Brar BPLL_CON0, NULL), 1461cba9d2faSAndrzej Hajda [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 14623ff6e0d8SYadwinder Singh Brar KPLL_CON0, NULL), 1463c898c6b7SYadwinder Singh Brar }; 1464c898c6b7SYadwinder Singh Brar 1465bee4f87fSThomas Abraham #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1466bee4f87fSThomas Abraham ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1467bee4f87fSThomas Abraham ((cpud) << 4))) 1468bee4f87fSThomas Abraham 1469bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1470bee4f87fSThomas Abraham { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1471bee4f87fSThomas Abraham { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1472bee4f87fSThomas Abraham { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1473bee4f87fSThomas Abraham { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1474bee4f87fSThomas Abraham { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1475bee4f87fSThomas Abraham { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1476bee4f87fSThomas Abraham { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1477bee4f87fSThomas Abraham { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1478bee4f87fSThomas Abraham { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1479bee4f87fSThomas Abraham { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1480bee4f87fSThomas Abraham { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1481bee4f87fSThomas Abraham { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1482bee4f87fSThomas Abraham { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1483bee4f87fSThomas Abraham { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1484bee4f87fSThomas Abraham { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1485bee4f87fSThomas Abraham { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1486bee4f87fSThomas Abraham { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1487bee4f87fSThomas Abraham { 0 }, 1488bee4f87fSThomas Abraham }; 1489bee4f87fSThomas Abraham 149054abbdb4SBartlomiej Zolnierkiewicz static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 149154abbdb4SBartlomiej Zolnierkiewicz { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 149254abbdb4SBartlomiej Zolnierkiewicz { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 149354abbdb4SBartlomiej Zolnierkiewicz { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 149454abbdb4SBartlomiej Zolnierkiewicz { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 149554abbdb4SBartlomiej Zolnierkiewicz { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 149654abbdb4SBartlomiej Zolnierkiewicz { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 149754abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 149854abbdb4SBartlomiej Zolnierkiewicz { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 149954abbdb4SBartlomiej Zolnierkiewicz { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 150054abbdb4SBartlomiej Zolnierkiewicz { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 150154abbdb4SBartlomiej Zolnierkiewicz { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 150254abbdb4SBartlomiej Zolnierkiewicz { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 150354abbdb4SBartlomiej Zolnierkiewicz { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 150454abbdb4SBartlomiej Zolnierkiewicz { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 150554abbdb4SBartlomiej Zolnierkiewicz { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 150654abbdb4SBartlomiej Zolnierkiewicz { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 150754abbdb4SBartlomiej Zolnierkiewicz { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 150854abbdb4SBartlomiej Zolnierkiewicz { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 150954abbdb4SBartlomiej Zolnierkiewicz { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 151054abbdb4SBartlomiej Zolnierkiewicz { 0 }, 151154abbdb4SBartlomiej Zolnierkiewicz }; 151254abbdb4SBartlomiej Zolnierkiewicz 1513bee4f87fSThomas Abraham #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1514bee4f87fSThomas Abraham ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1515bee4f87fSThomas Abraham 1516bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 151754abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1518bee4f87fSThomas Abraham { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1519bee4f87fSThomas Abraham { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1520bee4f87fSThomas Abraham { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1521bee4f87fSThomas Abraham { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1522bee4f87fSThomas Abraham { 900000, E5420_KFC_DIV(3, 5, 2), }, 1523bee4f87fSThomas Abraham { 800000, E5420_KFC_DIV(3, 5, 2), }, 1524bee4f87fSThomas Abraham { 700000, E5420_KFC_DIV(3, 4, 2), }, 1525bee4f87fSThomas Abraham { 600000, E5420_KFC_DIV(3, 4, 2), }, 1526bee4f87fSThomas Abraham { 500000, E5420_KFC_DIV(3, 4, 2), }, 1527bee4f87fSThomas Abraham { 400000, E5420_KFC_DIV(3, 3, 2), }, 1528bee4f87fSThomas Abraham { 300000, E5420_KFC_DIV(3, 3, 2), }, 1529bee4f87fSThomas Abraham { 200000, E5420_KFC_DIV(3, 3, 2), }, 1530bee4f87fSThomas Abraham { 0 }, 1531bee4f87fSThomas Abraham }; 1532bee4f87fSThomas Abraham 1533305cfab0SKrzysztof Kozlowski static const struct of_device_id ext_clk_match[] __initconst = { 15341609027fSChander Kashyap { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 15351609027fSChander Kashyap { }, 15361609027fSChander Kashyap }; 15371609027fSChander Kashyap 15381609027fSChander Kashyap /* register exynos5420 clocks */ 15396520e968SAlim Akhtar static void __init exynos5x_clk_init(struct device_node *np, 15406520e968SAlim Akhtar enum exynos5x_soc soc) 15411609027fSChander Kashyap { 1542976face4SRahul Sharma struct samsung_clk_provider *ctx; 1543976face4SRahul Sharma 15441609027fSChander Kashyap if (np) { 15451609027fSChander Kashyap reg_base = of_iomap(np, 0); 15461609027fSChander Kashyap if (!reg_base) 15471609027fSChander Kashyap panic("%s: failed to map registers\n", __func__); 15481609027fSChander Kashyap } else { 15491609027fSChander Kashyap panic("%s: unable to determine soc\n", __func__); 15501609027fSChander Kashyap } 15511609027fSChander Kashyap 15526520e968SAlim Akhtar exynos5x_soc = soc; 15536520e968SAlim Akhtar 1554976face4SRahul Sharma ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1555976face4SRahul Sharma 15566520e968SAlim Akhtar samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 15576520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 15581609027fSChander Kashyap ext_clk_match); 1559ca5b4029SThomas Abraham 1560ca5b4029SThomas Abraham if (_get_rate("fin_pll") == 24 * MHZ) { 1561ca5b4029SThomas Abraham exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 15629842452aSSylwester Nawrocki exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; 1563ca5b4029SThomas Abraham exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1564ca5b4029SThomas Abraham } 1565ca5b4029SThomas Abraham 15668b4a7acfSLukasz Luba if (soc == EXYNOS5420) 15678b4a7acfSLukasz Luba exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 15688b4a7acfSLukasz Luba else 15698b4a7acfSLukasz Luba exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; 15708b4a7acfSLukasz Luba 15716520e968SAlim Akhtar samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1572c898c6b7SYadwinder Singh Brar reg_base); 15736520e968SAlim Akhtar samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 15746520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_clks)); 15756520e968SAlim Akhtar samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 15766520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_factor_clks)); 15776520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5x_mux_clks, 15786520e968SAlim Akhtar ARRAY_SIZE(exynos5x_mux_clks)); 15796520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5x_div_clks, 15806520e968SAlim Akhtar ARRAY_SIZE(exynos5x_div_clks)); 15816520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5x_gate_clks, 15826520e968SAlim Akhtar ARRAY_SIZE(exynos5x_gate_clks)); 15836520e968SAlim Akhtar 15846520e968SAlim Akhtar if (soc == EXYNOS5420) { 1585976face4SRahul Sharma samsung_clk_register_mux(ctx, exynos5420_mux_clks, 15861609027fSChander Kashyap ARRAY_SIZE(exynos5420_mux_clks)); 1587976face4SRahul Sharma samsung_clk_register_div(ctx, exynos5420_div_clks, 15881609027fSChander Kashyap ARRAY_SIZE(exynos5420_div_clks)); 158941097f25SSylwester Nawrocki samsung_clk_register_gate(ctx, exynos5420_gate_clks, 159041097f25SSylwester Nawrocki ARRAY_SIZE(exynos5420_gate_clks)); 15916520e968SAlim Akhtar } else { 15926520e968SAlim Akhtar samsung_clk_register_fixed_factor( 15936520e968SAlim Akhtar ctx, exynos5800_fixed_factor_clks, 15946520e968SAlim Akhtar ARRAY_SIZE(exynos5800_fixed_factor_clks)); 15956520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5800_mux_clks, 15966520e968SAlim Akhtar ARRAY_SIZE(exynos5800_mux_clks)); 15976520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5800_div_clks, 15986520e968SAlim Akhtar ARRAY_SIZE(exynos5800_div_clks)); 15996520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5800_gate_clks, 16006520e968SAlim Akhtar ARRAY_SIZE(exynos5800_gate_clks)); 16016520e968SAlim Akhtar } 1602388c7885STomasz Figa 160354abbdb4SBartlomiej Zolnierkiewicz if (soc == EXYNOS5420) { 1604bee4f87fSThomas Abraham exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1605bee4f87fSThomas Abraham mout_cpu_p[0], mout_cpu_p[1], 0x200, 1606bee4f87fSThomas Abraham exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); 160754abbdb4SBartlomiej Zolnierkiewicz } else { 160854abbdb4SBartlomiej Zolnierkiewicz exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 160954abbdb4SBartlomiej Zolnierkiewicz mout_cpu_p[0], mout_cpu_p[1], 0x200, 161054abbdb4SBartlomiej Zolnierkiewicz exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); 161154abbdb4SBartlomiej Zolnierkiewicz } 1612bee4f87fSThomas Abraham exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", 1613bee4f87fSThomas Abraham mout_kfc_p[0], mout_kfc_p[1], 0x28200, 1614bee4f87fSThomas Abraham exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); 1615bee4f87fSThomas Abraham 16162d77f77cSMarek Szyprowski samsung_clk_extended_sleep_init(reg_base, 16172d77f77cSMarek Szyprowski exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs), 16182d77f77cSMarek Szyprowski exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); 1619b6adeb6bSSylwester Nawrocki 1620b6adeb6bSSylwester Nawrocki if (soc == EXYNOS5800) { 16212d77f77cSMarek Szyprowski samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, 16222d77f77cSMarek Szyprowski ARRAY_SIZE(exynos5800_clk_regs)); 1623b6adeb6bSSylwester Nawrocki 1624b6adeb6bSSylwester Nawrocki exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus), 1625b6adeb6bSSylwester Nawrocki exynos5800_subcmus); 1626b6adeb6bSSylwester Nawrocki } else { 1627ec4016ffSMarek Szyprowski exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), 1628ec4016ffSMarek Szyprowski exynos5x_subcmus); 1629b6adeb6bSSylwester Nawrocki } 1630d5e136a2SSylwester Nawrocki 1631d5e136a2SSylwester Nawrocki samsung_clk_of_add_provider(np, ctx); 16321609027fSChander Kashyap } 16336520e968SAlim Akhtar 16346520e968SAlim Akhtar static void __init exynos5420_clk_init(struct device_node *np) 16356520e968SAlim Akhtar { 16366520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5420); 16376520e968SAlim Akhtar } 1638ec4016ffSMarek Szyprowski CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", 1639ec4016ffSMarek Szyprowski exynos5420_clk_init); 16406520e968SAlim Akhtar 16416520e968SAlim Akhtar static void __init exynos5800_clk_init(struct device_node *np) 16426520e968SAlim Akhtar { 16436520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5800); 16446520e968SAlim Akhtar } 1645ec4016ffSMarek Szyprowski CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", 1646ec4016ffSMarek Szyprowski exynos5800_clk_init); 1647