11609027fSChander Kashyap /* 21609027fSChander Kashyap * Copyright (c) 2013 Samsung Electronics Co., Ltd. 31609027fSChander Kashyap * Authors: Thomas Abraham <thomas.ab@samsung.com> 41609027fSChander Kashyap * Chander Kashyap <k.chander@samsung.com> 51609027fSChander Kashyap * 61609027fSChander Kashyap * This program is free software; you can redistribute it and/or modify 71609027fSChander Kashyap * it under the terms of the GNU General Public License version 2 as 81609027fSChander Kashyap * published by the Free Software Foundation. 91609027fSChander Kashyap * 101609027fSChander Kashyap * Common Clock Framework support for Exynos5420 SoC. 111609027fSChander Kashyap */ 121609027fSChander Kashyap 13cba9d2faSAndrzej Hajda #include <dt-bindings/clock/exynos5420.h> 141609027fSChander Kashyap #include <linux/clk.h> 151609027fSChander Kashyap #include <linux/clkdev.h> 161609027fSChander Kashyap #include <linux/clk-provider.h> 171609027fSChander Kashyap #include <linux/of.h> 181609027fSChander Kashyap #include <linux/of_address.h> 19388c7885STomasz Figa #include <linux/syscore_ops.h> 201609027fSChander Kashyap 211609027fSChander Kashyap #include "clk.h" 221609027fSChander Kashyap 23c898c6b7SYadwinder Singh Brar #define APLL_LOCK 0x0 24c898c6b7SYadwinder Singh Brar #define APLL_CON0 0x100 251609027fSChander Kashyap #define SRC_CPU 0x200 261609027fSChander Kashyap #define DIV_CPU0 0x500 271609027fSChander Kashyap #define DIV_CPU1 0x504 281609027fSChander Kashyap #define GATE_BUS_CPU 0x700 291609027fSChander Kashyap #define GATE_SCLK_CPU 0x800 305b73721bSNaveen Krishna Chatradhi #define GATE_IP_G2D 0x8800 31c898c6b7SYadwinder Singh Brar #define CPLL_LOCK 0x10020 32c898c6b7SYadwinder Singh Brar #define DPLL_LOCK 0x10030 33c898c6b7SYadwinder Singh Brar #define EPLL_LOCK 0x10040 34c898c6b7SYadwinder Singh Brar #define RPLL_LOCK 0x10050 35c898c6b7SYadwinder Singh Brar #define IPLL_LOCK 0x10060 36c898c6b7SYadwinder Singh Brar #define SPLL_LOCK 0x10070 3753cb6342SSachin Kamat #define VPLL_LOCK 0x10080 38c898c6b7SYadwinder Singh Brar #define MPLL_LOCK 0x10090 39c898c6b7SYadwinder Singh Brar #define CPLL_CON0 0x10120 40c898c6b7SYadwinder Singh Brar #define DPLL_CON0 0x10128 41c898c6b7SYadwinder Singh Brar #define EPLL_CON0 0x10130 42c898c6b7SYadwinder Singh Brar #define RPLL_CON0 0x10140 43c898c6b7SYadwinder Singh Brar #define IPLL_CON0 0x10150 44c898c6b7SYadwinder Singh Brar #define SPLL_CON0 0x10160 45c898c6b7SYadwinder Singh Brar #define VPLL_CON0 0x10170 46c898c6b7SYadwinder Singh Brar #define MPLL_CON0 0x10180 471609027fSChander Kashyap #define SRC_TOP0 0x10200 481609027fSChander Kashyap #define SRC_TOP1 0x10204 491609027fSChander Kashyap #define SRC_TOP2 0x10208 501609027fSChander Kashyap #define SRC_TOP3 0x1020c 511609027fSChander Kashyap #define SRC_TOP4 0x10210 521609027fSChander Kashyap #define SRC_TOP5 0x10214 531609027fSChander Kashyap #define SRC_TOP6 0x10218 541609027fSChander Kashyap #define SRC_TOP7 0x1021c 551609027fSChander Kashyap #define SRC_DISP10 0x1022c 561609027fSChander Kashyap #define SRC_MAU 0x10240 571609027fSChander Kashyap #define SRC_FSYS 0x10244 581609027fSChander Kashyap #define SRC_PERIC0 0x10250 591609027fSChander Kashyap #define SRC_PERIC1 0x10254 601609027fSChander Kashyap #define SRC_TOP10 0x10280 611609027fSChander Kashyap #define SRC_TOP11 0x10284 621609027fSChander Kashyap #define SRC_TOP12 0x10288 631609027fSChander Kashyap #define SRC_MASK_DISP10 0x1032c 641609027fSChander Kashyap #define SRC_MASK_FSYS 0x10340 651609027fSChander Kashyap #define SRC_MASK_PERIC0 0x10350 661609027fSChander Kashyap #define SRC_MASK_PERIC1 0x10354 671609027fSChander Kashyap #define DIV_TOP0 0x10500 681609027fSChander Kashyap #define DIV_TOP1 0x10504 691609027fSChander Kashyap #define DIV_TOP2 0x10508 701609027fSChander Kashyap #define DIV_DISP10 0x1052c 711609027fSChander Kashyap #define DIV_MAU 0x10544 721609027fSChander Kashyap #define DIV_FSYS0 0x10548 731609027fSChander Kashyap #define DIV_FSYS1 0x1054c 741609027fSChander Kashyap #define DIV_FSYS2 0x10550 751609027fSChander Kashyap #define DIV_PERIC0 0x10558 761609027fSChander Kashyap #define DIV_PERIC1 0x1055c 771609027fSChander Kashyap #define DIV_PERIC2 0x10560 781609027fSChander Kashyap #define DIV_PERIC3 0x10564 791609027fSChander Kashyap #define DIV_PERIC4 0x10568 801609027fSChander Kashyap #define GATE_BUS_TOP 0x10700 811609027fSChander Kashyap #define GATE_BUS_FSYS0 0x10740 821609027fSChander Kashyap #define GATE_BUS_PERIC 0x10750 831609027fSChander Kashyap #define GATE_BUS_PERIC1 0x10754 841609027fSChander Kashyap #define GATE_BUS_PERIS0 0x10760 851609027fSChander Kashyap #define GATE_BUS_PERIS1 0x10764 861609027fSChander Kashyap #define GATE_IP_GSCL0 0x10910 871609027fSChander Kashyap #define GATE_IP_GSCL1 0x10920 881609027fSChander Kashyap #define GATE_IP_MFC 0x1092c 891609027fSChander Kashyap #define GATE_IP_DISP1 0x10928 901609027fSChander Kashyap #define GATE_IP_G3D 0x10930 911609027fSChander Kashyap #define GATE_IP_GEN 0x10934 921609027fSChander Kashyap #define GATE_IP_MSCL 0x10970 931609027fSChander Kashyap #define GATE_TOP_SCLK_GSCL 0x10820 941609027fSChander Kashyap #define GATE_TOP_SCLK_DISP1 0x10828 951609027fSChander Kashyap #define GATE_TOP_SCLK_MAU 0x1083c 961609027fSChander Kashyap #define GATE_TOP_SCLK_FSYS 0x10840 971609027fSChander Kashyap #define GATE_TOP_SCLK_PERIC 0x10850 98c898c6b7SYadwinder Singh Brar #define BPLL_LOCK 0x20010 99c898c6b7SYadwinder Singh Brar #define BPLL_CON0 0x20110 1001609027fSChander Kashyap #define SRC_CDREX 0x20200 101c898c6b7SYadwinder Singh Brar #define KPLL_LOCK 0x28000 102c898c6b7SYadwinder Singh Brar #define KPLL_CON0 0x28100 1031609027fSChander Kashyap #define SRC_KFC 0x28200 1041609027fSChander Kashyap #define DIV_KFC0 0x28500 1051609027fSChander Kashyap 106c898c6b7SYadwinder Singh Brar /* list of PLLs */ 107c898c6b7SYadwinder Singh Brar enum exynos5420_plls { 108c898c6b7SYadwinder Singh Brar apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 109c898c6b7SYadwinder Singh Brar bpll, kpll, 110c898c6b7SYadwinder Singh Brar nr_plls /* number of PLLs */ 111c898c6b7SYadwinder Singh Brar }; 112c898c6b7SYadwinder Singh Brar 113388c7885STomasz Figa static void __iomem *reg_base; 114388c7885STomasz Figa 115388c7885STomasz Figa #ifdef CONFIG_PM_SLEEP 116388c7885STomasz Figa static struct samsung_clk_reg_dump *exynos5420_save; 117388c7885STomasz Figa 1181609027fSChander Kashyap /* 1191609027fSChander Kashyap * list of controller registers to be saved and restored during a 1201609027fSChander Kashyap * suspend/resume cycle. 1211609027fSChander Kashyap */ 122202e5ae9SSachin Kamat static unsigned long exynos5420_clk_regs[] __initdata = { 1231609027fSChander Kashyap SRC_CPU, 1241609027fSChander Kashyap DIV_CPU0, 1251609027fSChander Kashyap DIV_CPU1, 1261609027fSChander Kashyap GATE_BUS_CPU, 1271609027fSChander Kashyap GATE_SCLK_CPU, 1281609027fSChander Kashyap SRC_TOP0, 1291609027fSChander Kashyap SRC_TOP1, 1301609027fSChander Kashyap SRC_TOP2, 1311609027fSChander Kashyap SRC_TOP3, 1321609027fSChander Kashyap SRC_TOP4, 1331609027fSChander Kashyap SRC_TOP5, 1341609027fSChander Kashyap SRC_TOP6, 1351609027fSChander Kashyap SRC_TOP7, 1361609027fSChander Kashyap SRC_DISP10, 1371609027fSChander Kashyap SRC_MAU, 1381609027fSChander Kashyap SRC_FSYS, 1391609027fSChander Kashyap SRC_PERIC0, 1401609027fSChander Kashyap SRC_PERIC1, 1411609027fSChander Kashyap SRC_TOP10, 1421609027fSChander Kashyap SRC_TOP11, 1431609027fSChander Kashyap SRC_TOP12, 1441609027fSChander Kashyap SRC_MASK_DISP10, 1451609027fSChander Kashyap SRC_MASK_FSYS, 1461609027fSChander Kashyap SRC_MASK_PERIC0, 1471609027fSChander Kashyap SRC_MASK_PERIC1, 1481609027fSChander Kashyap DIV_TOP0, 1491609027fSChander Kashyap DIV_TOP1, 1501609027fSChander Kashyap DIV_TOP2, 1511609027fSChander Kashyap DIV_DISP10, 1521609027fSChander Kashyap DIV_MAU, 1531609027fSChander Kashyap DIV_FSYS0, 1541609027fSChander Kashyap DIV_FSYS1, 1551609027fSChander Kashyap DIV_FSYS2, 1561609027fSChander Kashyap DIV_PERIC0, 1571609027fSChander Kashyap DIV_PERIC1, 1581609027fSChander Kashyap DIV_PERIC2, 1591609027fSChander Kashyap DIV_PERIC3, 1601609027fSChander Kashyap DIV_PERIC4, 1611609027fSChander Kashyap GATE_BUS_TOP, 1621609027fSChander Kashyap GATE_BUS_FSYS0, 1631609027fSChander Kashyap GATE_BUS_PERIC, 1641609027fSChander Kashyap GATE_BUS_PERIC1, 1651609027fSChander Kashyap GATE_BUS_PERIS0, 1661609027fSChander Kashyap GATE_BUS_PERIS1, 1671609027fSChander Kashyap GATE_IP_GSCL0, 1681609027fSChander Kashyap GATE_IP_GSCL1, 1691609027fSChander Kashyap GATE_IP_MFC, 1701609027fSChander Kashyap GATE_IP_DISP1, 1711609027fSChander Kashyap GATE_IP_G3D, 1721609027fSChander Kashyap GATE_IP_GEN, 1731609027fSChander Kashyap GATE_IP_MSCL, 1741609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 1751609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 1761609027fSChander Kashyap GATE_TOP_SCLK_MAU, 1771609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1781609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1791609027fSChander Kashyap SRC_CDREX, 1801609027fSChander Kashyap SRC_KFC, 1811609027fSChander Kashyap DIV_KFC0, 1821609027fSChander Kashyap }; 1831609027fSChander Kashyap 184388c7885STomasz Figa static int exynos5420_clk_suspend(void) 185388c7885STomasz Figa { 186388c7885STomasz Figa samsung_clk_save(reg_base, exynos5420_save, 187388c7885STomasz Figa ARRAY_SIZE(exynos5420_clk_regs)); 188388c7885STomasz Figa 189388c7885STomasz Figa return 0; 190388c7885STomasz Figa } 191388c7885STomasz Figa 192388c7885STomasz Figa static void exynos5420_clk_resume(void) 193388c7885STomasz Figa { 194388c7885STomasz Figa samsung_clk_restore(reg_base, exynos5420_save, 195388c7885STomasz Figa ARRAY_SIZE(exynos5420_clk_regs)); 196388c7885STomasz Figa } 197388c7885STomasz Figa 198388c7885STomasz Figa static struct syscore_ops exynos5420_clk_syscore_ops = { 199388c7885STomasz Figa .suspend = exynos5420_clk_suspend, 200388c7885STomasz Figa .resume = exynos5420_clk_resume, 201388c7885STomasz Figa }; 202388c7885STomasz Figa 203388c7885STomasz Figa static void exynos5420_clk_sleep_init(void) 204388c7885STomasz Figa { 205388c7885STomasz Figa exynos5420_save = samsung_clk_alloc_reg_dump(exynos5420_clk_regs, 206388c7885STomasz Figa ARRAY_SIZE(exynos5420_clk_regs)); 207388c7885STomasz Figa if (!exynos5420_save) { 208388c7885STomasz Figa pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 209388c7885STomasz Figa __func__); 210388c7885STomasz Figa return; 211388c7885STomasz Figa } 212388c7885STomasz Figa 213388c7885STomasz Figa register_syscore_ops(&exynos5420_clk_syscore_ops); 214388c7885STomasz Figa } 215388c7885STomasz Figa #else 216388c7885STomasz Figa static void exynos5420_clk_sleep_init(void) {} 217388c7885STomasz Figa #endif 218388c7885STomasz Figa 2191609027fSChander Kashyap /* list of all parent clocks */ 220dbd713bbSShaik Ameer Basha PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 221dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 222dbd713bbSShaik Ameer Basha PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 223dbd713bbSShaik Ameer Basha PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 224dbd713bbSShaik Ameer Basha PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 225dbd713bbSShaik Ameer Basha PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 226dbd713bbSShaik Ameer Basha PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 227dbd713bbSShaik Ameer Basha PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 228dbd713bbSShaik Ameer Basha PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 229dbd713bbSShaik Ameer Basha PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 230dbd713bbSShaik Ameer Basha PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 231dbd713bbSShaik Ameer Basha PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 232dbd713bbSShaik Ameer Basha PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 233dbd713bbSShaik Ameer Basha PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 234dbd713bbSShaik Ameer Basha PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 2351609027fSChander Kashyap 236dbd713bbSShaik Ameer Basha PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 237dbd713bbSShaik Ameer Basha "mout_sclk_mpll"}; 238dbd713bbSShaik Ameer Basha PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 239dbd713bbSShaik Ameer Basha "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 240dbd713bbSShaik Ameer Basha "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 241dbd713bbSShaik Ameer Basha PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 242dbd713bbSShaik Ameer Basha PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 243dbd713bbSShaik Ameer Basha PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 2441609027fSChander Kashyap 245dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 246dbd713bbSShaik Ameer Basha PNAME(mout_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" }; 2471609027fSChander Kashyap 248dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 249dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 2501609027fSChander Kashyap 251dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 252dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 2531609027fSChander Kashyap 254dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 255dbd713bbSShaik Ameer Basha PNAME(mout_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 2561609027fSChander Kashyap 257dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 258dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 2591609027fSChander Kashyap 260dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 261dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 2621609027fSChander Kashyap 263dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 264dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 2651609027fSChander Kashyap 266dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 267dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 2681609027fSChander Kashyap 269dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 270dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 2711609027fSChander Kashyap 272dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 273dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 2741609027fSChander Kashyap 275dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 276dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 2771609027fSChander Kashyap 278dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 279dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 2801609027fSChander Kashyap 281dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 282dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 2831609027fSChander Kashyap 284dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 285dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 2861609027fSChander Kashyap 287dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 288dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 2891609027fSChander Kashyap 290dbd713bbSShaik Ameer Basha PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 291dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 292dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 293dbd713bbSShaik Ameer Basha PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 294dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 295dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 296dbd713bbSShaik Ameer Basha PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 297dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 298dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 299dbd713bbSShaik Ameer Basha PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 300dbd713bbSShaik Ameer Basha "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 301dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 302dbd713bbSShaik Ameer Basha PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 303dbd713bbSShaik Ameer Basha PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 304dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 305dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 3061609027fSChander Kashyap 3071609027fSChander Kashyap /* fixed rate clocks generated outside the soc */ 308c7306229SSachin Kamat static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 309cba9d2faSAndrzej Hajda FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 3101609027fSChander Kashyap }; 3111609027fSChander Kashyap 3121609027fSChander Kashyap /* fixed rate clocks generated inside the soc */ 313c7306229SSachin Kamat static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { 314cba9d2faSAndrzej Hajda FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 315cba9d2faSAndrzej Hajda FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 316cba9d2faSAndrzej Hajda FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 317cba9d2faSAndrzej Hajda FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), 318cba9d2faSAndrzej Hajda FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 3191609027fSChander Kashyap }; 3201609027fSChander Kashyap 321c7306229SSachin Kamat static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 322cba9d2faSAndrzej Hajda FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0), 3231609027fSChander Kashyap }; 3241609027fSChander Kashyap 325c7306229SSachin Kamat static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 326dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 327dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 328dbd713bbSShaik Ameer Basha MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), 329dbd713bbSShaik Ameer Basha MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 330dbd713bbSShaik Ameer Basha MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1), 331dbd713bbSShaik Ameer Basha MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 3321609027fSChander Kashyap 333dbd713bbSShaik Ameer Basha MUX(0, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 3341609027fSChander Kashyap 335dbd713bbSShaik Ameer Basha MUX_A(0, "mout_aclk400_mscl", mout_group1_p, 3361609027fSChander Kashyap SRC_TOP0, 4, 2, "aclk400_mscl"), 337dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 338dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 339dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 3401609027fSChander Kashyap 341dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 342dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 343dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 344dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 345dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 3461609027fSChander Kashyap 347dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 348dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 349dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 350dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 351dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 352dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 3531609027fSChander Kashyap 354dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 3551609027fSChander Kashyap SRC_TOP3, 4, 1), 356dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_disp1", mout_aclk200_disp1_p, SRC_TOP3, 8, 1), 357dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 3581609027fSChander Kashyap SRC_TOP3, 12, 1), 359dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 3601609027fSChander Kashyap SRC_TOP3, 28, 1), 3611609027fSChander Kashyap 362dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 3631609027fSChander Kashyap SRC_TOP4, 0, 1), 364dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66_peric", mout_aclk66_peric_p, SRC_TOP4, 8, 1), 365dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 366dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 367dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1), 3681609027fSChander Kashyap 369dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66_psgen", mout_aclk66_peric_p, SRC_TOP5, 4, 1), 370dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, SRC_TOP5, 371dbd713bbSShaik Ameer Basha 8, 1), 372dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, SRC_TOP5, 373dbd713bbSShaik Ameer Basha 12, 1), 374dbd713bbSShaik Ameer Basha MUX_A(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 3751609027fSChander Kashyap SRC_TOP5, 16, 1, "aclkg3d"), 376dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 3771609027fSChander Kashyap SRC_TOP5, 20, 1), 378dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p, 3791609027fSChander Kashyap SRC_TOP5, 24, 1), 380dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p, 3811609027fSChander Kashyap SRC_TOP5, 28, 1), 3821609027fSChander Kashyap 383dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 384dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 385dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 386dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 387dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 388dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1), 389dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 390dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 3911609027fSChander Kashyap 392dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 393dbd713bbSShaik Ameer Basha SRC_TOP10, 4, 1), 394dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1), 395dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 3961609027fSChander Kashyap SRC_TOP10, 12, 1), 397dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 398dbd713bbSShaik Ameer Basha SRC_TOP10, 28, 1), 399dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 4001609027fSChander Kashyap SRC_TOP11, 0, 1), 401dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 402dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 403dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 404dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1), 4051609027fSChander Kashyap 406dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 407dbd713bbSShaik Ameer Basha SRC_TOP12, 8, 1), 408dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 409dbd713bbSShaik Ameer Basha SRC_TOP12, 12, 1), 410dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 411dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 412dbd713bbSShaik Ameer Basha SRC_TOP12, 20, 1), 413dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p, 4141609027fSChander Kashyap SRC_TOP12, 24, 1), 415dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p, 416dbd713bbSShaik Ameer Basha SRC_TOP12, 28, 1), 4171609027fSChander Kashyap 4181609027fSChander Kashyap /* DISP1 Block */ 419dbd713bbSShaik Ameer Basha MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 420dbd713bbSShaik Ameer Basha MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 421dbd713bbSShaik Ameer Basha MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 422dbd713bbSShaik Ameer Basha MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 423dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 4241609027fSChander Kashyap 4251609027fSChander Kashyap /* MAU Block */ 426dbd713bbSShaik Ameer Basha MUX(0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 4271609027fSChander Kashyap 4281609027fSChander Kashyap /* FSYS Block */ 429dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 430dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 431dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 432dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 433dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 434dbd713bbSShaik Ameer Basha MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 4351609027fSChander Kashyap 4361609027fSChander Kashyap /* PERIC Block */ 437dbd713bbSShaik Ameer Basha MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 438dbd713bbSShaik Ameer Basha MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 439dbd713bbSShaik Ameer Basha MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 440dbd713bbSShaik Ameer Basha MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 441dbd713bbSShaik Ameer Basha MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 442dbd713bbSShaik Ameer Basha MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 443dbd713bbSShaik Ameer Basha MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 444dbd713bbSShaik Ameer Basha MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 445dbd713bbSShaik Ameer Basha MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 446dbd713bbSShaik Ameer Basha MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 447dbd713bbSShaik Ameer Basha MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 448dbd713bbSShaik Ameer Basha MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 4491609027fSChander Kashyap }; 4501609027fSChander Kashyap 451c7306229SSachin Kamat static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 452cba9d2faSAndrzej Hajda DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 453cba9d2faSAndrzej Hajda DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 454cba9d2faSAndrzej Hajda DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 455dbd713bbSShaik Ameer Basha DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 456cba9d2faSAndrzej Hajda DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 4571609027fSChander Kashyap 458cba9d2faSAndrzej Hajda DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 459cba9d2faSAndrzej Hajda DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 460cba9d2faSAndrzej Hajda DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 461cba9d2faSAndrzej Hajda DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 462cba9d2faSAndrzej Hajda DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 4631609027fSChander Kashyap 464cba9d2faSAndrzej Hajda DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 4651609027fSChander Kashyap DIV_TOP1, 0, 3), 466cba9d2faSAndrzej Hajda DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 467cba9d2faSAndrzej Hajda DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 468cba9d2faSAndrzej Hajda DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 469cba9d2faSAndrzej Hajda DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 4701609027fSChander Kashyap 471cba9d2faSAndrzej Hajda DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), 472cba9d2faSAndrzej Hajda DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 473cba9d2faSAndrzej Hajda DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 474cba9d2faSAndrzej Hajda DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 475cba9d2faSAndrzej Hajda DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1", 4761609027fSChander Kashyap DIV_TOP2, 24, 3, "aclk300_disp1"), 477cba9d2faSAndrzej Hajda DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 4781609027fSChander Kashyap 4791609027fSChander Kashyap /* DISP1 Block */ 480cba9d2faSAndrzej Hajda DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), 481cba9d2faSAndrzej Hajda DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 482cba9d2faSAndrzej Hajda DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 483cba9d2faSAndrzej Hajda DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 4841609027fSChander Kashyap 4851609027fSChander Kashyap /* Audio Block */ 486cba9d2faSAndrzej Hajda DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 487cba9d2faSAndrzej Hajda DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 4881609027fSChander Kashyap 4891609027fSChander Kashyap /* USB3.0 */ 490cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 491cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 492cba9d2faSAndrzej Hajda DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 493cba9d2faSAndrzej Hajda DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 4941609027fSChander Kashyap 4951609027fSChander Kashyap /* MMC */ 496cba9d2faSAndrzej Hajda DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 497cba9d2faSAndrzej Hajda DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 498cba9d2faSAndrzej Hajda DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 4991609027fSChander Kashyap 500cba9d2faSAndrzej Hajda DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 5011609027fSChander Kashyap 5021609027fSChander Kashyap /* UART and PWM */ 503cba9d2faSAndrzej Hajda DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 504cba9d2faSAndrzej Hajda DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 505cba9d2faSAndrzej Hajda DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 506cba9d2faSAndrzej Hajda DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 507cba9d2faSAndrzej Hajda DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 5081609027fSChander Kashyap 5091609027fSChander Kashyap /* SPI */ 510cba9d2faSAndrzej Hajda DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 511cba9d2faSAndrzej Hajda DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 512cba9d2faSAndrzej Hajda DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 5131609027fSChander Kashyap 5141609027fSChander Kashyap /* PCM */ 515cba9d2faSAndrzej Hajda DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 516cba9d2faSAndrzej Hajda DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 5171609027fSChander Kashyap 5181609027fSChander Kashyap /* Audio - I2S */ 519cba9d2faSAndrzej Hajda DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 520cba9d2faSAndrzej Hajda DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 521cba9d2faSAndrzej Hajda DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 522cba9d2faSAndrzej Hajda DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 523cba9d2faSAndrzej Hajda DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 5241609027fSChander Kashyap 5251609027fSChander Kashyap /* SPI Pre-Ratio */ 526cba9d2faSAndrzej Hajda DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), 527cba9d2faSAndrzej Hajda DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), 528cba9d2faSAndrzej Hajda DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), 5291609027fSChander Kashyap }; 5301609027fSChander Kashyap 531c7306229SSachin Kamat static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 5325b73721bSNaveen Krishna Chatradhi /* G2D */ 5335b73721bSNaveen Krishna Chatradhi GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 5345b73721bSNaveen Krishna Chatradhi 5351609027fSChander Kashyap /* TODO: Re-verify the CG bits for all the gate clocks */ 536cba9d2faSAndrzej Hajda GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, 537cba9d2faSAndrzej Hajda "mct"), 5381609027fSChander Kashyap 5391609027fSChander Kashyap GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 5401609027fSChander Kashyap GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 5411609027fSChander Kashyap GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 5421609027fSChander Kashyap GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 5431609027fSChander Kashyap 5441609027fSChander Kashyap GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 5451609027fSChander Kashyap GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 5461609027fSChander Kashyap GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 5471609027fSChander Kashyap GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), 5481609027fSChander Kashyap GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 5491609027fSChander Kashyap GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 5501609027fSChander Kashyap GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 5511609027fSChander Kashyap GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), 5521609027fSChander Kashyap GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 5531609027fSChander Kashyap GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 5541609027fSChander Kashyap GATE(0, "pclk66_gpio", "mout_sw_aclk66", 5551609027fSChander Kashyap GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 5561609027fSChander Kashyap GATE(0, "aclk66_psgen", "mout_aclk66_psgen", 5571609027fSChander Kashyap GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 5581609027fSChander Kashyap GATE(0, "aclk66_peric", "mout_aclk66_peric", 5591609027fSChander Kashyap GATE_BUS_TOP, 11, 0, 0), 5601609027fSChander Kashyap GATE(0, "aclk166", "mout_user_aclk166", 5611609027fSChander Kashyap GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 5621609027fSChander Kashyap GATE(0, "aclk333", "mout_aclk333", 5631609027fSChander Kashyap GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 5641609027fSChander Kashyap 5651609027fSChander Kashyap /* sclk */ 566cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 5671609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 568cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 5691609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 570cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 5711609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 572cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 5731609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 574cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0", 5751609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 576cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1", 5771609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 578cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2", 5791609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 580cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 5811609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 582cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 5831609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 584cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 5851609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 586cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 5871609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 588cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 5891609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 590cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 5911609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 5921609027fSChander Kashyap 593cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 5941609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 595cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 5961609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 597cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 5981609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 599cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 6001609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 601cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 6021609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 603cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 6041609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 605cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 6061609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 6071609027fSChander Kashyap 608cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro", 6091609027fSChander Kashyap SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 6101609027fSChander Kashyap 611cba9d2faSAndrzej Hajda GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl", 6121609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0), 613cba9d2faSAndrzej Hajda GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl", 6141609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0), 6151609027fSChander Kashyap 6161609027fSChander Kashyap /* Display */ 617cba9d2faSAndrzej Hajda GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 6181609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 619cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 6201609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 621cba9d2faSAndrzej Hajda GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 6221609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), 623cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 6241609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 625cba9d2faSAndrzej Hajda GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 6261609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 6271609027fSChander Kashyap 6281609027fSChander Kashyap /* Maudio Block */ 629cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 6301609027fSChander Kashyap GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 631cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 6321609027fSChander Kashyap GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 6331609027fSChander Kashyap /* FSYS */ 634cba9d2faSAndrzej Hajda GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 635cba9d2faSAndrzej Hajda GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 636cba9d2faSAndrzej Hajda GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 637cba9d2faSAndrzej Hajda GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 638cba9d2faSAndrzej Hajda GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), 639cba9d2faSAndrzej Hajda GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), 640cba9d2faSAndrzej Hajda GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), 641cba9d2faSAndrzej Hajda GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), 642cba9d2faSAndrzej Hajda GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 6431609027fSChander Kashyap GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), 644cba9d2faSAndrzej Hajda GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), 645cba9d2faSAndrzej Hajda GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), 646cba9d2faSAndrzej Hajda GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), 6471609027fSChander Kashyap 6481609027fSChander Kashyap /* UART */ 649cba9d2faSAndrzej Hajda GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0), 650cba9d2faSAndrzej Hajda GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0), 651cba9d2faSAndrzej Hajda GATE_A(CLK_UART2, "uart2", "aclk66_peric", 6521609027fSChander Kashyap GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"), 653cba9d2faSAndrzej Hajda GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0), 6541609027fSChander Kashyap /* I2C */ 655cba9d2faSAndrzej Hajda GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0), 656cba9d2faSAndrzej Hajda GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0), 657cba9d2faSAndrzej Hajda GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0), 658cba9d2faSAndrzej Hajda GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0), 659cba9d2faSAndrzej Hajda GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0), 660cba9d2faSAndrzej Hajda GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0), 661cba9d2faSAndrzej Hajda GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0), 662cba9d2faSAndrzej Hajda GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0), 663cba9d2faSAndrzej Hajda GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 664cba9d2faSAndrzej Hajda 0), 665cba9d2faSAndrzej Hajda GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0), 6661609027fSChander Kashyap /* SPI */ 667cba9d2faSAndrzej Hajda GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0), 668cba9d2faSAndrzej Hajda GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0), 669cba9d2faSAndrzej Hajda GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0), 670cba9d2faSAndrzej Hajda GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0), 6711609027fSChander Kashyap /* I2S */ 672cba9d2faSAndrzej Hajda GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0), 673cba9d2faSAndrzej Hajda GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0), 6741609027fSChander Kashyap /* PCM */ 675cba9d2faSAndrzej Hajda GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0), 676cba9d2faSAndrzej Hajda GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0), 6771609027fSChander Kashyap /* PWM */ 678cba9d2faSAndrzej Hajda GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0), 6791609027fSChander Kashyap /* SPDIF */ 680cba9d2faSAndrzej Hajda GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0), 6811609027fSChander Kashyap 682cba9d2faSAndrzej Hajda GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0), 683cba9d2faSAndrzej Hajda GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0), 684cba9d2faSAndrzej Hajda GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0), 6851609027fSChander Kashyap 686cba9d2faSAndrzej Hajda GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 6871609027fSChander Kashyap GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0), 688cba9d2faSAndrzej Hajda GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 6891609027fSChander Kashyap GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0), 690cba9d2faSAndrzej Hajda GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0), 691cba9d2faSAndrzej Hajda GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0), 692cba9d2faSAndrzej Hajda GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0), 693cba9d2faSAndrzej Hajda GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0), 694cba9d2faSAndrzej Hajda GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0), 695cba9d2faSAndrzej Hajda GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0), 696cba9d2faSAndrzej Hajda GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0), 697cba9d2faSAndrzej Hajda GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0), 698cba9d2faSAndrzej Hajda GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0), 699cba9d2faSAndrzej Hajda GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0), 7001609027fSChander Kashyap 701cba9d2faSAndrzej Hajda GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 702cba9d2faSAndrzej Hajda 0), 703cba9d2faSAndrzej Hajda GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 704cba9d2faSAndrzej Hajda GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0), 705cba9d2faSAndrzej Hajda GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0), 706cba9d2faSAndrzej Hajda GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0), 707cba9d2faSAndrzej Hajda GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0), 7081609027fSChander Kashyap 709cba9d2faSAndrzej Hajda GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 710cba9d2faSAndrzej Hajda GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 711cba9d2faSAndrzej Hajda GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0), 7121609027fSChander Kashyap 713cba9d2faSAndrzej Hajda GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 714cba9d2faSAndrzej Hajda 0), 715cba9d2faSAndrzej Hajda GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl", 7161609027fSChander Kashyap GATE_IP_GSCL1, 3, 0, 0), 717cba9d2faSAndrzej Hajda GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl", 7181609027fSChander Kashyap GATE_IP_GSCL1, 4, 0, 0), 719cba9d2faSAndrzej Hajda GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 720cba9d2faSAndrzej Hajda 0), 721cba9d2faSAndrzej Hajda GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 722cba9d2faSAndrzej Hajda 0), 723cba9d2faSAndrzej Hajda GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0), 724cba9d2faSAndrzej Hajda GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0), 725cba9d2faSAndrzej Hajda GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl", 7261609027fSChander Kashyap GATE_IP_GSCL1, 16, 0, 0), 727cba9d2faSAndrzej Hajda GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 7281609027fSChander Kashyap GATE_IP_GSCL1, 17, 0, 0), 7291609027fSChander Kashyap 730cba9d2faSAndrzej Hajda GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 731cba9d2faSAndrzej Hajda GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 732cba9d2faSAndrzej Hajda GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 733cba9d2faSAndrzej Hajda GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0), 734cba9d2faSAndrzej Hajda GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 735cba9d2faSAndrzej Hajda GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 736cba9d2faSAndrzej Hajda 0), 7371609027fSChander Kashyap 738cba9d2faSAndrzej Hajda GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 739cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 740cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 7411609027fSChander Kashyap 742cba9d2faSAndrzej Hajda GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0), 7431609027fSChander Kashyap 744cba9d2faSAndrzej Hajda GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 745cba9d2faSAndrzej Hajda GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 746cba9d2faSAndrzej Hajda GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 747cba9d2faSAndrzej Hajda GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), 748cba9d2faSAndrzej Hajda GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), 749cba9d2faSAndrzej Hajda GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0), 750cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0), 7511609027fSChander Kashyap 752cba9d2faSAndrzej Hajda GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 753cba9d2faSAndrzej Hajda GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 754cba9d2faSAndrzej Hajda GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 755cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 756cba9d2faSAndrzej Hajda 0), 757cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 758cba9d2faSAndrzej Hajda 0), 759cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 760cba9d2faSAndrzej Hajda 0), 761cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 762cba9d2faSAndrzej Hajda 0), 7631609027fSChander Kashyap }; 7641609027fSChander Kashyap 765202e5ae9SSachin Kamat static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { 766cba9d2faSAndrzej Hajda [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 7673ff6e0d8SYadwinder Singh Brar APLL_CON0, NULL), 768cba9d2faSAndrzej Hajda [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 769cdf64eeeSChander Kashyap CPLL_CON0, NULL), 770cba9d2faSAndrzej Hajda [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 7713ff6e0d8SYadwinder Singh Brar DPLL_CON0, NULL), 772cba9d2faSAndrzej Hajda [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 7733ff6e0d8SYadwinder Singh Brar EPLL_CON0, NULL), 774cba9d2faSAndrzej Hajda [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 7753ff6e0d8SYadwinder Singh Brar RPLL_CON0, NULL), 776cba9d2faSAndrzej Hajda [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 7773ff6e0d8SYadwinder Singh Brar IPLL_CON0, NULL), 778cba9d2faSAndrzej Hajda [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 7793ff6e0d8SYadwinder Singh Brar SPLL_CON0, NULL), 780cba9d2faSAndrzej Hajda [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 7813ff6e0d8SYadwinder Singh Brar VPLL_CON0, NULL), 782cba9d2faSAndrzej Hajda [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 7833ff6e0d8SYadwinder Singh Brar MPLL_CON0, NULL), 784cba9d2faSAndrzej Hajda [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 7853ff6e0d8SYadwinder Singh Brar BPLL_CON0, NULL), 786cba9d2faSAndrzej Hajda [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 7873ff6e0d8SYadwinder Singh Brar KPLL_CON0, NULL), 788c898c6b7SYadwinder Singh Brar }; 789c898c6b7SYadwinder Singh Brar 790202e5ae9SSachin Kamat static struct of_device_id ext_clk_match[] __initdata = { 7911609027fSChander Kashyap { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 7921609027fSChander Kashyap { }, 7931609027fSChander Kashyap }; 7941609027fSChander Kashyap 7951609027fSChander Kashyap /* register exynos5420 clocks */ 796c7306229SSachin Kamat static void __init exynos5420_clk_init(struct device_node *np) 7971609027fSChander Kashyap { 798976face4SRahul Sharma struct samsung_clk_provider *ctx; 799976face4SRahul Sharma 8001609027fSChander Kashyap if (np) { 8011609027fSChander Kashyap reg_base = of_iomap(np, 0); 8021609027fSChander Kashyap if (!reg_base) 8031609027fSChander Kashyap panic("%s: failed to map registers\n", __func__); 8041609027fSChander Kashyap } else { 8051609027fSChander Kashyap panic("%s: unable to determine soc\n", __func__); 8061609027fSChander Kashyap } 8071609027fSChander Kashyap 808976face4SRahul Sharma ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 809976face4SRahul Sharma if (!ctx) 810976face4SRahul Sharma panic("%s: unable to allocate context.\n", __func__); 811976face4SRahul Sharma 812976face4SRahul Sharma samsung_clk_of_register_fixed_ext(ctx, exynos5420_fixed_rate_ext_clks, 8131609027fSChander Kashyap ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), 8141609027fSChander Kashyap ext_clk_match); 815976face4SRahul Sharma samsung_clk_register_pll(ctx, exynos5420_plls, 816976face4SRahul Sharma ARRAY_SIZE(exynos5420_plls), 817c898c6b7SYadwinder Singh Brar reg_base); 818976face4SRahul Sharma samsung_clk_register_fixed_rate(ctx, exynos5420_fixed_rate_clks, 8191609027fSChander Kashyap ARRAY_SIZE(exynos5420_fixed_rate_clks)); 820976face4SRahul Sharma samsung_clk_register_fixed_factor(ctx, exynos5420_fixed_factor_clks, 8211609027fSChander Kashyap ARRAY_SIZE(exynos5420_fixed_factor_clks)); 822976face4SRahul Sharma samsung_clk_register_mux(ctx, exynos5420_mux_clks, 8231609027fSChander Kashyap ARRAY_SIZE(exynos5420_mux_clks)); 824976face4SRahul Sharma samsung_clk_register_div(ctx, exynos5420_div_clks, 8251609027fSChander Kashyap ARRAY_SIZE(exynos5420_div_clks)); 826976face4SRahul Sharma samsung_clk_register_gate(ctx, exynos5420_gate_clks, 8271609027fSChander Kashyap ARRAY_SIZE(exynos5420_gate_clks)); 828388c7885STomasz Figa 829388c7885STomasz Figa exynos5420_clk_sleep_init(); 8301609027fSChander Kashyap } 8311609027fSChander Kashyap CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 832