1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 21609027fSChander Kashyap /* 31609027fSChander Kashyap * Copyright (c) 2013 Samsung Electronics Co., Ltd. 41609027fSChander Kashyap * Authors: Thomas Abraham <thomas.ab@samsung.com> 51609027fSChander Kashyap * Chander Kashyap <k.chander@samsung.com> 61609027fSChander Kashyap * 71609027fSChander Kashyap * Common Clock Framework support for Exynos5420 SoC. 81609027fSChander Kashyap */ 91609027fSChander Kashyap 10cba9d2faSAndrzej Hajda #include <dt-bindings/clock/exynos5420.h> 116f1ed07aSStephen Boyd #include <linux/slab.h> 121609027fSChander Kashyap #include <linux/clk-provider.h> 131609027fSChander Kashyap #include <linux/of.h> 141609027fSChander Kashyap #include <linux/of_address.h> 151609027fSChander Kashyap 161609027fSChander Kashyap #include "clk.h" 17bee4f87fSThomas Abraham #include "clk-cpu.h" 18ec4016ffSMarek Szyprowski #include "clk-exynos5-subcmu.h" 191609027fSChander Kashyap 20c898c6b7SYadwinder Singh Brar #define APLL_LOCK 0x0 21c898c6b7SYadwinder Singh Brar #define APLL_CON0 0x100 221609027fSChander Kashyap #define SRC_CPU 0x200 231609027fSChander Kashyap #define DIV_CPU0 0x500 241609027fSChander Kashyap #define DIV_CPU1 0x504 251609027fSChander Kashyap #define GATE_BUS_CPU 0x700 261609027fSChander Kashyap #define GATE_SCLK_CPU 0x800 2777342432SShaik Ameer Basha #define CLKOUT_CMU_CPU 0xa00 28e9d52956SVikas Sajjan #define SRC_MASK_CPERI 0x4300 295b73721bSNaveen Krishna Chatradhi #define GATE_IP_G2D 0x8800 30c898c6b7SYadwinder Singh Brar #define CPLL_LOCK 0x10020 31c898c6b7SYadwinder Singh Brar #define DPLL_LOCK 0x10030 32c898c6b7SYadwinder Singh Brar #define EPLL_LOCK 0x10040 33c898c6b7SYadwinder Singh Brar #define RPLL_LOCK 0x10050 34c898c6b7SYadwinder Singh Brar #define IPLL_LOCK 0x10060 35c898c6b7SYadwinder Singh Brar #define SPLL_LOCK 0x10070 3653cb6342SSachin Kamat #define VPLL_LOCK 0x10080 37c898c6b7SYadwinder Singh Brar #define MPLL_LOCK 0x10090 38c898c6b7SYadwinder Singh Brar #define CPLL_CON0 0x10120 39c898c6b7SYadwinder Singh Brar #define DPLL_CON0 0x10128 40c898c6b7SYadwinder Singh Brar #define EPLL_CON0 0x10130 4177342432SShaik Ameer Basha #define EPLL_CON1 0x10134 4277342432SShaik Ameer Basha #define EPLL_CON2 0x10138 43c898c6b7SYadwinder Singh Brar #define RPLL_CON0 0x10140 4477342432SShaik Ameer Basha #define RPLL_CON1 0x10144 4577342432SShaik Ameer Basha #define RPLL_CON2 0x10148 46c898c6b7SYadwinder Singh Brar #define IPLL_CON0 0x10150 47c898c6b7SYadwinder Singh Brar #define SPLL_CON0 0x10160 48c898c6b7SYadwinder Singh Brar #define VPLL_CON0 0x10170 49c898c6b7SYadwinder Singh Brar #define MPLL_CON0 0x10180 501609027fSChander Kashyap #define SRC_TOP0 0x10200 511609027fSChander Kashyap #define SRC_TOP1 0x10204 521609027fSChander Kashyap #define SRC_TOP2 0x10208 531609027fSChander Kashyap #define SRC_TOP3 0x1020c 541609027fSChander Kashyap #define SRC_TOP4 0x10210 551609027fSChander Kashyap #define SRC_TOP5 0x10214 561609027fSChander Kashyap #define SRC_TOP6 0x10218 571609027fSChander Kashyap #define SRC_TOP7 0x1021c 586520e968SAlim Akhtar #define SRC_TOP8 0x10220 /* 5800 specific */ 596520e968SAlim Akhtar #define SRC_TOP9 0x10224 /* 5800 specific */ 601609027fSChander Kashyap #define SRC_DISP10 0x1022c 611609027fSChander Kashyap #define SRC_MAU 0x10240 621609027fSChander Kashyap #define SRC_FSYS 0x10244 631609027fSChander Kashyap #define SRC_PERIC0 0x10250 641609027fSChander Kashyap #define SRC_PERIC1 0x10254 653a767b35SShaik Ameer Basha #define SRC_ISP 0x10270 666520e968SAlim Akhtar #define SRC_CAM 0x10274 /* 5800 specific */ 671609027fSChander Kashyap #define SRC_TOP10 0x10280 681609027fSChander Kashyap #define SRC_TOP11 0x10284 691609027fSChander Kashyap #define SRC_TOP12 0x10288 706520e968SAlim Akhtar #define SRC_TOP13 0x1028c /* 5800 specific */ 71e9d52956SVikas Sajjan #define SRC_MASK_TOP0 0x10300 72e9d52956SVikas Sajjan #define SRC_MASK_TOP1 0x10304 73424b673aSShaik Ameer Basha #define SRC_MASK_TOP2 0x10308 7431116a64SShaik Ameer Basha #define SRC_MASK_TOP7 0x1031c 751609027fSChander Kashyap #define SRC_MASK_DISP10 0x1032c 7631116a64SShaik Ameer Basha #define SRC_MASK_MAU 0x10334 771609027fSChander Kashyap #define SRC_MASK_FSYS 0x10340 781609027fSChander Kashyap #define SRC_MASK_PERIC0 0x10350 791609027fSChander Kashyap #define SRC_MASK_PERIC1 0x10354 80e9d52956SVikas Sajjan #define SRC_MASK_ISP 0x10370 811609027fSChander Kashyap #define DIV_TOP0 0x10500 821609027fSChander Kashyap #define DIV_TOP1 0x10504 831609027fSChander Kashyap #define DIV_TOP2 0x10508 846520e968SAlim Akhtar #define DIV_TOP8 0x10520 /* 5800 specific */ 856520e968SAlim Akhtar #define DIV_TOP9 0x10524 /* 5800 specific */ 861609027fSChander Kashyap #define DIV_DISP10 0x1052c 871609027fSChander Kashyap #define DIV_MAU 0x10544 881609027fSChander Kashyap #define DIV_FSYS0 0x10548 891609027fSChander Kashyap #define DIV_FSYS1 0x1054c 901609027fSChander Kashyap #define DIV_FSYS2 0x10550 911609027fSChander Kashyap #define DIV_PERIC0 0x10558 921609027fSChander Kashyap #define DIV_PERIC1 0x1055c 931609027fSChander Kashyap #define DIV_PERIC2 0x10560 941609027fSChander Kashyap #define DIV_PERIC3 0x10564 951609027fSChander Kashyap #define DIV_PERIC4 0x10568 966520e968SAlim Akhtar #define DIV_CAM 0x10574 /* 5800 specific */ 973a767b35SShaik Ameer Basha #define SCLK_DIV_ISP0 0x10580 983a767b35SShaik Ameer Basha #define SCLK_DIV_ISP1 0x10584 9902932381SShaik Ameer Basha #define DIV2_RATIO0 0x10590 1001d87db4dSShaik Ameer Basha #define DIV4_RATIO 0x105a0 1011609027fSChander Kashyap #define GATE_BUS_TOP 0x10700 102e9d52956SVikas Sajjan #define GATE_BUS_DISP1 0x10728 1030a22c306SShaik Ameer Basha #define GATE_BUS_GEN 0x1073c 1041609027fSChander Kashyap #define GATE_BUS_FSYS0 0x10740 1056b5ae463SShaik Ameer Basha #define GATE_BUS_FSYS2 0x10748 1061609027fSChander Kashyap #define GATE_BUS_PERIC 0x10750 1071609027fSChander Kashyap #define GATE_BUS_PERIC1 0x10754 1081609027fSChander Kashyap #define GATE_BUS_PERIS0 0x10760 1091609027fSChander Kashyap #define GATE_BUS_PERIS1 0x10764 1106575fa76SShaik Ameer Basha #define GATE_BUS_NOC 0x10770 1113a767b35SShaik Ameer Basha #define GATE_TOP_SCLK_ISP 0x10870 1121609027fSChander Kashyap #define GATE_IP_GSCL0 0x10910 1131609027fSChander Kashyap #define GATE_IP_GSCL1 0x10920 1146520e968SAlim Akhtar #define GATE_IP_CAM 0x10924 /* 5800 specific */ 1151609027fSChander Kashyap #define GATE_IP_MFC 0x1092c 1161609027fSChander Kashyap #define GATE_IP_DISP1 0x10928 1171609027fSChander Kashyap #define GATE_IP_G3D 0x10930 1181609027fSChander Kashyap #define GATE_IP_GEN 0x10934 1196b5ae463SShaik Ameer Basha #define GATE_IP_FSYS 0x10944 120faec151bSShaik Ameer Basha #define GATE_IP_PERIC 0x10950 1210a22c306SShaik Ameer Basha #define GATE_IP_PERIS 0x10960 1221609027fSChander Kashyap #define GATE_IP_MSCL 0x10970 1231609027fSChander Kashyap #define GATE_TOP_SCLK_GSCL 0x10820 1241609027fSChander Kashyap #define GATE_TOP_SCLK_DISP1 0x10828 1251609027fSChander Kashyap #define GATE_TOP_SCLK_MAU 0x1083c 1261609027fSChander Kashyap #define GATE_TOP_SCLK_FSYS 0x10840 1271609027fSChander Kashyap #define GATE_TOP_SCLK_PERIC 0x10850 128424b673aSShaik Ameer Basha #define TOP_SPARE2 0x10b08 129c898c6b7SYadwinder Singh Brar #define BPLL_LOCK 0x20010 130c898c6b7SYadwinder Singh Brar #define BPLL_CON0 0x20110 131e867e8faSChanwoo Choi #define SRC_CDREX 0x20200 132e867e8faSChanwoo Choi #define DIV_CDREX0 0x20500 133e867e8faSChanwoo Choi #define DIV_CDREX1 0x20504 134c898c6b7SYadwinder Singh Brar #define KPLL_LOCK 0x28000 135c898c6b7SYadwinder Singh Brar #define KPLL_CON0 0x28100 1361609027fSChander Kashyap #define SRC_KFC 0x28200 1371609027fSChander Kashyap #define DIV_KFC0 0x28500 1381609027fSChander Kashyap 1396520e968SAlim Akhtar /* Exynos5x SoC type */ 1406520e968SAlim Akhtar enum exynos5x_soc { 1416520e968SAlim Akhtar EXYNOS5420, 1426520e968SAlim Akhtar EXYNOS5800, 1436520e968SAlim Akhtar }; 1446520e968SAlim Akhtar 145c898c6b7SYadwinder Singh Brar /* list of PLLs */ 1466520e968SAlim Akhtar enum exynos5x_plls { 147c898c6b7SYadwinder Singh Brar apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 148c898c6b7SYadwinder Singh Brar bpll, kpll, 149c898c6b7SYadwinder Singh Brar nr_plls /* number of PLLs */ 150c898c6b7SYadwinder Singh Brar }; 151c898c6b7SYadwinder Singh Brar 152388c7885STomasz Figa static void __iomem *reg_base; 1536520e968SAlim Akhtar static enum exynos5x_soc exynos5x_soc; 154388c7885STomasz Figa 1551609027fSChander Kashyap /* 1561609027fSChander Kashyap * list of controller registers to be saved and restored during a 1571609027fSChander Kashyap * suspend/resume cycle. 1581609027fSChander Kashyap */ 159ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5x_clk_regs[] __initconst = { 1601609027fSChander Kashyap SRC_CPU, 1611609027fSChander Kashyap DIV_CPU0, 1621609027fSChander Kashyap DIV_CPU1, 1631609027fSChander Kashyap GATE_BUS_CPU, 1641609027fSChander Kashyap GATE_SCLK_CPU, 16577342432SShaik Ameer Basha CLKOUT_CMU_CPU, 16677342432SShaik Ameer Basha EPLL_CON0, 16777342432SShaik Ameer Basha EPLL_CON1, 16877342432SShaik Ameer Basha EPLL_CON2, 16977342432SShaik Ameer Basha RPLL_CON0, 17077342432SShaik Ameer Basha RPLL_CON1, 17177342432SShaik Ameer Basha RPLL_CON2, 1721609027fSChander Kashyap SRC_TOP0, 1731609027fSChander Kashyap SRC_TOP1, 1741609027fSChander Kashyap SRC_TOP2, 1751609027fSChander Kashyap SRC_TOP3, 1761609027fSChander Kashyap SRC_TOP4, 1771609027fSChander Kashyap SRC_TOP5, 1781609027fSChander Kashyap SRC_TOP6, 1791609027fSChander Kashyap SRC_TOP7, 1801609027fSChander Kashyap SRC_DISP10, 1811609027fSChander Kashyap SRC_MAU, 1821609027fSChander Kashyap SRC_FSYS, 1831609027fSChander Kashyap SRC_PERIC0, 1841609027fSChander Kashyap SRC_PERIC1, 1851609027fSChander Kashyap SRC_TOP10, 1861609027fSChander Kashyap SRC_TOP11, 1871609027fSChander Kashyap SRC_TOP12, 188424b673aSShaik Ameer Basha SRC_MASK_TOP2, 18931116a64SShaik Ameer Basha SRC_MASK_TOP7, 1901609027fSChander Kashyap SRC_MASK_DISP10, 1911609027fSChander Kashyap SRC_MASK_FSYS, 1921609027fSChander Kashyap SRC_MASK_PERIC0, 1931609027fSChander Kashyap SRC_MASK_PERIC1, 194e9d52956SVikas Sajjan SRC_MASK_TOP0, 195e9d52956SVikas Sajjan SRC_MASK_TOP1, 196e9d52956SVikas Sajjan SRC_MASK_MAU, 197e9d52956SVikas Sajjan SRC_MASK_ISP, 1983a767b35SShaik Ameer Basha SRC_ISP, 1991609027fSChander Kashyap DIV_TOP0, 2001609027fSChander Kashyap DIV_TOP1, 2011609027fSChander Kashyap DIV_TOP2, 2021609027fSChander Kashyap DIV_DISP10, 2031609027fSChander Kashyap DIV_MAU, 2041609027fSChander Kashyap DIV_FSYS0, 2051609027fSChander Kashyap DIV_FSYS1, 2061609027fSChander Kashyap DIV_FSYS2, 2071609027fSChander Kashyap DIV_PERIC0, 2081609027fSChander Kashyap DIV_PERIC1, 2091609027fSChander Kashyap DIV_PERIC2, 2101609027fSChander Kashyap DIV_PERIC3, 2111609027fSChander Kashyap DIV_PERIC4, 2123a767b35SShaik Ameer Basha SCLK_DIV_ISP0, 2133a767b35SShaik Ameer Basha SCLK_DIV_ISP1, 21402932381SShaik Ameer Basha DIV2_RATIO0, 2151d87db4dSShaik Ameer Basha DIV4_RATIO, 216e9d52956SVikas Sajjan GATE_BUS_DISP1, 2171609027fSChander Kashyap GATE_BUS_TOP, 2180a22c306SShaik Ameer Basha GATE_BUS_GEN, 2191609027fSChander Kashyap GATE_BUS_FSYS0, 2206b5ae463SShaik Ameer Basha GATE_BUS_FSYS2, 2211609027fSChander Kashyap GATE_BUS_PERIC, 2221609027fSChander Kashyap GATE_BUS_PERIC1, 2231609027fSChander Kashyap GATE_BUS_PERIS0, 2241609027fSChander Kashyap GATE_BUS_PERIS1, 2256575fa76SShaik Ameer Basha GATE_BUS_NOC, 2263a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2271609027fSChander Kashyap GATE_IP_GSCL0, 2281609027fSChander Kashyap GATE_IP_GSCL1, 2291609027fSChander Kashyap GATE_IP_MFC, 2301609027fSChander Kashyap GATE_IP_DISP1, 2311609027fSChander Kashyap GATE_IP_G3D, 2321609027fSChander Kashyap GATE_IP_GEN, 2336b5ae463SShaik Ameer Basha GATE_IP_FSYS, 234faec151bSShaik Ameer Basha GATE_IP_PERIC, 2350a22c306SShaik Ameer Basha GATE_IP_PERIS, 2361609027fSChander Kashyap GATE_IP_MSCL, 2371609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 2381609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 2391609027fSChander Kashyap GATE_TOP_SCLK_MAU, 2401609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2411609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 242424b673aSShaik Ameer Basha TOP_SPARE2, 243e867e8faSChanwoo Choi SRC_CDREX, 244e867e8faSChanwoo Choi DIV_CDREX0, 245e867e8faSChanwoo Choi DIV_CDREX1, 2461609027fSChander Kashyap SRC_KFC, 2471609027fSChander Kashyap DIV_KFC0, 2481609027fSChander Kashyap }; 2491609027fSChander Kashyap 250ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5800_clk_regs[] __initconst = { 2516520e968SAlim Akhtar SRC_TOP8, 2526520e968SAlim Akhtar SRC_TOP9, 2536520e968SAlim Akhtar SRC_CAM, 2546520e968SAlim Akhtar SRC_TOP1, 2556520e968SAlim Akhtar DIV_TOP8, 2566520e968SAlim Akhtar DIV_TOP9, 2576520e968SAlim Akhtar DIV_CAM, 2586520e968SAlim Akhtar GATE_IP_CAM, 2596520e968SAlim Akhtar }; 2606520e968SAlim Akhtar 261e9d52956SVikas Sajjan static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 262e9d52956SVikas Sajjan { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 263e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 264e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 265e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 266e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 267e9d52956SVikas Sajjan { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 268e9d52956SVikas Sajjan { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 269e9d52956SVikas Sajjan { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 270e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 271e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 272e9d52956SVikas Sajjan { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 27397372e5aSJavier Martinez Canillas { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 274e9d52956SVikas Sajjan { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 275e9d52956SVikas Sajjan { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 276b3322802SMarek Szyprowski { .offset = GATE_IP_PERIS, .value = 0xffffffff, }, 277e9d52956SVikas Sajjan }; 278e9d52956SVikas Sajjan 2791609027fSChander Kashyap /* list of all parent clocks */ 280dbd713bbSShaik Ameer Basha PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 281dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 282dbd713bbSShaik Ameer Basha PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 283dbd713bbSShaik Ameer Basha PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 284dbd713bbSShaik Ameer Basha PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 285dbd713bbSShaik Ameer Basha PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 286dbd713bbSShaik Ameer Basha PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 287dbd713bbSShaik Ameer Basha PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 288dbd713bbSShaik Ameer Basha PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 289dbd713bbSShaik Ameer Basha PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 290dbd713bbSShaik Ameer Basha PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 291dbd713bbSShaik Ameer Basha PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 292dbd713bbSShaik Ameer Basha PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 293dbd713bbSShaik Ameer Basha PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 294dbd713bbSShaik Ameer Basha PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 2951609027fSChander Kashyap 296dbd713bbSShaik Ameer Basha PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 297dbd713bbSShaik Ameer Basha "mout_sclk_mpll"}; 298dbd713bbSShaik Ameer Basha PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 299dbd713bbSShaik Ameer Basha "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 300dbd713bbSShaik Ameer Basha "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 301dbd713bbSShaik Ameer Basha PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 302dbd713bbSShaik Ameer Basha PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 303dbd713bbSShaik Ameer Basha PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 3041609027fSChander Kashyap 305424b673aSShaik Ameer Basha PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 306dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 307faec151bSShaik Ameer Basha PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 308b31ca2a0SShaik Ameer Basha PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 3091609027fSChander Kashyap 310dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 3116b5ae463SShaik Ameer Basha PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 3126b5ae463SShaik Ameer Basha PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 313dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 3141609027fSChander Kashyap 315dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 316dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 3176575fa76SShaik Ameer Basha PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 3186575fa76SShaik Ameer Basha PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 3196575fa76SShaik Ameer Basha 3206575fa76SShaik Ameer Basha PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 3216575fa76SShaik Ameer Basha PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 3226575fa76SShaik Ameer Basha PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 3236575fa76SShaik Ameer Basha 3243a767b35SShaik Ameer Basha PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 3253a767b35SShaik Ameer Basha PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 3263a767b35SShaik Ameer Basha 3273a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 3283a767b35SShaik Ameer Basha "mout_sclk_spll"}; 3293a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 3303a767b35SShaik Ameer Basha 3313a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 3323a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 3331609027fSChander Kashyap 334dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 335424b673aSShaik Ameer Basha PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 3361609027fSChander Kashyap 337dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 338dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 3391609027fSChander Kashyap 340dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 341dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 3421609027fSChander Kashyap 343dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 344dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 3451609027fSChander Kashyap 346dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 347dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 3483a767b35SShaik Ameer Basha PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 3491609027fSChander Kashyap 350dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 351dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 3521609027fSChander Kashyap 353dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 354dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 3551609027fSChander Kashyap 356dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 357424b673aSShaik Ameer Basha PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 358dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 359424b673aSShaik Ameer Basha PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 3601609027fSChander Kashyap 361dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 362dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 3631609027fSChander Kashyap 364dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 365dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 3661609027fSChander Kashyap 367dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 368dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 3691609027fSChander Kashyap 370dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 371dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 3721609027fSChander Kashyap 373dbd713bbSShaik Ameer Basha PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 374dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 375dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 376dbd713bbSShaik Ameer Basha PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 377dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 378dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 379dbd713bbSShaik Ameer Basha PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 380dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 381dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 382dbd713bbSShaik Ameer Basha PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 383dbd713bbSShaik Ameer Basha "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 384dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 385dbd713bbSShaik Ameer Basha PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 386dbd713bbSShaik Ameer Basha PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 387dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 388dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 38931116a64SShaik Ameer Basha PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 39031116a64SShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 391e867e8faSChanwoo Choi PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"}; 392e867e8faSChanwoo Choi 3936520e968SAlim Akhtar /* List of parents specific to exynos5800 */ 3946520e968SAlim Akhtar PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 3956520e968SAlim Akhtar PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 3966520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 3976520e968SAlim Akhtar PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 3986520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 3996520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 4006520e968SAlim Akhtar PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4016520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4026520e968SAlim Akhtar "mout_epll2" }; 4036520e968SAlim Akhtar PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4046520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll" }; 4056520e968SAlim Akhtar PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 4066520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4076520e968SAlim Akhtar PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4086520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll", 4096520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 410e867e8faSChanwoo Choi PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll", 411e867e8faSChanwoo Choi "mout_sclk_mpll", "ff_dout_spll2", 412e867e8faSChanwoo Choi "mout_sclk_spll", "mout_sclk_epll"}; 4136520e968SAlim Akhtar PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 4146520e968SAlim Akhtar "mout_sclk_mpll", 4156520e968SAlim Akhtar "ff_dout_spll2" }; 4166520e968SAlim Akhtar PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 4176520e968SAlim Akhtar PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 4186520e968SAlim Akhtar PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 4196520e968SAlim Akhtar PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 4206520e968SAlim Akhtar PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 4216520e968SAlim Akhtar PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 4226520e968SAlim Akhtar PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 4236520e968SAlim Akhtar PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 4248a9cf26eSSylwester Nawrocki PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; 4251609027fSChander Kashyap 4261609027fSChander Kashyap /* fixed rate clocks generated outside the soc */ 4276520e968SAlim Akhtar static struct samsung_fixed_rate_clock 4286520e968SAlim Akhtar exynos5x_fixed_rate_ext_clks[] __initdata = { 429728f288dSStephen Boyd FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 4301609027fSChander Kashyap }; 4311609027fSChander Kashyap 4321609027fSChander Kashyap /* fixed rate clocks generated inside the soc */ 433ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { 434728f288dSStephen Boyd FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 435728f288dSStephen Boyd FRATE(0, "sclk_pwi", NULL, 0, 24000000), 436728f288dSStephen Boyd FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 437728f288dSStephen Boyd FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 438728f288dSStephen Boyd FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 4391609027fSChander Kashyap }; 4401609027fSChander Kashyap 441ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 442ad98c64fSKrzysztof Kozlowski exynos5x_fixed_factor_clks[] __initconst = { 443b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 444b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 4451609027fSChander Kashyap }; 4461609027fSChander Kashyap 447ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 448ad98c64fSKrzysztof Kozlowski exynos5800_fixed_factor_clks[] __initconst = { 4496520e968SAlim Akhtar FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 4506520e968SAlim Akhtar FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 4516520e968SAlim Akhtar }; 4526520e968SAlim Akhtar 453ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 4546520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 4556520e968SAlim Akhtar MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 4566520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 4576520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 4586520e968SAlim Akhtar 4596520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 4606520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 4616520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 4626520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 4636520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 4646520e968SAlim Akhtar 4656520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 4666520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 4676520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 4686520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 4696520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 4706520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 4716520e968SAlim Akhtar 472e867e8faSChanwoo Choi MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 473e867e8faSChanwoo Choi mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), 474599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, 475599cebeaSSylwester Nawrocki SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), 4766520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 4776520e968SAlim Akhtar MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 4786520e968SAlim Akhtar 4796520e968SAlim Akhtar MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 4806520e968SAlim Akhtar MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 4816520e968SAlim Akhtar MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 4826520e968SAlim Akhtar MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 4836520e968SAlim Akhtar 484599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, 485599cebeaSSylwester Nawrocki SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0), 4866520e968SAlim Akhtar MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 4876520e968SAlim Akhtar SRC_TOP9, 16, 1), 4886520e968SAlim Akhtar MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 4896520e968SAlim Akhtar SRC_TOP9, 20, 1), 4906520e968SAlim Akhtar MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 4916520e968SAlim Akhtar SRC_TOP9, 24, 1), 4926520e968SAlim Akhtar MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 4936520e968SAlim Akhtar SRC_TOP9, 28, 1), 4946520e968SAlim Akhtar 4956520e968SAlim Akhtar MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 4966520e968SAlim Akhtar MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 4976520e968SAlim Akhtar SRC_TOP13, 20, 1), 4986520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 4996520e968SAlim Akhtar SRC_TOP13, 24, 1), 5006520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 5016520e968SAlim Akhtar SRC_TOP13, 28, 1), 5026520e968SAlim Akhtar 5036520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 5046520e968SAlim Akhtar }; 5056520e968SAlim Akhtar 506ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { 50781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 50881fed6e3SChanwoo Choi "mout_aclk400_wcore", DIV_TOP0, 16, 3), 5096520e968SAlim Akhtar DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 5106520e968SAlim Akhtar DIV_TOP8, 16, 3), 5116520e968SAlim Akhtar DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 5126520e968SAlim Akhtar DIV_TOP8, 20, 3), 5136520e968SAlim Akhtar DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 5146520e968SAlim Akhtar DIV_TOP8, 24, 3), 5156520e968SAlim Akhtar DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 5166520e968SAlim Akhtar DIV_TOP8, 28, 3), 5176520e968SAlim Akhtar 5186520e968SAlim Akhtar DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 5196520e968SAlim Akhtar DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 5206520e968SAlim Akhtar }; 5216520e968SAlim Akhtar 522ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 5236520e968SAlim Akhtar GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 5246520e968SAlim Akhtar GATE_BUS_TOP, 24, 0, 0), 5256520e968SAlim Akhtar GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 526318fa46cSMarek Szyprowski GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), 52741097f25SSylwester Nawrocki GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", 528599cebeaSSylwester Nawrocki SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 5296520e968SAlim Akhtar }; 5306520e968SAlim Akhtar 531ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 5326520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 5336520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 5346520e968SAlim Akhtar TOP_SPARE2, 4, 1), 5356520e968SAlim Akhtar 5366520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 53736ba4824SMarek Szyprowski MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2), 5386520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 5396520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 5406520e968SAlim Akhtar 5416520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 5426520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group4_p, 5436520e968SAlim Akhtar SRC_TOP1, 4, 2), 5446520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 5456520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 5466520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 5476520e968SAlim Akhtar 5486520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 5496520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 5506520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 5516520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 5526520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 5536520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 5546520e968SAlim Akhtar 555e867e8faSChanwoo Choi MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 556e867e8faSChanwoo Choi mout_group5_5800_p, SRC_TOP7, 16, 2), 55706255a92SSylwester Nawrocki MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2, 55806255a92SSylwester Nawrocki CLK_SET_RATE_PARENT, 0), 5596520e968SAlim Akhtar 5606520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 5616520e968SAlim Akhtar }; 5626520e968SAlim Akhtar 563ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 56481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 56581fed6e3SChanwoo Choi "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 5666520e968SAlim Akhtar }; 5676520e968SAlim Akhtar 56841097f25SSylwester Nawrocki static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { 569d32dd2a1SJoonyoung Shim GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 57041097f25SSylwester Nawrocki GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 571599cebeaSSylwester Nawrocki SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 57241097f25SSylwester Nawrocki }; 57341097f25SSylwester Nawrocki 574ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 575b31ca2a0SShaik Ameer Basha MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 576b31ca2a0SShaik Ameer Basha SRC_TOP7, 4, 1), 577dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 578dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 57931116a64SShaik Ameer Basha 580bee4f87fSThomas Abraham MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 581bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 582dbd713bbSShaik Ameer Basha MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 583bee4f87fSThomas Abraham MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 584bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 585dbd713bbSShaik Ameer Basha MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 5861609027fSChander Kashyap 587dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 588dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 5896b5ae463SShaik Ameer Basha MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 590dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 5911609027fSChander Kashyap 592dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 593dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 5941609027fSChander Kashyap 595dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 5961609027fSChander Kashyap 5973a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 5983a767b35SShaik Ameer Basha SRC_TOP3, 0, 1), 599dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 6001609027fSChander Kashyap SRC_TOP3, 4, 1), 60188560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 60288560100SJavier Martinez Canillas mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 603dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 6041609027fSChander Kashyap SRC_TOP3, 12, 1), 6056575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 6066575fa76SShaik Ameer Basha SRC_TOP3, 16, 1), 6076575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 6086575fa76SShaik Ameer Basha SRC_TOP3, 20, 1), 6096b5ae463SShaik Ameer Basha MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 6106b5ae463SShaik Ameer Basha SRC_TOP3, 24, 1), 611dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 6121609027fSChander Kashyap SRC_TOP3, 28, 1), 6131609027fSChander Kashyap 614dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 6151609027fSChander Kashyap SRC_TOP4, 0, 1), 6163a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 6173a767b35SShaik Ameer Basha SRC_TOP4, 4, 1), 618faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 619faec151bSShaik Ameer Basha SRC_TOP4, 8, 1), 6203a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 6213a767b35SShaik Ameer Basha SRC_TOP4, 12, 1), 6223a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 6233a767b35SShaik Ameer Basha SRC_TOP4, 16, 1), 624dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 625dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 626c0fb262bSArun Kumar K MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 627c0fb262bSArun Kumar K SRC_TOP4, 28, 1), 6281609027fSChander Kashyap 62988560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 63088560100SJavier Martinez Canillas mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 631faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 632faec151bSShaik Ameer Basha SRC_TOP5, 4, 1), 6333fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 6343fac5941SShaik Ameer Basha SRC_TOP5, 8, 1), 6353fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 6363fac5941SShaik Ameer Basha SRC_TOP5, 12, 1), 6373fac5941SShaik Ameer Basha MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 6383fac5941SShaik Ameer Basha SRC_TOP5, 16, 1), 639dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 6401609027fSChander Kashyap SRC_TOP5, 20, 1), 64188560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 64288560100SJavier Martinez Canillas mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 643c0feb268SMarek Szyprowski MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 644c0feb268SMarek Szyprowski mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 6451609027fSChander Kashyap 646dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 647dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 648dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 649dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 650dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 651599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, 652599cebeaSSylwester Nawrocki CLK_SET_RATE_PARENT, 0), 653dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 654dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 6551609027fSChander Kashyap 6563a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 6573a767b35SShaik Ameer Basha SRC_TOP10, 0, 1), 658dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 659dbd713bbSShaik Ameer Basha SRC_TOP10, 4, 1), 66088560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 66188560100SJavier Martinez Canillas SRC_TOP10, 8, 1), 662dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 6631609027fSChander Kashyap SRC_TOP10, 12, 1), 6646575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 6656575fa76SShaik Ameer Basha SRC_TOP10, 16, 1), 6666575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 6676575fa76SShaik Ameer Basha SRC_TOP10, 20, 1), 6686b5ae463SShaik Ameer Basha MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 6696b5ae463SShaik Ameer Basha SRC_TOP10, 24, 1), 670dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 671dbd713bbSShaik Ameer Basha SRC_TOP10, 28, 1), 6723a767b35SShaik Ameer Basha 673dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 6741609027fSChander Kashyap SRC_TOP11, 0, 1), 6753a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 6763a767b35SShaik Ameer Basha SRC_TOP11, 4, 1), 677dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 6783a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 6793a767b35SShaik Ameer Basha SRC_TOP11, 12, 1), 680dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 681dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 682c0fb262bSArun Kumar K MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 683c0fb262bSArun Kumar K SRC_TOP11, 28, 1), 6841609027fSChander Kashyap 68588560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 68688560100SJavier Martinez Canillas mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 687dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 688dbd713bbSShaik Ameer Basha SRC_TOP12, 8, 1), 689dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 690dbd713bbSShaik Ameer Basha SRC_TOP12, 12, 1), 691dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 692dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 693dbd713bbSShaik Ameer Basha SRC_TOP12, 20, 1), 69488560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 69588560100SJavier Martinez Canillas mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 696c0feb268SMarek Szyprowski MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 697c0feb268SMarek Szyprowski mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 6981609027fSChander Kashyap 6991609027fSChander Kashyap /* DISP1 Block */ 700dbd713bbSShaik Ameer Basha MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 701dbd713bbSShaik Ameer Basha MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 702dbd713bbSShaik Ameer Basha MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 703dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 704424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 7056575fa76SShaik Ameer Basha 706424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 7071609027fSChander Kashyap 708e867e8faSChanwoo Choi /* CDREX block */ 709e867e8faSChanwoo Choi MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p, 710e867e8faSChanwoo Choi SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0), 711e867e8faSChanwoo Choi MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1, 712e867e8faSChanwoo Choi CLK_SET_RATE_PARENT, 0), 713e867e8faSChanwoo Choi 7141609027fSChander Kashyap /* MAU Block */ 71531116a64SShaik Ameer Basha MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 7161609027fSChander Kashyap 7171609027fSChander Kashyap /* FSYS Block */ 718dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 719dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 720dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 721dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 722dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 723dbd713bbSShaik Ameer Basha MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 7246b5ae463SShaik Ameer Basha MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 7251609027fSChander Kashyap 7261609027fSChander Kashyap /* PERIC Block */ 727dbd713bbSShaik Ameer Basha MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 728dbd713bbSShaik Ameer Basha MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 729dbd713bbSShaik Ameer Basha MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 730dbd713bbSShaik Ameer Basha MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 731dbd713bbSShaik Ameer Basha MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 732dbd713bbSShaik Ameer Basha MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 733dbd713bbSShaik Ameer Basha MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 734dbd713bbSShaik Ameer Basha MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 735dbd713bbSShaik Ameer Basha MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 736dbd713bbSShaik Ameer Basha MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 737dbd713bbSShaik Ameer Basha MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 738dbd713bbSShaik Ameer Basha MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 7393a767b35SShaik Ameer Basha 7403a767b35SShaik Ameer Basha /* ISP Block */ 7413a767b35SShaik Ameer Basha MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 7423a767b35SShaik Ameer Basha MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 7433a767b35SShaik Ameer Basha MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 7443a767b35SShaik Ameer Basha MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 7453a767b35SShaik Ameer Basha MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 7461609027fSChander Kashyap }; 7471609027fSChander Kashyap 748ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 749cba9d2faSAndrzej Hajda DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 750cba9d2faSAndrzej Hajda DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 751cba9d2faSAndrzej Hajda DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 752dbd713bbSShaik Ameer Basha DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 753cba9d2faSAndrzej Hajda DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 7541609027fSChander Kashyap 75581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 75681fed6e3SChanwoo Choi DIV_TOP0, 0, 3), 75781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 75881fed6e3SChanwoo Choi DIV_TOP0, 4, 3), 75981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 76081fed6e3SChanwoo Choi DIV_TOP0, 8, 3), 76181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 76281fed6e3SChanwoo Choi DIV_TOP0, 12, 3), 76381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 76481fed6e3SChanwoo Choi DIV_TOP0, 20, 3), 76581fed6e3SChanwoo Choi DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 76681fed6e3SChanwoo Choi DIV_TOP0, 24, 3), 76781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 76881fed6e3SChanwoo Choi DIV_TOP0, 28, 3), 76981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 77081fed6e3SChanwoo Choi "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 77181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 77281fed6e3SChanwoo Choi "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 77381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 77481fed6e3SChanwoo Choi DIV_TOP1, 8, 6), 77581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 77681fed6e3SChanwoo Choi "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 77781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 77881fed6e3SChanwoo Choi DIV_TOP1, 20, 3), 77981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 78081fed6e3SChanwoo Choi DIV_TOP1, 24, 3), 78181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 78281fed6e3SChanwoo Choi DIV_TOP1, 28, 3), 7831609027fSChander Kashyap 78481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 78581fed6e3SChanwoo Choi DIV_TOP2, 8, 3), 78681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 78781fed6e3SChanwoo Choi DIV_TOP2, 12, 3), 78881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 78981fed6e3SChanwoo Choi 16, 3), 79081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 79181fed6e3SChanwoo Choi DIV_TOP2, 20, 3), 79281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 79381fed6e3SChanwoo Choi "mout_aclk300_disp1", DIV_TOP2, 24, 3), 79481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 79581fed6e3SChanwoo Choi DIV_TOP2, 28, 3), 7961609027fSChander Kashyap 7971609027fSChander Kashyap /* DISP1 Block */ 798424b673aSShaik Ameer Basha DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 799cba9d2faSAndrzej Hajda DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 800cba9d2faSAndrzej Hajda DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 801cba9d2faSAndrzej Hajda DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 80281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 80381fed6e3SChanwoo Choi "mout_aclk400_disp1", DIV_TOP2, 4, 3), 8041609027fSChander Kashyap 805e867e8faSChanwoo Choi /* CDREX Block */ 806e867e8faSChanwoo Choi DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", 807e867e8faSChanwoo Choi DIV_CDREX0, 28, 3), 808e867e8faSChanwoo Choi DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", 809e867e8faSChanwoo Choi DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), 810e867e8faSChanwoo Choi DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", 811e867e8faSChanwoo Choi DIV_CDREX0, 16, 3), 812e867e8faSChanwoo Choi DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", 813e867e8faSChanwoo Choi DIV_CDREX0, 8, 3), 814e867e8faSChanwoo Choi DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", 815e867e8faSChanwoo Choi DIV_CDREX0, 3, 5), 816e867e8faSChanwoo Choi 817e867e8faSChanwoo Choi DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", 818e867e8faSChanwoo Choi DIV_CDREX1, 8, 3), 819e867e8faSChanwoo Choi 8201609027fSChander Kashyap /* Audio Block */ 821cba9d2faSAndrzej Hajda DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 822cba9d2faSAndrzej Hajda DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 8231609027fSChander Kashyap 8241609027fSChander Kashyap /* USB3.0 */ 825cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 826cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 827cba9d2faSAndrzej Hajda DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 828cba9d2faSAndrzej Hajda DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 8291609027fSChander Kashyap 8301609027fSChander Kashyap /* MMC */ 831cba9d2faSAndrzej Hajda DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 832cba9d2faSAndrzej Hajda DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 833cba9d2faSAndrzej Hajda DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 8341609027fSChander Kashyap 835cba9d2faSAndrzej Hajda DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 8366b5ae463SShaik Ameer Basha DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 8371609027fSChander Kashyap 8381609027fSChander Kashyap /* UART and PWM */ 839cba9d2faSAndrzej Hajda DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 840cba9d2faSAndrzej Hajda DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 841cba9d2faSAndrzej Hajda DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 842cba9d2faSAndrzej Hajda DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 843cba9d2faSAndrzej Hajda DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 8441609027fSChander Kashyap 8451609027fSChander Kashyap /* SPI */ 846cba9d2faSAndrzej Hajda DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 847cba9d2faSAndrzej Hajda DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 848cba9d2faSAndrzej Hajda DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 8491609027fSChander Kashyap 8501d87db4dSShaik Ameer Basha 8511609027fSChander Kashyap /* PCM */ 852cba9d2faSAndrzej Hajda DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 853cba9d2faSAndrzej Hajda DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 8541609027fSChander Kashyap 8551609027fSChander Kashyap /* Audio - I2S */ 856cba9d2faSAndrzej Hajda DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 857cba9d2faSAndrzej Hajda DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 858cba9d2faSAndrzej Hajda DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 859cba9d2faSAndrzej Hajda DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 860cba9d2faSAndrzej Hajda DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 8611609027fSChander Kashyap 8621609027fSChander Kashyap /* SPI Pre-Ratio */ 863faec151bSShaik Ameer Basha DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 864faec151bSShaik Ameer Basha DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 865faec151bSShaik Ameer Basha DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 8663a767b35SShaik Ameer Basha 86702932381SShaik Ameer Basha /* GSCL Block */ 86802932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 86902932381SShaik Ameer Basha 8704549d93dSShaik Ameer Basha /* MSCL Block */ 8714549d93dSShaik Ameer Basha DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 8724549d93dSShaik Ameer Basha 8730a22c306SShaik Ameer Basha /* PSGEN */ 8740a22c306SShaik Ameer Basha DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 8750a22c306SShaik Ameer Basha DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 8760a22c306SShaik Ameer Basha 8773a767b35SShaik Ameer Basha /* ISP Block */ 8783a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 8793a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 8803a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 8813a767b35SShaik Ameer Basha DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 8823a767b35SShaik Ameer Basha DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 8833a767b35SShaik Ameer Basha DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 8843a767b35SShaik Ameer Basha DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 8853a767b35SShaik Ameer Basha DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 8863a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 8873a767b35SShaik Ameer Basha DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 8883a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 8891609027fSChander Kashyap }; 8901609027fSChander Kashyap 891ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 8925b73721bSNaveen Krishna Chatradhi /* G2D */ 8933fac5941SShaik Ameer Basha GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 8945b73721bSNaveen Krishna Chatradhi GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 8953fac5941SShaik Ameer Basha GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 8963fac5941SShaik Ameer Basha GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 8973fac5941SShaik Ameer Basha GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 8985b73721bSNaveen Krishna Chatradhi 8991609027fSChander Kashyap GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 900318fa46cSMarek Szyprowski GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), 9011609027fSChander Kashyap GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 9021609027fSChander Kashyap GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 9031609027fSChander Kashyap 9041609027fSChander Kashyap GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 9051609027fSChander Kashyap GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 9061609027fSChander Kashyap GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 907318fa46cSMarek Szyprowski GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), 9081609027fSChander Kashyap GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 9091609027fSChander Kashyap GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 9103a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 9113a767b35SShaik Ameer Basha GATE_BUS_TOP, 5, 0, 0), 9121609027fSChander Kashyap GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 913318fa46cSMarek Szyprowski GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), 9141609027fSChander Kashyap GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 9151609027fSChander Kashyap GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 9163a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 9173a767b35SShaik Ameer Basha GATE_BUS_TOP, 8, 0, 0), 918b31ca2a0SShaik Ameer Basha GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 9191609027fSChander Kashyap GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 920faec151bSShaik Ameer Basha GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 9211609027fSChander Kashyap GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 9223a767b35SShaik Ameer Basha GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 9233a767b35SShaik Ameer Basha GATE_BUS_TOP, 13, 0, 0), 9241609027fSChander Kashyap GATE(0, "aclk166", "mout_user_aclk166", 9251609027fSChander Kashyap GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 92634cba900SJavier Martinez Canillas GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", 927318fa46cSMarek Szyprowski GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), 9283a767b35SShaik Ameer Basha GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 9293a767b35SShaik Ameer Basha GATE_BUS_TOP, 16, 0, 0), 93002932381SShaik Ameer Basha GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 931c07c1a0fSAndrzej Pietrasiewicz GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), 932424b673aSShaik Ameer Basha GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 933318fa46cSMarek Szyprowski GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), 934b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 935b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 28, 0, 0), 936b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 937b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 29, 0, 0), 938424b673aSShaik Ameer Basha 939424b673aSShaik Ameer Basha GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 940318fa46cSMarek Szyprowski SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), 9411609027fSChander Kashyap 9421609027fSChander Kashyap /* sclk */ 943cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 9441609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 945cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 9461609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 947cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 9481609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 949cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 9501609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 951faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 9521609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 953faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 9541609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 955faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 9561609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 957cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 9581609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 959cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 9601609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 961cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 9621609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 963cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 9641609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 965cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 9661609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 967cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 9681609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 9691609027fSChander Kashyap 970cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 9711609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 972cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 9731609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 974cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 9751609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 976cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 9771609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 978cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 9791609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 980cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 9811609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 982cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 9831609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 9841609027fSChander Kashyap 9851609027fSChander Kashyap /* Display */ 986cba9d2faSAndrzej Hajda GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 9871609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 988cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 9891609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 990cba9d2faSAndrzej Hajda GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 991424b673aSShaik Ameer Basha GATE_TOP_SCLK_DISP1, 9, 0, 0), 992cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 9931609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 994cba9d2faSAndrzej Hajda GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 9951609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 9961609027fSChander Kashyap 9971609027fSChander Kashyap /* Maudio Block */ 998cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 9991609027fSChander Kashyap GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1000cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 10011609027fSChander Kashyap GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 10026b5ae463SShaik Ameer Basha 10036b5ae463SShaik Ameer Basha /* FSYS Block */ 1004cba9d2faSAndrzej Hajda GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1005cba9d2faSAndrzej Hajda GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1006cba9d2faSAndrzej Hajda GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1007cba9d2faSAndrzej Hajda GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 10086b5ae463SShaik Ameer Basha GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 10096b5ae463SShaik Ameer Basha GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 10106b5ae463SShaik Ameer Basha GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 10116b5ae463SShaik Ameer Basha GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1012cba9d2faSAndrzej Hajda GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 10136b5ae463SShaik Ameer Basha GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 10146b5ae463SShaik Ameer Basha GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 10156b5ae463SShaik Ameer Basha GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 10166b5ae463SShaik Ameer Basha GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 10176b5ae463SShaik Ameer Basha GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 10186b5ae463SShaik Ameer Basha SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 10191609027fSChander Kashyap 1020faec151bSShaik Ameer Basha /* PERIC Block */ 102144ff0254SDoug Anderson GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 102244ff0254SDoug Anderson GATE_IP_PERIC, 0, 0, 0), 102344ff0254SDoug Anderson GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 102444ff0254SDoug Anderson GATE_IP_PERIC, 1, 0, 0), 102544ff0254SDoug Anderson GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 102644ff0254SDoug Anderson GATE_IP_PERIC, 2, 0, 0), 102744ff0254SDoug Anderson GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 102844ff0254SDoug Anderson GATE_IP_PERIC, 3, 0, 0), 102944ff0254SDoug Anderson GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 103044ff0254SDoug Anderson GATE_IP_PERIC, 6, 0, 0), 103144ff0254SDoug Anderson GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 103244ff0254SDoug Anderson GATE_IP_PERIC, 7, 0, 0), 103344ff0254SDoug Anderson GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 103444ff0254SDoug Anderson GATE_IP_PERIC, 8, 0, 0), 103544ff0254SDoug Anderson GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 103644ff0254SDoug Anderson GATE_IP_PERIC, 9, 0, 0), 103744ff0254SDoug Anderson GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 103844ff0254SDoug Anderson GATE_IP_PERIC, 10, 0, 0), 103944ff0254SDoug Anderson GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 104044ff0254SDoug Anderson GATE_IP_PERIC, 11, 0, 0), 104144ff0254SDoug Anderson GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 104244ff0254SDoug Anderson GATE_IP_PERIC, 12, 0, 0), 104344ff0254SDoug Anderson GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 104444ff0254SDoug Anderson GATE_IP_PERIC, 13, 0, 0), 104544ff0254SDoug Anderson GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 104644ff0254SDoug Anderson GATE_IP_PERIC, 14, 0, 0), 104744ff0254SDoug Anderson GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 104844ff0254SDoug Anderson GATE_IP_PERIC, 15, 0, 0), 104944ff0254SDoug Anderson GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 105044ff0254SDoug Anderson GATE_IP_PERIC, 16, 0, 0), 105144ff0254SDoug Anderson GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 105244ff0254SDoug Anderson GATE_IP_PERIC, 17, 0, 0), 105344ff0254SDoug Anderson GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 105444ff0254SDoug Anderson GATE_IP_PERIC, 18, 0, 0), 105544ff0254SDoug Anderson GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 105644ff0254SDoug Anderson GATE_IP_PERIC, 20, 0, 0), 105744ff0254SDoug Anderson GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 105844ff0254SDoug Anderson GATE_IP_PERIC, 21, 0, 0), 105944ff0254SDoug Anderson GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 106044ff0254SDoug Anderson GATE_IP_PERIC, 22, 0, 0), 106144ff0254SDoug Anderson GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 106244ff0254SDoug Anderson GATE_IP_PERIC, 23, 0, 0), 106344ff0254SDoug Anderson GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 106444ff0254SDoug Anderson GATE_IP_PERIC, 24, 0, 0), 106544ff0254SDoug Anderson GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 106644ff0254SDoug Anderson GATE_IP_PERIC, 26, 0, 0), 106744ff0254SDoug Anderson GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 106844ff0254SDoug Anderson GATE_IP_PERIC, 28, 0, 0), 106944ff0254SDoug Anderson GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 107044ff0254SDoug Anderson GATE_IP_PERIC, 30, 0, 0), 107144ff0254SDoug Anderson GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 107244ff0254SDoug Anderson GATE_IP_PERIC, 31, 0, 0), 10731609027fSChander Kashyap 107444ff0254SDoug Anderson GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 107544ff0254SDoug Anderson GATE_BUS_PERIC, 22, 0, 0), 10761609027fSChander Kashyap 10770a22c306SShaik Ameer Basha /* PERIS Block */ 1078cba9d2faSAndrzej Hajda GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 10790a22c306SShaik Ameer Basha GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1080cba9d2faSAndrzej Hajda GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 10810a22c306SShaik Ameer Basha GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 10820a22c306SShaik Ameer Basha GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 10830a22c306SShaik Ameer Basha GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 10840a22c306SShaik Ameer Basha GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 10850a22c306SShaik Ameer Basha GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 10860a22c306SShaik Ameer Basha GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 10870a22c306SShaik Ameer Basha GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 10880a22c306SShaik Ameer Basha GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 10890a22c306SShaik Ameer Basha GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 10900a22c306SShaik Ameer Basha GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 10910a22c306SShaik Ameer Basha GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 10920a22c306SShaik Ameer Basha GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 10930a22c306SShaik Ameer Basha GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 10940a22c306SShaik Ameer Basha GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 10950a22c306SShaik Ameer Basha GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 10960a22c306SShaik Ameer Basha GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 10970a22c306SShaik Ameer Basha GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 10981609027fSChander Kashyap 10990a22c306SShaik Ameer Basha /* GEN Block */ 11000a22c306SShaik Ameer Basha GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 11010a22c306SShaik Ameer Basha GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 11020a22c306SShaik Ameer Basha GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 11030a22c306SShaik Ameer Basha GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 11040a22c306SShaik Ameer Basha GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 11050a22c306SShaik Ameer Basha GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 11060a22c306SShaik Ameer Basha GATE_IP_GEN, 6, 0, 0), 11070a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 11080a22c306SShaik Ameer Basha GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 11090a22c306SShaik Ameer Basha GATE_IP_GEN, 9, 0, 0), 11100a22c306SShaik Ameer Basha 11110a22c306SShaik Ameer Basha /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 11120a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 11130a22c306SShaik Ameer Basha GATE_BUS_GEN, 28, 0, 0), 11140a22c306SShaik Ameer Basha GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 11151609027fSChander Kashyap 111602932381SShaik Ameer Basha /* GSCL Block */ 111702932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 111802932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 6, 0, 0), 111902932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 112002932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 7, 0, 0), 112102932381SShaik Ameer Basha 112202932381SShaik Ameer Basha GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 112302932381SShaik Ameer Basha GATE_IP_GSCL0, 4, 0, 0), 112402932381SShaik Ameer Basha GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 112502932381SShaik Ameer Basha GATE_IP_GSCL0, 5, 0, 0), 112602932381SShaik Ameer Basha GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 112702932381SShaik Ameer Basha GATE_IP_GSCL0, 6, 0, 0), 11281609027fSChander Kashyap 112902932381SShaik Ameer Basha GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 113002932381SShaik Ameer Basha GATE_IP_GSCL1, 2, 0, 0), 113102932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 11321609027fSChander Kashyap GATE_IP_GSCL1, 3, 0, 0), 113302932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 11341609027fSChander Kashyap GATE_IP_GSCL1, 4, 0, 0), 113502932381SShaik Ameer Basha GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 113602932381SShaik Ameer Basha GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 113702932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 11381609027fSChander Kashyap GATE_IP_GSCL1, 16, 0, 0), 1139cba9d2faSAndrzej Hajda GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 11401609027fSChander Kashyap GATE_IP_GSCL1, 17, 0, 0), 11411609027fSChander Kashyap 114202932381SShaik Ameer Basha /* MSCL Block */ 114302932381SShaik Ameer Basha GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 114402932381SShaik Ameer Basha GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 114502932381SShaik Ameer Basha GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 11464549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 114702932381SShaik Ameer Basha GATE_IP_MSCL, 8, 0, 0), 11484549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 114902932381SShaik Ameer Basha GATE_IP_MSCL, 9, 0, 0), 11504549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 115102932381SShaik Ameer Basha GATE_IP_MSCL, 10, 0, 0), 115202932381SShaik Ameer Basha 11533a767b35SShaik Ameer Basha /* ISP */ 11543a767b35SShaik Ameer Basha GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 11553a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 11563a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 11573a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 11583a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 11593a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 11603a767b35SShaik Ameer Basha GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 11613a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 11623a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 11633a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 11643a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 11653a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 11663a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 11673a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 11683a767b35SShaik Ameer Basha 1169ec4016ffSMarek Szyprowski GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 1170ec4016ffSMarek Szyprowski }; 1171ec4016ffSMarek Szyprowski 1172ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { 1173ec4016ffSMarek Szyprowski DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 1174ec4016ffSMarek Szyprowski }; 1175ec4016ffSMarek Szyprowski 1176ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { 1177ec4016ffSMarek Szyprowski GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1178ec4016ffSMarek Szyprowski GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1179ec4016ffSMarek Szyprowski GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1180ec4016ffSMarek Szyprowski GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1181ec4016ffSMarek Szyprowski GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1182ec4016ffSMarek Szyprowski GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1183ec4016ffSMarek Szyprowski GATE_IP_DISP1, 7, 0, 0), 1184ec4016ffSMarek Szyprowski GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1185ec4016ffSMarek Szyprowski GATE_IP_DISP1, 8, 0, 0), 1186ec4016ffSMarek Szyprowski GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1187ec4016ffSMarek Szyprowski GATE_IP_DISP1, 9, 0, 0), 1188ec4016ffSMarek Szyprowski }; 1189ec4016ffSMarek Szyprowski 1190ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = { 1191ec4016ffSMarek Szyprowski { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ 1192ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ 1193ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ 1194ec4016ffSMarek Szyprowski { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ 1195ec4016ffSMarek Szyprowski { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ 1196ec4016ffSMarek Szyprowski }; 1197ec4016ffSMarek Szyprowski 1198ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { 1199ec4016ffSMarek Szyprowski DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 1200ec4016ffSMarek Szyprowski DIV2_RATIO0, 4, 2), 1201ec4016ffSMarek Szyprowski }; 1202ec4016ffSMarek Szyprowski 1203ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { 1204ec4016ffSMarek Szyprowski GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1205ec4016ffSMarek Szyprowski GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1206ec4016ffSMarek Szyprowski GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 1207ec4016ffSMarek Szyprowski GATE_IP_GSCL1, 6, 0, 0), 1208ec4016ffSMarek Szyprowski GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 1209ec4016ffSMarek Szyprowski GATE_IP_GSCL1, 7, 0, 0), 1210ec4016ffSMarek Szyprowski }; 1211ec4016ffSMarek Szyprowski 1212ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { 1213ec4016ffSMarek Szyprowski { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ 1214ec4016ffSMarek Szyprowski { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ 1215ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ 1216ec4016ffSMarek Szyprowski { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ 1217ec4016ffSMarek Szyprowski }; 1218ec4016ffSMarek Szyprowski 1219ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { 1220ec4016ffSMarek Szyprowski DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 1221ec4016ffSMarek Szyprowski }; 1222ec4016ffSMarek Szyprowski 1223ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { 1224cba9d2faSAndrzej Hajda GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 12251d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 12261d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 1227ec4016ffSMarek Szyprowski }; 12281609027fSChander Kashyap 1229ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { 1230ec4016ffSMarek Szyprowski { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ 1231ec4016ffSMarek Szyprowski { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ 1232ec4016ffSMarek Szyprowski { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ 1233ec4016ffSMarek Szyprowski }; 1234ec4016ffSMarek Szyprowski 1235ec4016ffSMarek Szyprowski static const struct exynos5_subcmu_info exynos5x_subcmus[] = { 1236ec4016ffSMarek Szyprowski { 1237ec4016ffSMarek Szyprowski .div_clks = exynos5x_disp_div_clks, 1238ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), 1239ec4016ffSMarek Szyprowski .gate_clks = exynos5x_disp_gate_clks, 1240ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), 1241ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_disp_suspend_regs, 1242ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), 1243ec4016ffSMarek Szyprowski .pd_name = "DISP", 1244ec4016ffSMarek Szyprowski }, { 1245ec4016ffSMarek Szyprowski .div_clks = exynos5x_gsc_div_clks, 1246ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), 1247ec4016ffSMarek Szyprowski .gate_clks = exynos5x_gsc_gate_clks, 1248ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), 1249ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_gsc_suspend_regs, 1250ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), 1251ec4016ffSMarek Szyprowski .pd_name = "GSC", 1252ec4016ffSMarek Szyprowski }, { 1253ec4016ffSMarek Szyprowski .div_clks = exynos5x_mfc_div_clks, 1254ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), 1255ec4016ffSMarek Szyprowski .gate_clks = exynos5x_mfc_gate_clks, 1256ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), 1257ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_mfc_suspend_regs, 1258ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), 1259ec4016ffSMarek Szyprowski .pd_name = "MFC", 1260ec4016ffSMarek Szyprowski }, 12611609027fSChander Kashyap }; 12621609027fSChander Kashyap 1263ebd217e1SKrzysztof Kozlowski static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { 12641d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0), 12651d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0), 12661d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0), 12671d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), 12681d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 12691d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 12701d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 12711d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 12721d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1), 12731d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), 12741d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), 12751d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1), 12761d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), 12771d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 12781d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2), 12791d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), 12801d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), 12811d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3), 12821d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), 1283ca5b4029SThomas Abraham }; 1284ca5b4029SThomas Abraham 12859842452aSSylwester Nawrocki static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 12861d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), 12871d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), 12881d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), 12891d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671), 12901d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0), 12911d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), 12921d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671), 12931d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719), 12941d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0), 1295948e0684SSylwester Nawrocki PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923), 1296948e0684SSylwester Nawrocki PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762), 12971d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719), 12981d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690), 1299948e0684SSylwester Nawrocki PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762), 13001d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), 13019842452aSSylwester Nawrocki }; 13029842452aSSylwester Nawrocki 13036520e968SAlim Akhtar static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1304cba9d2faSAndrzej Hajda [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 13053ff6e0d8SYadwinder Singh Brar APLL_CON0, NULL), 1306cba9d2faSAndrzej Hajda [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1307cdf64eeeSChander Kashyap CPLL_CON0, NULL), 1308cba9d2faSAndrzej Hajda [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 13093ff6e0d8SYadwinder Singh Brar DPLL_CON0, NULL), 13109842452aSSylwester Nawrocki [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 13113ff6e0d8SYadwinder Singh Brar EPLL_CON0, NULL), 1312cba9d2faSAndrzej Hajda [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 13133ff6e0d8SYadwinder Singh Brar RPLL_CON0, NULL), 1314cba9d2faSAndrzej Hajda [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 13153ff6e0d8SYadwinder Singh Brar IPLL_CON0, NULL), 1316cba9d2faSAndrzej Hajda [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 13173ff6e0d8SYadwinder Singh Brar SPLL_CON0, NULL), 1318cba9d2faSAndrzej Hajda [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 13193ff6e0d8SYadwinder Singh Brar VPLL_CON0, NULL), 1320cba9d2faSAndrzej Hajda [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 13213ff6e0d8SYadwinder Singh Brar MPLL_CON0, NULL), 1322cba9d2faSAndrzej Hajda [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 13233ff6e0d8SYadwinder Singh Brar BPLL_CON0, NULL), 1324cba9d2faSAndrzej Hajda [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 13253ff6e0d8SYadwinder Singh Brar KPLL_CON0, NULL), 1326c898c6b7SYadwinder Singh Brar }; 1327c898c6b7SYadwinder Singh Brar 1328bee4f87fSThomas Abraham #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1329bee4f87fSThomas Abraham ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1330bee4f87fSThomas Abraham ((cpud) << 4))) 1331bee4f87fSThomas Abraham 1332bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1333bee4f87fSThomas Abraham { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1334bee4f87fSThomas Abraham { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1335bee4f87fSThomas Abraham { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1336bee4f87fSThomas Abraham { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1337bee4f87fSThomas Abraham { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1338bee4f87fSThomas Abraham { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1339bee4f87fSThomas Abraham { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1340bee4f87fSThomas Abraham { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1341bee4f87fSThomas Abraham { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1342bee4f87fSThomas Abraham { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1343bee4f87fSThomas Abraham { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1344bee4f87fSThomas Abraham { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1345bee4f87fSThomas Abraham { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1346bee4f87fSThomas Abraham { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1347bee4f87fSThomas Abraham { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1348bee4f87fSThomas Abraham { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1349bee4f87fSThomas Abraham { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1350bee4f87fSThomas Abraham { 0 }, 1351bee4f87fSThomas Abraham }; 1352bee4f87fSThomas Abraham 135354abbdb4SBartlomiej Zolnierkiewicz static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 135454abbdb4SBartlomiej Zolnierkiewicz { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 135554abbdb4SBartlomiej Zolnierkiewicz { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 135654abbdb4SBartlomiej Zolnierkiewicz { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 135754abbdb4SBartlomiej Zolnierkiewicz { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 135854abbdb4SBartlomiej Zolnierkiewicz { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 135954abbdb4SBartlomiej Zolnierkiewicz { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 136054abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 136154abbdb4SBartlomiej Zolnierkiewicz { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 136254abbdb4SBartlomiej Zolnierkiewicz { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 136354abbdb4SBartlomiej Zolnierkiewicz { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 136454abbdb4SBartlomiej Zolnierkiewicz { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 136554abbdb4SBartlomiej Zolnierkiewicz { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 136654abbdb4SBartlomiej Zolnierkiewicz { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 136754abbdb4SBartlomiej Zolnierkiewicz { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 136854abbdb4SBartlomiej Zolnierkiewicz { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 136954abbdb4SBartlomiej Zolnierkiewicz { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 137054abbdb4SBartlomiej Zolnierkiewicz { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 137154abbdb4SBartlomiej Zolnierkiewicz { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 137254abbdb4SBartlomiej Zolnierkiewicz { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 137354abbdb4SBartlomiej Zolnierkiewicz { 0 }, 137454abbdb4SBartlomiej Zolnierkiewicz }; 137554abbdb4SBartlomiej Zolnierkiewicz 1376bee4f87fSThomas Abraham #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1377bee4f87fSThomas Abraham ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1378bee4f87fSThomas Abraham 1379bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 138054abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1381bee4f87fSThomas Abraham { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1382bee4f87fSThomas Abraham { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1383bee4f87fSThomas Abraham { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1384bee4f87fSThomas Abraham { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1385bee4f87fSThomas Abraham { 900000, E5420_KFC_DIV(3, 5, 2), }, 1386bee4f87fSThomas Abraham { 800000, E5420_KFC_DIV(3, 5, 2), }, 1387bee4f87fSThomas Abraham { 700000, E5420_KFC_DIV(3, 4, 2), }, 1388bee4f87fSThomas Abraham { 600000, E5420_KFC_DIV(3, 4, 2), }, 1389bee4f87fSThomas Abraham { 500000, E5420_KFC_DIV(3, 4, 2), }, 1390bee4f87fSThomas Abraham { 400000, E5420_KFC_DIV(3, 3, 2), }, 1391bee4f87fSThomas Abraham { 300000, E5420_KFC_DIV(3, 3, 2), }, 1392bee4f87fSThomas Abraham { 200000, E5420_KFC_DIV(3, 3, 2), }, 1393bee4f87fSThomas Abraham { 0 }, 1394bee4f87fSThomas Abraham }; 1395bee4f87fSThomas Abraham 1396305cfab0SKrzysztof Kozlowski static const struct of_device_id ext_clk_match[] __initconst = { 13971609027fSChander Kashyap { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 13981609027fSChander Kashyap { }, 13991609027fSChander Kashyap }; 14001609027fSChander Kashyap 14011609027fSChander Kashyap /* register exynos5420 clocks */ 14026520e968SAlim Akhtar static void __init exynos5x_clk_init(struct device_node *np, 14036520e968SAlim Akhtar enum exynos5x_soc soc) 14041609027fSChander Kashyap { 1405976face4SRahul Sharma struct samsung_clk_provider *ctx; 1406976face4SRahul Sharma 14071609027fSChander Kashyap if (np) { 14081609027fSChander Kashyap reg_base = of_iomap(np, 0); 14091609027fSChander Kashyap if (!reg_base) 14101609027fSChander Kashyap panic("%s: failed to map registers\n", __func__); 14111609027fSChander Kashyap } else { 14121609027fSChander Kashyap panic("%s: unable to determine soc\n", __func__); 14131609027fSChander Kashyap } 14141609027fSChander Kashyap 14156520e968SAlim Akhtar exynos5x_soc = soc; 14166520e968SAlim Akhtar 1417976face4SRahul Sharma ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1418976face4SRahul Sharma 14196520e968SAlim Akhtar samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 14206520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 14211609027fSChander Kashyap ext_clk_match); 1422ca5b4029SThomas Abraham 1423ca5b4029SThomas Abraham if (_get_rate("fin_pll") == 24 * MHZ) { 1424ca5b4029SThomas Abraham exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 14259842452aSSylwester Nawrocki exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; 1426ca5b4029SThomas Abraham exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1427e867e8faSChanwoo Choi exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1428ca5b4029SThomas Abraham } 1429ca5b4029SThomas Abraham 14306520e968SAlim Akhtar samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1431c898c6b7SYadwinder Singh Brar reg_base); 14326520e968SAlim Akhtar samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 14336520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_clks)); 14346520e968SAlim Akhtar samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 14356520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_factor_clks)); 14366520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5x_mux_clks, 14376520e968SAlim Akhtar ARRAY_SIZE(exynos5x_mux_clks)); 14386520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5x_div_clks, 14396520e968SAlim Akhtar ARRAY_SIZE(exynos5x_div_clks)); 14406520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5x_gate_clks, 14416520e968SAlim Akhtar ARRAY_SIZE(exynos5x_gate_clks)); 14426520e968SAlim Akhtar 14436520e968SAlim Akhtar if (soc == EXYNOS5420) { 1444976face4SRahul Sharma samsung_clk_register_mux(ctx, exynos5420_mux_clks, 14451609027fSChander Kashyap ARRAY_SIZE(exynos5420_mux_clks)); 1446976face4SRahul Sharma samsung_clk_register_div(ctx, exynos5420_div_clks, 14471609027fSChander Kashyap ARRAY_SIZE(exynos5420_div_clks)); 144841097f25SSylwester Nawrocki samsung_clk_register_gate(ctx, exynos5420_gate_clks, 144941097f25SSylwester Nawrocki ARRAY_SIZE(exynos5420_gate_clks)); 14506520e968SAlim Akhtar } else { 14516520e968SAlim Akhtar samsung_clk_register_fixed_factor( 14526520e968SAlim Akhtar ctx, exynos5800_fixed_factor_clks, 14536520e968SAlim Akhtar ARRAY_SIZE(exynos5800_fixed_factor_clks)); 14546520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5800_mux_clks, 14556520e968SAlim Akhtar ARRAY_SIZE(exynos5800_mux_clks)); 14566520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5800_div_clks, 14576520e968SAlim Akhtar ARRAY_SIZE(exynos5800_div_clks)); 14586520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5800_gate_clks, 14596520e968SAlim Akhtar ARRAY_SIZE(exynos5800_gate_clks)); 14606520e968SAlim Akhtar } 1461388c7885STomasz Figa 146254abbdb4SBartlomiej Zolnierkiewicz if (soc == EXYNOS5420) { 1463bee4f87fSThomas Abraham exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1464bee4f87fSThomas Abraham mout_cpu_p[0], mout_cpu_p[1], 0x200, 1465bee4f87fSThomas Abraham exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); 146654abbdb4SBartlomiej Zolnierkiewicz } else { 146754abbdb4SBartlomiej Zolnierkiewicz exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 146854abbdb4SBartlomiej Zolnierkiewicz mout_cpu_p[0], mout_cpu_p[1], 0x200, 146954abbdb4SBartlomiej Zolnierkiewicz exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); 147054abbdb4SBartlomiej Zolnierkiewicz } 1471bee4f87fSThomas Abraham exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", 1472bee4f87fSThomas Abraham mout_kfc_p[0], mout_kfc_p[1], 0x28200, 1473bee4f87fSThomas Abraham exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); 1474bee4f87fSThomas Abraham 14752d77f77cSMarek Szyprowski samsung_clk_extended_sleep_init(reg_base, 14762d77f77cSMarek Szyprowski exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs), 14772d77f77cSMarek Szyprowski exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); 14782d77f77cSMarek Szyprowski if (soc == EXYNOS5800) 14792d77f77cSMarek Szyprowski samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, 14802d77f77cSMarek Szyprowski ARRAY_SIZE(exynos5800_clk_regs)); 1481ec4016ffSMarek Szyprowski exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), 1482ec4016ffSMarek Szyprowski exynos5x_subcmus); 1483d5e136a2SSylwester Nawrocki 1484d5e136a2SSylwester Nawrocki samsung_clk_of_add_provider(np, ctx); 14851609027fSChander Kashyap } 14866520e968SAlim Akhtar 14876520e968SAlim Akhtar static void __init exynos5420_clk_init(struct device_node *np) 14886520e968SAlim Akhtar { 14896520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5420); 14906520e968SAlim Akhtar } 1491ec4016ffSMarek Szyprowski CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", 1492ec4016ffSMarek Szyprowski exynos5420_clk_init); 14936520e968SAlim Akhtar 14946520e968SAlim Akhtar static void __init exynos5800_clk_init(struct device_node *np) 14956520e968SAlim Akhtar { 14966520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5800); 14976520e968SAlim Akhtar } 1498ec4016ffSMarek Szyprowski CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", 1499ec4016ffSMarek Szyprowski exynos5800_clk_init); 1500