11609027fSChander Kashyap /* 21609027fSChander Kashyap * Copyright (c) 2013 Samsung Electronics Co., Ltd. 31609027fSChander Kashyap * Authors: Thomas Abraham <thomas.ab@samsung.com> 41609027fSChander Kashyap * Chander Kashyap <k.chander@samsung.com> 51609027fSChander Kashyap * 61609027fSChander Kashyap * This program is free software; you can redistribute it and/or modify 71609027fSChander Kashyap * it under the terms of the GNU General Public License version 2 as 81609027fSChander Kashyap * published by the Free Software Foundation. 91609027fSChander Kashyap * 101609027fSChander Kashyap * Common Clock Framework support for Exynos5420 SoC. 111609027fSChander Kashyap */ 121609027fSChander Kashyap 13cba9d2faSAndrzej Hajda #include <dt-bindings/clock/exynos5420.h> 146f1ed07aSStephen Boyd #include <linux/slab.h> 151609027fSChander Kashyap #include <linux/clk-provider.h> 161609027fSChander Kashyap #include <linux/of.h> 171609027fSChander Kashyap #include <linux/of_address.h> 18388c7885STomasz Figa #include <linux/syscore_ops.h> 191609027fSChander Kashyap 201609027fSChander Kashyap #include "clk.h" 21bee4f87fSThomas Abraham #include "clk-cpu.h" 221609027fSChander Kashyap 23c898c6b7SYadwinder Singh Brar #define APLL_LOCK 0x0 24c898c6b7SYadwinder Singh Brar #define APLL_CON0 0x100 251609027fSChander Kashyap #define SRC_CPU 0x200 261609027fSChander Kashyap #define DIV_CPU0 0x500 271609027fSChander Kashyap #define DIV_CPU1 0x504 281609027fSChander Kashyap #define GATE_BUS_CPU 0x700 291609027fSChander Kashyap #define GATE_SCLK_CPU 0x800 3077342432SShaik Ameer Basha #define CLKOUT_CMU_CPU 0xa00 31e9d52956SVikas Sajjan #define SRC_MASK_CPERI 0x4300 325b73721bSNaveen Krishna Chatradhi #define GATE_IP_G2D 0x8800 33c898c6b7SYadwinder Singh Brar #define CPLL_LOCK 0x10020 34c898c6b7SYadwinder Singh Brar #define DPLL_LOCK 0x10030 35c898c6b7SYadwinder Singh Brar #define EPLL_LOCK 0x10040 36c898c6b7SYadwinder Singh Brar #define RPLL_LOCK 0x10050 37c898c6b7SYadwinder Singh Brar #define IPLL_LOCK 0x10060 38c898c6b7SYadwinder Singh Brar #define SPLL_LOCK 0x10070 3953cb6342SSachin Kamat #define VPLL_LOCK 0x10080 40c898c6b7SYadwinder Singh Brar #define MPLL_LOCK 0x10090 41c898c6b7SYadwinder Singh Brar #define CPLL_CON0 0x10120 42c898c6b7SYadwinder Singh Brar #define DPLL_CON0 0x10128 43c898c6b7SYadwinder Singh Brar #define EPLL_CON0 0x10130 4477342432SShaik Ameer Basha #define EPLL_CON1 0x10134 4577342432SShaik Ameer Basha #define EPLL_CON2 0x10138 46c898c6b7SYadwinder Singh Brar #define RPLL_CON0 0x10140 4777342432SShaik Ameer Basha #define RPLL_CON1 0x10144 4877342432SShaik Ameer Basha #define RPLL_CON2 0x10148 49c898c6b7SYadwinder Singh Brar #define IPLL_CON0 0x10150 50c898c6b7SYadwinder Singh Brar #define SPLL_CON0 0x10160 51c898c6b7SYadwinder Singh Brar #define VPLL_CON0 0x10170 52c898c6b7SYadwinder Singh Brar #define MPLL_CON0 0x10180 531609027fSChander Kashyap #define SRC_TOP0 0x10200 541609027fSChander Kashyap #define SRC_TOP1 0x10204 551609027fSChander Kashyap #define SRC_TOP2 0x10208 561609027fSChander Kashyap #define SRC_TOP3 0x1020c 571609027fSChander Kashyap #define SRC_TOP4 0x10210 581609027fSChander Kashyap #define SRC_TOP5 0x10214 591609027fSChander Kashyap #define SRC_TOP6 0x10218 601609027fSChander Kashyap #define SRC_TOP7 0x1021c 616520e968SAlim Akhtar #define SRC_TOP8 0x10220 /* 5800 specific */ 626520e968SAlim Akhtar #define SRC_TOP9 0x10224 /* 5800 specific */ 631609027fSChander Kashyap #define SRC_DISP10 0x1022c 641609027fSChander Kashyap #define SRC_MAU 0x10240 651609027fSChander Kashyap #define SRC_FSYS 0x10244 661609027fSChander Kashyap #define SRC_PERIC0 0x10250 671609027fSChander Kashyap #define SRC_PERIC1 0x10254 683a767b35SShaik Ameer Basha #define SRC_ISP 0x10270 696520e968SAlim Akhtar #define SRC_CAM 0x10274 /* 5800 specific */ 701609027fSChander Kashyap #define SRC_TOP10 0x10280 711609027fSChander Kashyap #define SRC_TOP11 0x10284 721609027fSChander Kashyap #define SRC_TOP12 0x10288 736520e968SAlim Akhtar #define SRC_TOP13 0x1028c /* 5800 specific */ 74e9d52956SVikas Sajjan #define SRC_MASK_TOP0 0x10300 75e9d52956SVikas Sajjan #define SRC_MASK_TOP1 0x10304 76424b673aSShaik Ameer Basha #define SRC_MASK_TOP2 0x10308 7731116a64SShaik Ameer Basha #define SRC_MASK_TOP7 0x1031c 781609027fSChander Kashyap #define SRC_MASK_DISP10 0x1032c 7931116a64SShaik Ameer Basha #define SRC_MASK_MAU 0x10334 801609027fSChander Kashyap #define SRC_MASK_FSYS 0x10340 811609027fSChander Kashyap #define SRC_MASK_PERIC0 0x10350 821609027fSChander Kashyap #define SRC_MASK_PERIC1 0x10354 83e9d52956SVikas Sajjan #define SRC_MASK_ISP 0x10370 841609027fSChander Kashyap #define DIV_TOP0 0x10500 851609027fSChander Kashyap #define DIV_TOP1 0x10504 861609027fSChander Kashyap #define DIV_TOP2 0x10508 876520e968SAlim Akhtar #define DIV_TOP8 0x10520 /* 5800 specific */ 886520e968SAlim Akhtar #define DIV_TOP9 0x10524 /* 5800 specific */ 891609027fSChander Kashyap #define DIV_DISP10 0x1052c 901609027fSChander Kashyap #define DIV_MAU 0x10544 911609027fSChander Kashyap #define DIV_FSYS0 0x10548 921609027fSChander Kashyap #define DIV_FSYS1 0x1054c 931609027fSChander Kashyap #define DIV_FSYS2 0x10550 941609027fSChander Kashyap #define DIV_PERIC0 0x10558 951609027fSChander Kashyap #define DIV_PERIC1 0x1055c 961609027fSChander Kashyap #define DIV_PERIC2 0x10560 971609027fSChander Kashyap #define DIV_PERIC3 0x10564 981609027fSChander Kashyap #define DIV_PERIC4 0x10568 996520e968SAlim Akhtar #define DIV_CAM 0x10574 /* 5800 specific */ 1003a767b35SShaik Ameer Basha #define SCLK_DIV_ISP0 0x10580 1013a767b35SShaik Ameer Basha #define SCLK_DIV_ISP1 0x10584 10202932381SShaik Ameer Basha #define DIV2_RATIO0 0x10590 1031d87db4dSShaik Ameer Basha #define DIV4_RATIO 0x105a0 1041609027fSChander Kashyap #define GATE_BUS_TOP 0x10700 105e9d52956SVikas Sajjan #define GATE_BUS_DISP1 0x10728 1060a22c306SShaik Ameer Basha #define GATE_BUS_GEN 0x1073c 1071609027fSChander Kashyap #define GATE_BUS_FSYS0 0x10740 1086b5ae463SShaik Ameer Basha #define GATE_BUS_FSYS2 0x10748 1091609027fSChander Kashyap #define GATE_BUS_PERIC 0x10750 1101609027fSChander Kashyap #define GATE_BUS_PERIC1 0x10754 1111609027fSChander Kashyap #define GATE_BUS_PERIS0 0x10760 1121609027fSChander Kashyap #define GATE_BUS_PERIS1 0x10764 1136575fa76SShaik Ameer Basha #define GATE_BUS_NOC 0x10770 1143a767b35SShaik Ameer Basha #define GATE_TOP_SCLK_ISP 0x10870 1151609027fSChander Kashyap #define GATE_IP_GSCL0 0x10910 1161609027fSChander Kashyap #define GATE_IP_GSCL1 0x10920 1176520e968SAlim Akhtar #define GATE_IP_CAM 0x10924 /* 5800 specific */ 1181609027fSChander Kashyap #define GATE_IP_MFC 0x1092c 1191609027fSChander Kashyap #define GATE_IP_DISP1 0x10928 1201609027fSChander Kashyap #define GATE_IP_G3D 0x10930 1211609027fSChander Kashyap #define GATE_IP_GEN 0x10934 1226b5ae463SShaik Ameer Basha #define GATE_IP_FSYS 0x10944 123faec151bSShaik Ameer Basha #define GATE_IP_PERIC 0x10950 1240a22c306SShaik Ameer Basha #define GATE_IP_PERIS 0x10960 1251609027fSChander Kashyap #define GATE_IP_MSCL 0x10970 1261609027fSChander Kashyap #define GATE_TOP_SCLK_GSCL 0x10820 1271609027fSChander Kashyap #define GATE_TOP_SCLK_DISP1 0x10828 1281609027fSChander Kashyap #define GATE_TOP_SCLK_MAU 0x1083c 1291609027fSChander Kashyap #define GATE_TOP_SCLK_FSYS 0x10840 1301609027fSChander Kashyap #define GATE_TOP_SCLK_PERIC 0x10850 131424b673aSShaik Ameer Basha #define TOP_SPARE2 0x10b08 132c898c6b7SYadwinder Singh Brar #define BPLL_LOCK 0x20010 133c898c6b7SYadwinder Singh Brar #define BPLL_CON0 0x20110 134c898c6b7SYadwinder Singh Brar #define KPLL_LOCK 0x28000 135c898c6b7SYadwinder Singh Brar #define KPLL_CON0 0x28100 1361609027fSChander Kashyap #define SRC_KFC 0x28200 1371609027fSChander Kashyap #define DIV_KFC0 0x28500 1381609027fSChander Kashyap 1396520e968SAlim Akhtar /* Exynos5x SoC type */ 1406520e968SAlim Akhtar enum exynos5x_soc { 1416520e968SAlim Akhtar EXYNOS5420, 1426520e968SAlim Akhtar EXYNOS5800, 1436520e968SAlim Akhtar }; 1446520e968SAlim Akhtar 145c898c6b7SYadwinder Singh Brar /* list of PLLs */ 1466520e968SAlim Akhtar enum exynos5x_plls { 147c898c6b7SYadwinder Singh Brar apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 148c898c6b7SYadwinder Singh Brar bpll, kpll, 149c898c6b7SYadwinder Singh Brar nr_plls /* number of PLLs */ 150c898c6b7SYadwinder Singh Brar }; 151c898c6b7SYadwinder Singh Brar 152388c7885STomasz Figa static void __iomem *reg_base; 1536520e968SAlim Akhtar static enum exynos5x_soc exynos5x_soc; 154388c7885STomasz Figa 155388c7885STomasz Figa #ifdef CONFIG_PM_SLEEP 1566520e968SAlim Akhtar static struct samsung_clk_reg_dump *exynos5x_save; 1576520e968SAlim Akhtar static struct samsung_clk_reg_dump *exynos5800_save; 158388c7885STomasz Figa 1591609027fSChander Kashyap /* 1601609027fSChander Kashyap * list of controller registers to be saved and restored during a 1611609027fSChander Kashyap * suspend/resume cycle. 1621609027fSChander Kashyap */ 163ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5x_clk_regs[] __initconst = { 1641609027fSChander Kashyap SRC_CPU, 1651609027fSChander Kashyap DIV_CPU0, 1661609027fSChander Kashyap DIV_CPU1, 1671609027fSChander Kashyap GATE_BUS_CPU, 1681609027fSChander Kashyap GATE_SCLK_CPU, 16977342432SShaik Ameer Basha CLKOUT_CMU_CPU, 17077342432SShaik Ameer Basha EPLL_CON0, 17177342432SShaik Ameer Basha EPLL_CON1, 17277342432SShaik Ameer Basha EPLL_CON2, 17377342432SShaik Ameer Basha RPLL_CON0, 17477342432SShaik Ameer Basha RPLL_CON1, 17577342432SShaik Ameer Basha RPLL_CON2, 1761609027fSChander Kashyap SRC_TOP0, 1771609027fSChander Kashyap SRC_TOP1, 1781609027fSChander Kashyap SRC_TOP2, 1791609027fSChander Kashyap SRC_TOP3, 1801609027fSChander Kashyap SRC_TOP4, 1811609027fSChander Kashyap SRC_TOP5, 1821609027fSChander Kashyap SRC_TOP6, 1831609027fSChander Kashyap SRC_TOP7, 1841609027fSChander Kashyap SRC_DISP10, 1851609027fSChander Kashyap SRC_MAU, 1861609027fSChander Kashyap SRC_FSYS, 1871609027fSChander Kashyap SRC_PERIC0, 1881609027fSChander Kashyap SRC_PERIC1, 1891609027fSChander Kashyap SRC_TOP10, 1901609027fSChander Kashyap SRC_TOP11, 1911609027fSChander Kashyap SRC_TOP12, 192424b673aSShaik Ameer Basha SRC_MASK_TOP2, 19331116a64SShaik Ameer Basha SRC_MASK_TOP7, 1941609027fSChander Kashyap SRC_MASK_DISP10, 1951609027fSChander Kashyap SRC_MASK_FSYS, 1961609027fSChander Kashyap SRC_MASK_PERIC0, 1971609027fSChander Kashyap SRC_MASK_PERIC1, 198e9d52956SVikas Sajjan SRC_MASK_TOP0, 199e9d52956SVikas Sajjan SRC_MASK_TOP1, 200e9d52956SVikas Sajjan SRC_MASK_MAU, 201e9d52956SVikas Sajjan SRC_MASK_ISP, 2023a767b35SShaik Ameer Basha SRC_ISP, 2031609027fSChander Kashyap DIV_TOP0, 2041609027fSChander Kashyap DIV_TOP1, 2051609027fSChander Kashyap DIV_TOP2, 2061609027fSChander Kashyap DIV_DISP10, 2071609027fSChander Kashyap DIV_MAU, 2081609027fSChander Kashyap DIV_FSYS0, 2091609027fSChander Kashyap DIV_FSYS1, 2101609027fSChander Kashyap DIV_FSYS2, 2111609027fSChander Kashyap DIV_PERIC0, 2121609027fSChander Kashyap DIV_PERIC1, 2131609027fSChander Kashyap DIV_PERIC2, 2141609027fSChander Kashyap DIV_PERIC3, 2151609027fSChander Kashyap DIV_PERIC4, 2163a767b35SShaik Ameer Basha SCLK_DIV_ISP0, 2173a767b35SShaik Ameer Basha SCLK_DIV_ISP1, 21802932381SShaik Ameer Basha DIV2_RATIO0, 2191d87db4dSShaik Ameer Basha DIV4_RATIO, 220e9d52956SVikas Sajjan GATE_BUS_DISP1, 2211609027fSChander Kashyap GATE_BUS_TOP, 2220a22c306SShaik Ameer Basha GATE_BUS_GEN, 2231609027fSChander Kashyap GATE_BUS_FSYS0, 2246b5ae463SShaik Ameer Basha GATE_BUS_FSYS2, 2251609027fSChander Kashyap GATE_BUS_PERIC, 2261609027fSChander Kashyap GATE_BUS_PERIC1, 2271609027fSChander Kashyap GATE_BUS_PERIS0, 2281609027fSChander Kashyap GATE_BUS_PERIS1, 2296575fa76SShaik Ameer Basha GATE_BUS_NOC, 2303a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2311609027fSChander Kashyap GATE_IP_GSCL0, 2321609027fSChander Kashyap GATE_IP_GSCL1, 2331609027fSChander Kashyap GATE_IP_MFC, 2341609027fSChander Kashyap GATE_IP_DISP1, 2351609027fSChander Kashyap GATE_IP_G3D, 2361609027fSChander Kashyap GATE_IP_GEN, 2376b5ae463SShaik Ameer Basha GATE_IP_FSYS, 238faec151bSShaik Ameer Basha GATE_IP_PERIC, 2390a22c306SShaik Ameer Basha GATE_IP_PERIS, 2401609027fSChander Kashyap GATE_IP_MSCL, 2411609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 2421609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 2431609027fSChander Kashyap GATE_TOP_SCLK_MAU, 2441609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2451609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 246424b673aSShaik Ameer Basha TOP_SPARE2, 2471609027fSChander Kashyap SRC_KFC, 2481609027fSChander Kashyap DIV_KFC0, 2491609027fSChander Kashyap }; 2501609027fSChander Kashyap 251ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5800_clk_regs[] __initconst = { 2526520e968SAlim Akhtar SRC_TOP8, 2536520e968SAlim Akhtar SRC_TOP9, 2546520e968SAlim Akhtar SRC_CAM, 2556520e968SAlim Akhtar SRC_TOP1, 2566520e968SAlim Akhtar DIV_TOP8, 2576520e968SAlim Akhtar DIV_TOP9, 2586520e968SAlim Akhtar DIV_CAM, 2596520e968SAlim Akhtar GATE_IP_CAM, 2606520e968SAlim Akhtar }; 2616520e968SAlim Akhtar 262e9d52956SVikas Sajjan static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 263e9d52956SVikas Sajjan { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 264e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 265e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 266e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 267e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 268e9d52956SVikas Sajjan { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 269e9d52956SVikas Sajjan { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 270e9d52956SVikas Sajjan { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 271e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 272e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 273e9d52956SVikas Sajjan { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 27497372e5aSJavier Martinez Canillas { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 275e9d52956SVikas Sajjan { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 276e9d52956SVikas Sajjan { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 277e9d52956SVikas Sajjan }; 278e9d52956SVikas Sajjan 279388c7885STomasz Figa static int exynos5420_clk_suspend(void) 280388c7885STomasz Figa { 2816520e968SAlim Akhtar samsung_clk_save(reg_base, exynos5x_save, 2826520e968SAlim Akhtar ARRAY_SIZE(exynos5x_clk_regs)); 2836520e968SAlim Akhtar 2846520e968SAlim Akhtar if (exynos5x_soc == EXYNOS5800) 2856520e968SAlim Akhtar samsung_clk_save(reg_base, exynos5800_save, 2866520e968SAlim Akhtar ARRAY_SIZE(exynos5800_clk_regs)); 287388c7885STomasz Figa 288e9d52956SVikas Sajjan samsung_clk_restore(reg_base, exynos5420_set_clksrc, 289e9d52956SVikas Sajjan ARRAY_SIZE(exynos5420_set_clksrc)); 290e9d52956SVikas Sajjan 291388c7885STomasz Figa return 0; 292388c7885STomasz Figa } 293388c7885STomasz Figa 294388c7885STomasz Figa static void exynos5420_clk_resume(void) 295388c7885STomasz Figa { 2966520e968SAlim Akhtar samsung_clk_restore(reg_base, exynos5x_save, 2976520e968SAlim Akhtar ARRAY_SIZE(exynos5x_clk_regs)); 2986520e968SAlim Akhtar 2996520e968SAlim Akhtar if (exynos5x_soc == EXYNOS5800) 3006520e968SAlim Akhtar samsung_clk_restore(reg_base, exynos5800_save, 3016520e968SAlim Akhtar ARRAY_SIZE(exynos5800_clk_regs)); 302388c7885STomasz Figa } 303388c7885STomasz Figa 304388c7885STomasz Figa static struct syscore_ops exynos5420_clk_syscore_ops = { 305388c7885STomasz Figa .suspend = exynos5420_clk_suspend, 306388c7885STomasz Figa .resume = exynos5420_clk_resume, 307388c7885STomasz Figa }; 308388c7885STomasz Figa 309388c7885STomasz Figa static void exynos5420_clk_sleep_init(void) 310388c7885STomasz Figa { 3116520e968SAlim Akhtar exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs, 3126520e968SAlim Akhtar ARRAY_SIZE(exynos5x_clk_regs)); 3136520e968SAlim Akhtar if (!exynos5x_save) { 314388c7885STomasz Figa pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 315388c7885STomasz Figa __func__); 316388c7885STomasz Figa return; 317388c7885STomasz Figa } 318388c7885STomasz Figa 3196520e968SAlim Akhtar if (exynos5x_soc == EXYNOS5800) { 3206520e968SAlim Akhtar exynos5800_save = 3216520e968SAlim Akhtar samsung_clk_alloc_reg_dump(exynos5800_clk_regs, 3226520e968SAlim Akhtar ARRAY_SIZE(exynos5800_clk_regs)); 3236520e968SAlim Akhtar if (!exynos5800_save) 3246520e968SAlim Akhtar goto err_soc; 3256520e968SAlim Akhtar } 3266520e968SAlim Akhtar 327388c7885STomasz Figa register_syscore_ops(&exynos5420_clk_syscore_ops); 3286520e968SAlim Akhtar return; 3296520e968SAlim Akhtar err_soc: 3306520e968SAlim Akhtar kfree(exynos5x_save); 3316520e968SAlim Akhtar pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 3326520e968SAlim Akhtar __func__); 3336520e968SAlim Akhtar return; 334388c7885STomasz Figa } 335388c7885STomasz Figa #else 336388c7885STomasz Figa static void exynos5420_clk_sleep_init(void) {} 337388c7885STomasz Figa #endif 338388c7885STomasz Figa 3391609027fSChander Kashyap /* list of all parent clocks */ 340dbd713bbSShaik Ameer Basha PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 341dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 342dbd713bbSShaik Ameer Basha PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 343dbd713bbSShaik Ameer Basha PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 344dbd713bbSShaik Ameer Basha PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 345dbd713bbSShaik Ameer Basha PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 346dbd713bbSShaik Ameer Basha PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 347dbd713bbSShaik Ameer Basha PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 348dbd713bbSShaik Ameer Basha PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 349dbd713bbSShaik Ameer Basha PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 350dbd713bbSShaik Ameer Basha PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 351dbd713bbSShaik Ameer Basha PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 352dbd713bbSShaik Ameer Basha PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 353dbd713bbSShaik Ameer Basha PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 354dbd713bbSShaik Ameer Basha PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 3551609027fSChander Kashyap 356dbd713bbSShaik Ameer Basha PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 357dbd713bbSShaik Ameer Basha "mout_sclk_mpll"}; 358dbd713bbSShaik Ameer Basha PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 359dbd713bbSShaik Ameer Basha "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 360dbd713bbSShaik Ameer Basha "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 361dbd713bbSShaik Ameer Basha PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 362dbd713bbSShaik Ameer Basha PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 363dbd713bbSShaik Ameer Basha PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 3641609027fSChander Kashyap 365424b673aSShaik Ameer Basha PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 366dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 367faec151bSShaik Ameer Basha PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 368b31ca2a0SShaik Ameer Basha PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 3691609027fSChander Kashyap 370dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 3716b5ae463SShaik Ameer Basha PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 3726b5ae463SShaik Ameer Basha PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 373dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 3741609027fSChander Kashyap 375dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 376dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 3776575fa76SShaik Ameer Basha PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 3786575fa76SShaik Ameer Basha PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 3796575fa76SShaik Ameer Basha 3806575fa76SShaik Ameer Basha PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 3816575fa76SShaik Ameer Basha PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 3826575fa76SShaik Ameer Basha PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 3836575fa76SShaik Ameer Basha 3843a767b35SShaik Ameer Basha PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 3853a767b35SShaik Ameer Basha PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 3863a767b35SShaik Ameer Basha 3873a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 3883a767b35SShaik Ameer Basha "mout_sclk_spll"}; 3893a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 3903a767b35SShaik Ameer Basha 3913a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 3923a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 3931609027fSChander Kashyap 394dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 395424b673aSShaik Ameer Basha PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 3961609027fSChander Kashyap 397dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 398dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 3991609027fSChander Kashyap 400dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 401dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 4021609027fSChander Kashyap 403dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 404dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 4051609027fSChander Kashyap 406dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 407dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 4083a767b35SShaik Ameer Basha PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 4091609027fSChander Kashyap 410dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 411dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 4121609027fSChander Kashyap 413dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 414dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 4151609027fSChander Kashyap 416dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 417424b673aSShaik Ameer Basha PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 418dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 419424b673aSShaik Ameer Basha PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 4201609027fSChander Kashyap 421dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 422dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 4231609027fSChander Kashyap 424dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 425dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 4261609027fSChander Kashyap 427dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 428dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 4291609027fSChander Kashyap 430dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 431dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 4321609027fSChander Kashyap 433dbd713bbSShaik Ameer Basha PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 434dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 435dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 436dbd713bbSShaik Ameer Basha PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 437dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 438dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 439dbd713bbSShaik Ameer Basha PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 440dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 441dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 442dbd713bbSShaik Ameer Basha PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 443dbd713bbSShaik Ameer Basha "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 444dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 445dbd713bbSShaik Ameer Basha PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 446dbd713bbSShaik Ameer Basha PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 447dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 448dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 44931116a64SShaik Ameer Basha PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 45031116a64SShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 4516520e968SAlim Akhtar /* List of parents specific to exynos5800 */ 4526520e968SAlim Akhtar PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 4536520e968SAlim Akhtar PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4546520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4556520e968SAlim Akhtar PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4566520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4576520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 4586520e968SAlim Akhtar PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4596520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4606520e968SAlim Akhtar "mout_epll2" }; 4616520e968SAlim Akhtar PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4626520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll" }; 4636520e968SAlim Akhtar PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 4646520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4656520e968SAlim Akhtar PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4666520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll", 4676520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 4686520e968SAlim Akhtar PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 4696520e968SAlim Akhtar "mout_sclk_mpll", 4706520e968SAlim Akhtar "ff_dout_spll2" }; 4716520e968SAlim Akhtar PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 4726520e968SAlim Akhtar PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 4736520e968SAlim Akhtar PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 4746520e968SAlim Akhtar PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 4756520e968SAlim Akhtar PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 4766520e968SAlim Akhtar PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 4776520e968SAlim Akhtar PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 4786520e968SAlim Akhtar PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 4791609027fSChander Kashyap 4801609027fSChander Kashyap /* fixed rate clocks generated outside the soc */ 4816520e968SAlim Akhtar static struct samsung_fixed_rate_clock 4826520e968SAlim Akhtar exynos5x_fixed_rate_ext_clks[] __initdata = { 483728f288dSStephen Boyd FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 4841609027fSChander Kashyap }; 4851609027fSChander Kashyap 4861609027fSChander Kashyap /* fixed rate clocks generated inside the soc */ 487ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { 488728f288dSStephen Boyd FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 489728f288dSStephen Boyd FRATE(0, "sclk_pwi", NULL, 0, 24000000), 490728f288dSStephen Boyd FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 491728f288dSStephen Boyd FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 492728f288dSStephen Boyd FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 4931609027fSChander Kashyap }; 4941609027fSChander Kashyap 495ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 496ad98c64fSKrzysztof Kozlowski exynos5x_fixed_factor_clks[] __initconst = { 497b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 498b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 4991609027fSChander Kashyap }; 5001609027fSChander Kashyap 501ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 502ad98c64fSKrzysztof Kozlowski exynos5800_fixed_factor_clks[] __initconst = { 5036520e968SAlim Akhtar FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 5046520e968SAlim Akhtar FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 5056520e968SAlim Akhtar }; 5066520e968SAlim Akhtar 507ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 5086520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 5096520e968SAlim Akhtar MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 5106520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 5116520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 5126520e968SAlim Akhtar 5136520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 5146520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 5156520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 5166520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 5176520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 5186520e968SAlim Akhtar 5196520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 5206520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 5216520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 5226520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 5236520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 5246520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 5256520e968SAlim Akhtar 5266520e968SAlim Akhtar MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7, 5276520e968SAlim Akhtar 20, 2), 5286520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 5296520e968SAlim Akhtar MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 5306520e968SAlim Akhtar 5316520e968SAlim Akhtar MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 5326520e968SAlim Akhtar MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 5336520e968SAlim Akhtar MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 5346520e968SAlim Akhtar MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 5356520e968SAlim Akhtar 5366520e968SAlim Akhtar MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 5376520e968SAlim Akhtar SRC_TOP9, 16, 1), 5386520e968SAlim Akhtar MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 5396520e968SAlim Akhtar SRC_TOP9, 20, 1), 5406520e968SAlim Akhtar MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 5416520e968SAlim Akhtar SRC_TOP9, 24, 1), 5426520e968SAlim Akhtar MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 5436520e968SAlim Akhtar SRC_TOP9, 28, 1), 5446520e968SAlim Akhtar 5456520e968SAlim Akhtar MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 5466520e968SAlim Akhtar MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 5476520e968SAlim Akhtar SRC_TOP13, 20, 1), 5486520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 5496520e968SAlim Akhtar SRC_TOP13, 24, 1), 5506520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 5516520e968SAlim Akhtar SRC_TOP13, 28, 1), 5526520e968SAlim Akhtar 5536520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 5546520e968SAlim Akhtar }; 5556520e968SAlim Akhtar 556ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { 55781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 55881fed6e3SChanwoo Choi "mout_aclk400_wcore", DIV_TOP0, 16, 3), 5596520e968SAlim Akhtar DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 5606520e968SAlim Akhtar DIV_TOP8, 16, 3), 5616520e968SAlim Akhtar DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 5626520e968SAlim Akhtar DIV_TOP8, 20, 3), 5636520e968SAlim Akhtar DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 5646520e968SAlim Akhtar DIV_TOP8, 24, 3), 5656520e968SAlim Akhtar DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 5666520e968SAlim Akhtar DIV_TOP8, 28, 3), 5676520e968SAlim Akhtar 5686520e968SAlim Akhtar DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 5696520e968SAlim Akhtar DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 5706520e968SAlim Akhtar }; 5716520e968SAlim Akhtar 572ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 5736520e968SAlim Akhtar GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 5746520e968SAlim Akhtar GATE_BUS_TOP, 24, 0, 0), 5756520e968SAlim Akhtar GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 5766520e968SAlim Akhtar GATE_BUS_TOP, 27, 0, 0), 5776520e968SAlim Akhtar }; 5786520e968SAlim Akhtar 579ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 5806520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 5816520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 5826520e968SAlim Akhtar TOP_SPARE2, 4, 1), 5836520e968SAlim Akhtar 5846520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 5856520e968SAlim Akhtar MUX_A(0, "mout_aclk400_mscl", mout_group1_p, 5866520e968SAlim Akhtar SRC_TOP0, 4, 2, "aclk400_mscl"), 5876520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 5886520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 5896520e968SAlim Akhtar 5906520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 5916520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group4_p, 5926520e968SAlim Akhtar SRC_TOP1, 4, 2), 5936520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 5946520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 5956520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 5966520e968SAlim Akhtar 5976520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 5986520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 5996520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 6006520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 6016520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 6026520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 6036520e968SAlim Akhtar 6046520e968SAlim Akhtar MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2), 6056520e968SAlim Akhtar 6066520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 6076520e968SAlim Akhtar }; 6086520e968SAlim Akhtar 609ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 61081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 61181fed6e3SChanwoo Choi "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 6126520e968SAlim Akhtar }; 6136520e968SAlim Akhtar 614ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 615b31ca2a0SShaik Ameer Basha MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 616b31ca2a0SShaik Ameer Basha SRC_TOP7, 4, 1), 617dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 618dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 61931116a64SShaik Ameer Basha 620bee4f87fSThomas Abraham MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 621bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 622dbd713bbSShaik Ameer Basha MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 623bee4f87fSThomas Abraham MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 624bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 625dbd713bbSShaik Ameer Basha MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 6261609027fSChander Kashyap 627dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 628dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 6296b5ae463SShaik Ameer Basha MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 630dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 6311609027fSChander Kashyap 632dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 633dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 6341609027fSChander Kashyap 635dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 6361609027fSChander Kashyap 6373a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 6383a767b35SShaik Ameer Basha SRC_TOP3, 0, 1), 639dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 6401609027fSChander Kashyap SRC_TOP3, 4, 1), 64188560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 64288560100SJavier Martinez Canillas mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 643dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 6441609027fSChander Kashyap SRC_TOP3, 12, 1), 6456575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 6466575fa76SShaik Ameer Basha SRC_TOP3, 16, 1), 6476575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 6486575fa76SShaik Ameer Basha SRC_TOP3, 20, 1), 6496b5ae463SShaik Ameer Basha MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 6506b5ae463SShaik Ameer Basha SRC_TOP3, 24, 1), 651dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 6521609027fSChander Kashyap SRC_TOP3, 28, 1), 6531609027fSChander Kashyap 654dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 6551609027fSChander Kashyap SRC_TOP4, 0, 1), 6563a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 6573a767b35SShaik Ameer Basha SRC_TOP4, 4, 1), 658faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 659faec151bSShaik Ameer Basha SRC_TOP4, 8, 1), 6603a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 6613a767b35SShaik Ameer Basha SRC_TOP4, 12, 1), 6623a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 6633a767b35SShaik Ameer Basha SRC_TOP4, 16, 1), 664dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 665dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 666c0fb262bSArun Kumar K MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 667c0fb262bSArun Kumar K SRC_TOP4, 28, 1), 6681609027fSChander Kashyap 66988560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 67088560100SJavier Martinez Canillas mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 671faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 672faec151bSShaik Ameer Basha SRC_TOP5, 4, 1), 6733fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 6743fac5941SShaik Ameer Basha SRC_TOP5, 8, 1), 6753fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 6763fac5941SShaik Ameer Basha SRC_TOP5, 12, 1), 6773fac5941SShaik Ameer Basha MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 6783fac5941SShaik Ameer Basha SRC_TOP5, 16, 1), 679dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 6801609027fSChander Kashyap SRC_TOP5, 20, 1), 68188560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 68288560100SJavier Martinez Canillas mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 683c0feb268SMarek Szyprowski MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 684c0feb268SMarek Szyprowski mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 6851609027fSChander Kashyap 686dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 687dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 688dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 689dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 690dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 691dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1), 692dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 693dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 6941609027fSChander Kashyap 6953a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 6963a767b35SShaik Ameer Basha SRC_TOP10, 0, 1), 697dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 698dbd713bbSShaik Ameer Basha SRC_TOP10, 4, 1), 69988560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 70088560100SJavier Martinez Canillas SRC_TOP10, 8, 1), 701dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 7021609027fSChander Kashyap SRC_TOP10, 12, 1), 7036575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 7046575fa76SShaik Ameer Basha SRC_TOP10, 16, 1), 7056575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 7066575fa76SShaik Ameer Basha SRC_TOP10, 20, 1), 7076b5ae463SShaik Ameer Basha MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 7086b5ae463SShaik Ameer Basha SRC_TOP10, 24, 1), 709dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 710dbd713bbSShaik Ameer Basha SRC_TOP10, 28, 1), 7113a767b35SShaik Ameer Basha 712dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 7131609027fSChander Kashyap SRC_TOP11, 0, 1), 7143a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 7153a767b35SShaik Ameer Basha SRC_TOP11, 4, 1), 716dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 7173a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 7183a767b35SShaik Ameer Basha SRC_TOP11, 12, 1), 719dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 720dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 721c0fb262bSArun Kumar K MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 722c0fb262bSArun Kumar K SRC_TOP11, 28, 1), 7231609027fSChander Kashyap 72488560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 72588560100SJavier Martinez Canillas mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 726dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 727dbd713bbSShaik Ameer Basha SRC_TOP12, 8, 1), 728dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 729dbd713bbSShaik Ameer Basha SRC_TOP12, 12, 1), 730dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 731dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 732dbd713bbSShaik Ameer Basha SRC_TOP12, 20, 1), 73388560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 73488560100SJavier Martinez Canillas mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 735c0feb268SMarek Szyprowski MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 736c0feb268SMarek Szyprowski mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 7371609027fSChander Kashyap 7381609027fSChander Kashyap /* DISP1 Block */ 739dbd713bbSShaik Ameer Basha MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 740dbd713bbSShaik Ameer Basha MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 741dbd713bbSShaik Ameer Basha MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 742dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 743424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 7446575fa76SShaik Ameer Basha 745424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 7461609027fSChander Kashyap 7471609027fSChander Kashyap /* MAU Block */ 74831116a64SShaik Ameer Basha MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 7491609027fSChander Kashyap 7501609027fSChander Kashyap /* FSYS Block */ 751dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 752dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 753dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 754dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 755dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 756dbd713bbSShaik Ameer Basha MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 7576b5ae463SShaik Ameer Basha MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 7581609027fSChander Kashyap 7591609027fSChander Kashyap /* PERIC Block */ 760dbd713bbSShaik Ameer Basha MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 761dbd713bbSShaik Ameer Basha MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 762dbd713bbSShaik Ameer Basha MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 763dbd713bbSShaik Ameer Basha MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 764dbd713bbSShaik Ameer Basha MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 765dbd713bbSShaik Ameer Basha MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 766dbd713bbSShaik Ameer Basha MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 767dbd713bbSShaik Ameer Basha MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 768dbd713bbSShaik Ameer Basha MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 769dbd713bbSShaik Ameer Basha MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 770dbd713bbSShaik Ameer Basha MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 771dbd713bbSShaik Ameer Basha MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 7723a767b35SShaik Ameer Basha 7733a767b35SShaik Ameer Basha /* ISP Block */ 7743a767b35SShaik Ameer Basha MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 7753a767b35SShaik Ameer Basha MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 7763a767b35SShaik Ameer Basha MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 7773a767b35SShaik Ameer Basha MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 7783a767b35SShaik Ameer Basha MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 7791609027fSChander Kashyap }; 7801609027fSChander Kashyap 781ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 782cba9d2faSAndrzej Hajda DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 783cba9d2faSAndrzej Hajda DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 784cba9d2faSAndrzej Hajda DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 785dbd713bbSShaik Ameer Basha DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 786cba9d2faSAndrzej Hajda DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 7871609027fSChander Kashyap 78881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 78981fed6e3SChanwoo Choi DIV_TOP0, 0, 3), 79081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 79181fed6e3SChanwoo Choi DIV_TOP0, 4, 3), 79281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 79381fed6e3SChanwoo Choi DIV_TOP0, 8, 3), 79481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 79581fed6e3SChanwoo Choi DIV_TOP0, 12, 3), 79681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 79781fed6e3SChanwoo Choi DIV_TOP0, 20, 3), 79881fed6e3SChanwoo Choi DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 79981fed6e3SChanwoo Choi DIV_TOP0, 24, 3), 80081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 80181fed6e3SChanwoo Choi DIV_TOP0, 28, 3), 80281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 80381fed6e3SChanwoo Choi "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 80481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 80581fed6e3SChanwoo Choi "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 80681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 80781fed6e3SChanwoo Choi DIV_TOP1, 8, 6), 80881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 80981fed6e3SChanwoo Choi "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 81081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 81181fed6e3SChanwoo Choi DIV_TOP1, 20, 3), 81281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 81381fed6e3SChanwoo Choi DIV_TOP1, 24, 3), 81481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 81581fed6e3SChanwoo Choi DIV_TOP1, 28, 3), 8161609027fSChander Kashyap 81781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 81881fed6e3SChanwoo Choi DIV_TOP2, 8, 3), 81981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 82081fed6e3SChanwoo Choi DIV_TOP2, 12, 3), 82181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 82281fed6e3SChanwoo Choi 16, 3), 82381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 82481fed6e3SChanwoo Choi DIV_TOP2, 20, 3), 82581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 82681fed6e3SChanwoo Choi "mout_aclk300_disp1", DIV_TOP2, 24, 3), 82781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 82881fed6e3SChanwoo Choi DIV_TOP2, 28, 3), 8291609027fSChander Kashyap 8301609027fSChander Kashyap /* DISP1 Block */ 831424b673aSShaik Ameer Basha DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 832cba9d2faSAndrzej Hajda DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 833cba9d2faSAndrzej Hajda DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 834cba9d2faSAndrzej Hajda DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 835424b673aSShaik Ameer Basha DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 83681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 83781fed6e3SChanwoo Choi "mout_aclk400_disp1", DIV_TOP2, 4, 3), 8381609027fSChander Kashyap 8391609027fSChander Kashyap /* Audio Block */ 840cba9d2faSAndrzej Hajda DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 841cba9d2faSAndrzej Hajda DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 8421609027fSChander Kashyap 8431609027fSChander Kashyap /* USB3.0 */ 844cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 845cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 846cba9d2faSAndrzej Hajda DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 847cba9d2faSAndrzej Hajda DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 8481609027fSChander Kashyap 8491609027fSChander Kashyap /* MMC */ 850cba9d2faSAndrzej Hajda DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 851cba9d2faSAndrzej Hajda DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 852cba9d2faSAndrzej Hajda DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 8531609027fSChander Kashyap 854cba9d2faSAndrzej Hajda DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 8556b5ae463SShaik Ameer Basha DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 8561609027fSChander Kashyap 8571609027fSChander Kashyap /* UART and PWM */ 858cba9d2faSAndrzej Hajda DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 859cba9d2faSAndrzej Hajda DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 860cba9d2faSAndrzej Hajda DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 861cba9d2faSAndrzej Hajda DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 862cba9d2faSAndrzej Hajda DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 8631609027fSChander Kashyap 8641609027fSChander Kashyap /* SPI */ 865cba9d2faSAndrzej Hajda DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 866cba9d2faSAndrzej Hajda DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 867cba9d2faSAndrzej Hajda DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 8681609027fSChander Kashyap 8691d87db4dSShaik Ameer Basha /* Mfc Block */ 8701d87db4dSShaik Ameer Basha DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 8711d87db4dSShaik Ameer Basha 8721609027fSChander Kashyap /* PCM */ 873cba9d2faSAndrzej Hajda DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 874cba9d2faSAndrzej Hajda DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 8751609027fSChander Kashyap 8761609027fSChander Kashyap /* Audio - I2S */ 877cba9d2faSAndrzej Hajda DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 878cba9d2faSAndrzej Hajda DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 879cba9d2faSAndrzej Hajda DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 880cba9d2faSAndrzej Hajda DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 881cba9d2faSAndrzej Hajda DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 8821609027fSChander Kashyap 8831609027fSChander Kashyap /* SPI Pre-Ratio */ 884faec151bSShaik Ameer Basha DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 885faec151bSShaik Ameer Basha DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 886faec151bSShaik Ameer Basha DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 8873a767b35SShaik Ameer Basha 88802932381SShaik Ameer Basha /* GSCL Block */ 88902932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 89002932381SShaik Ameer Basha DIV2_RATIO0, 4, 2), 89102932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 89202932381SShaik Ameer Basha 8934549d93dSShaik Ameer Basha /* MSCL Block */ 8944549d93dSShaik Ameer Basha DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 8954549d93dSShaik Ameer Basha 8960a22c306SShaik Ameer Basha /* PSGEN */ 8970a22c306SShaik Ameer Basha DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 8980a22c306SShaik Ameer Basha DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 8990a22c306SShaik Ameer Basha 9003a767b35SShaik Ameer Basha /* ISP Block */ 9013a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 9023a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 9033a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 9043a767b35SShaik Ameer Basha DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 9053a767b35SShaik Ameer Basha DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 9063a767b35SShaik Ameer Basha DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 9073a767b35SShaik Ameer Basha DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 9083a767b35SShaik Ameer Basha DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 9093a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 9103a767b35SShaik Ameer Basha DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 9113a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 9121609027fSChander Kashyap }; 9131609027fSChander Kashyap 914ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 9155b73721bSNaveen Krishna Chatradhi /* G2D */ 9163fac5941SShaik Ameer Basha GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 9175b73721bSNaveen Krishna Chatradhi GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 9183fac5941SShaik Ameer Basha GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 9193fac5941SShaik Ameer Basha GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 9203fac5941SShaik Ameer Basha GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 9215b73721bSNaveen Krishna Chatradhi 9221609027fSChander Kashyap GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 9231609027fSChander Kashyap GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 9241609027fSChander Kashyap GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 9251609027fSChander Kashyap GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 9261609027fSChander Kashyap 9271609027fSChander Kashyap GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 9281609027fSChander Kashyap GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 9291609027fSChander Kashyap GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 9301609027fSChander Kashyap GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), 9311609027fSChander Kashyap GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 9321609027fSChander Kashyap GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 9333a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 9343a767b35SShaik Ameer Basha GATE_BUS_TOP, 5, 0, 0), 9351609027fSChander Kashyap GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 9361609027fSChander Kashyap GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), 9371609027fSChander Kashyap GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 9381609027fSChander Kashyap GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 9393a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 9403a767b35SShaik Ameer Basha GATE_BUS_TOP, 8, 0, 0), 941b31ca2a0SShaik Ameer Basha GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 9421609027fSChander Kashyap GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 943faec151bSShaik Ameer Basha GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 9441609027fSChander Kashyap GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 9453a767b35SShaik Ameer Basha GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 9463a767b35SShaik Ameer Basha GATE_BUS_TOP, 13, 0, 0), 9471609027fSChander Kashyap GATE(0, "aclk166", "mout_user_aclk166", 9481609027fSChander Kashyap GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 94934d3b674SMarek Szyprowski GATE(0, "aclk333", "mout_user_aclk333", 9501609027fSChander Kashyap GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 9513a767b35SShaik Ameer Basha GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 9523a767b35SShaik Ameer Basha GATE_BUS_TOP, 16, 0, 0), 95302932381SShaik Ameer Basha GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 95402932381SShaik Ameer Basha GATE_BUS_TOP, 17, 0, 0), 955424b673aSShaik Ameer Basha GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 956424b673aSShaik Ameer Basha GATE_BUS_TOP, 18, 0, 0), 957b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 958b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 28, 0, 0), 959b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 960b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 29, 0, 0), 961424b673aSShaik Ameer Basha 962424b673aSShaik Ameer Basha GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 963424b673aSShaik Ameer Basha SRC_MASK_TOP2, 24, 0, 0), 9641609027fSChander Kashyap 96531116a64SShaik Ameer Basha GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 96631116a64SShaik Ameer Basha SRC_MASK_TOP7, 20, 0, 0), 96731116a64SShaik Ameer Basha 9681609027fSChander Kashyap /* sclk */ 969cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 9701609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 971cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 9721609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 973cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 9741609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 975cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 9761609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 977faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 9781609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 979faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 9801609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 981faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 9821609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 983cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 9841609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 985cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 9861609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 987cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 9881609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 989cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 9901609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 991cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 9921609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 993cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 9941609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 9951609027fSChander Kashyap 996cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 9971609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 998cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 9991609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 1000cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 10011609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 1002cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 10031609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 1004cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 10051609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 1006cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 10071609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 1008cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 10091609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 10101609027fSChander Kashyap 10111609027fSChander Kashyap /* Display */ 1012cba9d2faSAndrzej Hajda GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 10131609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 1014cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 10151609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 1016cba9d2faSAndrzej Hajda GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 1017424b673aSShaik Ameer Basha GATE_TOP_SCLK_DISP1, 9, 0, 0), 1018cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 10191609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 1020cba9d2faSAndrzej Hajda GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 10211609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 10221609027fSChander Kashyap 10231609027fSChander Kashyap /* Maudio Block */ 1024cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 10251609027fSChander Kashyap GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1026cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 10271609027fSChander Kashyap GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 10286b5ae463SShaik Ameer Basha 10296b5ae463SShaik Ameer Basha /* FSYS Block */ 1030cba9d2faSAndrzej Hajda GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1031cba9d2faSAndrzej Hajda GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1032cba9d2faSAndrzej Hajda GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1033cba9d2faSAndrzej Hajda GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 10346b5ae463SShaik Ameer Basha GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 10356b5ae463SShaik Ameer Basha GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 10366b5ae463SShaik Ameer Basha GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 10376b5ae463SShaik Ameer Basha GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1038cba9d2faSAndrzej Hajda GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 10396b5ae463SShaik Ameer Basha GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 10406b5ae463SShaik Ameer Basha GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 10416b5ae463SShaik Ameer Basha GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 10426b5ae463SShaik Ameer Basha GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 10436b5ae463SShaik Ameer Basha GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 10446b5ae463SShaik Ameer Basha SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 10451609027fSChander Kashyap 1046faec151bSShaik Ameer Basha /* PERIC Block */ 104744ff0254SDoug Anderson GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 104844ff0254SDoug Anderson GATE_IP_PERIC, 0, 0, 0), 104944ff0254SDoug Anderson GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 105044ff0254SDoug Anderson GATE_IP_PERIC, 1, 0, 0), 105144ff0254SDoug Anderson GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 105244ff0254SDoug Anderson GATE_IP_PERIC, 2, 0, 0), 105344ff0254SDoug Anderson GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 105444ff0254SDoug Anderson GATE_IP_PERIC, 3, 0, 0), 105544ff0254SDoug Anderson GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 105644ff0254SDoug Anderson GATE_IP_PERIC, 6, 0, 0), 105744ff0254SDoug Anderson GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 105844ff0254SDoug Anderson GATE_IP_PERIC, 7, 0, 0), 105944ff0254SDoug Anderson GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 106044ff0254SDoug Anderson GATE_IP_PERIC, 8, 0, 0), 106144ff0254SDoug Anderson GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 106244ff0254SDoug Anderson GATE_IP_PERIC, 9, 0, 0), 106344ff0254SDoug Anderson GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 106444ff0254SDoug Anderson GATE_IP_PERIC, 10, 0, 0), 106544ff0254SDoug Anderson GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 106644ff0254SDoug Anderson GATE_IP_PERIC, 11, 0, 0), 106744ff0254SDoug Anderson GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 106844ff0254SDoug Anderson GATE_IP_PERIC, 12, 0, 0), 106944ff0254SDoug Anderson GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 107044ff0254SDoug Anderson GATE_IP_PERIC, 13, 0, 0), 107144ff0254SDoug Anderson GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 107244ff0254SDoug Anderson GATE_IP_PERIC, 14, 0, 0), 107344ff0254SDoug Anderson GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 107444ff0254SDoug Anderson GATE_IP_PERIC, 15, 0, 0), 107544ff0254SDoug Anderson GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 107644ff0254SDoug Anderson GATE_IP_PERIC, 16, 0, 0), 107744ff0254SDoug Anderson GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 107844ff0254SDoug Anderson GATE_IP_PERIC, 17, 0, 0), 107944ff0254SDoug Anderson GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 108044ff0254SDoug Anderson GATE_IP_PERIC, 18, 0, 0), 108144ff0254SDoug Anderson GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 108244ff0254SDoug Anderson GATE_IP_PERIC, 20, 0, 0), 108344ff0254SDoug Anderson GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 108444ff0254SDoug Anderson GATE_IP_PERIC, 21, 0, 0), 108544ff0254SDoug Anderson GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 108644ff0254SDoug Anderson GATE_IP_PERIC, 22, 0, 0), 108744ff0254SDoug Anderson GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 108844ff0254SDoug Anderson GATE_IP_PERIC, 23, 0, 0), 108944ff0254SDoug Anderson GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 109044ff0254SDoug Anderson GATE_IP_PERIC, 24, 0, 0), 109144ff0254SDoug Anderson GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 109244ff0254SDoug Anderson GATE_IP_PERIC, 26, 0, 0), 109344ff0254SDoug Anderson GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 109444ff0254SDoug Anderson GATE_IP_PERIC, 28, 0, 0), 109544ff0254SDoug Anderson GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 109644ff0254SDoug Anderson GATE_IP_PERIC, 30, 0, 0), 109744ff0254SDoug Anderson GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 109844ff0254SDoug Anderson GATE_IP_PERIC, 31, 0, 0), 10991609027fSChander Kashyap 110044ff0254SDoug Anderson GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 110144ff0254SDoug Anderson GATE_BUS_PERIC, 22, 0, 0), 11021609027fSChander Kashyap 11030a22c306SShaik Ameer Basha /* PERIS Block */ 1104cba9d2faSAndrzej Hajda GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 11050a22c306SShaik Ameer Basha GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1106cba9d2faSAndrzej Hajda GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 11070a22c306SShaik Ameer Basha GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 11080a22c306SShaik Ameer Basha GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 11090a22c306SShaik Ameer Basha GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 11100a22c306SShaik Ameer Basha GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 11110a22c306SShaik Ameer Basha GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 11120a22c306SShaik Ameer Basha GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 11130a22c306SShaik Ameer Basha GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 11140a22c306SShaik Ameer Basha GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 11150a22c306SShaik Ameer Basha GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 11160a22c306SShaik Ameer Basha GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 11170a22c306SShaik Ameer Basha GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 11180a22c306SShaik Ameer Basha GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 11190a22c306SShaik Ameer Basha GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 11200a22c306SShaik Ameer Basha GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 11210a22c306SShaik Ameer Basha GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 11220a22c306SShaik Ameer Basha GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 11230a22c306SShaik Ameer Basha GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 11241609027fSChander Kashyap 1125cba9d2faSAndrzej Hajda GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 11260a22c306SShaik Ameer Basha 11270a22c306SShaik Ameer Basha /* GEN Block */ 11280a22c306SShaik Ameer Basha GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 11290a22c306SShaik Ameer Basha GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 11300a22c306SShaik Ameer Basha GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 11310a22c306SShaik Ameer Basha GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 11320a22c306SShaik Ameer Basha GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 11330a22c306SShaik Ameer Basha GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 11340a22c306SShaik Ameer Basha GATE_IP_GEN, 6, 0, 0), 11350a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 11360a22c306SShaik Ameer Basha GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 11370a22c306SShaik Ameer Basha GATE_IP_GEN, 9, 0, 0), 11380a22c306SShaik Ameer Basha 11390a22c306SShaik Ameer Basha /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 11400a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 11410a22c306SShaik Ameer Basha GATE_BUS_GEN, 28, 0, 0), 11420a22c306SShaik Ameer Basha GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 11431609027fSChander Kashyap 114402932381SShaik Ameer Basha /* GSCL Block */ 114502932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 114602932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 6, 0, 0), 114702932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 114802932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 7, 0, 0), 114902932381SShaik Ameer Basha 1150cba9d2faSAndrzej Hajda GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1151cba9d2faSAndrzej Hajda GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 115202932381SShaik Ameer Basha GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 115302932381SShaik Ameer Basha GATE_IP_GSCL0, 4, 0, 0), 115402932381SShaik Ameer Basha GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 115502932381SShaik Ameer Basha GATE_IP_GSCL0, 5, 0, 0), 115602932381SShaik Ameer Basha GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 115702932381SShaik Ameer Basha GATE_IP_GSCL0, 6, 0, 0), 11581609027fSChander Kashyap 115902932381SShaik Ameer Basha GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 116002932381SShaik Ameer Basha GATE_IP_GSCL1, 2, 0, 0), 116102932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 11621609027fSChander Kashyap GATE_IP_GSCL1, 3, 0, 0), 116302932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 11641609027fSChander Kashyap GATE_IP_GSCL1, 4, 0, 0), 116502932381SShaik Ameer Basha GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 116602932381SShaik Ameer Basha GATE_IP_GSCL1, 6, 0, 0), 116702932381SShaik Ameer Basha GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 116802932381SShaik Ameer Basha GATE_IP_GSCL1, 7, 0, 0), 116902932381SShaik Ameer Basha GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 117002932381SShaik Ameer Basha GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 117102932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 11721609027fSChander Kashyap GATE_IP_GSCL1, 16, 0, 0), 1173cba9d2faSAndrzej Hajda GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 11741609027fSChander Kashyap GATE_IP_GSCL1, 17, 0, 0), 11751609027fSChander Kashyap 117602932381SShaik Ameer Basha /* MSCL Block */ 117702932381SShaik Ameer Basha GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 117802932381SShaik Ameer Basha GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 117902932381SShaik Ameer Basha GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 11804549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 118102932381SShaik Ameer Basha GATE_IP_MSCL, 8, 0, 0), 11824549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 118302932381SShaik Ameer Basha GATE_IP_MSCL, 9, 0, 0), 11844549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 118502932381SShaik Ameer Basha GATE_IP_MSCL, 10, 0, 0), 118602932381SShaik Ameer Basha 1187cba9d2faSAndrzej Hajda GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1188cba9d2faSAndrzej Hajda GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1189cba9d2faSAndrzej Hajda GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1190424b673aSShaik Ameer Basha GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1191cba9d2faSAndrzej Hajda GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1192424b673aSShaik Ameer Basha GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1193424b673aSShaik Ameer Basha GATE_IP_DISP1, 7, 0, 0), 1194424b673aSShaik Ameer Basha GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1195424b673aSShaik Ameer Basha GATE_IP_DISP1, 8, 0, 0), 1196424b673aSShaik Ameer Basha GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1197424b673aSShaik Ameer Basha GATE_IP_DISP1, 9, 0, 0), 11981609027fSChander Kashyap 11993a767b35SShaik Ameer Basha /* ISP */ 12003a767b35SShaik Ameer Basha GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 12013a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 12023a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 12033a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 12043a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 12053a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 12063a767b35SShaik Ameer Basha GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 12073a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 12083a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 12093a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 12103a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 12113a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 12123a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 12133a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 12143a767b35SShaik Ameer Basha 1215cba9d2faSAndrzej Hajda GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 12161d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 12171d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 12181609027fSChander Kashyap 12193fac5941SShaik Ameer Basha GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 12201609027fSChander Kashyap }; 12211609027fSChander Kashyap 1222ca5b4029SThomas Abraham static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = { 1223ca5b4029SThomas Abraham PLL_35XX_RATE(2000000000, 250, 3, 0), 1224ca5b4029SThomas Abraham PLL_35XX_RATE(1900000000, 475, 6, 0), 1225ca5b4029SThomas Abraham PLL_35XX_RATE(1800000000, 225, 3, 0), 1226ca5b4029SThomas Abraham PLL_35XX_RATE(1700000000, 425, 6, 0), 1227ca5b4029SThomas Abraham PLL_35XX_RATE(1600000000, 200, 3, 0), 1228ca5b4029SThomas Abraham PLL_35XX_RATE(1500000000, 250, 4, 0), 1229ca5b4029SThomas Abraham PLL_35XX_RATE(1400000000, 175, 3, 0), 1230ca5b4029SThomas Abraham PLL_35XX_RATE(1300000000, 325, 6, 0), 1231ca5b4029SThomas Abraham PLL_35XX_RATE(1200000000, 200, 2, 1), 1232ca5b4029SThomas Abraham PLL_35XX_RATE(1100000000, 275, 3, 1), 1233ca5b4029SThomas Abraham PLL_35XX_RATE(1000000000, 250, 3, 1), 1234ca5b4029SThomas Abraham PLL_35XX_RATE(900000000, 150, 2, 1), 1235ca5b4029SThomas Abraham PLL_35XX_RATE(800000000, 200, 3, 1), 1236ca5b4029SThomas Abraham PLL_35XX_RATE(700000000, 175, 3, 1), 1237ca5b4029SThomas Abraham PLL_35XX_RATE(600000000, 200, 2, 2), 1238ca5b4029SThomas Abraham PLL_35XX_RATE(500000000, 250, 3, 2), 1239ca5b4029SThomas Abraham PLL_35XX_RATE(400000000, 200, 3, 2), 1240ca5b4029SThomas Abraham PLL_35XX_RATE(300000000, 200, 2, 3), 1241ca5b4029SThomas Abraham PLL_35XX_RATE(200000000, 200, 3, 3), 1242ca5b4029SThomas Abraham }; 1243ca5b4029SThomas Abraham 12446520e968SAlim Akhtar static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1245cba9d2faSAndrzej Hajda [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 12463ff6e0d8SYadwinder Singh Brar APLL_CON0, NULL), 1247cba9d2faSAndrzej Hajda [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1248cdf64eeeSChander Kashyap CPLL_CON0, NULL), 1249cba9d2faSAndrzej Hajda [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 12503ff6e0d8SYadwinder Singh Brar DPLL_CON0, NULL), 1251cba9d2faSAndrzej Hajda [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 12523ff6e0d8SYadwinder Singh Brar EPLL_CON0, NULL), 1253cba9d2faSAndrzej Hajda [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 12543ff6e0d8SYadwinder Singh Brar RPLL_CON0, NULL), 1255cba9d2faSAndrzej Hajda [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 12563ff6e0d8SYadwinder Singh Brar IPLL_CON0, NULL), 1257cba9d2faSAndrzej Hajda [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 12583ff6e0d8SYadwinder Singh Brar SPLL_CON0, NULL), 1259cba9d2faSAndrzej Hajda [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 12603ff6e0d8SYadwinder Singh Brar VPLL_CON0, NULL), 1261cba9d2faSAndrzej Hajda [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 12623ff6e0d8SYadwinder Singh Brar MPLL_CON0, NULL), 1263cba9d2faSAndrzej Hajda [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 12643ff6e0d8SYadwinder Singh Brar BPLL_CON0, NULL), 1265cba9d2faSAndrzej Hajda [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 12663ff6e0d8SYadwinder Singh Brar KPLL_CON0, NULL), 1267c898c6b7SYadwinder Singh Brar }; 1268c898c6b7SYadwinder Singh Brar 1269bee4f87fSThomas Abraham #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1270bee4f87fSThomas Abraham ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1271bee4f87fSThomas Abraham ((cpud) << 4))) 1272bee4f87fSThomas Abraham 1273bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1274bee4f87fSThomas Abraham { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1275bee4f87fSThomas Abraham { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1276bee4f87fSThomas Abraham { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1277bee4f87fSThomas Abraham { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1278bee4f87fSThomas Abraham { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1279bee4f87fSThomas Abraham { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1280bee4f87fSThomas Abraham { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1281bee4f87fSThomas Abraham { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1282bee4f87fSThomas Abraham { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1283bee4f87fSThomas Abraham { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1284bee4f87fSThomas Abraham { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1285bee4f87fSThomas Abraham { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1286bee4f87fSThomas Abraham { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1287bee4f87fSThomas Abraham { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1288bee4f87fSThomas Abraham { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1289bee4f87fSThomas Abraham { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1290bee4f87fSThomas Abraham { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1291bee4f87fSThomas Abraham { 0 }, 1292bee4f87fSThomas Abraham }; 1293bee4f87fSThomas Abraham 129454abbdb4SBartlomiej Zolnierkiewicz static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 129554abbdb4SBartlomiej Zolnierkiewicz { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 129654abbdb4SBartlomiej Zolnierkiewicz { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 129754abbdb4SBartlomiej Zolnierkiewicz { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 129854abbdb4SBartlomiej Zolnierkiewicz { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 129954abbdb4SBartlomiej Zolnierkiewicz { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 130054abbdb4SBartlomiej Zolnierkiewicz { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 130154abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 130254abbdb4SBartlomiej Zolnierkiewicz { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 130354abbdb4SBartlomiej Zolnierkiewicz { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 130454abbdb4SBartlomiej Zolnierkiewicz { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 130554abbdb4SBartlomiej Zolnierkiewicz { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 130654abbdb4SBartlomiej Zolnierkiewicz { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 130754abbdb4SBartlomiej Zolnierkiewicz { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 130854abbdb4SBartlomiej Zolnierkiewicz { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 130954abbdb4SBartlomiej Zolnierkiewicz { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 131054abbdb4SBartlomiej Zolnierkiewicz { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 131154abbdb4SBartlomiej Zolnierkiewicz { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 131254abbdb4SBartlomiej Zolnierkiewicz { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 131354abbdb4SBartlomiej Zolnierkiewicz { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 131454abbdb4SBartlomiej Zolnierkiewicz { 0 }, 131554abbdb4SBartlomiej Zolnierkiewicz }; 131654abbdb4SBartlomiej Zolnierkiewicz 1317bee4f87fSThomas Abraham #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1318bee4f87fSThomas Abraham ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1319bee4f87fSThomas Abraham 1320bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 132154abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1322bee4f87fSThomas Abraham { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1323bee4f87fSThomas Abraham { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1324bee4f87fSThomas Abraham { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1325bee4f87fSThomas Abraham { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1326bee4f87fSThomas Abraham { 900000, E5420_KFC_DIV(3, 5, 2), }, 1327bee4f87fSThomas Abraham { 800000, E5420_KFC_DIV(3, 5, 2), }, 1328bee4f87fSThomas Abraham { 700000, E5420_KFC_DIV(3, 4, 2), }, 1329bee4f87fSThomas Abraham { 600000, E5420_KFC_DIV(3, 4, 2), }, 1330bee4f87fSThomas Abraham { 500000, E5420_KFC_DIV(3, 4, 2), }, 1331bee4f87fSThomas Abraham { 400000, E5420_KFC_DIV(3, 3, 2), }, 1332bee4f87fSThomas Abraham { 300000, E5420_KFC_DIV(3, 3, 2), }, 1333bee4f87fSThomas Abraham { 200000, E5420_KFC_DIV(3, 3, 2), }, 1334bee4f87fSThomas Abraham { 0 }, 1335bee4f87fSThomas Abraham }; 1336bee4f87fSThomas Abraham 1337305cfab0SKrzysztof Kozlowski static const struct of_device_id ext_clk_match[] __initconst = { 13381609027fSChander Kashyap { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 13391609027fSChander Kashyap { }, 13401609027fSChander Kashyap }; 13411609027fSChander Kashyap 13421609027fSChander Kashyap /* register exynos5420 clocks */ 13436520e968SAlim Akhtar static void __init exynos5x_clk_init(struct device_node *np, 13446520e968SAlim Akhtar enum exynos5x_soc soc) 13451609027fSChander Kashyap { 1346976face4SRahul Sharma struct samsung_clk_provider *ctx; 1347976face4SRahul Sharma 13481609027fSChander Kashyap if (np) { 13491609027fSChander Kashyap reg_base = of_iomap(np, 0); 13501609027fSChander Kashyap if (!reg_base) 13511609027fSChander Kashyap panic("%s: failed to map registers\n", __func__); 13521609027fSChander Kashyap } else { 13531609027fSChander Kashyap panic("%s: unable to determine soc\n", __func__); 13541609027fSChander Kashyap } 13551609027fSChander Kashyap 13566520e968SAlim Akhtar exynos5x_soc = soc; 13576520e968SAlim Akhtar 1358976face4SRahul Sharma ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1359976face4SRahul Sharma 13606520e968SAlim Akhtar samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 13616520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 13621609027fSChander Kashyap ext_clk_match); 1363ca5b4029SThomas Abraham 1364ca5b4029SThomas Abraham if (_get_rate("fin_pll") == 24 * MHZ) { 1365ca5b4029SThomas Abraham exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1366ca5b4029SThomas Abraham exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1367ca5b4029SThomas Abraham } 1368ca5b4029SThomas Abraham 13696520e968SAlim Akhtar samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1370c898c6b7SYadwinder Singh Brar reg_base); 13716520e968SAlim Akhtar samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 13726520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_clks)); 13736520e968SAlim Akhtar samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 13746520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_factor_clks)); 13756520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5x_mux_clks, 13766520e968SAlim Akhtar ARRAY_SIZE(exynos5x_mux_clks)); 13776520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5x_div_clks, 13786520e968SAlim Akhtar ARRAY_SIZE(exynos5x_div_clks)); 13796520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5x_gate_clks, 13806520e968SAlim Akhtar ARRAY_SIZE(exynos5x_gate_clks)); 13816520e968SAlim Akhtar 13826520e968SAlim Akhtar if (soc == EXYNOS5420) { 1383976face4SRahul Sharma samsung_clk_register_mux(ctx, exynos5420_mux_clks, 13841609027fSChander Kashyap ARRAY_SIZE(exynos5420_mux_clks)); 1385976face4SRahul Sharma samsung_clk_register_div(ctx, exynos5420_div_clks, 13861609027fSChander Kashyap ARRAY_SIZE(exynos5420_div_clks)); 13876520e968SAlim Akhtar } else { 13886520e968SAlim Akhtar samsung_clk_register_fixed_factor( 13896520e968SAlim Akhtar ctx, exynos5800_fixed_factor_clks, 13906520e968SAlim Akhtar ARRAY_SIZE(exynos5800_fixed_factor_clks)); 13916520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5800_mux_clks, 13926520e968SAlim Akhtar ARRAY_SIZE(exynos5800_mux_clks)); 13936520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5800_div_clks, 13946520e968SAlim Akhtar ARRAY_SIZE(exynos5800_div_clks)); 13956520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5800_gate_clks, 13966520e968SAlim Akhtar ARRAY_SIZE(exynos5800_gate_clks)); 13976520e968SAlim Akhtar } 1398388c7885STomasz Figa 139954abbdb4SBartlomiej Zolnierkiewicz if (soc == EXYNOS5420) { 1400bee4f87fSThomas Abraham exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1401bee4f87fSThomas Abraham mout_cpu_p[0], mout_cpu_p[1], 0x200, 1402bee4f87fSThomas Abraham exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); 140354abbdb4SBartlomiej Zolnierkiewicz } else { 140454abbdb4SBartlomiej Zolnierkiewicz exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 140554abbdb4SBartlomiej Zolnierkiewicz mout_cpu_p[0], mout_cpu_p[1], 0x200, 140654abbdb4SBartlomiej Zolnierkiewicz exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); 140754abbdb4SBartlomiej Zolnierkiewicz } 1408bee4f87fSThomas Abraham exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", 1409bee4f87fSThomas Abraham mout_kfc_p[0], mout_kfc_p[1], 0x28200, 1410bee4f87fSThomas Abraham exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); 1411bee4f87fSThomas Abraham 1412388c7885STomasz Figa exynos5420_clk_sleep_init(); 1413d5e136a2SSylwester Nawrocki 1414d5e136a2SSylwester Nawrocki samsung_clk_of_add_provider(np, ctx); 14151609027fSChander Kashyap } 14166520e968SAlim Akhtar 14176520e968SAlim Akhtar static void __init exynos5420_clk_init(struct device_node *np) 14186520e968SAlim Akhtar { 14196520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5420); 14206520e968SAlim Akhtar } 14211609027fSChander Kashyap CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 14226520e968SAlim Akhtar 14236520e968SAlim Akhtar static void __init exynos5800_clk_init(struct device_node *np) 14246520e968SAlim Akhtar { 14256520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5800); 14266520e968SAlim Akhtar } 14276520e968SAlim Akhtar CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init); 1428