1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 21609027fSChander Kashyap /* 31609027fSChander Kashyap * Copyright (c) 2013 Samsung Electronics Co., Ltd. 41609027fSChander Kashyap * Authors: Thomas Abraham <thomas.ab@samsung.com> 51609027fSChander Kashyap * Chander Kashyap <k.chander@samsung.com> 61609027fSChander Kashyap * 71609027fSChander Kashyap * Common Clock Framework support for Exynos5420 SoC. 81609027fSChander Kashyap */ 91609027fSChander Kashyap 10cba9d2faSAndrzej Hajda #include <dt-bindings/clock/exynos5420.h> 116f1ed07aSStephen Boyd #include <linux/slab.h> 121609027fSChander Kashyap #include <linux/clk-provider.h> 131609027fSChander Kashyap #include <linux/of.h> 141609027fSChander Kashyap #include <linux/of_address.h> 1567f96ff7SMarek Szyprowski #include <linux/clk.h> 161609027fSChander Kashyap 171609027fSChander Kashyap #include "clk.h" 18bee4f87fSThomas Abraham #include "clk-cpu.h" 19ec4016ffSMarek Szyprowski #include "clk-exynos5-subcmu.h" 201609027fSChander Kashyap 21c898c6b7SYadwinder Singh Brar #define APLL_LOCK 0x0 22c898c6b7SYadwinder Singh Brar #define APLL_CON0 0x100 231609027fSChander Kashyap #define SRC_CPU 0x200 241609027fSChander Kashyap #define DIV_CPU0 0x500 251609027fSChander Kashyap #define DIV_CPU1 0x504 261609027fSChander Kashyap #define GATE_BUS_CPU 0x700 271609027fSChander Kashyap #define GATE_SCLK_CPU 0x800 2877342432SShaik Ameer Basha #define CLKOUT_CMU_CPU 0xa00 29e9d52956SVikas Sajjan #define SRC_MASK_CPERI 0x4300 305b73721bSNaveen Krishna Chatradhi #define GATE_IP_G2D 0x8800 31c898c6b7SYadwinder Singh Brar #define CPLL_LOCK 0x10020 32c898c6b7SYadwinder Singh Brar #define DPLL_LOCK 0x10030 33c898c6b7SYadwinder Singh Brar #define EPLL_LOCK 0x10040 34c898c6b7SYadwinder Singh Brar #define RPLL_LOCK 0x10050 35c898c6b7SYadwinder Singh Brar #define IPLL_LOCK 0x10060 36c898c6b7SYadwinder Singh Brar #define SPLL_LOCK 0x10070 3753cb6342SSachin Kamat #define VPLL_LOCK 0x10080 38c898c6b7SYadwinder Singh Brar #define MPLL_LOCK 0x10090 39c898c6b7SYadwinder Singh Brar #define CPLL_CON0 0x10120 40c898c6b7SYadwinder Singh Brar #define DPLL_CON0 0x10128 41c898c6b7SYadwinder Singh Brar #define EPLL_CON0 0x10130 4277342432SShaik Ameer Basha #define EPLL_CON1 0x10134 4377342432SShaik Ameer Basha #define EPLL_CON2 0x10138 44c898c6b7SYadwinder Singh Brar #define RPLL_CON0 0x10140 4577342432SShaik Ameer Basha #define RPLL_CON1 0x10144 4677342432SShaik Ameer Basha #define RPLL_CON2 0x10148 47c898c6b7SYadwinder Singh Brar #define IPLL_CON0 0x10150 48c898c6b7SYadwinder Singh Brar #define SPLL_CON0 0x10160 49c898c6b7SYadwinder Singh Brar #define VPLL_CON0 0x10170 50c898c6b7SYadwinder Singh Brar #define MPLL_CON0 0x10180 511609027fSChander Kashyap #define SRC_TOP0 0x10200 521609027fSChander Kashyap #define SRC_TOP1 0x10204 531609027fSChander Kashyap #define SRC_TOP2 0x10208 541609027fSChander Kashyap #define SRC_TOP3 0x1020c 551609027fSChander Kashyap #define SRC_TOP4 0x10210 561609027fSChander Kashyap #define SRC_TOP5 0x10214 571609027fSChander Kashyap #define SRC_TOP6 0x10218 581609027fSChander Kashyap #define SRC_TOP7 0x1021c 596520e968SAlim Akhtar #define SRC_TOP8 0x10220 /* 5800 specific */ 606520e968SAlim Akhtar #define SRC_TOP9 0x10224 /* 5800 specific */ 611609027fSChander Kashyap #define SRC_DISP10 0x1022c 621609027fSChander Kashyap #define SRC_MAU 0x10240 631609027fSChander Kashyap #define SRC_FSYS 0x10244 641609027fSChander Kashyap #define SRC_PERIC0 0x10250 651609027fSChander Kashyap #define SRC_PERIC1 0x10254 663a767b35SShaik Ameer Basha #define SRC_ISP 0x10270 676520e968SAlim Akhtar #define SRC_CAM 0x10274 /* 5800 specific */ 681609027fSChander Kashyap #define SRC_TOP10 0x10280 691609027fSChander Kashyap #define SRC_TOP11 0x10284 701609027fSChander Kashyap #define SRC_TOP12 0x10288 716520e968SAlim Akhtar #define SRC_TOP13 0x1028c /* 5800 specific */ 72e9d52956SVikas Sajjan #define SRC_MASK_TOP0 0x10300 73e9d52956SVikas Sajjan #define SRC_MASK_TOP1 0x10304 74424b673aSShaik Ameer Basha #define SRC_MASK_TOP2 0x10308 7531116a64SShaik Ameer Basha #define SRC_MASK_TOP7 0x1031c 761609027fSChander Kashyap #define SRC_MASK_DISP10 0x1032c 7731116a64SShaik Ameer Basha #define SRC_MASK_MAU 0x10334 781609027fSChander Kashyap #define SRC_MASK_FSYS 0x10340 791609027fSChander Kashyap #define SRC_MASK_PERIC0 0x10350 801609027fSChander Kashyap #define SRC_MASK_PERIC1 0x10354 81e9d52956SVikas Sajjan #define SRC_MASK_ISP 0x10370 821609027fSChander Kashyap #define DIV_TOP0 0x10500 831609027fSChander Kashyap #define DIV_TOP1 0x10504 841609027fSChander Kashyap #define DIV_TOP2 0x10508 856520e968SAlim Akhtar #define DIV_TOP8 0x10520 /* 5800 specific */ 866520e968SAlim Akhtar #define DIV_TOP9 0x10524 /* 5800 specific */ 871609027fSChander Kashyap #define DIV_DISP10 0x1052c 881609027fSChander Kashyap #define DIV_MAU 0x10544 891609027fSChander Kashyap #define DIV_FSYS0 0x10548 901609027fSChander Kashyap #define DIV_FSYS1 0x1054c 911609027fSChander Kashyap #define DIV_FSYS2 0x10550 921609027fSChander Kashyap #define DIV_PERIC0 0x10558 931609027fSChander Kashyap #define DIV_PERIC1 0x1055c 941609027fSChander Kashyap #define DIV_PERIC2 0x10560 951609027fSChander Kashyap #define DIV_PERIC3 0x10564 961609027fSChander Kashyap #define DIV_PERIC4 0x10568 976520e968SAlim Akhtar #define DIV_CAM 0x10574 /* 5800 specific */ 983a767b35SShaik Ameer Basha #define SCLK_DIV_ISP0 0x10580 993a767b35SShaik Ameer Basha #define SCLK_DIV_ISP1 0x10584 10002932381SShaik Ameer Basha #define DIV2_RATIO0 0x10590 1011d87db4dSShaik Ameer Basha #define DIV4_RATIO 0x105a0 1021609027fSChander Kashyap #define GATE_BUS_TOP 0x10700 103e9d52956SVikas Sajjan #define GATE_BUS_DISP1 0x10728 1040a22c306SShaik Ameer Basha #define GATE_BUS_GEN 0x1073c 1051609027fSChander Kashyap #define GATE_BUS_FSYS0 0x10740 1066b5ae463SShaik Ameer Basha #define GATE_BUS_FSYS2 0x10748 1071609027fSChander Kashyap #define GATE_BUS_PERIC 0x10750 1081609027fSChander Kashyap #define GATE_BUS_PERIC1 0x10754 1091609027fSChander Kashyap #define GATE_BUS_PERIS0 0x10760 1101609027fSChander Kashyap #define GATE_BUS_PERIS1 0x10764 1116575fa76SShaik Ameer Basha #define GATE_BUS_NOC 0x10770 1123a767b35SShaik Ameer Basha #define GATE_TOP_SCLK_ISP 0x10870 1131609027fSChander Kashyap #define GATE_IP_GSCL0 0x10910 1141609027fSChander Kashyap #define GATE_IP_GSCL1 0x10920 1156520e968SAlim Akhtar #define GATE_IP_CAM 0x10924 /* 5800 specific */ 1161609027fSChander Kashyap #define GATE_IP_MFC 0x1092c 1171609027fSChander Kashyap #define GATE_IP_DISP1 0x10928 1181609027fSChander Kashyap #define GATE_IP_G3D 0x10930 1191609027fSChander Kashyap #define GATE_IP_GEN 0x10934 1206b5ae463SShaik Ameer Basha #define GATE_IP_FSYS 0x10944 121faec151bSShaik Ameer Basha #define GATE_IP_PERIC 0x10950 1220a22c306SShaik Ameer Basha #define GATE_IP_PERIS 0x10960 1231609027fSChander Kashyap #define GATE_IP_MSCL 0x10970 1241609027fSChander Kashyap #define GATE_TOP_SCLK_GSCL 0x10820 1251609027fSChander Kashyap #define GATE_TOP_SCLK_DISP1 0x10828 1261609027fSChander Kashyap #define GATE_TOP_SCLK_MAU 0x1083c 1271609027fSChander Kashyap #define GATE_TOP_SCLK_FSYS 0x10840 1281609027fSChander Kashyap #define GATE_TOP_SCLK_PERIC 0x10850 129424b673aSShaik Ameer Basha #define TOP_SPARE2 0x10b08 130c898c6b7SYadwinder Singh Brar #define BPLL_LOCK 0x20010 131c898c6b7SYadwinder Singh Brar #define BPLL_CON0 0x20110 132e867e8faSChanwoo Choi #define SRC_CDREX 0x20200 133e867e8faSChanwoo Choi #define DIV_CDREX0 0x20500 134e867e8faSChanwoo Choi #define DIV_CDREX1 0x20504 1352f57b95cSLukasz Luba #define GATE_BUS_CDREX0 0x20700 1362f57b95cSLukasz Luba #define GATE_BUS_CDREX1 0x20704 137c898c6b7SYadwinder Singh Brar #define KPLL_LOCK 0x28000 138c898c6b7SYadwinder Singh Brar #define KPLL_CON0 0x28100 1391609027fSChander Kashyap #define SRC_KFC 0x28200 1401609027fSChander Kashyap #define DIV_KFC0 0x28500 1411609027fSChander Kashyap 1426520e968SAlim Akhtar /* Exynos5x SoC type */ 1436520e968SAlim Akhtar enum exynos5x_soc { 1446520e968SAlim Akhtar EXYNOS5420, 1456520e968SAlim Akhtar EXYNOS5800, 1466520e968SAlim Akhtar }; 1476520e968SAlim Akhtar 148c898c6b7SYadwinder Singh Brar /* list of PLLs */ 1496520e968SAlim Akhtar enum exynos5x_plls { 150c898c6b7SYadwinder Singh Brar apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 151c898c6b7SYadwinder Singh Brar bpll, kpll, 152c898c6b7SYadwinder Singh Brar nr_plls /* number of PLLs */ 153c898c6b7SYadwinder Singh Brar }; 154c898c6b7SYadwinder Singh Brar 155388c7885STomasz Figa static void __iomem *reg_base; 1566520e968SAlim Akhtar static enum exynos5x_soc exynos5x_soc; 157388c7885STomasz Figa 1581609027fSChander Kashyap /* 1591609027fSChander Kashyap * list of controller registers to be saved and restored during a 1601609027fSChander Kashyap * suspend/resume cycle. 1611609027fSChander Kashyap */ 162ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5x_clk_regs[] __initconst = { 1631609027fSChander Kashyap SRC_CPU, 1641609027fSChander Kashyap DIV_CPU0, 1651609027fSChander Kashyap DIV_CPU1, 1661609027fSChander Kashyap GATE_BUS_CPU, 1671609027fSChander Kashyap GATE_SCLK_CPU, 16877342432SShaik Ameer Basha CLKOUT_CMU_CPU, 169e21be0d1SMarian Mihailescu APLL_CON0, 170e21be0d1SMarian Mihailescu KPLL_CON0, 171e9323b66SMarek Szyprowski CPLL_CON0, 172e9323b66SMarek Szyprowski DPLL_CON0, 17377342432SShaik Ameer Basha EPLL_CON0, 17477342432SShaik Ameer Basha EPLL_CON1, 17577342432SShaik Ameer Basha EPLL_CON2, 17677342432SShaik Ameer Basha RPLL_CON0, 17777342432SShaik Ameer Basha RPLL_CON1, 17877342432SShaik Ameer Basha RPLL_CON2, 179e9323b66SMarek Szyprowski IPLL_CON0, 180e9323b66SMarek Szyprowski SPLL_CON0, 181e9323b66SMarek Szyprowski VPLL_CON0, 182e9323b66SMarek Szyprowski MPLL_CON0, 1831609027fSChander Kashyap SRC_TOP0, 1841609027fSChander Kashyap SRC_TOP1, 1851609027fSChander Kashyap SRC_TOP2, 1861609027fSChander Kashyap SRC_TOP3, 1871609027fSChander Kashyap SRC_TOP4, 1881609027fSChander Kashyap SRC_TOP5, 1891609027fSChander Kashyap SRC_TOP6, 1901609027fSChander Kashyap SRC_TOP7, 1911609027fSChander Kashyap SRC_DISP10, 1921609027fSChander Kashyap SRC_MAU, 1931609027fSChander Kashyap SRC_FSYS, 1941609027fSChander Kashyap SRC_PERIC0, 1951609027fSChander Kashyap SRC_PERIC1, 1961609027fSChander Kashyap SRC_TOP10, 1971609027fSChander Kashyap SRC_TOP11, 1981609027fSChander Kashyap SRC_TOP12, 199424b673aSShaik Ameer Basha SRC_MASK_TOP2, 20031116a64SShaik Ameer Basha SRC_MASK_TOP7, 2011609027fSChander Kashyap SRC_MASK_DISP10, 2021609027fSChander Kashyap SRC_MASK_FSYS, 2031609027fSChander Kashyap SRC_MASK_PERIC0, 2041609027fSChander Kashyap SRC_MASK_PERIC1, 205e9d52956SVikas Sajjan SRC_MASK_TOP0, 206e9d52956SVikas Sajjan SRC_MASK_TOP1, 207e9d52956SVikas Sajjan SRC_MASK_MAU, 208e9d52956SVikas Sajjan SRC_MASK_ISP, 2093a767b35SShaik Ameer Basha SRC_ISP, 2101609027fSChander Kashyap DIV_TOP0, 2111609027fSChander Kashyap DIV_TOP1, 2121609027fSChander Kashyap DIV_TOP2, 2131609027fSChander Kashyap DIV_DISP10, 2141609027fSChander Kashyap DIV_MAU, 2151609027fSChander Kashyap DIV_FSYS0, 2161609027fSChander Kashyap DIV_FSYS1, 2171609027fSChander Kashyap DIV_FSYS2, 2181609027fSChander Kashyap DIV_PERIC0, 2191609027fSChander Kashyap DIV_PERIC1, 2201609027fSChander Kashyap DIV_PERIC2, 2211609027fSChander Kashyap DIV_PERIC3, 2221609027fSChander Kashyap DIV_PERIC4, 2233a767b35SShaik Ameer Basha SCLK_DIV_ISP0, 2243a767b35SShaik Ameer Basha SCLK_DIV_ISP1, 22502932381SShaik Ameer Basha DIV2_RATIO0, 2261d87db4dSShaik Ameer Basha DIV4_RATIO, 227e9d52956SVikas Sajjan GATE_BUS_DISP1, 2281609027fSChander Kashyap GATE_BUS_TOP, 2290a22c306SShaik Ameer Basha GATE_BUS_GEN, 2301609027fSChander Kashyap GATE_BUS_FSYS0, 2316b5ae463SShaik Ameer Basha GATE_BUS_FSYS2, 2321609027fSChander Kashyap GATE_BUS_PERIC, 2331609027fSChander Kashyap GATE_BUS_PERIC1, 2341609027fSChander Kashyap GATE_BUS_PERIS0, 2351609027fSChander Kashyap GATE_BUS_PERIS1, 2366575fa76SShaik Ameer Basha GATE_BUS_NOC, 2373a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2381609027fSChander Kashyap GATE_IP_GSCL0, 2391609027fSChander Kashyap GATE_IP_GSCL1, 2401609027fSChander Kashyap GATE_IP_MFC, 2411609027fSChander Kashyap GATE_IP_DISP1, 2421609027fSChander Kashyap GATE_IP_G3D, 2431609027fSChander Kashyap GATE_IP_GEN, 2446b5ae463SShaik Ameer Basha GATE_IP_FSYS, 245faec151bSShaik Ameer Basha GATE_IP_PERIC, 2460a22c306SShaik Ameer Basha GATE_IP_PERIS, 2471609027fSChander Kashyap GATE_IP_MSCL, 2481609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 2491609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 2501609027fSChander Kashyap GATE_TOP_SCLK_MAU, 2511609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2521609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 253424b673aSShaik Ameer Basha TOP_SPARE2, 254e867e8faSChanwoo Choi SRC_CDREX, 255e867e8faSChanwoo Choi DIV_CDREX0, 256e867e8faSChanwoo Choi DIV_CDREX1, 2571609027fSChander Kashyap SRC_KFC, 2581609027fSChander Kashyap DIV_KFC0, 2592f57b95cSLukasz Luba GATE_BUS_CDREX0, 2602f57b95cSLukasz Luba GATE_BUS_CDREX1, 2611609027fSChander Kashyap }; 2621609027fSChander Kashyap 263ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5800_clk_regs[] __initconst = { 2646520e968SAlim Akhtar SRC_TOP8, 2656520e968SAlim Akhtar SRC_TOP9, 2666520e968SAlim Akhtar SRC_CAM, 2676520e968SAlim Akhtar SRC_TOP1, 2686520e968SAlim Akhtar DIV_TOP8, 2696520e968SAlim Akhtar DIV_TOP9, 2706520e968SAlim Akhtar DIV_CAM, 2716520e968SAlim Akhtar GATE_IP_CAM, 2726520e968SAlim Akhtar }; 2736520e968SAlim Akhtar 274e9d52956SVikas Sajjan static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 275e9d52956SVikas Sajjan { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 276e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 277e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 278e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 279e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 280e9d52956SVikas Sajjan { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 281e9d52956SVikas Sajjan { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 282e9d52956SVikas Sajjan { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 283e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 284e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 285e9d52956SVikas Sajjan { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 28697372e5aSJavier Martinez Canillas { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 287e9d52956SVikas Sajjan { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 288e9d52956SVikas Sajjan { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 289b3322802SMarek Szyprowski { .offset = GATE_IP_PERIS, .value = 0xffffffff, }, 290e9d52956SVikas Sajjan }; 291e9d52956SVikas Sajjan 2921609027fSChander Kashyap /* list of all parent clocks */ 293dbd713bbSShaik Ameer Basha PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 294dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 295dbd713bbSShaik Ameer Basha PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 296dbd713bbSShaik Ameer Basha PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 297dbd713bbSShaik Ameer Basha PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 298dbd713bbSShaik Ameer Basha PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 299dbd713bbSShaik Ameer Basha PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 300dbd713bbSShaik Ameer Basha PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 301dbd713bbSShaik Ameer Basha PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 302dbd713bbSShaik Ameer Basha PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 303dbd713bbSShaik Ameer Basha PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 304dbd713bbSShaik Ameer Basha PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 305dbd713bbSShaik Ameer Basha PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 306dbd713bbSShaik Ameer Basha PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 307dbd713bbSShaik Ameer Basha PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 3081609027fSChander Kashyap 309dbd713bbSShaik Ameer Basha PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 310dbd713bbSShaik Ameer Basha "mout_sclk_mpll"}; 311dbd713bbSShaik Ameer Basha PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 312dbd713bbSShaik Ameer Basha "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 313dbd713bbSShaik Ameer Basha "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 314dbd713bbSShaik Ameer Basha PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 315dbd713bbSShaik Ameer Basha PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 316dbd713bbSShaik Ameer Basha PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 3171609027fSChander Kashyap 318424b673aSShaik Ameer Basha PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 319dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 320faec151bSShaik Ameer Basha PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 321b31ca2a0SShaik Ameer Basha PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 3221609027fSChander Kashyap 323dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 3246b5ae463SShaik Ameer Basha PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 3256b5ae463SShaik Ameer Basha PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 326dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 3271609027fSChander Kashyap 328dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 329dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 3306575fa76SShaik Ameer Basha PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 3316575fa76SShaik Ameer Basha PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 3326575fa76SShaik Ameer Basha 3336575fa76SShaik Ameer Basha PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 3346575fa76SShaik Ameer Basha PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 3356575fa76SShaik Ameer Basha PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 3366575fa76SShaik Ameer Basha 3373a767b35SShaik Ameer Basha PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 3383a767b35SShaik Ameer Basha PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 3393a767b35SShaik Ameer Basha 3403a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 3413a767b35SShaik Ameer Basha "mout_sclk_spll"}; 3423a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 3433a767b35SShaik Ameer Basha 3443a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 3453a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 3461609027fSChander Kashyap 347dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 348424b673aSShaik Ameer Basha PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 3491609027fSChander Kashyap 350dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 351dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 3521609027fSChander Kashyap 353dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 354dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 3551609027fSChander Kashyap 356dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 357dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 3581609027fSChander Kashyap 359dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 360dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 3613a767b35SShaik Ameer Basha PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 3621609027fSChander Kashyap 363dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 364dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 3651609027fSChander Kashyap 366dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 367dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 3681609027fSChander Kashyap 369dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 370424b673aSShaik Ameer Basha PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 371dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 372424b673aSShaik Ameer Basha PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 3731609027fSChander Kashyap 374dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 375dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 3761609027fSChander Kashyap 377dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 378dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 3791609027fSChander Kashyap 380dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 381dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 3821609027fSChander Kashyap 383dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 384dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 3851609027fSChander Kashyap 386dbd713bbSShaik Ameer Basha PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 387dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 388dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 389dbd713bbSShaik Ameer Basha PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 390dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 391dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 392dbd713bbSShaik Ameer Basha PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 393dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 394dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 395dbd713bbSShaik Ameer Basha PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 396dbd713bbSShaik Ameer Basha "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 397dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 398dbd713bbSShaik Ameer Basha PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 399dbd713bbSShaik Ameer Basha PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 400dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 401dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 40231116a64SShaik Ameer Basha PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 40331116a64SShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 404e867e8faSChanwoo Choi PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"}; 405e867e8faSChanwoo Choi 4066520e968SAlim Akhtar /* List of parents specific to exynos5800 */ 4076520e968SAlim Akhtar PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 4086520e968SAlim Akhtar PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4096520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4106520e968SAlim Akhtar PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4116520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4126520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 4136520e968SAlim Akhtar PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4146520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4156520e968SAlim Akhtar "mout_epll2" }; 4166520e968SAlim Akhtar PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4176520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll" }; 4186520e968SAlim Akhtar PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 4196520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4206520e968SAlim Akhtar PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4216520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll", 4226520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 423e867e8faSChanwoo Choi PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll", 424e867e8faSChanwoo Choi "mout_sclk_mpll", "ff_dout_spll2", 425e867e8faSChanwoo Choi "mout_sclk_spll", "mout_sclk_epll"}; 4266520e968SAlim Akhtar PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 4276520e968SAlim Akhtar "mout_sclk_mpll", 4286520e968SAlim Akhtar "ff_dout_spll2" }; 4296520e968SAlim Akhtar PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 4306520e968SAlim Akhtar PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 4316520e968SAlim Akhtar PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 4326520e968SAlim Akhtar PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 4336520e968SAlim Akhtar PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 4346520e968SAlim Akhtar PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 4356520e968SAlim Akhtar PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 4366520e968SAlim Akhtar PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 4378a9cf26eSSylwester Nawrocki PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; 4382f57b95cSLukasz Luba PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll", 4392f57b95cSLukasz Luba "mout_sclk_mpll", "ff_dout_spll2", 4402f57b95cSLukasz Luba "mout_sclk_spll", "mout_sclk_epll"}; 4411609027fSChander Kashyap 4421609027fSChander Kashyap /* fixed rate clocks generated outside the soc */ 4436520e968SAlim Akhtar static struct samsung_fixed_rate_clock 4446520e968SAlim Akhtar exynos5x_fixed_rate_ext_clks[] __initdata = { 445728f288dSStephen Boyd FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 4461609027fSChander Kashyap }; 4471609027fSChander Kashyap 4481609027fSChander Kashyap /* fixed rate clocks generated inside the soc */ 449ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { 450728f288dSStephen Boyd FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 451728f288dSStephen Boyd FRATE(0, "sclk_pwi", NULL, 0, 24000000), 452728f288dSStephen Boyd FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 453728f288dSStephen Boyd FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 454728f288dSStephen Boyd FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 4551609027fSChander Kashyap }; 4561609027fSChander Kashyap 457ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 458ad98c64fSKrzysztof Kozlowski exynos5x_fixed_factor_clks[] __initconst = { 459b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 460b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 4611609027fSChander Kashyap }; 4621609027fSChander Kashyap 463ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 464ad98c64fSKrzysztof Kozlowski exynos5800_fixed_factor_clks[] __initconst = { 4656520e968SAlim Akhtar FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 4662f57b95cSLukasz Luba FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 4676520e968SAlim Akhtar }; 4686520e968SAlim Akhtar 469ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 4706520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 4716520e968SAlim Akhtar MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 4726520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 4736520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 4746520e968SAlim Akhtar 4756520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 4766520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 4776520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 4786520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 4796520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 4806520e968SAlim Akhtar 4816520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 4826520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 4836520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 4846520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 4856520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 4866520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 4876520e968SAlim Akhtar 4882f57b95cSLukasz Luba MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy", 4892f57b95cSLukasz Luba mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3), 4902f57b95cSLukasz Luba 491e867e8faSChanwoo Choi MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 4922f57b95cSLukasz Luba mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3), 493599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, 494599cebeaSSylwester Nawrocki SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), 4952f57b95cSLukasz Luba MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 4966520e968SAlim Akhtar MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 4976520e968SAlim Akhtar 4986520e968SAlim Akhtar MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 4996520e968SAlim Akhtar MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 5006520e968SAlim Akhtar MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 5016520e968SAlim Akhtar MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 5026520e968SAlim Akhtar 503599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, 504599cebeaSSylwester Nawrocki SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0), 5056520e968SAlim Akhtar MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 5066520e968SAlim Akhtar SRC_TOP9, 16, 1), 5076520e968SAlim Akhtar MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 5086520e968SAlim Akhtar SRC_TOP9, 20, 1), 5096520e968SAlim Akhtar MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 5106520e968SAlim Akhtar SRC_TOP9, 24, 1), 5116520e968SAlim Akhtar MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 5126520e968SAlim Akhtar SRC_TOP9, 28, 1), 5136520e968SAlim Akhtar 5146520e968SAlim Akhtar MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 5156520e968SAlim Akhtar MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 5166520e968SAlim Akhtar SRC_TOP13, 20, 1), 5176520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 5186520e968SAlim Akhtar SRC_TOP13, 24, 1), 5196520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 5206520e968SAlim Akhtar SRC_TOP13, 28, 1), 5216520e968SAlim Akhtar 5226520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 5236520e968SAlim Akhtar }; 5246520e968SAlim Akhtar 525ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { 52681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 52781fed6e3SChanwoo Choi "mout_aclk400_wcore", DIV_TOP0, 16, 3), 5286520e968SAlim Akhtar DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 5296520e968SAlim Akhtar DIV_TOP8, 16, 3), 5306520e968SAlim Akhtar DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 5316520e968SAlim Akhtar DIV_TOP8, 20, 3), 5326520e968SAlim Akhtar DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 5336520e968SAlim Akhtar DIV_TOP8, 24, 3), 5346520e968SAlim Akhtar DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 5356520e968SAlim Akhtar DIV_TOP8, 28, 3), 5366520e968SAlim Akhtar 5376520e968SAlim Akhtar DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 5386520e968SAlim Akhtar DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 5396520e968SAlim Akhtar }; 5406520e968SAlim Akhtar 541ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 5426520e968SAlim Akhtar GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 543e47bd937SMarek Szyprowski GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0), 5446520e968SAlim Akhtar GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 545318fa46cSMarek Szyprowski GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), 5466520e968SAlim Akhtar }; 5476520e968SAlim Akhtar 548ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 5496520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 5506520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 5516520e968SAlim Akhtar TOP_SPARE2, 4, 1), 5526520e968SAlim Akhtar 5536520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 55436ba4824SMarek Szyprowski MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2), 5556520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 5566520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 5576520e968SAlim Akhtar 5586520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 5596520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group4_p, 5606520e968SAlim Akhtar SRC_TOP1, 4, 2), 5616520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 5626520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 5636520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 5646520e968SAlim Akhtar 5656520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 5666520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 5676520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 5686520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 5696520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 5706520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 5716520e968SAlim Akhtar 572e867e8faSChanwoo Choi MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 573e867e8faSChanwoo Choi mout_group5_5800_p, SRC_TOP7, 16, 2), 57406255a92SSylwester Nawrocki MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2, 57506255a92SSylwester Nawrocki CLK_SET_RATE_PARENT, 0), 5766520e968SAlim Akhtar 5776520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 5786520e968SAlim Akhtar }; 5796520e968SAlim Akhtar 580ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 58181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 58281fed6e3SChanwoo Choi "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 5836520e968SAlim Akhtar }; 5846520e968SAlim Akhtar 58541097f25SSylwester Nawrocki static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { 586d32dd2a1SJoonyoung Shim GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 587b6adeb6bSSylwester Nawrocki /* Maudio Block */ 58841097f25SSylwester Nawrocki GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 589599cebeaSSylwester Nawrocki SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 590b6adeb6bSSylwester Nawrocki GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 591b6adeb6bSSylwester Nawrocki GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 592b6adeb6bSSylwester Nawrocki GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 593b6adeb6bSSylwester Nawrocki GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 59441097f25SSylwester Nawrocki }; 59541097f25SSylwester Nawrocki 596ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 597b31ca2a0SShaik Ameer Basha MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 598b31ca2a0SShaik Ameer Basha SRC_TOP7, 4, 1), 5991f6e17d2SSylwester Nawrocki MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p, 6001f6e17d2SSylwester Nawrocki SRC_TOP7, 8, 2), 6011f6e17d2SSylwester Nawrocki MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p, 6021f6e17d2SSylwester Nawrocki SRC_TOP7, 12, 2), 6031f6e17d2SSylwester Nawrocki MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 604bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 605dbd713bbSShaik Ameer Basha MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 6061f6e17d2SSylwester Nawrocki MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 607bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 608dbd713bbSShaik Ameer Basha MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 6091609027fSChander Kashyap 610dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 611dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 6126b5ae463SShaik Ameer Basha MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 613dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 6141609027fSChander Kashyap 615dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 616dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 6171609027fSChander Kashyap 61845f10dabSMarek Szyprowski MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1, 61945f10dabSMarek Szyprowski CLK_SET_RATE_PARENT, 0), 6201609027fSChander Kashyap 6213a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 6223a767b35SShaik Ameer Basha SRC_TOP3, 0, 1), 623dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 6241609027fSChander Kashyap SRC_TOP3, 4, 1), 62588560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 62688560100SJavier Martinez Canillas mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 627dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 6281609027fSChander Kashyap SRC_TOP3, 12, 1), 6296575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 6306575fa76SShaik Ameer Basha SRC_TOP3, 16, 1), 6316575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 6326575fa76SShaik Ameer Basha SRC_TOP3, 20, 1), 6336b5ae463SShaik Ameer Basha MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 6346b5ae463SShaik Ameer Basha SRC_TOP3, 24, 1), 635dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 6361609027fSChander Kashyap SRC_TOP3, 28, 1), 6371609027fSChander Kashyap 638dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 6391609027fSChander Kashyap SRC_TOP4, 0, 1), 6403a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 6413a767b35SShaik Ameer Basha SRC_TOP4, 4, 1), 642faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 643faec151bSShaik Ameer Basha SRC_TOP4, 8, 1), 6443a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 6453a767b35SShaik Ameer Basha SRC_TOP4, 12, 1), 6463a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 6473a767b35SShaik Ameer Basha SRC_TOP4, 16, 1), 648dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 649dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 650c0fb262bSArun Kumar K MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 651c0fb262bSArun Kumar K SRC_TOP4, 28, 1), 6521609027fSChander Kashyap 65388560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 65488560100SJavier Martinez Canillas mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 655faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 656faec151bSShaik Ameer Basha SRC_TOP5, 4, 1), 6573fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 6583fac5941SShaik Ameer Basha SRC_TOP5, 8, 1), 6593fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 6603fac5941SShaik Ameer Basha SRC_TOP5, 12, 1), 66145f10dabSMarek Szyprowski MUX_F(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 66245f10dabSMarek Szyprowski SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0), 663dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 6641609027fSChander Kashyap SRC_TOP5, 20, 1), 66588560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 66688560100SJavier Martinez Canillas mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 667c0feb268SMarek Szyprowski MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 668c0feb268SMarek Szyprowski mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 6691609027fSChander Kashyap 670dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 67145f10dabSMarek Szyprowski MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1, 67245f10dabSMarek Szyprowski CLK_SET_RATE_PARENT, 0), 6732f57b95cSLukasz Luba MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 674dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 675dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 676599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, 677599cebeaSSylwester Nawrocki CLK_SET_RATE_PARENT, 0), 678dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 679dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 6801609027fSChander Kashyap 6813a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 6823a767b35SShaik Ameer Basha SRC_TOP10, 0, 1), 683dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 684dbd713bbSShaik Ameer Basha SRC_TOP10, 4, 1), 68588560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 68688560100SJavier Martinez Canillas SRC_TOP10, 8, 1), 687dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 6881609027fSChander Kashyap SRC_TOP10, 12, 1), 6896575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 6906575fa76SShaik Ameer Basha SRC_TOP10, 16, 1), 6916575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 6926575fa76SShaik Ameer Basha SRC_TOP10, 20, 1), 6936b5ae463SShaik Ameer Basha MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 6946b5ae463SShaik Ameer Basha SRC_TOP10, 24, 1), 695dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 696dbd713bbSShaik Ameer Basha SRC_TOP10, 28, 1), 6973a767b35SShaik Ameer Basha 698dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 6991609027fSChander Kashyap SRC_TOP11, 0, 1), 7003a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 7013a767b35SShaik Ameer Basha SRC_TOP11, 4, 1), 702dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 7033a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 7043a767b35SShaik Ameer Basha SRC_TOP11, 12, 1), 705dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 706dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 707c0fb262bSArun Kumar K MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 708c0fb262bSArun Kumar K SRC_TOP11, 28, 1), 7091609027fSChander Kashyap 71088560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 71188560100SJavier Martinez Canillas mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 712dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 713dbd713bbSShaik Ameer Basha SRC_TOP12, 8, 1), 714dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 715dbd713bbSShaik Ameer Basha SRC_TOP12, 12, 1), 7168b066520SSylwester Nawrocki MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, 7178b066520SSylwester Nawrocki SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0), 718dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 719dbd713bbSShaik Ameer Basha SRC_TOP12, 20, 1), 72088560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 72188560100SJavier Martinez Canillas mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 722c0feb268SMarek Szyprowski MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 723c0feb268SMarek Szyprowski mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 7241609027fSChander Kashyap 7251609027fSChander Kashyap /* DISP1 Block */ 726dbd713bbSShaik Ameer Basha MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 727dbd713bbSShaik Ameer Basha MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 728dbd713bbSShaik Ameer Basha MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 729dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 730424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 7316575fa76SShaik Ameer Basha 732424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 7331609027fSChander Kashyap 734e867e8faSChanwoo Choi /* CDREX block */ 735e867e8faSChanwoo Choi MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p, 736e867e8faSChanwoo Choi SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0), 737e867e8faSChanwoo Choi MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1, 738e867e8faSChanwoo Choi CLK_SET_RATE_PARENT, 0), 739e867e8faSChanwoo Choi 7401609027fSChander Kashyap /* MAU Block */ 74131116a64SShaik Ameer Basha MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 7421609027fSChander Kashyap 7431609027fSChander Kashyap /* FSYS Block */ 744dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 745dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 746dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 747dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 748dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 749dbd713bbSShaik Ameer Basha MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 7506b5ae463SShaik Ameer Basha MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 7511609027fSChander Kashyap 7521609027fSChander Kashyap /* PERIC Block */ 753dbd713bbSShaik Ameer Basha MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 754dbd713bbSShaik Ameer Basha MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 755dbd713bbSShaik Ameer Basha MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 756dbd713bbSShaik Ameer Basha MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 757dbd713bbSShaik Ameer Basha MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 758dbd713bbSShaik Ameer Basha MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 759dbd713bbSShaik Ameer Basha MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 760dbd713bbSShaik Ameer Basha MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 761dbd713bbSShaik Ameer Basha MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 762dbd713bbSShaik Ameer Basha MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 763dbd713bbSShaik Ameer Basha MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 764dbd713bbSShaik Ameer Basha MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 7653a767b35SShaik Ameer Basha 7663a767b35SShaik Ameer Basha /* ISP Block */ 7673a767b35SShaik Ameer Basha MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 7683a767b35SShaik Ameer Basha MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 7693a767b35SShaik Ameer Basha MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 7703a767b35SShaik Ameer Basha MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 7713a767b35SShaik Ameer Basha MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 7721609027fSChander Kashyap }; 7731609027fSChander Kashyap 774ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 775cba9d2faSAndrzej Hajda DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 776cba9d2faSAndrzej Hajda DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 777cba9d2faSAndrzej Hajda DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 778dbd713bbSShaik Ameer Basha DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 779cba9d2faSAndrzej Hajda DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 7801609027fSChander Kashyap 78181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 78281fed6e3SChanwoo Choi DIV_TOP0, 0, 3), 78381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 78481fed6e3SChanwoo Choi DIV_TOP0, 4, 3), 78581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 78681fed6e3SChanwoo Choi DIV_TOP0, 8, 3), 78781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 78881fed6e3SChanwoo Choi DIV_TOP0, 12, 3), 78981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 79081fed6e3SChanwoo Choi DIV_TOP0, 20, 3), 79181fed6e3SChanwoo Choi DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 79281fed6e3SChanwoo Choi DIV_TOP0, 24, 3), 79381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 79481fed6e3SChanwoo Choi DIV_TOP0, 28, 3), 79581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 79681fed6e3SChanwoo Choi "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 79781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 79881fed6e3SChanwoo Choi "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 79981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 80081fed6e3SChanwoo Choi DIV_TOP1, 8, 6), 80181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 80281fed6e3SChanwoo Choi "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 80381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 80481fed6e3SChanwoo Choi DIV_TOP1, 20, 3), 80581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 80681fed6e3SChanwoo Choi DIV_TOP1, 24, 3), 80781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 80881fed6e3SChanwoo Choi DIV_TOP1, 28, 3), 8091609027fSChander Kashyap 81081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 81181fed6e3SChanwoo Choi DIV_TOP2, 8, 3), 81281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 81381fed6e3SChanwoo Choi DIV_TOP2, 12, 3), 81445f10dabSMarek Szyprowski DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 81545f10dabSMarek Szyprowski 16, 3, CLK_SET_RATE_PARENT, 0), 81681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 81781fed6e3SChanwoo Choi DIV_TOP2, 20, 3), 81881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 81981fed6e3SChanwoo Choi "mout_aclk300_disp1", DIV_TOP2, 24, 3), 82081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 82181fed6e3SChanwoo Choi DIV_TOP2, 28, 3), 8221609027fSChander Kashyap 8231609027fSChander Kashyap /* DISP1 Block */ 824424b673aSShaik Ameer Basha DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 825cba9d2faSAndrzej Hajda DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 826cba9d2faSAndrzej Hajda DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 827cba9d2faSAndrzej Hajda DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 82881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 82981fed6e3SChanwoo Choi "mout_aclk400_disp1", DIV_TOP2, 4, 3), 8301609027fSChander Kashyap 831e867e8faSChanwoo Choi /* CDREX Block */ 8322f57b95cSLukasz Luba /* 8332f57b95cSLukasz Luba * The three clocks below are controlled using the same register and 8342f57b95cSLukasz Luba * bits. They are put into one because there is a need of 8352f57b95cSLukasz Luba * synchronization between the BUS and DREXs (two external memory 8362f57b95cSLukasz Luba * interfaces). 8372f57b95cSLukasz Luba * They are put here to show this HW assumption and for clock 8382f57b95cSLukasz Luba * information summary completeness. 8392f57b95cSLukasz Luba */ 8402f57b95cSLukasz Luba DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", 8412f57b95cSLukasz Luba DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 8422f57b95cSLukasz Luba DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0", 8432f57b95cSLukasz Luba DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 8442f57b95cSLukasz Luba DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0", 8452f57b95cSLukasz Luba DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 8462f57b95cSLukasz Luba 847e867e8faSChanwoo Choi DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", 848e867e8faSChanwoo Choi DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), 849e867e8faSChanwoo Choi DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", 850e867e8faSChanwoo Choi DIV_CDREX0, 16, 3), 851e867e8faSChanwoo Choi DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", 852e867e8faSChanwoo Choi DIV_CDREX0, 8, 3), 853e867e8faSChanwoo Choi DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", 854e867e8faSChanwoo Choi DIV_CDREX0, 3, 5), 855e867e8faSChanwoo Choi 856e867e8faSChanwoo Choi DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", 857e867e8faSChanwoo Choi DIV_CDREX1, 8, 3), 858e867e8faSChanwoo Choi 8591609027fSChander Kashyap /* Audio Block */ 860cba9d2faSAndrzej Hajda DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 861cba9d2faSAndrzej Hajda DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 8621609027fSChander Kashyap 8631609027fSChander Kashyap /* USB3.0 */ 864cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 865cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 866cba9d2faSAndrzej Hajda DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 867cba9d2faSAndrzej Hajda DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 8681609027fSChander Kashyap 8691609027fSChander Kashyap /* MMC */ 870cba9d2faSAndrzej Hajda DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 871cba9d2faSAndrzej Hajda DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 872cba9d2faSAndrzej Hajda DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 8731609027fSChander Kashyap 874cba9d2faSAndrzej Hajda DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 8756b5ae463SShaik Ameer Basha DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 8761609027fSChander Kashyap 8771609027fSChander Kashyap /* UART and PWM */ 878cba9d2faSAndrzej Hajda DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 879cba9d2faSAndrzej Hajda DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 880cba9d2faSAndrzej Hajda DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 881cba9d2faSAndrzej Hajda DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 882cba9d2faSAndrzej Hajda DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 8831609027fSChander Kashyap 8841609027fSChander Kashyap /* SPI */ 885cba9d2faSAndrzej Hajda DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 886cba9d2faSAndrzej Hajda DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 887cba9d2faSAndrzej Hajda DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 8881609027fSChander Kashyap 8891d87db4dSShaik Ameer Basha 8901609027fSChander Kashyap /* PCM */ 891cba9d2faSAndrzej Hajda DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 892cba9d2faSAndrzej Hajda DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 8931609027fSChander Kashyap 8941609027fSChander Kashyap /* Audio - I2S */ 895cba9d2faSAndrzej Hajda DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 896cba9d2faSAndrzej Hajda DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 897cba9d2faSAndrzej Hajda DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 898cba9d2faSAndrzej Hajda DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 899cba9d2faSAndrzej Hajda DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 9001609027fSChander Kashyap 9011609027fSChander Kashyap /* SPI Pre-Ratio */ 902faec151bSShaik Ameer Basha DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 903faec151bSShaik Ameer Basha DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 904faec151bSShaik Ameer Basha DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 9053a767b35SShaik Ameer Basha 90602932381SShaik Ameer Basha /* GSCL Block */ 90702932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 90802932381SShaik Ameer Basha 9090a22c306SShaik Ameer Basha /* PSGEN */ 9100a22c306SShaik Ameer Basha DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 9110a22c306SShaik Ameer Basha DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 9120a22c306SShaik Ameer Basha 9133a767b35SShaik Ameer Basha /* ISP Block */ 9143a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 9153a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 9163a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 9173a767b35SShaik Ameer Basha DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 9183a767b35SShaik Ameer Basha DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 9193a767b35SShaik Ameer Basha DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 9203a767b35SShaik Ameer Basha DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 9213a767b35SShaik Ameer Basha DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 9223a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 9233a767b35SShaik Ameer Basha DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 9243a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 9251609027fSChander Kashyap }; 9261609027fSChander Kashyap 927ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 9285b73721bSNaveen Krishna Chatradhi /* G2D */ 9293fac5941SShaik Ameer Basha GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 9305b73721bSNaveen Krishna Chatradhi GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 9313fac5941SShaik Ameer Basha GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 9323fac5941SShaik Ameer Basha GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 9333fac5941SShaik Ameer Basha GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 9345b73721bSNaveen Krishna Chatradhi 9351609027fSChander Kashyap GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 936318fa46cSMarek Szyprowski GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), 9371609027fSChander Kashyap GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 9381609027fSChander Kashyap GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 9391609027fSChander Kashyap 9401609027fSChander Kashyap GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 9411609027fSChander Kashyap GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 9421609027fSChander Kashyap GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 943318fa46cSMarek Szyprowski GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), 9441609027fSChander Kashyap GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 9451609027fSChander Kashyap GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 9463a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 947e47bd937SMarek Szyprowski GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0), 9481609027fSChander Kashyap GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 949318fa46cSMarek Szyprowski GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), 9501609027fSChander Kashyap GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 9511609027fSChander Kashyap GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 9523a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 953e47bd937SMarek Szyprowski GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0), 954b31ca2a0SShaik Ameer Basha GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 9551609027fSChander Kashyap GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 956faec151bSShaik Ameer Basha GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 9571609027fSChander Kashyap GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 9583a767b35SShaik Ameer Basha GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 959e47bd937SMarek Szyprowski GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0), 9601609027fSChander Kashyap GATE(0, "aclk166", "mout_user_aclk166", 9611609027fSChander Kashyap GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 96234cba900SJavier Martinez Canillas GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", 963318fa46cSMarek Szyprowski GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), 9643a767b35SShaik Ameer Basha GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 965e47bd937SMarek Szyprowski GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0), 96602932381SShaik Ameer Basha GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 967c07c1a0fSAndrzej Pietrasiewicz GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), 968424b673aSShaik Ameer Basha GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 969318fa46cSMarek Szyprowski GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), 970b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 971b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 28, 0, 0), 972b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 973b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 29, 0, 0), 974424b673aSShaik Ameer Basha 975424b673aSShaik Ameer Basha GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 976318fa46cSMarek Szyprowski SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), 9771609027fSChander Kashyap 9781609027fSChander Kashyap /* sclk */ 979cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 9801609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 981cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 9821609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 983cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 9841609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 985cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 9861609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 987faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 9881609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 989faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 9901609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 991faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 9921609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 993cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 9941609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 995cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 9961609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 997cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 9981609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 999cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 10001609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 1001cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 10021609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 1003cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 10041609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 10051609027fSChander Kashyap 1006cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 10071609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 1008cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 10091609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 1010cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 10111609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 1012cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 10131609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 1014cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 10151609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 1016cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 10171609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 1018cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 10191609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 10201609027fSChander Kashyap 10211609027fSChander Kashyap /* Display */ 1022cba9d2faSAndrzej Hajda GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 10231609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 1024cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 10251609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 1026cba9d2faSAndrzej Hajda GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 1027424b673aSShaik Ameer Basha GATE_TOP_SCLK_DISP1, 9, 0, 0), 1028cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 10291609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 1030cba9d2faSAndrzej Hajda GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 10311609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 10321609027fSChander Kashyap 10336b5ae463SShaik Ameer Basha /* FSYS Block */ 1034cba9d2faSAndrzej Hajda GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1035cba9d2faSAndrzej Hajda GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1036cba9d2faSAndrzej Hajda GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1037cba9d2faSAndrzej Hajda GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 10386b5ae463SShaik Ameer Basha GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 10396b5ae463SShaik Ameer Basha GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 10406b5ae463SShaik Ameer Basha GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 10416b5ae463SShaik Ameer Basha GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1042cba9d2faSAndrzej Hajda GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 10436b5ae463SShaik Ameer Basha GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 10446b5ae463SShaik Ameer Basha GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 10456b5ae463SShaik Ameer Basha GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 10466b5ae463SShaik Ameer Basha GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 10476b5ae463SShaik Ameer Basha GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 10486b5ae463SShaik Ameer Basha SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 10491609027fSChander Kashyap 1050faec151bSShaik Ameer Basha /* PERIC Block */ 105144ff0254SDoug Anderson GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 105244ff0254SDoug Anderson GATE_IP_PERIC, 0, 0, 0), 105344ff0254SDoug Anderson GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 105444ff0254SDoug Anderson GATE_IP_PERIC, 1, 0, 0), 105544ff0254SDoug Anderson GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 105644ff0254SDoug Anderson GATE_IP_PERIC, 2, 0, 0), 105744ff0254SDoug Anderson GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 105844ff0254SDoug Anderson GATE_IP_PERIC, 3, 0, 0), 105944ff0254SDoug Anderson GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 106044ff0254SDoug Anderson GATE_IP_PERIC, 6, 0, 0), 106144ff0254SDoug Anderson GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 106244ff0254SDoug Anderson GATE_IP_PERIC, 7, 0, 0), 106344ff0254SDoug Anderson GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 106444ff0254SDoug Anderson GATE_IP_PERIC, 8, 0, 0), 106544ff0254SDoug Anderson GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 106644ff0254SDoug Anderson GATE_IP_PERIC, 9, 0, 0), 106744ff0254SDoug Anderson GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 106844ff0254SDoug Anderson GATE_IP_PERIC, 10, 0, 0), 106944ff0254SDoug Anderson GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 107044ff0254SDoug Anderson GATE_IP_PERIC, 11, 0, 0), 107144ff0254SDoug Anderson GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 107244ff0254SDoug Anderson GATE_IP_PERIC, 12, 0, 0), 107344ff0254SDoug Anderson GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 107444ff0254SDoug Anderson GATE_IP_PERIC, 13, 0, 0), 107544ff0254SDoug Anderson GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 107644ff0254SDoug Anderson GATE_IP_PERIC, 14, 0, 0), 107744ff0254SDoug Anderson GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 107844ff0254SDoug Anderson GATE_IP_PERIC, 15, 0, 0), 107944ff0254SDoug Anderson GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 108044ff0254SDoug Anderson GATE_IP_PERIC, 16, 0, 0), 108144ff0254SDoug Anderson GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 108244ff0254SDoug Anderson GATE_IP_PERIC, 17, 0, 0), 108344ff0254SDoug Anderson GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 108444ff0254SDoug Anderson GATE_IP_PERIC, 18, 0, 0), 108544ff0254SDoug Anderson GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 108644ff0254SDoug Anderson GATE_IP_PERIC, 20, 0, 0), 108744ff0254SDoug Anderson GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 108844ff0254SDoug Anderson GATE_IP_PERIC, 21, 0, 0), 108944ff0254SDoug Anderson GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 109044ff0254SDoug Anderson GATE_IP_PERIC, 22, 0, 0), 109144ff0254SDoug Anderson GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 109244ff0254SDoug Anderson GATE_IP_PERIC, 23, 0, 0), 109344ff0254SDoug Anderson GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 109444ff0254SDoug Anderson GATE_IP_PERIC, 24, 0, 0), 109544ff0254SDoug Anderson GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 109644ff0254SDoug Anderson GATE_IP_PERIC, 26, 0, 0), 109744ff0254SDoug Anderson GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 109844ff0254SDoug Anderson GATE_IP_PERIC, 28, 0, 0), 109944ff0254SDoug Anderson GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 110044ff0254SDoug Anderson GATE_IP_PERIC, 30, 0, 0), 110144ff0254SDoug Anderson GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 110244ff0254SDoug Anderson GATE_IP_PERIC, 31, 0, 0), 11031609027fSChander Kashyap 110444ff0254SDoug Anderson GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 110544ff0254SDoug Anderson GATE_BUS_PERIC, 22, 0, 0), 11061609027fSChander Kashyap 11070a22c306SShaik Ameer Basha /* PERIS Block */ 1108cba9d2faSAndrzej Hajda GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 11090a22c306SShaik Ameer Basha GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1110cba9d2faSAndrzej Hajda GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 11110a22c306SShaik Ameer Basha GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 11120a22c306SShaik Ameer Basha GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 11130a22c306SShaik Ameer Basha GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 11140a22c306SShaik Ameer Basha GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 11150a22c306SShaik Ameer Basha GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 11160a22c306SShaik Ameer Basha GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 11170a22c306SShaik Ameer Basha GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 11180a22c306SShaik Ameer Basha GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 11190a22c306SShaik Ameer Basha GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 11200a22c306SShaik Ameer Basha GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 11210a22c306SShaik Ameer Basha GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 11220a22c306SShaik Ameer Basha GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 11230a22c306SShaik Ameer Basha GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 11240a22c306SShaik Ameer Basha GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 11250a22c306SShaik Ameer Basha GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 11260a22c306SShaik Ameer Basha GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 11270a22c306SShaik Ameer Basha GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 11281609027fSChander Kashyap 11290a22c306SShaik Ameer Basha /* GEN Block */ 11300a22c306SShaik Ameer Basha GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 11310a22c306SShaik Ameer Basha GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 11320a22c306SShaik Ameer Basha GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 11330a22c306SShaik Ameer Basha GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 11340a22c306SShaik Ameer Basha GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 11350a22c306SShaik Ameer Basha GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 11360a22c306SShaik Ameer Basha GATE_IP_GEN, 6, 0, 0), 11370a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 11380a22c306SShaik Ameer Basha GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 11390a22c306SShaik Ameer Basha GATE_IP_GEN, 9, 0, 0), 11400a22c306SShaik Ameer Basha 11410a22c306SShaik Ameer Basha /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 11420a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 11430a22c306SShaik Ameer Basha GATE_BUS_GEN, 28, 0, 0), 11440a22c306SShaik Ameer Basha GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 11451609027fSChander Kashyap 114602932381SShaik Ameer Basha /* GSCL Block */ 114702932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 114802932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 6, 0, 0), 114902932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 115002932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 7, 0, 0), 115102932381SShaik Ameer Basha 115202932381SShaik Ameer Basha GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 115302932381SShaik Ameer Basha GATE_IP_GSCL0, 4, 0, 0), 115402932381SShaik Ameer Basha GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 115502932381SShaik Ameer Basha GATE_IP_GSCL0, 5, 0, 0), 115602932381SShaik Ameer Basha GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 115702932381SShaik Ameer Basha GATE_IP_GSCL0, 6, 0, 0), 11581609027fSChander Kashyap 115902932381SShaik Ameer Basha GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 116002932381SShaik Ameer Basha GATE_IP_GSCL1, 2, 0, 0), 116102932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 11621609027fSChander Kashyap GATE_IP_GSCL1, 3, 0, 0), 116302932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 11641609027fSChander Kashyap GATE_IP_GSCL1, 4, 0, 0), 1165e47bd937SMarek Szyprowski GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 1166e47bd937SMarek Szyprowski CLK_IS_CRITICAL, 0), 1167e47bd937SMarek Szyprowski GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 1168e47bd937SMarek Szyprowski CLK_IS_CRITICAL, 0), 11694b159cf1SMarek Szyprowski GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3", "dout_gscl_blk_333", 11701609027fSChander Kashyap GATE_IP_GSCL1, 16, 0, 0), 1171cba9d2faSAndrzej Hajda GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 11721609027fSChander Kashyap GATE_IP_GSCL1, 17, 0, 0), 11731609027fSChander Kashyap 11743a767b35SShaik Ameer Basha /* ISP */ 11753a767b35SShaik Ameer Basha GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 11763a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 11773a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 11783a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 11793a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 11803a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 11813a767b35SShaik Ameer Basha GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 11823a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 11833a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 11843a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 11853a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 11863a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 11873a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 11883a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 11893a767b35SShaik Ameer Basha 11902f57b95cSLukasz Luba /* CDREX */ 11912f57b95cSLukasz Luba GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", 11922f57b95cSLukasz Luba GATE_BUS_CDREX0, 0, 0, 0), 11932f57b95cSLukasz Luba GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex", 11942f57b95cSLukasz Luba GATE_BUS_CDREX0, 1, 0, 0), 11952f57b95cSLukasz Luba GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy", 11962f57b95cSLukasz Luba SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0), 11972f57b95cSLukasz Luba 11982f57b95cSLukasz Luba GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1", 11992f57b95cSLukasz Luba GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0), 12002f57b95cSLukasz Luba GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1", 12012f57b95cSLukasz Luba GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0), 12022f57b95cSLukasz Luba GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1", 12032f57b95cSLukasz Luba GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0), 12042f57b95cSLukasz Luba GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1", 12052f57b95cSLukasz Luba GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0), 12062f57b95cSLukasz Luba 12072f57b95cSLukasz Luba GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex", 12082f57b95cSLukasz Luba GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0), 12092f57b95cSLukasz Luba GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex", 12102f57b95cSLukasz Luba GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0), 12112f57b95cSLukasz Luba GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex", 12122f57b95cSLukasz Luba GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0), 12132f57b95cSLukasz Luba GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex", 12142f57b95cSLukasz Luba GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0), 1215ec4016ffSMarek Szyprowski }; 1216ec4016ffSMarek Szyprowski 1217ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { 1218ec4016ffSMarek Szyprowski DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 1219ec4016ffSMarek Szyprowski }; 1220ec4016ffSMarek Szyprowski 1221ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { 1222ec4016ffSMarek Szyprowski GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1223ec4016ffSMarek Szyprowski GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1224ec4016ffSMarek Szyprowski GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1225ec4016ffSMarek Szyprowski GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1226ec4016ffSMarek Szyprowski GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1227ec4016ffSMarek Szyprowski GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1228ec4016ffSMarek Szyprowski GATE_IP_DISP1, 7, 0, 0), 1229ec4016ffSMarek Szyprowski GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1230ec4016ffSMarek Szyprowski GATE_IP_DISP1, 8, 0, 0), 1231ec4016ffSMarek Szyprowski GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1232ec4016ffSMarek Szyprowski GATE_IP_DISP1, 9, 0, 0), 1233ec4016ffSMarek Szyprowski }; 1234ec4016ffSMarek Szyprowski 1235ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = { 1236ec4016ffSMarek Szyprowski { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ 1237ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ 1238ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ 1239ec4016ffSMarek Szyprowski { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ 1240ec4016ffSMarek Szyprowski { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ 1241ec4016ffSMarek Szyprowski }; 1242ec4016ffSMarek Szyprowski 1243ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { 1244ec4016ffSMarek Szyprowski DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 1245ec4016ffSMarek Szyprowski DIV2_RATIO0, 4, 2), 1246ec4016ffSMarek Szyprowski }; 1247ec4016ffSMarek Szyprowski 1248ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { 1249ec4016ffSMarek Szyprowski GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1250ec4016ffSMarek Szyprowski GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1251ec4016ffSMarek Szyprowski GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 1252ec4016ffSMarek Szyprowski GATE_IP_GSCL1, 6, 0, 0), 1253ec4016ffSMarek Szyprowski GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 1254ec4016ffSMarek Szyprowski GATE_IP_GSCL1, 7, 0, 0), 1255ec4016ffSMarek Szyprowski }; 1256ec4016ffSMarek Szyprowski 1257ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { 1258ec4016ffSMarek Szyprowski { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ 1259ec4016ffSMarek Szyprowski { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ 1260ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ 1261ec4016ffSMarek Szyprowski { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ 1262ec4016ffSMarek Szyprowski }; 1263ec4016ffSMarek Szyprowski 1264c9f7567aSMarek Szyprowski static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = { 126545f10dabSMarek Szyprowski GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 126645f10dabSMarek Szyprowski CLK_SET_RATE_PARENT, 0), 1267c9f7567aSMarek Szyprowski }; 1268c9f7567aSMarek Szyprowski 1269c9f7567aSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = { 1270c9f7567aSMarek Szyprowski { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */ 1271c9f7567aSMarek Szyprowski { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */ 1272c9f7567aSMarek Szyprowski }; 1273c9f7567aSMarek Szyprowski 1274ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { 1275ec4016ffSMarek Szyprowski DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 1276ec4016ffSMarek Szyprowski }; 1277ec4016ffSMarek Szyprowski 1278ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { 1279cba9d2faSAndrzej Hajda GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 12801d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 12811d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 1282ec4016ffSMarek Szyprowski }; 12831609027fSChander Kashyap 1284ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { 1285ec4016ffSMarek Szyprowski { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ 1286ec4016ffSMarek Szyprowski { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ 1287ec4016ffSMarek Szyprowski { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ 1288ec4016ffSMarek Szyprowski }; 1289ec4016ffSMarek Szyprowski 1290baf7b79eSMarek Szyprowski static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = { 1291baf7b79eSMarek Szyprowski /* MSCL Block */ 1292baf7b79eSMarek Szyprowski GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 1293baf7b79eSMarek Szyprowski GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 1294baf7b79eSMarek Szyprowski GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 1295baf7b79eSMarek Szyprowski GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 1296baf7b79eSMarek Szyprowski GATE_IP_MSCL, 8, 0, 0), 1297baf7b79eSMarek Szyprowski GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 1298baf7b79eSMarek Szyprowski GATE_IP_MSCL, 9, 0, 0), 1299baf7b79eSMarek Szyprowski GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 1300baf7b79eSMarek Szyprowski GATE_IP_MSCL, 10, 0, 0), 1301baf7b79eSMarek Szyprowski }; 1302baf7b79eSMarek Szyprowski 1303baf7b79eSMarek Szyprowski static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = { 1304baf7b79eSMarek Szyprowski DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 1305baf7b79eSMarek Szyprowski }; 1306baf7b79eSMarek Szyprowski 1307baf7b79eSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = { 1308baf7b79eSMarek Szyprowski { GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */ 1309baf7b79eSMarek Szyprowski { SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */ 1310baf7b79eSMarek Szyprowski { DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */ 1311baf7b79eSMarek Szyprowski }; 1312b6adeb6bSSylwester Nawrocki 1313b6adeb6bSSylwester Nawrocki static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = { 1314b6adeb6bSSylwester Nawrocki GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", 1315b6adeb6bSSylwester Nawrocki SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 1316b6adeb6bSSylwester Nawrocki GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 1317b6adeb6bSSylwester Nawrocki GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1318b6adeb6bSSylwester Nawrocki GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 1319b6adeb6bSSylwester Nawrocki GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 1320b6adeb6bSSylwester Nawrocki }; 1321b6adeb6bSSylwester Nawrocki 1322b6adeb6bSSylwester Nawrocki static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = { 1323b6adeb6bSSylwester Nawrocki { SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */ 1324b6adeb6bSSylwester Nawrocki }; 1325b6adeb6bSSylwester Nawrocki 1326bf32e7dbSSylwester Nawrocki static const struct exynos5_subcmu_info exynos5x_disp_subcmu = { 1327ec4016ffSMarek Szyprowski .div_clks = exynos5x_disp_div_clks, 1328ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), 1329ec4016ffSMarek Szyprowski .gate_clks = exynos5x_disp_gate_clks, 1330ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), 1331ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_disp_suspend_regs, 1332ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), 1333ec4016ffSMarek Szyprowski .pd_name = "DISP", 1334bf32e7dbSSylwester Nawrocki }; 1335bf32e7dbSSylwester Nawrocki 1336bf32e7dbSSylwester Nawrocki static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = { 1337ec4016ffSMarek Szyprowski .div_clks = exynos5x_gsc_div_clks, 1338ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), 1339ec4016ffSMarek Szyprowski .gate_clks = exynos5x_gsc_gate_clks, 1340ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), 1341ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_gsc_suspend_regs, 1342ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), 1343ec4016ffSMarek Szyprowski .pd_name = "GSC", 1344bf32e7dbSSylwester Nawrocki }; 1345bf32e7dbSSylwester Nawrocki 1346c9f7567aSMarek Szyprowski static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = { 1347c9f7567aSMarek Szyprowski .gate_clks = exynos5x_g3d_gate_clks, 1348c9f7567aSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks), 1349c9f7567aSMarek Szyprowski .suspend_regs = exynos5x_g3d_suspend_regs, 1350c9f7567aSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs), 1351c9f7567aSMarek Szyprowski .pd_name = "G3D", 1352c9f7567aSMarek Szyprowski }; 1353c9f7567aSMarek Szyprowski 1354bf32e7dbSSylwester Nawrocki static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = { 1355ec4016ffSMarek Szyprowski .div_clks = exynos5x_mfc_div_clks, 1356ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), 1357ec4016ffSMarek Szyprowski .gate_clks = exynos5x_mfc_gate_clks, 1358ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), 1359ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_mfc_suspend_regs, 1360ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), 1361ec4016ffSMarek Szyprowski .pd_name = "MFC", 1362bf32e7dbSSylwester Nawrocki }; 1363bf32e7dbSSylwester Nawrocki 1364baf7b79eSMarek Szyprowski static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = { 1365baf7b79eSMarek Szyprowski .div_clks = exynos5x_mscl_div_clks, 1366baf7b79eSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_mscl_div_clks), 1367baf7b79eSMarek Szyprowski .gate_clks = exynos5x_mscl_gate_clks, 1368baf7b79eSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_mscl_gate_clks), 1369baf7b79eSMarek Szyprowski .suspend_regs = exynos5x_mscl_suspend_regs, 1370baf7b79eSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_mscl_suspend_regs), 1371baf7b79eSMarek Szyprowski .pd_name = "MSC", 1372baf7b79eSMarek Szyprowski }; 1373baf7b79eSMarek Szyprowski 1374b6adeb6bSSylwester Nawrocki static const struct exynos5_subcmu_info exynos5800_mau_subcmu = { 1375b6adeb6bSSylwester Nawrocki .gate_clks = exynos5800_mau_gate_clks, 1376b6adeb6bSSylwester Nawrocki .nr_gate_clks = ARRAY_SIZE(exynos5800_mau_gate_clks), 1377b6adeb6bSSylwester Nawrocki .suspend_regs = exynos5800_mau_suspend_regs, 1378b6adeb6bSSylwester Nawrocki .nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs), 1379b6adeb6bSSylwester Nawrocki .pd_name = "MAU", 1380b6adeb6bSSylwester Nawrocki }; 1381b6adeb6bSSylwester Nawrocki 1382bf32e7dbSSylwester Nawrocki static const struct exynos5_subcmu_info *exynos5x_subcmus[] = { 1383bf32e7dbSSylwester Nawrocki &exynos5x_disp_subcmu, 1384bf32e7dbSSylwester Nawrocki &exynos5x_gsc_subcmu, 1385c9f7567aSMarek Szyprowski &exynos5x_g3d_subcmu, 1386bf32e7dbSSylwester Nawrocki &exynos5x_mfc_subcmu, 1387baf7b79eSMarek Szyprowski &exynos5x_mscl_subcmu, 13881609027fSChander Kashyap }; 13891609027fSChander Kashyap 1390b6adeb6bSSylwester Nawrocki static const struct exynos5_subcmu_info *exynos5800_subcmus[] = { 1391b6adeb6bSSylwester Nawrocki &exynos5x_disp_subcmu, 1392b6adeb6bSSylwester Nawrocki &exynos5x_gsc_subcmu, 1393c9f7567aSMarek Szyprowski &exynos5x_g3d_subcmu, 1394b6adeb6bSSylwester Nawrocki &exynos5x_mfc_subcmu, 1395baf7b79eSMarek Szyprowski &exynos5x_mscl_subcmu, 1396b6adeb6bSSylwester Nawrocki &exynos5800_mau_subcmu, 1397b6adeb6bSSylwester Nawrocki }; 1398b6adeb6bSSylwester Nawrocki 1399ebd217e1SKrzysztof Kozlowski static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { 14001d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0), 14011d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0), 14021d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0), 14031d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), 14041d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 14051d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 14061d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 14071d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 14081d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1), 14091d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), 14101d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), 14111d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1), 14121d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), 14131d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 14141d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2), 14151d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), 14161d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), 14171d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3), 14181d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), 1419ca5b4029SThomas Abraham }; 1420ca5b4029SThomas Abraham 14218b4a7acfSLukasz Luba static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { 14228b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), 14238b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), 14248b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), 14258b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), 14268b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), 14278b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), 14288b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), 14298b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), 14308b4a7acfSLukasz Luba }; 14318b4a7acfSLukasz Luba 14329842452aSSylwester Nawrocki static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 14331d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), 14341d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), 14351d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), 14361d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671), 14371d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0), 14381d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), 14391d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671), 14401d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719), 14411d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0), 1442948e0684SSylwester Nawrocki PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923), 1443948e0684SSylwester Nawrocki PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762), 14441d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719), 14451d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690), 1446948e0684SSylwester Nawrocki PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762), 14471d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), 14489842452aSSylwester Nawrocki }; 14499842452aSSylwester Nawrocki 1450b92981deSMarian Mihailescu static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = { 1451b92981deSMarian Mihailescu PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2), 1452b92981deSMarian Mihailescu PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2), 1453b92981deSMarian Mihailescu PLL_35XX_RATE(24 * MHZ, 480000000U, 160, 2, 2), 1454b92981deSMarian Mihailescu PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2), 1455b92981deSMarian Mihailescu PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2), 1456b92981deSMarian Mihailescu PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3), 1457b92981deSMarian Mihailescu PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3), 1458b92981deSMarian Mihailescu PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4), 1459b92981deSMarian Mihailescu }; 1460b92981deSMarian Mihailescu 14616520e968SAlim Akhtar static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1462cba9d2faSAndrzej Hajda [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 14633ff6e0d8SYadwinder Singh Brar APLL_CON0, NULL), 1464cba9d2faSAndrzej Hajda [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1465cdf64eeeSChander Kashyap CPLL_CON0, NULL), 1466cba9d2faSAndrzej Hajda [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 14673ff6e0d8SYadwinder Singh Brar DPLL_CON0, NULL), 14689842452aSSylwester Nawrocki [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 14693ff6e0d8SYadwinder Singh Brar EPLL_CON0, NULL), 1470cba9d2faSAndrzej Hajda [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 14713ff6e0d8SYadwinder Singh Brar RPLL_CON0, NULL), 1472cba9d2faSAndrzej Hajda [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 14733ff6e0d8SYadwinder Singh Brar IPLL_CON0, NULL), 1474cba9d2faSAndrzej Hajda [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 14753ff6e0d8SYadwinder Singh Brar SPLL_CON0, NULL), 1476cba9d2faSAndrzej Hajda [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 14773ff6e0d8SYadwinder Singh Brar VPLL_CON0, NULL), 1478cba9d2faSAndrzej Hajda [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 14793ff6e0d8SYadwinder Singh Brar MPLL_CON0, NULL), 1480cba9d2faSAndrzej Hajda [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 14813ff6e0d8SYadwinder Singh Brar BPLL_CON0, NULL), 1482cba9d2faSAndrzej Hajda [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 14833ff6e0d8SYadwinder Singh Brar KPLL_CON0, NULL), 1484c898c6b7SYadwinder Singh Brar }; 1485c898c6b7SYadwinder Singh Brar 1486bee4f87fSThomas Abraham #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1487bee4f87fSThomas Abraham ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1488bee4f87fSThomas Abraham ((cpud) << 4))) 1489bee4f87fSThomas Abraham 1490bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1491bee4f87fSThomas Abraham { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1492bee4f87fSThomas Abraham { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1493bee4f87fSThomas Abraham { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1494bee4f87fSThomas Abraham { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1495bee4f87fSThomas Abraham { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1496bee4f87fSThomas Abraham { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1497bee4f87fSThomas Abraham { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1498bee4f87fSThomas Abraham { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1499bee4f87fSThomas Abraham { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1500bee4f87fSThomas Abraham { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1501bee4f87fSThomas Abraham { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1502bee4f87fSThomas Abraham { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1503bee4f87fSThomas Abraham { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1504bee4f87fSThomas Abraham { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1505bee4f87fSThomas Abraham { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1506bee4f87fSThomas Abraham { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1507bee4f87fSThomas Abraham { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1508bee4f87fSThomas Abraham { 0 }, 1509bee4f87fSThomas Abraham }; 1510bee4f87fSThomas Abraham 151154abbdb4SBartlomiej Zolnierkiewicz static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 151254abbdb4SBartlomiej Zolnierkiewicz { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 151354abbdb4SBartlomiej Zolnierkiewicz { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 151454abbdb4SBartlomiej Zolnierkiewicz { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 151554abbdb4SBartlomiej Zolnierkiewicz { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 151654abbdb4SBartlomiej Zolnierkiewicz { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 151754abbdb4SBartlomiej Zolnierkiewicz { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 151854abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 151954abbdb4SBartlomiej Zolnierkiewicz { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 152054abbdb4SBartlomiej Zolnierkiewicz { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 152154abbdb4SBartlomiej Zolnierkiewicz { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 152254abbdb4SBartlomiej Zolnierkiewicz { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 152354abbdb4SBartlomiej Zolnierkiewicz { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 152454abbdb4SBartlomiej Zolnierkiewicz { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 152554abbdb4SBartlomiej Zolnierkiewicz { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 152654abbdb4SBartlomiej Zolnierkiewicz { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 152754abbdb4SBartlomiej Zolnierkiewicz { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 152854abbdb4SBartlomiej Zolnierkiewicz { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 152954abbdb4SBartlomiej Zolnierkiewicz { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 153054abbdb4SBartlomiej Zolnierkiewicz { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 153154abbdb4SBartlomiej Zolnierkiewicz { 0 }, 153254abbdb4SBartlomiej Zolnierkiewicz }; 153354abbdb4SBartlomiej Zolnierkiewicz 1534bee4f87fSThomas Abraham #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1535bee4f87fSThomas Abraham ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1536bee4f87fSThomas Abraham 1537bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 153854abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1539bee4f87fSThomas Abraham { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1540bee4f87fSThomas Abraham { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1541bee4f87fSThomas Abraham { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1542bee4f87fSThomas Abraham { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1543bee4f87fSThomas Abraham { 900000, E5420_KFC_DIV(3, 5, 2), }, 1544bee4f87fSThomas Abraham { 800000, E5420_KFC_DIV(3, 5, 2), }, 1545bee4f87fSThomas Abraham { 700000, E5420_KFC_DIV(3, 4, 2), }, 1546bee4f87fSThomas Abraham { 600000, E5420_KFC_DIV(3, 4, 2), }, 1547bee4f87fSThomas Abraham { 500000, E5420_KFC_DIV(3, 4, 2), }, 1548bee4f87fSThomas Abraham { 400000, E5420_KFC_DIV(3, 3, 2), }, 1549bee4f87fSThomas Abraham { 300000, E5420_KFC_DIV(3, 3, 2), }, 1550bee4f87fSThomas Abraham { 200000, E5420_KFC_DIV(3, 3, 2), }, 1551bee4f87fSThomas Abraham { 0 }, 1552bee4f87fSThomas Abraham }; 1553bee4f87fSThomas Abraham 1554ac48ea3bSWill McVicker static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = { 1555ac48ea3bSWill McVicker CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200, 1556ac48ea3bSWill McVicker exynos5420_eglclk_d), 1557ac48ea3bSWill McVicker CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200, 1558ac48ea3bSWill McVicker exynos5420_kfcclk_d), 1559ac48ea3bSWill McVicker }; 1560ac48ea3bSWill McVicker 1561ac48ea3bSWill McVicker static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = { 1562ac48ea3bSWill McVicker CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200, 1563ac48ea3bSWill McVicker exynos5800_eglclk_d), 1564ac48ea3bSWill McVicker CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200, 1565ac48ea3bSWill McVicker exynos5420_kfcclk_d), 1566ac48ea3bSWill McVicker }; 1567ac48ea3bSWill McVicker 1568305cfab0SKrzysztof Kozlowski static const struct of_device_id ext_clk_match[] __initconst = { 15691609027fSChander Kashyap { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 15701609027fSChander Kashyap { }, 15711609027fSChander Kashyap }; 15721609027fSChander Kashyap 15731609027fSChander Kashyap /* register exynos5420 clocks */ 15746520e968SAlim Akhtar static void __init exynos5x_clk_init(struct device_node *np, 15756520e968SAlim Akhtar enum exynos5x_soc soc) 15761609027fSChander Kashyap { 1577976face4SRahul Sharma struct samsung_clk_provider *ctx; 15788b066520SSylwester Nawrocki struct clk_hw **hws; 1579976face4SRahul Sharma 15801609027fSChander Kashyap if (np) { 15811609027fSChander Kashyap reg_base = of_iomap(np, 0); 15821609027fSChander Kashyap if (!reg_base) 15831609027fSChander Kashyap panic("%s: failed to map registers\n", __func__); 15841609027fSChander Kashyap } else { 15851609027fSChander Kashyap panic("%s: unable to determine soc\n", __func__); 15861609027fSChander Kashyap } 15871609027fSChander Kashyap 15886520e968SAlim Akhtar exynos5x_soc = soc; 15896520e968SAlim Akhtar 1590*45dab818SSam Protsenko ctx = samsung_clk_init(reg_base, CLK_NR_CLKS); 1591ff8e0ff9SSylwester Nawrocki hws = ctx->clk_data.hws; 1592976face4SRahul Sharma 15936520e968SAlim Akhtar samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 15946520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 15951609027fSChander Kashyap ext_clk_match); 1596ca5b4029SThomas Abraham 1597015e7058SMarek Szyprowski if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { 1598ca5b4029SThomas Abraham exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 15999842452aSSylwester Nawrocki exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; 1600ca5b4029SThomas Abraham exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1601b92981deSMarian Mihailescu exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl; 1602ca5b4029SThomas Abraham } 1603ca5b4029SThomas Abraham 16048b4a7acfSLukasz Luba if (soc == EXYNOS5420) 16058b4a7acfSLukasz Luba exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 16068b4a7acfSLukasz Luba else 16078b4a7acfSLukasz Luba exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; 16088b4a7acfSLukasz Luba 16096520e968SAlim Akhtar samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1610c898c6b7SYadwinder Singh Brar reg_base); 16116520e968SAlim Akhtar samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 16126520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_clks)); 16136520e968SAlim Akhtar samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 16146520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_factor_clks)); 16156520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5x_mux_clks, 16166520e968SAlim Akhtar ARRAY_SIZE(exynos5x_mux_clks)); 16176520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5x_div_clks, 16186520e968SAlim Akhtar ARRAY_SIZE(exynos5x_div_clks)); 16196520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5x_gate_clks, 16206520e968SAlim Akhtar ARRAY_SIZE(exynos5x_gate_clks)); 16216520e968SAlim Akhtar 16226520e968SAlim Akhtar if (soc == EXYNOS5420) { 1623976face4SRahul Sharma samsung_clk_register_mux(ctx, exynos5420_mux_clks, 16241609027fSChander Kashyap ARRAY_SIZE(exynos5420_mux_clks)); 1625976face4SRahul Sharma samsung_clk_register_div(ctx, exynos5420_div_clks, 16261609027fSChander Kashyap ARRAY_SIZE(exynos5420_div_clks)); 162741097f25SSylwester Nawrocki samsung_clk_register_gate(ctx, exynos5420_gate_clks, 162841097f25SSylwester Nawrocki ARRAY_SIZE(exynos5420_gate_clks)); 16296520e968SAlim Akhtar } else { 16306520e968SAlim Akhtar samsung_clk_register_fixed_factor( 16316520e968SAlim Akhtar ctx, exynos5800_fixed_factor_clks, 16326520e968SAlim Akhtar ARRAY_SIZE(exynos5800_fixed_factor_clks)); 16336520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5800_mux_clks, 16346520e968SAlim Akhtar ARRAY_SIZE(exynos5800_mux_clks)); 16356520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5800_div_clks, 16366520e968SAlim Akhtar ARRAY_SIZE(exynos5800_div_clks)); 16376520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5800_gate_clks, 16386520e968SAlim Akhtar ARRAY_SIZE(exynos5800_gate_clks)); 16396520e968SAlim Akhtar } 1640388c7885STomasz Figa 164154abbdb4SBartlomiej Zolnierkiewicz if (soc == EXYNOS5420) { 1642ac48ea3bSWill McVicker samsung_clk_register_cpu(ctx, exynos5420_cpu_clks, 1643ac48ea3bSWill McVicker ARRAY_SIZE(exynos5420_cpu_clks)); 164454abbdb4SBartlomiej Zolnierkiewicz } else { 1645ac48ea3bSWill McVicker samsung_clk_register_cpu(ctx, exynos5800_cpu_clks, 1646ac48ea3bSWill McVicker ARRAY_SIZE(exynos5800_cpu_clks)); 164754abbdb4SBartlomiej Zolnierkiewicz } 1648bee4f87fSThomas Abraham 16492d77f77cSMarek Szyprowski samsung_clk_extended_sleep_init(reg_base, 16502d77f77cSMarek Szyprowski exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs), 16512d77f77cSMarek Szyprowski exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); 1652b6adeb6bSSylwester Nawrocki 1653b6adeb6bSSylwester Nawrocki if (soc == EXYNOS5800) { 16542d77f77cSMarek Szyprowski samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, 16552d77f77cSMarek Szyprowski ARRAY_SIZE(exynos5800_clk_regs)); 1656b6adeb6bSSylwester Nawrocki 1657b6adeb6bSSylwester Nawrocki exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus), 1658b6adeb6bSSylwester Nawrocki exynos5800_subcmus); 1659b6adeb6bSSylwester Nawrocki } else { 1660ec4016ffSMarek Szyprowski exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), 1661ec4016ffSMarek Szyprowski exynos5x_subcmus); 1662b6adeb6bSSylwester Nawrocki } 1663d5e136a2SSylwester Nawrocki 166467f96ff7SMarek Szyprowski /* 166567f96ff7SMarek Szyprowski * Keep top part of G3D clock path enabled permanently to ensure 166667f96ff7SMarek Szyprowski * that the internal busses get their clock regardless of the 166767f96ff7SMarek Szyprowski * main G3D clock enablement status. 166867f96ff7SMarek Szyprowski */ 16698b066520SSylwester Nawrocki clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk); 16700212a048SMarek Szyprowski /* 16710212a048SMarek Szyprowski * Keep top BPLL mux enabled permanently to ensure that DRAM operates 16720212a048SMarek Szyprowski * properly. 16730212a048SMarek Szyprowski */ 16748b066520SSylwester Nawrocki clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk); 167567f96ff7SMarek Szyprowski 1676d5e136a2SSylwester Nawrocki samsung_clk_of_add_provider(np, ctx); 16771609027fSChander Kashyap } 16786520e968SAlim Akhtar 16796520e968SAlim Akhtar static void __init exynos5420_clk_init(struct device_node *np) 16806520e968SAlim Akhtar { 16816520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5420); 16826520e968SAlim Akhtar } 1683ec4016ffSMarek Szyprowski CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", 1684ec4016ffSMarek Szyprowski exynos5420_clk_init); 16856520e968SAlim Akhtar 16866520e968SAlim Akhtar static void __init exynos5800_clk_init(struct device_node *np) 16876520e968SAlim Akhtar { 16886520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5800); 16896520e968SAlim Akhtar } 1690ec4016ffSMarek Szyprowski CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", 1691ec4016ffSMarek Szyprowski exynos5800_clk_init); 1692