11609027fSChander Kashyap /* 21609027fSChander Kashyap * Copyright (c) 2013 Samsung Electronics Co., Ltd. 31609027fSChander Kashyap * Authors: Thomas Abraham <thomas.ab@samsung.com> 41609027fSChander Kashyap * Chander Kashyap <k.chander@samsung.com> 51609027fSChander Kashyap * 61609027fSChander Kashyap * This program is free software; you can redistribute it and/or modify 71609027fSChander Kashyap * it under the terms of the GNU General Public License version 2 as 81609027fSChander Kashyap * published by the Free Software Foundation. 91609027fSChander Kashyap * 101609027fSChander Kashyap * Common Clock Framework support for Exynos5420 SoC. 111609027fSChander Kashyap */ 121609027fSChander Kashyap 13cba9d2faSAndrzej Hajda #include <dt-bindings/clock/exynos5420.h> 141609027fSChander Kashyap #include <linux/clk.h> 151609027fSChander Kashyap #include <linux/clkdev.h> 161609027fSChander Kashyap #include <linux/clk-provider.h> 171609027fSChander Kashyap #include <linux/of.h> 181609027fSChander Kashyap #include <linux/of_address.h> 19388c7885STomasz Figa #include <linux/syscore_ops.h> 201609027fSChander Kashyap 211609027fSChander Kashyap #include "clk.h" 221609027fSChander Kashyap 23c898c6b7SYadwinder Singh Brar #define APLL_LOCK 0x0 24c898c6b7SYadwinder Singh Brar #define APLL_CON0 0x100 251609027fSChander Kashyap #define SRC_CPU 0x200 261609027fSChander Kashyap #define DIV_CPU0 0x500 271609027fSChander Kashyap #define DIV_CPU1 0x504 281609027fSChander Kashyap #define GATE_BUS_CPU 0x700 291609027fSChander Kashyap #define GATE_SCLK_CPU 0x800 3077342432SShaik Ameer Basha #define CLKOUT_CMU_CPU 0xa00 315b73721bSNaveen Krishna Chatradhi #define GATE_IP_G2D 0x8800 32c898c6b7SYadwinder Singh Brar #define CPLL_LOCK 0x10020 33c898c6b7SYadwinder Singh Brar #define DPLL_LOCK 0x10030 34c898c6b7SYadwinder Singh Brar #define EPLL_LOCK 0x10040 35c898c6b7SYadwinder Singh Brar #define RPLL_LOCK 0x10050 36c898c6b7SYadwinder Singh Brar #define IPLL_LOCK 0x10060 37c898c6b7SYadwinder Singh Brar #define SPLL_LOCK 0x10070 3853cb6342SSachin Kamat #define VPLL_LOCK 0x10080 39c898c6b7SYadwinder Singh Brar #define MPLL_LOCK 0x10090 40c898c6b7SYadwinder Singh Brar #define CPLL_CON0 0x10120 41c898c6b7SYadwinder Singh Brar #define DPLL_CON0 0x10128 42c898c6b7SYadwinder Singh Brar #define EPLL_CON0 0x10130 4377342432SShaik Ameer Basha #define EPLL_CON1 0x10134 4477342432SShaik Ameer Basha #define EPLL_CON2 0x10138 45c898c6b7SYadwinder Singh Brar #define RPLL_CON0 0x10140 4677342432SShaik Ameer Basha #define RPLL_CON1 0x10144 4777342432SShaik Ameer Basha #define RPLL_CON2 0x10148 48c898c6b7SYadwinder Singh Brar #define IPLL_CON0 0x10150 49c898c6b7SYadwinder Singh Brar #define SPLL_CON0 0x10160 50c898c6b7SYadwinder Singh Brar #define VPLL_CON0 0x10170 51c898c6b7SYadwinder Singh Brar #define MPLL_CON0 0x10180 521609027fSChander Kashyap #define SRC_TOP0 0x10200 531609027fSChander Kashyap #define SRC_TOP1 0x10204 541609027fSChander Kashyap #define SRC_TOP2 0x10208 551609027fSChander Kashyap #define SRC_TOP3 0x1020c 561609027fSChander Kashyap #define SRC_TOP4 0x10210 571609027fSChander Kashyap #define SRC_TOP5 0x10214 581609027fSChander Kashyap #define SRC_TOP6 0x10218 591609027fSChander Kashyap #define SRC_TOP7 0x1021c 606520e968SAlim Akhtar #define SRC_TOP8 0x10220 /* 5800 specific */ 616520e968SAlim Akhtar #define SRC_TOP9 0x10224 /* 5800 specific */ 621609027fSChander Kashyap #define SRC_DISP10 0x1022c 631609027fSChander Kashyap #define SRC_MAU 0x10240 641609027fSChander Kashyap #define SRC_FSYS 0x10244 651609027fSChander Kashyap #define SRC_PERIC0 0x10250 661609027fSChander Kashyap #define SRC_PERIC1 0x10254 673a767b35SShaik Ameer Basha #define SRC_ISP 0x10270 686520e968SAlim Akhtar #define SRC_CAM 0x10274 /* 5800 specific */ 691609027fSChander Kashyap #define SRC_TOP10 0x10280 701609027fSChander Kashyap #define SRC_TOP11 0x10284 711609027fSChander Kashyap #define SRC_TOP12 0x10288 726520e968SAlim Akhtar #define SRC_TOP13 0x1028c /* 5800 specific */ 73424b673aSShaik Ameer Basha #define SRC_MASK_TOP2 0x10308 7431116a64SShaik Ameer Basha #define SRC_MASK_TOP7 0x1031c 751609027fSChander Kashyap #define SRC_MASK_DISP10 0x1032c 7631116a64SShaik Ameer Basha #define SRC_MASK_MAU 0x10334 771609027fSChander Kashyap #define SRC_MASK_FSYS 0x10340 781609027fSChander Kashyap #define SRC_MASK_PERIC0 0x10350 791609027fSChander Kashyap #define SRC_MASK_PERIC1 0x10354 801609027fSChander Kashyap #define DIV_TOP0 0x10500 811609027fSChander Kashyap #define DIV_TOP1 0x10504 821609027fSChander Kashyap #define DIV_TOP2 0x10508 836520e968SAlim Akhtar #define DIV_TOP8 0x10520 /* 5800 specific */ 846520e968SAlim Akhtar #define DIV_TOP9 0x10524 /* 5800 specific */ 851609027fSChander Kashyap #define DIV_DISP10 0x1052c 861609027fSChander Kashyap #define DIV_MAU 0x10544 871609027fSChander Kashyap #define DIV_FSYS0 0x10548 881609027fSChander Kashyap #define DIV_FSYS1 0x1054c 891609027fSChander Kashyap #define DIV_FSYS2 0x10550 901609027fSChander Kashyap #define DIV_PERIC0 0x10558 911609027fSChander Kashyap #define DIV_PERIC1 0x1055c 921609027fSChander Kashyap #define DIV_PERIC2 0x10560 931609027fSChander Kashyap #define DIV_PERIC3 0x10564 941609027fSChander Kashyap #define DIV_PERIC4 0x10568 956520e968SAlim Akhtar #define DIV_CAM 0x10574 /* 5800 specific */ 963a767b35SShaik Ameer Basha #define SCLK_DIV_ISP0 0x10580 973a767b35SShaik Ameer Basha #define SCLK_DIV_ISP1 0x10584 9802932381SShaik Ameer Basha #define DIV2_RATIO0 0x10590 991d87db4dSShaik Ameer Basha #define DIV4_RATIO 0x105a0 1001609027fSChander Kashyap #define GATE_BUS_TOP 0x10700 1010a22c306SShaik Ameer Basha #define GATE_BUS_GEN 0x1073c 1021609027fSChander Kashyap #define GATE_BUS_FSYS0 0x10740 1036b5ae463SShaik Ameer Basha #define GATE_BUS_FSYS2 0x10748 1041609027fSChander Kashyap #define GATE_BUS_PERIC 0x10750 1051609027fSChander Kashyap #define GATE_BUS_PERIC1 0x10754 1061609027fSChander Kashyap #define GATE_BUS_PERIS0 0x10760 1071609027fSChander Kashyap #define GATE_BUS_PERIS1 0x10764 1086575fa76SShaik Ameer Basha #define GATE_BUS_NOC 0x10770 1093a767b35SShaik Ameer Basha #define GATE_TOP_SCLK_ISP 0x10870 1101609027fSChander Kashyap #define GATE_IP_GSCL0 0x10910 1111609027fSChander Kashyap #define GATE_IP_GSCL1 0x10920 1126520e968SAlim Akhtar #define GATE_IP_CAM 0x10924 /* 5800 specific */ 1131609027fSChander Kashyap #define GATE_IP_MFC 0x1092c 1141609027fSChander Kashyap #define GATE_IP_DISP1 0x10928 1151609027fSChander Kashyap #define GATE_IP_G3D 0x10930 1161609027fSChander Kashyap #define GATE_IP_GEN 0x10934 1176b5ae463SShaik Ameer Basha #define GATE_IP_FSYS 0x10944 118faec151bSShaik Ameer Basha #define GATE_IP_PERIC 0x10950 1190a22c306SShaik Ameer Basha #define GATE_IP_PERIS 0x10960 1201609027fSChander Kashyap #define GATE_IP_MSCL 0x10970 1211609027fSChander Kashyap #define GATE_TOP_SCLK_GSCL 0x10820 1221609027fSChander Kashyap #define GATE_TOP_SCLK_DISP1 0x10828 1231609027fSChander Kashyap #define GATE_TOP_SCLK_MAU 0x1083c 1241609027fSChander Kashyap #define GATE_TOP_SCLK_FSYS 0x10840 1251609027fSChander Kashyap #define GATE_TOP_SCLK_PERIC 0x10850 126424b673aSShaik Ameer Basha #define TOP_SPARE2 0x10b08 127c898c6b7SYadwinder Singh Brar #define BPLL_LOCK 0x20010 128c898c6b7SYadwinder Singh Brar #define BPLL_CON0 0x20110 129c898c6b7SYadwinder Singh Brar #define KPLL_LOCK 0x28000 130c898c6b7SYadwinder Singh Brar #define KPLL_CON0 0x28100 1311609027fSChander Kashyap #define SRC_KFC 0x28200 1321609027fSChander Kashyap #define DIV_KFC0 0x28500 1331609027fSChander Kashyap 1346520e968SAlim Akhtar /* Exynos5x SoC type */ 1356520e968SAlim Akhtar enum exynos5x_soc { 1366520e968SAlim Akhtar EXYNOS5420, 1376520e968SAlim Akhtar EXYNOS5800, 1386520e968SAlim Akhtar }; 1396520e968SAlim Akhtar 140c898c6b7SYadwinder Singh Brar /* list of PLLs */ 1416520e968SAlim Akhtar enum exynos5x_plls { 142c898c6b7SYadwinder Singh Brar apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 143c898c6b7SYadwinder Singh Brar bpll, kpll, 144c898c6b7SYadwinder Singh Brar nr_plls /* number of PLLs */ 145c898c6b7SYadwinder Singh Brar }; 146c898c6b7SYadwinder Singh Brar 147388c7885STomasz Figa static void __iomem *reg_base; 1486520e968SAlim Akhtar static enum exynos5x_soc exynos5x_soc; 149388c7885STomasz Figa 150388c7885STomasz Figa #ifdef CONFIG_PM_SLEEP 1516520e968SAlim Akhtar static struct samsung_clk_reg_dump *exynos5x_save; 1526520e968SAlim Akhtar static struct samsung_clk_reg_dump *exynos5800_save; 153388c7885STomasz Figa 1541609027fSChander Kashyap /* 1551609027fSChander Kashyap * list of controller registers to be saved and restored during a 1561609027fSChander Kashyap * suspend/resume cycle. 1571609027fSChander Kashyap */ 1586520e968SAlim Akhtar static unsigned long exynos5x_clk_regs[] __initdata = { 1591609027fSChander Kashyap SRC_CPU, 1601609027fSChander Kashyap DIV_CPU0, 1611609027fSChander Kashyap DIV_CPU1, 1621609027fSChander Kashyap GATE_BUS_CPU, 1631609027fSChander Kashyap GATE_SCLK_CPU, 16477342432SShaik Ameer Basha CLKOUT_CMU_CPU, 16577342432SShaik Ameer Basha EPLL_CON0, 16677342432SShaik Ameer Basha EPLL_CON1, 16777342432SShaik Ameer Basha EPLL_CON2, 16877342432SShaik Ameer Basha RPLL_CON0, 16977342432SShaik Ameer Basha RPLL_CON1, 17077342432SShaik Ameer Basha RPLL_CON2, 1711609027fSChander Kashyap SRC_TOP0, 1721609027fSChander Kashyap SRC_TOP1, 1731609027fSChander Kashyap SRC_TOP2, 1741609027fSChander Kashyap SRC_TOP3, 1751609027fSChander Kashyap SRC_TOP4, 1761609027fSChander Kashyap SRC_TOP5, 1771609027fSChander Kashyap SRC_TOP6, 1781609027fSChander Kashyap SRC_TOP7, 1791609027fSChander Kashyap SRC_DISP10, 1801609027fSChander Kashyap SRC_MAU, 1811609027fSChander Kashyap SRC_FSYS, 1821609027fSChander Kashyap SRC_PERIC0, 1831609027fSChander Kashyap SRC_PERIC1, 1841609027fSChander Kashyap SRC_TOP10, 1851609027fSChander Kashyap SRC_TOP11, 1861609027fSChander Kashyap SRC_TOP12, 187424b673aSShaik Ameer Basha SRC_MASK_TOP2, 18831116a64SShaik Ameer Basha SRC_MASK_TOP7, 1891609027fSChander Kashyap SRC_MASK_DISP10, 1901609027fSChander Kashyap SRC_MASK_FSYS, 1911609027fSChander Kashyap SRC_MASK_PERIC0, 1921609027fSChander Kashyap SRC_MASK_PERIC1, 1933a767b35SShaik Ameer Basha SRC_ISP, 1941609027fSChander Kashyap DIV_TOP0, 1951609027fSChander Kashyap DIV_TOP1, 1961609027fSChander Kashyap DIV_TOP2, 1971609027fSChander Kashyap DIV_DISP10, 1981609027fSChander Kashyap DIV_MAU, 1991609027fSChander Kashyap DIV_FSYS0, 2001609027fSChander Kashyap DIV_FSYS1, 2011609027fSChander Kashyap DIV_FSYS2, 2021609027fSChander Kashyap DIV_PERIC0, 2031609027fSChander Kashyap DIV_PERIC1, 2041609027fSChander Kashyap DIV_PERIC2, 2051609027fSChander Kashyap DIV_PERIC3, 2061609027fSChander Kashyap DIV_PERIC4, 2073a767b35SShaik Ameer Basha SCLK_DIV_ISP0, 2083a767b35SShaik Ameer Basha SCLK_DIV_ISP1, 20902932381SShaik Ameer Basha DIV2_RATIO0, 2101d87db4dSShaik Ameer Basha DIV4_RATIO, 2111609027fSChander Kashyap GATE_BUS_TOP, 2120a22c306SShaik Ameer Basha GATE_BUS_GEN, 2131609027fSChander Kashyap GATE_BUS_FSYS0, 2146b5ae463SShaik Ameer Basha GATE_BUS_FSYS2, 2151609027fSChander Kashyap GATE_BUS_PERIC, 2161609027fSChander Kashyap GATE_BUS_PERIC1, 2171609027fSChander Kashyap GATE_BUS_PERIS0, 2181609027fSChander Kashyap GATE_BUS_PERIS1, 2196575fa76SShaik Ameer Basha GATE_BUS_NOC, 2203a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2211609027fSChander Kashyap GATE_IP_GSCL0, 2221609027fSChander Kashyap GATE_IP_GSCL1, 2231609027fSChander Kashyap GATE_IP_MFC, 2241609027fSChander Kashyap GATE_IP_DISP1, 2251609027fSChander Kashyap GATE_IP_G3D, 2261609027fSChander Kashyap GATE_IP_GEN, 2276b5ae463SShaik Ameer Basha GATE_IP_FSYS, 228faec151bSShaik Ameer Basha GATE_IP_PERIC, 2290a22c306SShaik Ameer Basha GATE_IP_PERIS, 2301609027fSChander Kashyap GATE_IP_MSCL, 2311609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 2321609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 2331609027fSChander Kashyap GATE_TOP_SCLK_MAU, 2341609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2351609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 236424b673aSShaik Ameer Basha TOP_SPARE2, 2371609027fSChander Kashyap SRC_KFC, 2381609027fSChander Kashyap DIV_KFC0, 2391609027fSChander Kashyap }; 2401609027fSChander Kashyap 2416520e968SAlim Akhtar static unsigned long exynos5800_clk_regs[] __initdata = { 2426520e968SAlim Akhtar SRC_TOP8, 2436520e968SAlim Akhtar SRC_TOP9, 2446520e968SAlim Akhtar SRC_CAM, 2456520e968SAlim Akhtar SRC_TOP1, 2466520e968SAlim Akhtar DIV_TOP8, 2476520e968SAlim Akhtar DIV_TOP9, 2486520e968SAlim Akhtar DIV_CAM, 2496520e968SAlim Akhtar GATE_IP_CAM, 2506520e968SAlim Akhtar }; 2516520e968SAlim Akhtar 252388c7885STomasz Figa static int exynos5420_clk_suspend(void) 253388c7885STomasz Figa { 2546520e968SAlim Akhtar samsung_clk_save(reg_base, exynos5x_save, 2556520e968SAlim Akhtar ARRAY_SIZE(exynos5x_clk_regs)); 2566520e968SAlim Akhtar 2576520e968SAlim Akhtar if (exynos5x_soc == EXYNOS5800) 2586520e968SAlim Akhtar samsung_clk_save(reg_base, exynos5800_save, 2596520e968SAlim Akhtar ARRAY_SIZE(exynos5800_clk_regs)); 260388c7885STomasz Figa 261388c7885STomasz Figa return 0; 262388c7885STomasz Figa } 263388c7885STomasz Figa 264388c7885STomasz Figa static void exynos5420_clk_resume(void) 265388c7885STomasz Figa { 2666520e968SAlim Akhtar samsung_clk_restore(reg_base, exynos5x_save, 2676520e968SAlim Akhtar ARRAY_SIZE(exynos5x_clk_regs)); 2686520e968SAlim Akhtar 2696520e968SAlim Akhtar if (exynos5x_soc == EXYNOS5800) 2706520e968SAlim Akhtar samsung_clk_restore(reg_base, exynos5800_save, 2716520e968SAlim Akhtar ARRAY_SIZE(exynos5800_clk_regs)); 272388c7885STomasz Figa } 273388c7885STomasz Figa 274388c7885STomasz Figa static struct syscore_ops exynos5420_clk_syscore_ops = { 275388c7885STomasz Figa .suspend = exynos5420_clk_suspend, 276388c7885STomasz Figa .resume = exynos5420_clk_resume, 277388c7885STomasz Figa }; 278388c7885STomasz Figa 279388c7885STomasz Figa static void exynos5420_clk_sleep_init(void) 280388c7885STomasz Figa { 2816520e968SAlim Akhtar exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs, 2826520e968SAlim Akhtar ARRAY_SIZE(exynos5x_clk_regs)); 2836520e968SAlim Akhtar if (!exynos5x_save) { 284388c7885STomasz Figa pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 285388c7885STomasz Figa __func__); 286388c7885STomasz Figa return; 287388c7885STomasz Figa } 288388c7885STomasz Figa 2896520e968SAlim Akhtar if (exynos5x_soc == EXYNOS5800) { 2906520e968SAlim Akhtar exynos5800_save = 2916520e968SAlim Akhtar samsung_clk_alloc_reg_dump(exynos5800_clk_regs, 2926520e968SAlim Akhtar ARRAY_SIZE(exynos5800_clk_regs)); 2936520e968SAlim Akhtar if (!exynos5800_save) 2946520e968SAlim Akhtar goto err_soc; 2956520e968SAlim Akhtar } 2966520e968SAlim Akhtar 297388c7885STomasz Figa register_syscore_ops(&exynos5420_clk_syscore_ops); 2986520e968SAlim Akhtar return; 2996520e968SAlim Akhtar err_soc: 3006520e968SAlim Akhtar kfree(exynos5x_save); 3016520e968SAlim Akhtar pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 3026520e968SAlim Akhtar __func__); 3036520e968SAlim Akhtar return; 304388c7885STomasz Figa } 305388c7885STomasz Figa #else 306388c7885STomasz Figa static void exynos5420_clk_sleep_init(void) {} 307388c7885STomasz Figa #endif 308388c7885STomasz Figa 3091609027fSChander Kashyap /* list of all parent clocks */ 310dbd713bbSShaik Ameer Basha PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 311dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 312dbd713bbSShaik Ameer Basha PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 313dbd713bbSShaik Ameer Basha PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 314dbd713bbSShaik Ameer Basha PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 315dbd713bbSShaik Ameer Basha PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 316dbd713bbSShaik Ameer Basha PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 317dbd713bbSShaik Ameer Basha PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 318dbd713bbSShaik Ameer Basha PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 319dbd713bbSShaik Ameer Basha PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 320dbd713bbSShaik Ameer Basha PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 321dbd713bbSShaik Ameer Basha PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 322dbd713bbSShaik Ameer Basha PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 323dbd713bbSShaik Ameer Basha PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 324dbd713bbSShaik Ameer Basha PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 3251609027fSChander Kashyap 326dbd713bbSShaik Ameer Basha PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 327dbd713bbSShaik Ameer Basha "mout_sclk_mpll"}; 328dbd713bbSShaik Ameer Basha PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 329dbd713bbSShaik Ameer Basha "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 330dbd713bbSShaik Ameer Basha "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 331dbd713bbSShaik Ameer Basha PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 332dbd713bbSShaik Ameer Basha PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 333dbd713bbSShaik Ameer Basha PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 3341609027fSChander Kashyap 335424b673aSShaik Ameer Basha PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 336dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 337faec151bSShaik Ameer Basha PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 338b31ca2a0SShaik Ameer Basha PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 3391609027fSChander Kashyap 340dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 3416b5ae463SShaik Ameer Basha PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 3426b5ae463SShaik Ameer Basha PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 343dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 3441609027fSChander Kashyap 345dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 346dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 3476575fa76SShaik Ameer Basha PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 3486575fa76SShaik Ameer Basha PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 3496575fa76SShaik Ameer Basha 3506575fa76SShaik Ameer Basha PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 3516575fa76SShaik Ameer Basha PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 3526575fa76SShaik Ameer Basha PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 3536575fa76SShaik Ameer Basha 3543a767b35SShaik Ameer Basha PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 3553a767b35SShaik Ameer Basha PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 3563a767b35SShaik Ameer Basha 3573a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 3583a767b35SShaik Ameer Basha "mout_sclk_spll"}; 3593a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 3603a767b35SShaik Ameer Basha 3613a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 3623a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 3631609027fSChander Kashyap 364dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 365424b673aSShaik Ameer Basha PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 3661609027fSChander Kashyap 367dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 368dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 3691609027fSChander Kashyap 370dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 371dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 3721609027fSChander Kashyap 373dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 374dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 3751609027fSChander Kashyap 376dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 377dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 3783a767b35SShaik Ameer Basha PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 3791609027fSChander Kashyap 380dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 381dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 3821609027fSChander Kashyap 383dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 384dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 3851609027fSChander Kashyap 386dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 387424b673aSShaik Ameer Basha PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 388dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 389424b673aSShaik Ameer Basha PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 3901609027fSChander Kashyap 391dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 392dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 3931609027fSChander Kashyap 394dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 395dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 3961609027fSChander Kashyap 397dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 398dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 3991609027fSChander Kashyap 400dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 401dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 4021609027fSChander Kashyap 403dbd713bbSShaik Ameer Basha PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 404dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 405dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 406dbd713bbSShaik Ameer Basha PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 407dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 408dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 409dbd713bbSShaik Ameer Basha PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 410dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 411dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 412dbd713bbSShaik Ameer Basha PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 413dbd713bbSShaik Ameer Basha "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 414dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 415dbd713bbSShaik Ameer Basha PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 416dbd713bbSShaik Ameer Basha PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 417dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 418dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 41931116a64SShaik Ameer Basha PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 42031116a64SShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 4216520e968SAlim Akhtar /* List of parents specific to exynos5800 */ 4226520e968SAlim Akhtar PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 4236520e968SAlim Akhtar PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4246520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4256520e968SAlim Akhtar PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4266520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4276520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 4286520e968SAlim Akhtar PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4296520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4306520e968SAlim Akhtar "mout_epll2" }; 4316520e968SAlim Akhtar PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4326520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll" }; 4336520e968SAlim Akhtar PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 4346520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4356520e968SAlim Akhtar PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4366520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll", 4376520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 4386520e968SAlim Akhtar PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 4396520e968SAlim Akhtar "mout_sclk_mpll", 4406520e968SAlim Akhtar "ff_dout_spll2" }; 4416520e968SAlim Akhtar PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 4426520e968SAlim Akhtar PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 4436520e968SAlim Akhtar PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 4446520e968SAlim Akhtar PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 4456520e968SAlim Akhtar PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 4466520e968SAlim Akhtar PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 4476520e968SAlim Akhtar PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 4486520e968SAlim Akhtar PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 4491609027fSChander Kashyap 4501609027fSChander Kashyap /* fixed rate clocks generated outside the soc */ 4516520e968SAlim Akhtar static struct samsung_fixed_rate_clock 4526520e968SAlim Akhtar exynos5x_fixed_rate_ext_clks[] __initdata = { 453cba9d2faSAndrzej Hajda FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 4541609027fSChander Kashyap }; 4551609027fSChander Kashyap 4561609027fSChander Kashyap /* fixed rate clocks generated inside the soc */ 4576520e968SAlim Akhtar static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = { 458cba9d2faSAndrzej Hajda FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 459cba9d2faSAndrzej Hajda FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 460cba9d2faSAndrzej Hajda FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 461cba9d2faSAndrzej Hajda FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), 462cba9d2faSAndrzej Hajda FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 4631609027fSChander Kashyap }; 4641609027fSChander Kashyap 4656520e968SAlim Akhtar static struct samsung_fixed_factor_clock 4666520e968SAlim Akhtar exynos5x_fixed_factor_clks[] __initdata = { 467b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 468b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 4691609027fSChander Kashyap }; 4701609027fSChander Kashyap 4716520e968SAlim Akhtar static struct samsung_fixed_factor_clock 4726520e968SAlim Akhtar exynos5800_fixed_factor_clks[] __initdata = { 4736520e968SAlim Akhtar FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 4746520e968SAlim Akhtar FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 4756520e968SAlim Akhtar }; 4766520e968SAlim Akhtar 4776520e968SAlim Akhtar struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { 4786520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 4796520e968SAlim Akhtar MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 4806520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 4816520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 4826520e968SAlim Akhtar 4836520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 4846520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 4856520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 4866520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 4876520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 4886520e968SAlim Akhtar 4896520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 4906520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 4916520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 4926520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 4936520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 4946520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 4956520e968SAlim Akhtar 4966520e968SAlim Akhtar MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7, 4976520e968SAlim Akhtar 20, 2), 4986520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 4996520e968SAlim Akhtar MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 5006520e968SAlim Akhtar 5016520e968SAlim Akhtar MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 5026520e968SAlim Akhtar MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 5036520e968SAlim Akhtar MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 5046520e968SAlim Akhtar MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 5056520e968SAlim Akhtar 5066520e968SAlim Akhtar MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 5076520e968SAlim Akhtar SRC_TOP9, 16, 1), 5086520e968SAlim Akhtar MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 5096520e968SAlim Akhtar SRC_TOP9, 20, 1), 5106520e968SAlim Akhtar MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 5116520e968SAlim Akhtar SRC_TOP9, 24, 1), 5126520e968SAlim Akhtar MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 5136520e968SAlim Akhtar SRC_TOP9, 28, 1), 5146520e968SAlim Akhtar 5156520e968SAlim Akhtar MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 5166520e968SAlim Akhtar MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 5176520e968SAlim Akhtar SRC_TOP13, 20, 1), 5186520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 5196520e968SAlim Akhtar SRC_TOP13, 24, 1), 5206520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 5216520e968SAlim Akhtar SRC_TOP13, 28, 1), 5226520e968SAlim Akhtar 5236520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 5246520e968SAlim Akhtar }; 5256520e968SAlim Akhtar 5266520e968SAlim Akhtar struct samsung_div_clock exynos5800_div_clks[] __initdata = { 5276520e968SAlim Akhtar DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3), 5286520e968SAlim Akhtar 5296520e968SAlim Akhtar DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 5306520e968SAlim Akhtar DIV_TOP8, 16, 3), 5316520e968SAlim Akhtar DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 5326520e968SAlim Akhtar DIV_TOP8, 20, 3), 5336520e968SAlim Akhtar DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 5346520e968SAlim Akhtar DIV_TOP8, 24, 3), 5356520e968SAlim Akhtar DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 5366520e968SAlim Akhtar DIV_TOP8, 28, 3), 5376520e968SAlim Akhtar 5386520e968SAlim Akhtar DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 5396520e968SAlim Akhtar DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 5406520e968SAlim Akhtar }; 5416520e968SAlim Akhtar 5426520e968SAlim Akhtar struct samsung_gate_clock exynos5800_gate_clks[] __initdata = { 5436520e968SAlim Akhtar GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 5446520e968SAlim Akhtar GATE_BUS_TOP, 24, 0, 0), 5456520e968SAlim Akhtar GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 5466520e968SAlim Akhtar GATE_BUS_TOP, 27, 0, 0), 5476520e968SAlim Akhtar }; 5486520e968SAlim Akhtar 5496520e968SAlim Akhtar struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 5506520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 5516520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 5526520e968SAlim Akhtar TOP_SPARE2, 4, 1), 5536520e968SAlim Akhtar 5546520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 5556520e968SAlim Akhtar MUX_A(0, "mout_aclk400_mscl", mout_group1_p, 5566520e968SAlim Akhtar SRC_TOP0, 4, 2, "aclk400_mscl"), 5576520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 5586520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 5596520e968SAlim Akhtar 5606520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 5616520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group4_p, 5626520e968SAlim Akhtar SRC_TOP1, 4, 2), 5636520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 5646520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 5656520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 5666520e968SAlim Akhtar 5676520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 5686520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 5696520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 5706520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 5716520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 5726520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 5736520e968SAlim Akhtar 5746520e968SAlim Akhtar MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2), 5756520e968SAlim Akhtar 5766520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 5776520e968SAlim Akhtar }; 5786520e968SAlim Akhtar 5796520e968SAlim Akhtar struct samsung_div_clock exynos5420_div_clks[] __initdata = { 5806520e968SAlim Akhtar DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll", 5816520e968SAlim Akhtar DIV_TOP0, 16, 3), 5826520e968SAlim Akhtar }; 5836520e968SAlim Akhtar 5846520e968SAlim Akhtar static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 585b31ca2a0SShaik Ameer Basha MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 586b31ca2a0SShaik Ameer Basha SRC_TOP7, 4, 1), 587dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 588dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 58931116a64SShaik Ameer Basha 590dbd713bbSShaik Ameer Basha MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), 591dbd713bbSShaik Ameer Basha MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 592dbd713bbSShaik Ameer Basha MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1), 593dbd713bbSShaik Ameer Basha MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 5941609027fSChander Kashyap 595dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 596dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 5976b5ae463SShaik Ameer Basha MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 598dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 5991609027fSChander Kashyap 600dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 601dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 6021609027fSChander Kashyap 603dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 6041609027fSChander Kashyap 6053a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 6063a767b35SShaik Ameer Basha SRC_TOP3, 0, 1), 607dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 6081609027fSChander Kashyap SRC_TOP3, 4, 1), 609424b673aSShaik Ameer Basha MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p, 610424b673aSShaik Ameer Basha SRC_TOP3, 8, 1), 611dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 6121609027fSChander Kashyap SRC_TOP3, 12, 1), 6136575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 6146575fa76SShaik Ameer Basha SRC_TOP3, 16, 1), 6156575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 6166575fa76SShaik Ameer Basha SRC_TOP3, 20, 1), 6176b5ae463SShaik Ameer Basha MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 6186b5ae463SShaik Ameer Basha SRC_TOP3, 24, 1), 619dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 6201609027fSChander Kashyap SRC_TOP3, 28, 1), 6211609027fSChander Kashyap 622dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 6231609027fSChander Kashyap SRC_TOP4, 0, 1), 6243a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 6253a767b35SShaik Ameer Basha SRC_TOP4, 4, 1), 626faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 627faec151bSShaik Ameer Basha SRC_TOP4, 8, 1), 6283a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 6293a767b35SShaik Ameer Basha SRC_TOP4, 12, 1), 6303a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 6313a767b35SShaik Ameer Basha SRC_TOP4, 16, 1), 632dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 633dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 634dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1), 6351609027fSChander Kashyap 636424b673aSShaik Ameer Basha MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p, 637424b673aSShaik Ameer Basha SRC_TOP5, 0, 1), 638faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 639faec151bSShaik Ameer Basha SRC_TOP5, 4, 1), 6403fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 6413fac5941SShaik Ameer Basha SRC_TOP5, 8, 1), 6423fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 6433fac5941SShaik Ameer Basha SRC_TOP5, 12, 1), 6443fac5941SShaik Ameer Basha MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 6453fac5941SShaik Ameer Basha SRC_TOP5, 16, 1), 646dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 6471609027fSChander Kashyap SRC_TOP5, 20, 1), 648dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p, 6491609027fSChander Kashyap SRC_TOP5, 24, 1), 650dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p, 6511609027fSChander Kashyap SRC_TOP5, 28, 1), 6521609027fSChander Kashyap 653dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 654dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 655dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 656dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 657dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 658dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1), 659dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 660dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 6611609027fSChander Kashyap 6623a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 6633a767b35SShaik Ameer Basha SRC_TOP10, 0, 1), 664dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 665dbd713bbSShaik Ameer Basha SRC_TOP10, 4, 1), 666dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1), 667dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 6681609027fSChander Kashyap SRC_TOP10, 12, 1), 6696575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 6706575fa76SShaik Ameer Basha SRC_TOP10, 16, 1), 6716575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 6726575fa76SShaik Ameer Basha SRC_TOP10, 20, 1), 6736b5ae463SShaik Ameer Basha MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 6746b5ae463SShaik Ameer Basha SRC_TOP10, 24, 1), 675dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 676dbd713bbSShaik Ameer Basha SRC_TOP10, 28, 1), 6773a767b35SShaik Ameer Basha 678dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 6791609027fSChander Kashyap SRC_TOP11, 0, 1), 6803a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 6813a767b35SShaik Ameer Basha SRC_TOP11, 4, 1), 682dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 6833a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 6843a767b35SShaik Ameer Basha SRC_TOP11, 12, 1), 685dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 686dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 687dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1), 6881609027fSChander Kashyap 689424b673aSShaik Ameer Basha MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p, 690424b673aSShaik Ameer Basha SRC_TOP12, 4, 1), 691dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 692dbd713bbSShaik Ameer Basha SRC_TOP12, 8, 1), 693dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 694dbd713bbSShaik Ameer Basha SRC_TOP12, 12, 1), 695dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 696dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 697dbd713bbSShaik Ameer Basha SRC_TOP12, 20, 1), 698dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p, 6991609027fSChander Kashyap SRC_TOP12, 24, 1), 700dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p, 701dbd713bbSShaik Ameer Basha SRC_TOP12, 28, 1), 7021609027fSChander Kashyap 7031609027fSChander Kashyap /* DISP1 Block */ 704dbd713bbSShaik Ameer Basha MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 705dbd713bbSShaik Ameer Basha MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 706dbd713bbSShaik Ameer Basha MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 707dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 708424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 7096575fa76SShaik Ameer Basha 710424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 7111609027fSChander Kashyap 7121609027fSChander Kashyap /* MAU Block */ 71331116a64SShaik Ameer Basha MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 7141609027fSChander Kashyap 7151609027fSChander Kashyap /* FSYS Block */ 716dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 717dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 718dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 719dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 720dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 721dbd713bbSShaik Ameer Basha MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 7226b5ae463SShaik Ameer Basha MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 7231609027fSChander Kashyap 7241609027fSChander Kashyap /* PERIC Block */ 725dbd713bbSShaik Ameer Basha MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 726dbd713bbSShaik Ameer Basha MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 727dbd713bbSShaik Ameer Basha MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 728dbd713bbSShaik Ameer Basha MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 729dbd713bbSShaik Ameer Basha MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 730dbd713bbSShaik Ameer Basha MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 731dbd713bbSShaik Ameer Basha MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 732dbd713bbSShaik Ameer Basha MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 733dbd713bbSShaik Ameer Basha MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 734dbd713bbSShaik Ameer Basha MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 735dbd713bbSShaik Ameer Basha MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 736dbd713bbSShaik Ameer Basha MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 7373a767b35SShaik Ameer Basha 7383a767b35SShaik Ameer Basha /* ISP Block */ 7393a767b35SShaik Ameer Basha MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 7403a767b35SShaik Ameer Basha MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 7413a767b35SShaik Ameer Basha MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 7423a767b35SShaik Ameer Basha MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 7433a767b35SShaik Ameer Basha MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 7441609027fSChander Kashyap }; 7451609027fSChander Kashyap 7466520e968SAlim Akhtar static struct samsung_div_clock exynos5x_div_clks[] __initdata = { 747cba9d2faSAndrzej Hajda DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 748cba9d2faSAndrzej Hajda DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 749cba9d2faSAndrzej Hajda DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 750dbd713bbSShaik Ameer Basha DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 751cba9d2faSAndrzej Hajda DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 7521609027fSChander Kashyap 7533a767b35SShaik Ameer Basha DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3), 754cba9d2faSAndrzej Hajda DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 755cba9d2faSAndrzej Hajda DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 756cba9d2faSAndrzej Hajda DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 7576575fa76SShaik Ameer Basha DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3), 758cba9d2faSAndrzej Hajda DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 759cba9d2faSAndrzej Hajda DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 7601609027fSChander Kashyap 761cba9d2faSAndrzej Hajda DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 7621609027fSChander Kashyap DIV_TOP1, 0, 3), 7633a767b35SShaik Ameer Basha DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp", 7643a767b35SShaik Ameer Basha DIV_TOP1, 4, 3), 765cba9d2faSAndrzej Hajda DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 7663a767b35SShaik Ameer Basha DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0", 7673a767b35SShaik Ameer Basha DIV_TOP1, 16, 3), 768cba9d2faSAndrzej Hajda DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 769cba9d2faSAndrzej Hajda DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 770cba9d2faSAndrzej Hajda DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 7711609027fSChander Kashyap 772cba9d2faSAndrzej Hajda DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), 773cba9d2faSAndrzej Hajda DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 774cba9d2faSAndrzej Hajda DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 775cba9d2faSAndrzej Hajda DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 776424b673aSShaik Ameer Basha DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3), 777cba9d2faSAndrzej Hajda DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 7781609027fSChander Kashyap 7791609027fSChander Kashyap /* DISP1 Block */ 780424b673aSShaik Ameer Basha DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 781cba9d2faSAndrzej Hajda DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 782cba9d2faSAndrzej Hajda DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 783cba9d2faSAndrzej Hajda DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 784424b673aSShaik Ameer Basha DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 785424b673aSShaik Ameer Basha DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3), 7861609027fSChander Kashyap 7871609027fSChander Kashyap /* Audio Block */ 788cba9d2faSAndrzej Hajda DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 789cba9d2faSAndrzej Hajda DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 7901609027fSChander Kashyap 7911609027fSChander Kashyap /* USB3.0 */ 792cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 793cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 794cba9d2faSAndrzej Hajda DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 795cba9d2faSAndrzej Hajda DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 7961609027fSChander Kashyap 7971609027fSChander Kashyap /* MMC */ 798cba9d2faSAndrzej Hajda DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 799cba9d2faSAndrzej Hajda DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 800cba9d2faSAndrzej Hajda DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 8011609027fSChander Kashyap 802cba9d2faSAndrzej Hajda DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 8036b5ae463SShaik Ameer Basha DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 8041609027fSChander Kashyap 8051609027fSChander Kashyap /* UART and PWM */ 806cba9d2faSAndrzej Hajda DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 807cba9d2faSAndrzej Hajda DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 808cba9d2faSAndrzej Hajda DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 809cba9d2faSAndrzej Hajda DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 810cba9d2faSAndrzej Hajda DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 8111609027fSChander Kashyap 8121609027fSChander Kashyap /* SPI */ 813cba9d2faSAndrzej Hajda DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 814cba9d2faSAndrzej Hajda DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 815cba9d2faSAndrzej Hajda DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 8161609027fSChander Kashyap 8171d87db4dSShaik Ameer Basha /* Mfc Block */ 8181d87db4dSShaik Ameer Basha DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 8191d87db4dSShaik Ameer Basha 8201609027fSChander Kashyap /* PCM */ 821cba9d2faSAndrzej Hajda DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 822cba9d2faSAndrzej Hajda DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 8231609027fSChander Kashyap 8241609027fSChander Kashyap /* Audio - I2S */ 825cba9d2faSAndrzej Hajda DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 826cba9d2faSAndrzej Hajda DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 827cba9d2faSAndrzej Hajda DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 828cba9d2faSAndrzej Hajda DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 829cba9d2faSAndrzej Hajda DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 8301609027fSChander Kashyap 8311609027fSChander Kashyap /* SPI Pre-Ratio */ 832faec151bSShaik Ameer Basha DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 833faec151bSShaik Ameer Basha DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 834faec151bSShaik Ameer Basha DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 8353a767b35SShaik Ameer Basha 83602932381SShaik Ameer Basha /* GSCL Block */ 83702932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 83802932381SShaik Ameer Basha DIV2_RATIO0, 4, 2), 83902932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 84002932381SShaik Ameer Basha 8414549d93dSShaik Ameer Basha /* MSCL Block */ 8424549d93dSShaik Ameer Basha DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 8434549d93dSShaik Ameer Basha 8440a22c306SShaik Ameer Basha /* PSGEN */ 8450a22c306SShaik Ameer Basha DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 8460a22c306SShaik Ameer Basha DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 8470a22c306SShaik Ameer Basha 8483a767b35SShaik Ameer Basha /* ISP Block */ 8493a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 8503a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 8513a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 8523a767b35SShaik Ameer Basha DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 8533a767b35SShaik Ameer Basha DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 8543a767b35SShaik Ameer Basha DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 8553a767b35SShaik Ameer Basha DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 8563a767b35SShaik Ameer Basha DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 8573a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 8583a767b35SShaik Ameer Basha DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 8593a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 8601609027fSChander Kashyap }; 8611609027fSChander Kashyap 8626520e968SAlim Akhtar static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = { 8635b73721bSNaveen Krishna Chatradhi /* G2D */ 8643fac5941SShaik Ameer Basha GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 8655b73721bSNaveen Krishna Chatradhi GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 8663fac5941SShaik Ameer Basha GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 8673fac5941SShaik Ameer Basha GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 8683fac5941SShaik Ameer Basha GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 8695b73721bSNaveen Krishna Chatradhi 8701609027fSChander Kashyap GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 8711609027fSChander Kashyap GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 8721609027fSChander Kashyap GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 8731609027fSChander Kashyap GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 8741609027fSChander Kashyap 8751609027fSChander Kashyap GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 8761609027fSChander Kashyap GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 8771609027fSChander Kashyap GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 8781609027fSChander Kashyap GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), 8791609027fSChander Kashyap GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 8801609027fSChander Kashyap GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 8813a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 8823a767b35SShaik Ameer Basha GATE_BUS_TOP, 5, 0, 0), 8831609027fSChander Kashyap GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 8841609027fSChander Kashyap GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), 8851609027fSChander Kashyap GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 8861609027fSChander Kashyap GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 8873a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 8883a767b35SShaik Ameer Basha GATE_BUS_TOP, 8, 0, 0), 889b31ca2a0SShaik Ameer Basha GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 8901609027fSChander Kashyap GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 891faec151bSShaik Ameer Basha GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 8921609027fSChander Kashyap GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 8933a767b35SShaik Ameer Basha GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 8943a767b35SShaik Ameer Basha GATE_BUS_TOP, 13, 0, 0), 8951609027fSChander Kashyap GATE(0, "aclk166", "mout_user_aclk166", 8961609027fSChander Kashyap GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 8971609027fSChander Kashyap GATE(0, "aclk333", "mout_aclk333", 8981609027fSChander Kashyap GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 8993a767b35SShaik Ameer Basha GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 9003a767b35SShaik Ameer Basha GATE_BUS_TOP, 16, 0, 0), 90102932381SShaik Ameer Basha GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 90202932381SShaik Ameer Basha GATE_BUS_TOP, 17, 0, 0), 903424b673aSShaik Ameer Basha GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 904424b673aSShaik Ameer Basha GATE_BUS_TOP, 18, 0, 0), 905b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 906b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 28, 0, 0), 907b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 908b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 29, 0, 0), 909424b673aSShaik Ameer Basha 910424b673aSShaik Ameer Basha GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 911424b673aSShaik Ameer Basha SRC_MASK_TOP2, 24, 0, 0), 9121609027fSChander Kashyap 91331116a64SShaik Ameer Basha GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 91431116a64SShaik Ameer Basha SRC_MASK_TOP7, 20, 0, 0), 91531116a64SShaik Ameer Basha 9161609027fSChander Kashyap /* sclk */ 917cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 9181609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 919cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 9201609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 921cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 9221609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 923cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 9241609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 925faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 9261609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 927faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 9281609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 929faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 9301609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 931cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 9321609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 933cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 9341609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 935cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 9361609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 937cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 9381609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 939cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 9401609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 941cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 9421609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 9431609027fSChander Kashyap 944cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 9451609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 946cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 9471609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 948cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 9491609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 950cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 9511609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 952cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 9531609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 954cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 9551609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 956cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 9571609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 9581609027fSChander Kashyap 9591609027fSChander Kashyap /* Display */ 960cba9d2faSAndrzej Hajda GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 9611609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 962cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 9631609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 964cba9d2faSAndrzej Hajda GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 965424b673aSShaik Ameer Basha GATE_TOP_SCLK_DISP1, 9, 0, 0), 966cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 9671609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 968cba9d2faSAndrzej Hajda GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 9691609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 9701609027fSChander Kashyap 9711609027fSChander Kashyap /* Maudio Block */ 972cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 9731609027fSChander Kashyap GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 974cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 9751609027fSChander Kashyap GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 9766b5ae463SShaik Ameer Basha 9776b5ae463SShaik Ameer Basha /* FSYS Block */ 978cba9d2faSAndrzej Hajda GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 979cba9d2faSAndrzej Hajda GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 980cba9d2faSAndrzej Hajda GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 981cba9d2faSAndrzej Hajda GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 9826b5ae463SShaik Ameer Basha GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 9836b5ae463SShaik Ameer Basha GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 9846b5ae463SShaik Ameer Basha GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 9856b5ae463SShaik Ameer Basha GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 986cba9d2faSAndrzej Hajda GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 9876b5ae463SShaik Ameer Basha GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 9886b5ae463SShaik Ameer Basha GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 9896b5ae463SShaik Ameer Basha GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 9906b5ae463SShaik Ameer Basha GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 9916b5ae463SShaik Ameer Basha GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 9926b5ae463SShaik Ameer Basha SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 9931609027fSChander Kashyap 994faec151bSShaik Ameer Basha /* PERIC Block */ 99544ff0254SDoug Anderson GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 99644ff0254SDoug Anderson GATE_IP_PERIC, 0, 0, 0), 99744ff0254SDoug Anderson GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 99844ff0254SDoug Anderson GATE_IP_PERIC, 1, 0, 0), 99944ff0254SDoug Anderson GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 100044ff0254SDoug Anderson GATE_IP_PERIC, 2, 0, 0), 100144ff0254SDoug Anderson GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 100244ff0254SDoug Anderson GATE_IP_PERIC, 3, 0, 0), 100344ff0254SDoug Anderson GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 100444ff0254SDoug Anderson GATE_IP_PERIC, 6, 0, 0), 100544ff0254SDoug Anderson GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 100644ff0254SDoug Anderson GATE_IP_PERIC, 7, 0, 0), 100744ff0254SDoug Anderson GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 100844ff0254SDoug Anderson GATE_IP_PERIC, 8, 0, 0), 100944ff0254SDoug Anderson GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 101044ff0254SDoug Anderson GATE_IP_PERIC, 9, 0, 0), 101144ff0254SDoug Anderson GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 101244ff0254SDoug Anderson GATE_IP_PERIC, 10, 0, 0), 101344ff0254SDoug Anderson GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 101444ff0254SDoug Anderson GATE_IP_PERIC, 11, 0, 0), 101544ff0254SDoug Anderson GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 101644ff0254SDoug Anderson GATE_IP_PERIC, 12, 0, 0), 101744ff0254SDoug Anderson GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 101844ff0254SDoug Anderson GATE_IP_PERIC, 13, 0, 0), 101944ff0254SDoug Anderson GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 102044ff0254SDoug Anderson GATE_IP_PERIC, 14, 0, 0), 102144ff0254SDoug Anderson GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 102244ff0254SDoug Anderson GATE_IP_PERIC, 15, 0, 0), 102344ff0254SDoug Anderson GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 102444ff0254SDoug Anderson GATE_IP_PERIC, 16, 0, 0), 102544ff0254SDoug Anderson GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 102644ff0254SDoug Anderson GATE_IP_PERIC, 17, 0, 0), 102744ff0254SDoug Anderson GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 102844ff0254SDoug Anderson GATE_IP_PERIC, 18, 0, 0), 102944ff0254SDoug Anderson GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 103044ff0254SDoug Anderson GATE_IP_PERIC, 20, 0, 0), 103144ff0254SDoug Anderson GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 103244ff0254SDoug Anderson GATE_IP_PERIC, 21, 0, 0), 103344ff0254SDoug Anderson GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 103444ff0254SDoug Anderson GATE_IP_PERIC, 22, 0, 0), 103544ff0254SDoug Anderson GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 103644ff0254SDoug Anderson GATE_IP_PERIC, 23, 0, 0), 103744ff0254SDoug Anderson GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 103844ff0254SDoug Anderson GATE_IP_PERIC, 24, 0, 0), 103944ff0254SDoug Anderson GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 104044ff0254SDoug Anderson GATE_IP_PERIC, 26, 0, 0), 104144ff0254SDoug Anderson GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 104244ff0254SDoug Anderson GATE_IP_PERIC, 28, 0, 0), 104344ff0254SDoug Anderson GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 104444ff0254SDoug Anderson GATE_IP_PERIC, 30, 0, 0), 104544ff0254SDoug Anderson GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 104644ff0254SDoug Anderson GATE_IP_PERIC, 31, 0, 0), 10471609027fSChander Kashyap 104844ff0254SDoug Anderson GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 104944ff0254SDoug Anderson GATE_BUS_PERIC, 22, 0, 0), 10501609027fSChander Kashyap 10510a22c306SShaik Ameer Basha /* PERIS Block */ 1052cba9d2faSAndrzej Hajda GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 10530a22c306SShaik Ameer Basha GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1054cba9d2faSAndrzej Hajda GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 10550a22c306SShaik Ameer Basha GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 10560a22c306SShaik Ameer Basha GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 10570a22c306SShaik Ameer Basha GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 10580a22c306SShaik Ameer Basha GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 10590a22c306SShaik Ameer Basha GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 10600a22c306SShaik Ameer Basha GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 10610a22c306SShaik Ameer Basha GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 10620a22c306SShaik Ameer Basha GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 10630a22c306SShaik Ameer Basha GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 10640a22c306SShaik Ameer Basha GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 10650a22c306SShaik Ameer Basha GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 10660a22c306SShaik Ameer Basha GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 10670a22c306SShaik Ameer Basha GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 10680a22c306SShaik Ameer Basha GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 10690a22c306SShaik Ameer Basha GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 10700a22c306SShaik Ameer Basha GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 10710a22c306SShaik Ameer Basha GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 10721609027fSChander Kashyap 1073cba9d2faSAndrzej Hajda GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 10740a22c306SShaik Ameer Basha 10750a22c306SShaik Ameer Basha /* GEN Block */ 10760a22c306SShaik Ameer Basha GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 10770a22c306SShaik Ameer Basha GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 10780a22c306SShaik Ameer Basha GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 10790a22c306SShaik Ameer Basha GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 10800a22c306SShaik Ameer Basha GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 10810a22c306SShaik Ameer Basha GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 10820a22c306SShaik Ameer Basha GATE_IP_GEN, 6, 0, 0), 10830a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 10840a22c306SShaik Ameer Basha GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 10850a22c306SShaik Ameer Basha GATE_IP_GEN, 9, 0, 0), 10860a22c306SShaik Ameer Basha 10870a22c306SShaik Ameer Basha /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 10880a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 10890a22c306SShaik Ameer Basha GATE_BUS_GEN, 28, 0, 0), 10900a22c306SShaik Ameer Basha GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 10911609027fSChander Kashyap 109202932381SShaik Ameer Basha /* GSCL Block */ 109302932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 109402932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 6, 0, 0), 109502932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 109602932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 7, 0, 0), 109702932381SShaik Ameer Basha 1098cba9d2faSAndrzej Hajda GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1099cba9d2faSAndrzej Hajda GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 110002932381SShaik Ameer Basha GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 110102932381SShaik Ameer Basha GATE_IP_GSCL0, 4, 0, 0), 110202932381SShaik Ameer Basha GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 110302932381SShaik Ameer Basha GATE_IP_GSCL0, 5, 0, 0), 110402932381SShaik Ameer Basha GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 110502932381SShaik Ameer Basha GATE_IP_GSCL0, 6, 0, 0), 11061609027fSChander Kashyap 110702932381SShaik Ameer Basha GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 110802932381SShaik Ameer Basha GATE_IP_GSCL1, 2, 0, 0), 110902932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 11101609027fSChander Kashyap GATE_IP_GSCL1, 3, 0, 0), 111102932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 11121609027fSChander Kashyap GATE_IP_GSCL1, 4, 0, 0), 111302932381SShaik Ameer Basha GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 111402932381SShaik Ameer Basha GATE_IP_GSCL1, 6, 0, 0), 111502932381SShaik Ameer Basha GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 111602932381SShaik Ameer Basha GATE_IP_GSCL1, 7, 0, 0), 111702932381SShaik Ameer Basha GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 111802932381SShaik Ameer Basha GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 111902932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 11201609027fSChander Kashyap GATE_IP_GSCL1, 16, 0, 0), 1121cba9d2faSAndrzej Hajda GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 11221609027fSChander Kashyap GATE_IP_GSCL1, 17, 0, 0), 11231609027fSChander Kashyap 112402932381SShaik Ameer Basha /* MSCL Block */ 112502932381SShaik Ameer Basha GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 112602932381SShaik Ameer Basha GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 112702932381SShaik Ameer Basha GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 11284549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 112902932381SShaik Ameer Basha GATE_IP_MSCL, 8, 0, 0), 11304549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 113102932381SShaik Ameer Basha GATE_IP_MSCL, 9, 0, 0), 11324549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 113302932381SShaik Ameer Basha GATE_IP_MSCL, 10, 0, 0), 113402932381SShaik Ameer Basha 1135cba9d2faSAndrzej Hajda GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1136cba9d2faSAndrzej Hajda GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1137cba9d2faSAndrzej Hajda GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1138424b673aSShaik Ameer Basha GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1139cba9d2faSAndrzej Hajda GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1140424b673aSShaik Ameer Basha GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1141424b673aSShaik Ameer Basha GATE_IP_DISP1, 7, 0, 0), 1142424b673aSShaik Ameer Basha GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1143424b673aSShaik Ameer Basha GATE_IP_DISP1, 8, 0, 0), 1144424b673aSShaik Ameer Basha GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1145424b673aSShaik Ameer Basha GATE_IP_DISP1, 9, 0, 0), 11461609027fSChander Kashyap 11473a767b35SShaik Ameer Basha /* ISP */ 11483a767b35SShaik Ameer Basha GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 11493a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 11503a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 11513a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 11523a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 11533a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 11543a767b35SShaik Ameer Basha GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 11553a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 11563a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 11573a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 11583a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 11593a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 11603a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 11613a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 11623a767b35SShaik Ameer Basha 1163cba9d2faSAndrzej Hajda GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 11641d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 11651d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 11661609027fSChander Kashyap 11673fac5941SShaik Ameer Basha GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 11681609027fSChander Kashyap }; 11691609027fSChander Kashyap 11706520e968SAlim Akhtar static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1171cba9d2faSAndrzej Hajda [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 11723ff6e0d8SYadwinder Singh Brar APLL_CON0, NULL), 1173cba9d2faSAndrzej Hajda [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1174cdf64eeeSChander Kashyap CPLL_CON0, NULL), 1175cba9d2faSAndrzej Hajda [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 11763ff6e0d8SYadwinder Singh Brar DPLL_CON0, NULL), 1177cba9d2faSAndrzej Hajda [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 11783ff6e0d8SYadwinder Singh Brar EPLL_CON0, NULL), 1179cba9d2faSAndrzej Hajda [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 11803ff6e0d8SYadwinder Singh Brar RPLL_CON0, NULL), 1181cba9d2faSAndrzej Hajda [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 11823ff6e0d8SYadwinder Singh Brar IPLL_CON0, NULL), 1183cba9d2faSAndrzej Hajda [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 11843ff6e0d8SYadwinder Singh Brar SPLL_CON0, NULL), 1185cba9d2faSAndrzej Hajda [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 11863ff6e0d8SYadwinder Singh Brar VPLL_CON0, NULL), 1187cba9d2faSAndrzej Hajda [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 11883ff6e0d8SYadwinder Singh Brar MPLL_CON0, NULL), 1189cba9d2faSAndrzej Hajda [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 11903ff6e0d8SYadwinder Singh Brar BPLL_CON0, NULL), 1191cba9d2faSAndrzej Hajda [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 11923ff6e0d8SYadwinder Singh Brar KPLL_CON0, NULL), 1193c898c6b7SYadwinder Singh Brar }; 1194c898c6b7SYadwinder Singh Brar 1195202e5ae9SSachin Kamat static struct of_device_id ext_clk_match[] __initdata = { 11961609027fSChander Kashyap { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 11971609027fSChander Kashyap { }, 11981609027fSChander Kashyap }; 11991609027fSChander Kashyap 12001609027fSChander Kashyap /* register exynos5420 clocks */ 12016520e968SAlim Akhtar static void __init exynos5x_clk_init(struct device_node *np, 12026520e968SAlim Akhtar enum exynos5x_soc soc) 12031609027fSChander Kashyap { 1204976face4SRahul Sharma struct samsung_clk_provider *ctx; 1205976face4SRahul Sharma 12061609027fSChander Kashyap if (np) { 12071609027fSChander Kashyap reg_base = of_iomap(np, 0); 12081609027fSChander Kashyap if (!reg_base) 12091609027fSChander Kashyap panic("%s: failed to map registers\n", __func__); 12101609027fSChander Kashyap } else { 12111609027fSChander Kashyap panic("%s: unable to determine soc\n", __func__); 12121609027fSChander Kashyap } 12131609027fSChander Kashyap 12146520e968SAlim Akhtar exynos5x_soc = soc; 12156520e968SAlim Akhtar 1216976face4SRahul Sharma ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1217976face4SRahul Sharma if (!ctx) 1218976face4SRahul Sharma panic("%s: unable to allocate context.\n", __func__); 1219976face4SRahul Sharma 12206520e968SAlim Akhtar samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 12216520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 12221609027fSChander Kashyap ext_clk_match); 12236520e968SAlim Akhtar samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1224c898c6b7SYadwinder Singh Brar reg_base); 12256520e968SAlim Akhtar samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 12266520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_clks)); 12276520e968SAlim Akhtar samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 12286520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_factor_clks)); 12296520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5x_mux_clks, 12306520e968SAlim Akhtar ARRAY_SIZE(exynos5x_mux_clks)); 12316520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5x_div_clks, 12326520e968SAlim Akhtar ARRAY_SIZE(exynos5x_div_clks)); 12336520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5x_gate_clks, 12346520e968SAlim Akhtar ARRAY_SIZE(exynos5x_gate_clks)); 12356520e968SAlim Akhtar 12366520e968SAlim Akhtar if (soc == EXYNOS5420) { 1237976face4SRahul Sharma samsung_clk_register_mux(ctx, exynos5420_mux_clks, 12381609027fSChander Kashyap ARRAY_SIZE(exynos5420_mux_clks)); 1239976face4SRahul Sharma samsung_clk_register_div(ctx, exynos5420_div_clks, 12401609027fSChander Kashyap ARRAY_SIZE(exynos5420_div_clks)); 12416520e968SAlim Akhtar } else { 12426520e968SAlim Akhtar samsung_clk_register_fixed_factor( 12436520e968SAlim Akhtar ctx, exynos5800_fixed_factor_clks, 12446520e968SAlim Akhtar ARRAY_SIZE(exynos5800_fixed_factor_clks)); 12456520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5800_mux_clks, 12466520e968SAlim Akhtar ARRAY_SIZE(exynos5800_mux_clks)); 12476520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5800_div_clks, 12486520e968SAlim Akhtar ARRAY_SIZE(exynos5800_div_clks)); 12496520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5800_gate_clks, 12506520e968SAlim Akhtar ARRAY_SIZE(exynos5800_gate_clks)); 12516520e968SAlim Akhtar } 1252388c7885STomasz Figa 1253388c7885STomasz Figa exynos5420_clk_sleep_init(); 12541609027fSChander Kashyap } 12556520e968SAlim Akhtar 12566520e968SAlim Akhtar static void __init exynos5420_clk_init(struct device_node *np) 12576520e968SAlim Akhtar { 12586520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5420); 12596520e968SAlim Akhtar } 12601609027fSChander Kashyap CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 12616520e968SAlim Akhtar 12626520e968SAlim Akhtar static void __init exynos5800_clk_init(struct device_node *np) 12636520e968SAlim Akhtar { 12646520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5800); 12656520e968SAlim Akhtar } 12666520e968SAlim Akhtar CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init); 1267