11609027fSChander Kashyap /* 21609027fSChander Kashyap * Copyright (c) 2013 Samsung Electronics Co., Ltd. 31609027fSChander Kashyap * Authors: Thomas Abraham <thomas.ab@samsung.com> 41609027fSChander Kashyap * Chander Kashyap <k.chander@samsung.com> 51609027fSChander Kashyap * 61609027fSChander Kashyap * This program is free software; you can redistribute it and/or modify 71609027fSChander Kashyap * it under the terms of the GNU General Public License version 2 as 81609027fSChander Kashyap * published by the Free Software Foundation. 91609027fSChander Kashyap * 101609027fSChander Kashyap * Common Clock Framework support for Exynos5420 SoC. 111609027fSChander Kashyap */ 121609027fSChander Kashyap 13cba9d2faSAndrzej Hajda #include <dt-bindings/clock/exynos5420.h> 141609027fSChander Kashyap #include <linux/clk.h> 151609027fSChander Kashyap #include <linux/clkdev.h> 161609027fSChander Kashyap #include <linux/clk-provider.h> 171609027fSChander Kashyap #include <linux/of.h> 181609027fSChander Kashyap #include <linux/of_address.h> 19388c7885STomasz Figa #include <linux/syscore_ops.h> 201609027fSChander Kashyap 211609027fSChander Kashyap #include "clk.h" 221609027fSChander Kashyap 23c898c6b7SYadwinder Singh Brar #define APLL_LOCK 0x0 24c898c6b7SYadwinder Singh Brar #define APLL_CON0 0x100 251609027fSChander Kashyap #define SRC_CPU 0x200 261609027fSChander Kashyap #define DIV_CPU0 0x500 271609027fSChander Kashyap #define DIV_CPU1 0x504 281609027fSChander Kashyap #define GATE_BUS_CPU 0x700 291609027fSChander Kashyap #define GATE_SCLK_CPU 0x800 30c898c6b7SYadwinder Singh Brar #define CPLL_LOCK 0x10020 31c898c6b7SYadwinder Singh Brar #define DPLL_LOCK 0x10030 32c898c6b7SYadwinder Singh Brar #define EPLL_LOCK 0x10040 33c898c6b7SYadwinder Singh Brar #define RPLL_LOCK 0x10050 34c898c6b7SYadwinder Singh Brar #define IPLL_LOCK 0x10060 35c898c6b7SYadwinder Singh Brar #define SPLL_LOCK 0x10070 36c898c6b7SYadwinder Singh Brar #define VPLL_LOCK 0x10070 37c898c6b7SYadwinder Singh Brar #define MPLL_LOCK 0x10090 38c898c6b7SYadwinder Singh Brar #define CPLL_CON0 0x10120 39c898c6b7SYadwinder Singh Brar #define DPLL_CON0 0x10128 40c898c6b7SYadwinder Singh Brar #define EPLL_CON0 0x10130 41c898c6b7SYadwinder Singh Brar #define RPLL_CON0 0x10140 42c898c6b7SYadwinder Singh Brar #define IPLL_CON0 0x10150 43c898c6b7SYadwinder Singh Brar #define SPLL_CON0 0x10160 44c898c6b7SYadwinder Singh Brar #define VPLL_CON0 0x10170 45c898c6b7SYadwinder Singh Brar #define MPLL_CON0 0x10180 461609027fSChander Kashyap #define SRC_TOP0 0x10200 471609027fSChander Kashyap #define SRC_TOP1 0x10204 481609027fSChander Kashyap #define SRC_TOP2 0x10208 491609027fSChander Kashyap #define SRC_TOP3 0x1020c 501609027fSChander Kashyap #define SRC_TOP4 0x10210 511609027fSChander Kashyap #define SRC_TOP5 0x10214 521609027fSChander Kashyap #define SRC_TOP6 0x10218 531609027fSChander Kashyap #define SRC_TOP7 0x1021c 541609027fSChander Kashyap #define SRC_DISP10 0x1022c 551609027fSChander Kashyap #define SRC_MAU 0x10240 561609027fSChander Kashyap #define SRC_FSYS 0x10244 571609027fSChander Kashyap #define SRC_PERIC0 0x10250 581609027fSChander Kashyap #define SRC_PERIC1 0x10254 591609027fSChander Kashyap #define SRC_TOP10 0x10280 601609027fSChander Kashyap #define SRC_TOP11 0x10284 611609027fSChander Kashyap #define SRC_TOP12 0x10288 621609027fSChander Kashyap #define SRC_MASK_DISP10 0x1032c 631609027fSChander Kashyap #define SRC_MASK_FSYS 0x10340 641609027fSChander Kashyap #define SRC_MASK_PERIC0 0x10350 651609027fSChander Kashyap #define SRC_MASK_PERIC1 0x10354 661609027fSChander Kashyap #define DIV_TOP0 0x10500 671609027fSChander Kashyap #define DIV_TOP1 0x10504 681609027fSChander Kashyap #define DIV_TOP2 0x10508 691609027fSChander Kashyap #define DIV_DISP10 0x1052c 701609027fSChander Kashyap #define DIV_MAU 0x10544 711609027fSChander Kashyap #define DIV_FSYS0 0x10548 721609027fSChander Kashyap #define DIV_FSYS1 0x1054c 731609027fSChander Kashyap #define DIV_FSYS2 0x10550 741609027fSChander Kashyap #define DIV_PERIC0 0x10558 751609027fSChander Kashyap #define DIV_PERIC1 0x1055c 761609027fSChander Kashyap #define DIV_PERIC2 0x10560 771609027fSChander Kashyap #define DIV_PERIC3 0x10564 781609027fSChander Kashyap #define DIV_PERIC4 0x10568 791609027fSChander Kashyap #define GATE_BUS_TOP 0x10700 801609027fSChander Kashyap #define GATE_BUS_FSYS0 0x10740 811609027fSChander Kashyap #define GATE_BUS_PERIC 0x10750 821609027fSChander Kashyap #define GATE_BUS_PERIC1 0x10754 831609027fSChander Kashyap #define GATE_BUS_PERIS0 0x10760 841609027fSChander Kashyap #define GATE_BUS_PERIS1 0x10764 851609027fSChander Kashyap #define GATE_IP_GSCL0 0x10910 861609027fSChander Kashyap #define GATE_IP_GSCL1 0x10920 871609027fSChander Kashyap #define GATE_IP_MFC 0x1092c 881609027fSChander Kashyap #define GATE_IP_DISP1 0x10928 891609027fSChander Kashyap #define GATE_IP_G3D 0x10930 901609027fSChander Kashyap #define GATE_IP_GEN 0x10934 911609027fSChander Kashyap #define GATE_IP_MSCL 0x10970 921609027fSChander Kashyap #define GATE_TOP_SCLK_GSCL 0x10820 931609027fSChander Kashyap #define GATE_TOP_SCLK_DISP1 0x10828 941609027fSChander Kashyap #define GATE_TOP_SCLK_MAU 0x1083c 951609027fSChander Kashyap #define GATE_TOP_SCLK_FSYS 0x10840 961609027fSChander Kashyap #define GATE_TOP_SCLK_PERIC 0x10850 97c898c6b7SYadwinder Singh Brar #define BPLL_LOCK 0x20010 98c898c6b7SYadwinder Singh Brar #define BPLL_CON0 0x20110 991609027fSChander Kashyap #define SRC_CDREX 0x20200 100c898c6b7SYadwinder Singh Brar #define KPLL_LOCK 0x28000 101c898c6b7SYadwinder Singh Brar #define KPLL_CON0 0x28100 1021609027fSChander Kashyap #define SRC_KFC 0x28200 1031609027fSChander Kashyap #define DIV_KFC0 0x28500 1041609027fSChander Kashyap 105c898c6b7SYadwinder Singh Brar /* list of PLLs */ 106c898c6b7SYadwinder Singh Brar enum exynos5420_plls { 107c898c6b7SYadwinder Singh Brar apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 108c898c6b7SYadwinder Singh Brar bpll, kpll, 109c898c6b7SYadwinder Singh Brar nr_plls /* number of PLLs */ 110c898c6b7SYadwinder Singh Brar }; 111c898c6b7SYadwinder Singh Brar 112388c7885STomasz Figa static void __iomem *reg_base; 113388c7885STomasz Figa 114388c7885STomasz Figa #ifdef CONFIG_PM_SLEEP 115388c7885STomasz Figa static struct samsung_clk_reg_dump *exynos5420_save; 116388c7885STomasz Figa 1171609027fSChander Kashyap /* 1181609027fSChander Kashyap * list of controller registers to be saved and restored during a 1191609027fSChander Kashyap * suspend/resume cycle. 1201609027fSChander Kashyap */ 121202e5ae9SSachin Kamat static unsigned long exynos5420_clk_regs[] __initdata = { 1221609027fSChander Kashyap SRC_CPU, 1231609027fSChander Kashyap DIV_CPU0, 1241609027fSChander Kashyap DIV_CPU1, 1251609027fSChander Kashyap GATE_BUS_CPU, 1261609027fSChander Kashyap GATE_SCLK_CPU, 1271609027fSChander Kashyap SRC_TOP0, 1281609027fSChander Kashyap SRC_TOP1, 1291609027fSChander Kashyap SRC_TOP2, 1301609027fSChander Kashyap SRC_TOP3, 1311609027fSChander Kashyap SRC_TOP4, 1321609027fSChander Kashyap SRC_TOP5, 1331609027fSChander Kashyap SRC_TOP6, 1341609027fSChander Kashyap SRC_TOP7, 1351609027fSChander Kashyap SRC_DISP10, 1361609027fSChander Kashyap SRC_MAU, 1371609027fSChander Kashyap SRC_FSYS, 1381609027fSChander Kashyap SRC_PERIC0, 1391609027fSChander Kashyap SRC_PERIC1, 1401609027fSChander Kashyap SRC_TOP10, 1411609027fSChander Kashyap SRC_TOP11, 1421609027fSChander Kashyap SRC_TOP12, 1431609027fSChander Kashyap SRC_MASK_DISP10, 1441609027fSChander Kashyap SRC_MASK_FSYS, 1451609027fSChander Kashyap SRC_MASK_PERIC0, 1461609027fSChander Kashyap SRC_MASK_PERIC1, 1471609027fSChander Kashyap DIV_TOP0, 1481609027fSChander Kashyap DIV_TOP1, 1491609027fSChander Kashyap DIV_TOP2, 1501609027fSChander Kashyap DIV_DISP10, 1511609027fSChander Kashyap DIV_MAU, 1521609027fSChander Kashyap DIV_FSYS0, 1531609027fSChander Kashyap DIV_FSYS1, 1541609027fSChander Kashyap DIV_FSYS2, 1551609027fSChander Kashyap DIV_PERIC0, 1561609027fSChander Kashyap DIV_PERIC1, 1571609027fSChander Kashyap DIV_PERIC2, 1581609027fSChander Kashyap DIV_PERIC3, 1591609027fSChander Kashyap DIV_PERIC4, 1601609027fSChander Kashyap GATE_BUS_TOP, 1611609027fSChander Kashyap GATE_BUS_FSYS0, 1621609027fSChander Kashyap GATE_BUS_PERIC, 1631609027fSChander Kashyap GATE_BUS_PERIC1, 1641609027fSChander Kashyap GATE_BUS_PERIS0, 1651609027fSChander Kashyap GATE_BUS_PERIS1, 1661609027fSChander Kashyap GATE_IP_GSCL0, 1671609027fSChander Kashyap GATE_IP_GSCL1, 1681609027fSChander Kashyap GATE_IP_MFC, 1691609027fSChander Kashyap GATE_IP_DISP1, 1701609027fSChander Kashyap GATE_IP_G3D, 1711609027fSChander Kashyap GATE_IP_GEN, 1721609027fSChander Kashyap GATE_IP_MSCL, 1731609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 1741609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 1751609027fSChander Kashyap GATE_TOP_SCLK_MAU, 1761609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1771609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1781609027fSChander Kashyap SRC_CDREX, 1791609027fSChander Kashyap SRC_KFC, 1801609027fSChander Kashyap DIV_KFC0, 1811609027fSChander Kashyap }; 1821609027fSChander Kashyap 183388c7885STomasz Figa static int exynos5420_clk_suspend(void) 184388c7885STomasz Figa { 185388c7885STomasz Figa samsung_clk_save(reg_base, exynos5420_save, 186388c7885STomasz Figa ARRAY_SIZE(exynos5420_clk_regs)); 187388c7885STomasz Figa 188388c7885STomasz Figa return 0; 189388c7885STomasz Figa } 190388c7885STomasz Figa 191388c7885STomasz Figa static void exynos5420_clk_resume(void) 192388c7885STomasz Figa { 193388c7885STomasz Figa samsung_clk_restore(reg_base, exynos5420_save, 194388c7885STomasz Figa ARRAY_SIZE(exynos5420_clk_regs)); 195388c7885STomasz Figa } 196388c7885STomasz Figa 197388c7885STomasz Figa static struct syscore_ops exynos5420_clk_syscore_ops = { 198388c7885STomasz Figa .suspend = exynos5420_clk_suspend, 199388c7885STomasz Figa .resume = exynos5420_clk_resume, 200388c7885STomasz Figa }; 201388c7885STomasz Figa 202388c7885STomasz Figa static void exynos5420_clk_sleep_init(void) 203388c7885STomasz Figa { 204388c7885STomasz Figa exynos5420_save = samsung_clk_alloc_reg_dump(exynos5420_clk_regs, 205388c7885STomasz Figa ARRAY_SIZE(exynos5420_clk_regs)); 206388c7885STomasz Figa if (!exynos5420_save) { 207388c7885STomasz Figa pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 208388c7885STomasz Figa __func__); 209388c7885STomasz Figa return; 210388c7885STomasz Figa } 211388c7885STomasz Figa 212388c7885STomasz Figa register_syscore_ops(&exynos5420_clk_syscore_ops); 213388c7885STomasz Figa } 214388c7885STomasz Figa #else 215388c7885STomasz Figa static void exynos5420_clk_sleep_init(void) {} 216388c7885STomasz Figa #endif 217388c7885STomasz Figa 2181609027fSChander Kashyap /* list of all parent clocks */ 2191609027fSChander Kashyap PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll", 2201609027fSChander Kashyap "sclk_mpll", "sclk_spll" }; 2211609027fSChander Kashyap PNAME(cpu_p) = { "mout_apll" , "mout_mspll_cpu" }; 2221609027fSChander Kashyap PNAME(kfc_p) = { "mout_kpll" , "mout_mspll_kfc" }; 2231609027fSChander Kashyap PNAME(apll_p) = { "fin_pll", "fout_apll", }; 2241609027fSChander Kashyap PNAME(bpll_p) = { "fin_pll", "fout_bpll", }; 2251609027fSChander Kashyap PNAME(cpll_p) = { "fin_pll", "fout_cpll", }; 2261609027fSChander Kashyap PNAME(dpll_p) = { "fin_pll", "fout_dpll", }; 2271609027fSChander Kashyap PNAME(epll_p) = { "fin_pll", "fout_epll", }; 2281609027fSChander Kashyap PNAME(ipll_p) = { "fin_pll", "fout_ipll", }; 2291609027fSChander Kashyap PNAME(kpll_p) = { "fin_pll", "fout_kpll", }; 2301609027fSChander Kashyap PNAME(mpll_p) = { "fin_pll", "fout_mpll", }; 2311609027fSChander Kashyap PNAME(rpll_p) = { "fin_pll", "fout_rpll", }; 2321609027fSChander Kashyap PNAME(spll_p) = { "fin_pll", "fout_spll", }; 2331609027fSChander Kashyap PNAME(vpll_p) = { "fin_pll", "fout_vpll", }; 2341609027fSChander Kashyap 2351609027fSChander Kashyap PNAME(group1_p) = { "sclk_cpll", "sclk_dpll", "sclk_mpll" }; 2361609027fSChander Kashyap PNAME(group2_p) = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll", 2371609027fSChander Kashyap "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 2381609027fSChander Kashyap PNAME(group3_p) = { "sclk_rpll", "sclk_spll" }; 2391609027fSChander Kashyap PNAME(group4_p) = { "sclk_ipll", "sclk_dpll", "sclk_mpll" }; 2401609027fSChander Kashyap PNAME(group5_p) = { "sclk_vpll", "sclk_dpll" }; 2411609027fSChander Kashyap 2421609027fSChander Kashyap PNAME(sw_aclk66_p) = { "dout_aclk66", "sclk_spll" }; 2431609027fSChander Kashyap PNAME(aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" }; 2441609027fSChander Kashyap 2451609027fSChander Kashyap PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"}; 2461609027fSChander Kashyap PNAME(user_aclk200_fsys_p) = { "fin_pll", "mout_sw_aclk200_fsys" }; 2471609027fSChander Kashyap 2481609027fSChander Kashyap PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"}; 2491609027fSChander Kashyap PNAME(user_aclk200_fsys2_p) = { "fin_pll", "mout_sw_aclk200_fsys2" }; 2501609027fSChander Kashyap 2511609027fSChander Kashyap PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"}; 2521609027fSChander Kashyap PNAME(aclk200_disp1_p) = { "fin_pll", "mout_sw_aclk200" }; 2531609027fSChander Kashyap 2541609027fSChander Kashyap PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"}; 2551609027fSChander Kashyap PNAME(user_aclk400_mscl_p) = { "fin_pll", "mout_sw_aclk400_mscl" }; 2561609027fSChander Kashyap 2571609027fSChander Kashyap PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"}; 2581609027fSChander Kashyap PNAME(user_aclk333_p) = { "fin_pll", "mout_sw_aclk333" }; 2591609027fSChander Kashyap 2601609027fSChander Kashyap PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"}; 2611609027fSChander Kashyap PNAME(user_aclk166_p) = { "fin_pll", "mout_sw_aclk166" }; 2621609027fSChander Kashyap 2631609027fSChander Kashyap PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"}; 2641609027fSChander Kashyap PNAME(user_aclk266_p) = { "fin_pll", "mout_sw_aclk266" }; 2651609027fSChander Kashyap 2661609027fSChander Kashyap PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"}; 2671609027fSChander Kashyap PNAME(user_aclk333_432_gscl_p) = { "fin_pll", "mout_sw_aclk333_432_gscl" }; 2681609027fSChander Kashyap 2691609027fSChander Kashyap PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"}; 2701609027fSChander Kashyap PNAME(user_aclk300_gscl_p) = { "fin_pll", "mout_sw_aclk300_gscl" }; 2711609027fSChander Kashyap 2721609027fSChander Kashyap PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"}; 2731609027fSChander Kashyap PNAME(user_aclk300_disp1_p) = { "fin_pll", "mout_sw_aclk300_disp1" }; 2741609027fSChander Kashyap 2751609027fSChander Kashyap PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"}; 2761609027fSChander Kashyap PNAME(user_aclk300_jpeg_p) = { "fin_pll", "mout_sw_aclk300_jpeg" }; 2771609027fSChander Kashyap 2781609027fSChander Kashyap PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"}; 2791609027fSChander Kashyap PNAME(user_aclk_g3d_p) = { "fin_pll", "mout_sw_aclk_g3d" }; 2801609027fSChander Kashyap 2811609027fSChander Kashyap PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"}; 2821609027fSChander Kashyap PNAME(user_aclk266_g2d_p) = { "fin_pll", "mout_sw_aclk266_g2d" }; 2831609027fSChander Kashyap 2841609027fSChander Kashyap PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"}; 2851609027fSChander Kashyap PNAME(user_aclk333_g2d_p) = { "fin_pll", "mout_sw_aclk333_g2d" }; 2861609027fSChander Kashyap 2871609027fSChander Kashyap PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll", 2881609027fSChander Kashyap "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 2891609027fSChander Kashyap PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll", 2901609027fSChander Kashyap "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 2911609027fSChander Kashyap PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll", 2921609027fSChander Kashyap "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 2931609027fSChander Kashyap PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2", 2941609027fSChander Kashyap "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 29514d87cdaSRahul Sharma PNAME(hdmi_p) = { "dout_hdmi_pixel", "sclk_hdmiphy" }; 2961609027fSChander Kashyap PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll", 2971609027fSChander Kashyap "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 2981609027fSChander Kashyap 2991609027fSChander Kashyap /* fixed rate clocks generated outside the soc */ 300c7306229SSachin Kamat static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 301cba9d2faSAndrzej Hajda FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 3021609027fSChander Kashyap }; 3031609027fSChander Kashyap 3041609027fSChander Kashyap /* fixed rate clocks generated inside the soc */ 305c7306229SSachin Kamat static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { 306cba9d2faSAndrzej Hajda FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 307cba9d2faSAndrzej Hajda FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 308cba9d2faSAndrzej Hajda FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 309cba9d2faSAndrzej Hajda FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), 310cba9d2faSAndrzej Hajda FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 3111609027fSChander Kashyap }; 3121609027fSChander Kashyap 313c7306229SSachin Kamat static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 314cba9d2faSAndrzej Hajda FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0), 3151609027fSChander Kashyap }; 3161609027fSChander Kashyap 317c7306229SSachin Kamat static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 318cba9d2faSAndrzej Hajda MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2), 319cba9d2faSAndrzej Hajda MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2), 320cba9d2faSAndrzej Hajda MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1), 321cba9d2faSAndrzej Hajda MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1), 322cba9d2faSAndrzej Hajda MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1), 323cba9d2faSAndrzej Hajda MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), 3241609027fSChander Kashyap 325cba9d2faSAndrzej Hajda MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), 3261609027fSChander Kashyap 327cba9d2faSAndrzej Hajda MUX_A(0, "mout_aclk400_mscl", group1_p, 3281609027fSChander Kashyap SRC_TOP0, 4, 2, "aclk400_mscl"), 329cba9d2faSAndrzej Hajda MUX(0, "mout_aclk200", group1_p, SRC_TOP0, 8, 2), 330cba9d2faSAndrzej Hajda MUX(0, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2), 331cba9d2faSAndrzej Hajda MUX(0, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2), 3321609027fSChander Kashyap 333cba9d2faSAndrzej Hajda MUX(0, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2), 334cba9d2faSAndrzej Hajda MUX(0, "mout_aclk66", group1_p, SRC_TOP1, 8, 2), 335cba9d2faSAndrzej Hajda MUX(0, "mout_aclk266", group1_p, SRC_TOP1, 20, 2), 336cba9d2faSAndrzej Hajda MUX(0, "mout_aclk166", group1_p, SRC_TOP1, 24, 2), 337cba9d2faSAndrzej Hajda MUX(0, "mout_aclk333", group1_p, SRC_TOP1, 28, 2), 3381609027fSChander Kashyap 339cba9d2faSAndrzej Hajda MUX(0, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2), 340cba9d2faSAndrzej Hajda MUX(0, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2), 341cba9d2faSAndrzej Hajda MUX(0, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1), 342cba9d2faSAndrzej Hajda MUX(0, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2), 343cba9d2faSAndrzej Hajda MUX(0, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2), 344cba9d2faSAndrzej Hajda MUX(0, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2), 3451609027fSChander Kashyap 346cba9d2faSAndrzej Hajda MUX(0, "mout_user_aclk400_mscl", user_aclk400_mscl_p, 3471609027fSChander Kashyap SRC_TOP3, 4, 1), 348cba9d2faSAndrzej Hajda MUX_A(0, "mout_aclk200_disp1", aclk200_disp1_p, 3491609027fSChander Kashyap SRC_TOP3, 8, 1, "aclk200_disp1"), 350cba9d2faSAndrzej Hajda MUX(0, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p, 3511609027fSChander Kashyap SRC_TOP3, 12, 1), 352cba9d2faSAndrzej Hajda MUX(0, "mout_user_aclk200_fsys", user_aclk200_fsys_p, 3531609027fSChander Kashyap SRC_TOP3, 28, 1), 3541609027fSChander Kashyap 355cba9d2faSAndrzej Hajda MUX(0, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p, 3561609027fSChander Kashyap SRC_TOP4, 0, 1), 357cba9d2faSAndrzej Hajda MUX(0, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1), 358cba9d2faSAndrzej Hajda MUX(0, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1), 359cba9d2faSAndrzej Hajda MUX(0, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1), 360cba9d2faSAndrzej Hajda MUX(0, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1), 3611609027fSChander Kashyap 362cba9d2faSAndrzej Hajda MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1), 363cba9d2faSAndrzej Hajda MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1), 364cba9d2faSAndrzej Hajda MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1), 365cba9d2faSAndrzej Hajda MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p, 3661609027fSChander Kashyap SRC_TOP5, 16, 1, "aclkg3d"), 367cba9d2faSAndrzej Hajda MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p, 3681609027fSChander Kashyap SRC_TOP5, 20, 1), 369cba9d2faSAndrzej Hajda MUX(0, "mout_user_aclk300_disp1", user_aclk300_disp1_p, 3701609027fSChander Kashyap SRC_TOP5, 24, 1), 371cba9d2faSAndrzej Hajda MUX(0, "mout_user_aclk300_gscl", user_aclk300_gscl_p, 3721609027fSChander Kashyap SRC_TOP5, 28, 1), 3731609027fSChander Kashyap 374cba9d2faSAndrzej Hajda MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1), 375cba9d2faSAndrzej Hajda MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1), 376cba9d2faSAndrzej Hajda MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1), 377cba9d2faSAndrzej Hajda MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1), 378cba9d2faSAndrzej Hajda MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1), 379cba9d2faSAndrzej Hajda MUX(0, "sclk_epll", epll_p, SRC_TOP6, 20, 1), 380cba9d2faSAndrzej Hajda MUX(0, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1), 381cba9d2faSAndrzej Hajda MUX(0, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1), 3821609027fSChander Kashyap 383cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1), 384cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1), 385cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p, 3861609027fSChander Kashyap SRC_TOP10, 12, 1), 387cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1), 3881609027fSChander Kashyap 389cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p, 3901609027fSChander Kashyap SRC_TOP11, 0, 1), 391cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1), 392cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1), 393cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1), 394cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1), 3951609027fSChander Kashyap 396cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1), 397cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1), 398cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1), 399cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), 400cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p, 4011609027fSChander Kashyap SRC_TOP12, 24, 1), 402cba9d2faSAndrzej Hajda MUX(0, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 4031609027fSChander Kashyap 4041609027fSChander Kashyap /* DISP1 Block */ 405cba9d2faSAndrzej Hajda MUX(0, "mout_fimd1", group3_p, SRC_DISP10, 4, 1), 406cba9d2faSAndrzej Hajda MUX(0, "mout_mipi1", group2_p, SRC_DISP10, 16, 3), 407cba9d2faSAndrzej Hajda MUX(0, "mout_dp1", group2_p, SRC_DISP10, 20, 3), 408cba9d2faSAndrzej Hajda MUX(0, "mout_pixel", group2_p, SRC_DISP10, 24, 3), 409cba9d2faSAndrzej Hajda MUX(CLK_MOUT_HDMI, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), 4101609027fSChander Kashyap 4111609027fSChander Kashyap /* MAU Block */ 412cba9d2faSAndrzej Hajda MUX(0, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3), 4131609027fSChander Kashyap 4141609027fSChander Kashyap /* FSYS Block */ 415cba9d2faSAndrzej Hajda MUX(0, "mout_usbd301", group2_p, SRC_FSYS, 4, 3), 416cba9d2faSAndrzej Hajda MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 8, 3), 417cba9d2faSAndrzej Hajda MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 12, 3), 418cba9d2faSAndrzej Hajda MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 16, 3), 419cba9d2faSAndrzej Hajda MUX(0, "mout_usbd300", group2_p, SRC_FSYS, 20, 3), 420cba9d2faSAndrzej Hajda MUX(0, "mout_unipro", group2_p, SRC_FSYS, 24, 3), 4211609027fSChander Kashyap 4221609027fSChander Kashyap /* PERIC Block */ 423cba9d2faSAndrzej Hajda MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 4, 3), 424cba9d2faSAndrzej Hajda MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 8, 3), 425cba9d2faSAndrzej Hajda MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 12, 3), 426cba9d2faSAndrzej Hajda MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 16, 3), 427cba9d2faSAndrzej Hajda MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 3), 428cba9d2faSAndrzej Hajda MUX(0, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3), 429cba9d2faSAndrzej Hajda MUX(0, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3), 430cba9d2faSAndrzej Hajda MUX(0, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3), 431cba9d2faSAndrzej Hajda MUX(0, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3), 432cba9d2faSAndrzej Hajda MUX(0, "mout_spi0", group2_p, SRC_PERIC1, 20, 3), 433cba9d2faSAndrzej Hajda MUX(0, "mout_spi1", group2_p, SRC_PERIC1, 24, 3), 434cba9d2faSAndrzej Hajda MUX(0, "mout_spi2", group2_p, SRC_PERIC1, 28, 3), 4351609027fSChander Kashyap }; 4361609027fSChander Kashyap 437c7306229SSachin Kamat static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 438cba9d2faSAndrzej Hajda DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 439cba9d2faSAndrzej Hajda DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 440cba9d2faSAndrzej Hajda DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 441cba9d2faSAndrzej Hajda DIV(0, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3), 442cba9d2faSAndrzej Hajda DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 4431609027fSChander Kashyap 444cba9d2faSAndrzej Hajda DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 445cba9d2faSAndrzej Hajda DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 446cba9d2faSAndrzej Hajda DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 447cba9d2faSAndrzej Hajda DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 448cba9d2faSAndrzej Hajda DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 4491609027fSChander Kashyap 450cba9d2faSAndrzej Hajda DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 4511609027fSChander Kashyap DIV_TOP1, 0, 3), 452cba9d2faSAndrzej Hajda DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 453cba9d2faSAndrzej Hajda DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 454cba9d2faSAndrzej Hajda DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 455cba9d2faSAndrzej Hajda DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 4561609027fSChander Kashyap 457cba9d2faSAndrzej Hajda DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), 458cba9d2faSAndrzej Hajda DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 459cba9d2faSAndrzej Hajda DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 460cba9d2faSAndrzej Hajda DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 461cba9d2faSAndrzej Hajda DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1", 4621609027fSChander Kashyap DIV_TOP2, 24, 3, "aclk300_disp1"), 463cba9d2faSAndrzej Hajda DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 4641609027fSChander Kashyap 4651609027fSChander Kashyap /* DISP1 Block */ 466cba9d2faSAndrzej Hajda DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), 467cba9d2faSAndrzej Hajda DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 468cba9d2faSAndrzej Hajda DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 469cba9d2faSAndrzej Hajda DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 4701609027fSChander Kashyap 4711609027fSChander Kashyap /* Audio Block */ 472cba9d2faSAndrzej Hajda DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 473cba9d2faSAndrzej Hajda DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 4741609027fSChander Kashyap 4751609027fSChander Kashyap /* USB3.0 */ 476cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 477cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 478cba9d2faSAndrzej Hajda DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 479cba9d2faSAndrzej Hajda DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 4801609027fSChander Kashyap 4811609027fSChander Kashyap /* MMC */ 482cba9d2faSAndrzej Hajda DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 483cba9d2faSAndrzej Hajda DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 484cba9d2faSAndrzej Hajda DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 4851609027fSChander Kashyap 486cba9d2faSAndrzej Hajda DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 4871609027fSChander Kashyap 4881609027fSChander Kashyap /* UART and PWM */ 489cba9d2faSAndrzej Hajda DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 490cba9d2faSAndrzej Hajda DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 491cba9d2faSAndrzej Hajda DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 492cba9d2faSAndrzej Hajda DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 493cba9d2faSAndrzej Hajda DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 4941609027fSChander Kashyap 4951609027fSChander Kashyap /* SPI */ 496cba9d2faSAndrzej Hajda DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 497cba9d2faSAndrzej Hajda DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 498cba9d2faSAndrzej Hajda DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 4991609027fSChander Kashyap 5001609027fSChander Kashyap /* PCM */ 501cba9d2faSAndrzej Hajda DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 502cba9d2faSAndrzej Hajda DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 5031609027fSChander Kashyap 5041609027fSChander Kashyap /* Audio - I2S */ 505cba9d2faSAndrzej Hajda DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 506cba9d2faSAndrzej Hajda DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 507cba9d2faSAndrzej Hajda DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 508cba9d2faSAndrzej Hajda DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 509cba9d2faSAndrzej Hajda DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 5101609027fSChander Kashyap 5111609027fSChander Kashyap /* SPI Pre-Ratio */ 512cba9d2faSAndrzej Hajda DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), 513cba9d2faSAndrzej Hajda DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), 514cba9d2faSAndrzej Hajda DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), 5151609027fSChander Kashyap }; 5161609027fSChander Kashyap 517c7306229SSachin Kamat static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 5181609027fSChander Kashyap /* TODO: Re-verify the CG bits for all the gate clocks */ 519cba9d2faSAndrzej Hajda GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, 520cba9d2faSAndrzej Hajda "mct"), 5211609027fSChander Kashyap 5221609027fSChander Kashyap GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 5231609027fSChander Kashyap GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 5241609027fSChander Kashyap GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 5251609027fSChander Kashyap GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 5261609027fSChander Kashyap 5271609027fSChander Kashyap GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 5281609027fSChander Kashyap GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 5291609027fSChander Kashyap GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 5301609027fSChander Kashyap GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), 5311609027fSChander Kashyap GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 5321609027fSChander Kashyap GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 5331609027fSChander Kashyap GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 5341609027fSChander Kashyap GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), 5351609027fSChander Kashyap GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 5361609027fSChander Kashyap GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 5371609027fSChander Kashyap GATE(0, "pclk66_gpio", "mout_sw_aclk66", 5381609027fSChander Kashyap GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 5391609027fSChander Kashyap GATE(0, "aclk66_psgen", "mout_aclk66_psgen", 5401609027fSChander Kashyap GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 5411609027fSChander Kashyap GATE(0, "aclk66_peric", "mout_aclk66_peric", 5421609027fSChander Kashyap GATE_BUS_TOP, 11, 0, 0), 5431609027fSChander Kashyap GATE(0, "aclk166", "mout_user_aclk166", 5441609027fSChander Kashyap GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 5451609027fSChander Kashyap GATE(0, "aclk333", "mout_aclk333", 5461609027fSChander Kashyap GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 5471609027fSChander Kashyap 5481609027fSChander Kashyap /* sclk */ 549cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 5501609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 551cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 5521609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 553cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 5541609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 555cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 5561609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 557cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0", 5581609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 559cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1", 5601609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 561cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2", 5621609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 563cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 5641609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 565cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 5661609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 567cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 5681609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 569cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 5701609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 571cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 5721609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 573cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 5741609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 5751609027fSChander Kashyap 576cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 5771609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 578cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 5791609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 580cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 5811609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 582cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 5831609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 584cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 5851609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 586cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 5871609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 588cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 5891609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 5901609027fSChander Kashyap 591cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro", 5921609027fSChander Kashyap SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 5931609027fSChander Kashyap 594cba9d2faSAndrzej Hajda GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl", 5951609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0), 596cba9d2faSAndrzej Hajda GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl", 5971609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0), 5981609027fSChander Kashyap 5991609027fSChander Kashyap /* Display */ 600cba9d2faSAndrzej Hajda GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 6011609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 602cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 6031609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 604cba9d2faSAndrzej Hajda GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 6051609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), 606cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 6071609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 608cba9d2faSAndrzej Hajda GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 6091609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 6101609027fSChander Kashyap 6111609027fSChander Kashyap /* Maudio Block */ 612cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 6131609027fSChander Kashyap GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 614cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 6151609027fSChander Kashyap GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 6161609027fSChander Kashyap /* FSYS */ 617cba9d2faSAndrzej Hajda GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 618cba9d2faSAndrzej Hajda GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 619cba9d2faSAndrzej Hajda GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 620cba9d2faSAndrzej Hajda GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 621cba9d2faSAndrzej Hajda GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), 622cba9d2faSAndrzej Hajda GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), 623cba9d2faSAndrzej Hajda GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), 624cba9d2faSAndrzej Hajda GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), 625cba9d2faSAndrzej Hajda GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 6261609027fSChander Kashyap GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), 627cba9d2faSAndrzej Hajda GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), 628cba9d2faSAndrzej Hajda GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), 629cba9d2faSAndrzej Hajda GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), 6301609027fSChander Kashyap 6311609027fSChander Kashyap /* UART */ 632cba9d2faSAndrzej Hajda GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0), 633cba9d2faSAndrzej Hajda GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0), 634cba9d2faSAndrzej Hajda GATE_A(CLK_UART2, "uart2", "aclk66_peric", 6351609027fSChander Kashyap GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"), 636cba9d2faSAndrzej Hajda GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0), 6371609027fSChander Kashyap /* I2C */ 638cba9d2faSAndrzej Hajda GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0), 639cba9d2faSAndrzej Hajda GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0), 640cba9d2faSAndrzej Hajda GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0), 641cba9d2faSAndrzej Hajda GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0), 642cba9d2faSAndrzej Hajda GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0), 643cba9d2faSAndrzej Hajda GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0), 644cba9d2faSAndrzej Hajda GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0), 645cba9d2faSAndrzej Hajda GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0), 646cba9d2faSAndrzej Hajda GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 647cba9d2faSAndrzej Hajda 0), 648cba9d2faSAndrzej Hajda GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0), 6491609027fSChander Kashyap /* SPI */ 650cba9d2faSAndrzej Hajda GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0), 651cba9d2faSAndrzej Hajda GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0), 652cba9d2faSAndrzej Hajda GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0), 653cba9d2faSAndrzej Hajda GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0), 6541609027fSChander Kashyap /* I2S */ 655cba9d2faSAndrzej Hajda GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0), 656cba9d2faSAndrzej Hajda GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0), 6571609027fSChander Kashyap /* PCM */ 658cba9d2faSAndrzej Hajda GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0), 659cba9d2faSAndrzej Hajda GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0), 6601609027fSChander Kashyap /* PWM */ 661cba9d2faSAndrzej Hajda GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0), 6621609027fSChander Kashyap /* SPDIF */ 663cba9d2faSAndrzej Hajda GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0), 6641609027fSChander Kashyap 665cba9d2faSAndrzej Hajda GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0), 666cba9d2faSAndrzej Hajda GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0), 667cba9d2faSAndrzej Hajda GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0), 6681609027fSChander Kashyap 669cba9d2faSAndrzej Hajda GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 6701609027fSChander Kashyap GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0), 671cba9d2faSAndrzej Hajda GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 6721609027fSChander Kashyap GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0), 673cba9d2faSAndrzej Hajda GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0), 674cba9d2faSAndrzej Hajda GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0), 675cba9d2faSAndrzej Hajda GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0), 676cba9d2faSAndrzej Hajda GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0), 677cba9d2faSAndrzej Hajda GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0), 678cba9d2faSAndrzej Hajda GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0), 679cba9d2faSAndrzej Hajda GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0), 680cba9d2faSAndrzej Hajda GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0), 681cba9d2faSAndrzej Hajda GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0), 682cba9d2faSAndrzej Hajda GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0), 6831609027fSChander Kashyap 684cba9d2faSAndrzej Hajda GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 685cba9d2faSAndrzej Hajda 0), 686cba9d2faSAndrzej Hajda GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 687cba9d2faSAndrzej Hajda GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0), 688cba9d2faSAndrzej Hajda GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0), 689cba9d2faSAndrzej Hajda GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0), 690cba9d2faSAndrzej Hajda GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0), 6911609027fSChander Kashyap 692cba9d2faSAndrzej Hajda GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 693cba9d2faSAndrzej Hajda GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 694cba9d2faSAndrzej Hajda GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0), 6951609027fSChander Kashyap 696cba9d2faSAndrzej Hajda GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 697cba9d2faSAndrzej Hajda 0), 698cba9d2faSAndrzej Hajda GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl", 6991609027fSChander Kashyap GATE_IP_GSCL1, 3, 0, 0), 700cba9d2faSAndrzej Hajda GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl", 7011609027fSChander Kashyap GATE_IP_GSCL1, 4, 0, 0), 702cba9d2faSAndrzej Hajda GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 703cba9d2faSAndrzej Hajda 0), 704cba9d2faSAndrzej Hajda GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 705cba9d2faSAndrzej Hajda 0), 706cba9d2faSAndrzej Hajda GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0), 707cba9d2faSAndrzej Hajda GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0), 708cba9d2faSAndrzej Hajda GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl", 7091609027fSChander Kashyap GATE_IP_GSCL1, 16, 0, 0), 710cba9d2faSAndrzej Hajda GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 7111609027fSChander Kashyap GATE_IP_GSCL1, 17, 0, 0), 7121609027fSChander Kashyap 713cba9d2faSAndrzej Hajda GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 714cba9d2faSAndrzej Hajda GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 715cba9d2faSAndrzej Hajda GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 716cba9d2faSAndrzej Hajda GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0), 717cba9d2faSAndrzej Hajda GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 718cba9d2faSAndrzej Hajda GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 719cba9d2faSAndrzej Hajda 0), 7201609027fSChander Kashyap 721cba9d2faSAndrzej Hajda GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 722cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 723cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 7241609027fSChander Kashyap 725cba9d2faSAndrzej Hajda GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0), 7261609027fSChander Kashyap 727cba9d2faSAndrzej Hajda GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 728cba9d2faSAndrzej Hajda GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 729cba9d2faSAndrzej Hajda GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 730cba9d2faSAndrzej Hajda GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), 731cba9d2faSAndrzej Hajda GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), 732cba9d2faSAndrzej Hajda GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0), 733cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0), 7341609027fSChander Kashyap 735cba9d2faSAndrzej Hajda GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 736cba9d2faSAndrzej Hajda GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 737cba9d2faSAndrzej Hajda GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 738cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 739cba9d2faSAndrzej Hajda 0), 740cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 741cba9d2faSAndrzej Hajda 0), 742cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 743cba9d2faSAndrzej Hajda 0), 744cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 745cba9d2faSAndrzej Hajda 0), 7461609027fSChander Kashyap }; 7471609027fSChander Kashyap 748202e5ae9SSachin Kamat static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { 749cba9d2faSAndrzej Hajda [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 7503ff6e0d8SYadwinder Singh Brar APLL_CON0, NULL), 751cba9d2faSAndrzej Hajda [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 752cdf64eeeSChander Kashyap CPLL_CON0, NULL), 753cba9d2faSAndrzej Hajda [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 7543ff6e0d8SYadwinder Singh Brar DPLL_CON0, NULL), 755cba9d2faSAndrzej Hajda [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 7563ff6e0d8SYadwinder Singh Brar EPLL_CON0, NULL), 757cba9d2faSAndrzej Hajda [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 7583ff6e0d8SYadwinder Singh Brar RPLL_CON0, NULL), 759cba9d2faSAndrzej Hajda [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 7603ff6e0d8SYadwinder Singh Brar IPLL_CON0, NULL), 761cba9d2faSAndrzej Hajda [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 7623ff6e0d8SYadwinder Singh Brar SPLL_CON0, NULL), 763cba9d2faSAndrzej Hajda [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 7643ff6e0d8SYadwinder Singh Brar VPLL_CON0, NULL), 765cba9d2faSAndrzej Hajda [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 7663ff6e0d8SYadwinder Singh Brar MPLL_CON0, NULL), 767cba9d2faSAndrzej Hajda [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 7683ff6e0d8SYadwinder Singh Brar BPLL_CON0, NULL), 769cba9d2faSAndrzej Hajda [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 7703ff6e0d8SYadwinder Singh Brar KPLL_CON0, NULL), 771c898c6b7SYadwinder Singh Brar }; 772c898c6b7SYadwinder Singh Brar 773202e5ae9SSachin Kamat static struct of_device_id ext_clk_match[] __initdata = { 7741609027fSChander Kashyap { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 7751609027fSChander Kashyap { }, 7761609027fSChander Kashyap }; 7771609027fSChander Kashyap 7781609027fSChander Kashyap /* register exynos5420 clocks */ 779c7306229SSachin Kamat static void __init exynos5420_clk_init(struct device_node *np) 7801609027fSChander Kashyap { 7811609027fSChander Kashyap if (np) { 7821609027fSChander Kashyap reg_base = of_iomap(np, 0); 7831609027fSChander Kashyap if (!reg_base) 7841609027fSChander Kashyap panic("%s: failed to map registers\n", __func__); 7851609027fSChander Kashyap } else { 7861609027fSChander Kashyap panic("%s: unable to determine soc\n", __func__); 7871609027fSChander Kashyap } 7881609027fSChander Kashyap 789388c7885STomasz Figa samsung_clk_init(np, reg_base, CLK_NR_CLKS, NULL, 0, NULL, 0); 7901609027fSChander Kashyap samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, 7911609027fSChander Kashyap ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), 7921609027fSChander Kashyap ext_clk_match); 793c898c6b7SYadwinder Singh Brar samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), 794c898c6b7SYadwinder Singh Brar reg_base); 7951609027fSChander Kashyap samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks, 7961609027fSChander Kashyap ARRAY_SIZE(exynos5420_fixed_rate_clks)); 7971609027fSChander Kashyap samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks, 7981609027fSChander Kashyap ARRAY_SIZE(exynos5420_fixed_factor_clks)); 7991609027fSChander Kashyap samsung_clk_register_mux(exynos5420_mux_clks, 8001609027fSChander Kashyap ARRAY_SIZE(exynos5420_mux_clks)); 8011609027fSChander Kashyap samsung_clk_register_div(exynos5420_div_clks, 8021609027fSChander Kashyap ARRAY_SIZE(exynos5420_div_clks)); 8031609027fSChander Kashyap samsung_clk_register_gate(exynos5420_gate_clks, 8041609027fSChander Kashyap ARRAY_SIZE(exynos5420_gate_clks)); 805388c7885STomasz Figa 806388c7885STomasz Figa exynos5420_clk_sleep_init(); 8071609027fSChander Kashyap } 8081609027fSChander Kashyap CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 809