11609027fSChander Kashyap /* 21609027fSChander Kashyap * Copyright (c) 2013 Samsung Electronics Co., Ltd. 31609027fSChander Kashyap * Authors: Thomas Abraham <thomas.ab@samsung.com> 41609027fSChander Kashyap * Chander Kashyap <k.chander@samsung.com> 51609027fSChander Kashyap * 61609027fSChander Kashyap * This program is free software; you can redistribute it and/or modify 71609027fSChander Kashyap * it under the terms of the GNU General Public License version 2 as 81609027fSChander Kashyap * published by the Free Software Foundation. 91609027fSChander Kashyap * 101609027fSChander Kashyap * Common Clock Framework support for Exynos5420 SoC. 111609027fSChander Kashyap */ 121609027fSChander Kashyap 13cba9d2faSAndrzej Hajda #include <dt-bindings/clock/exynos5420.h> 146f1ed07aSStephen Boyd #include <linux/slab.h> 151609027fSChander Kashyap #include <linux/clk-provider.h> 161609027fSChander Kashyap #include <linux/of.h> 171609027fSChander Kashyap #include <linux/of_address.h> 18388c7885STomasz Figa #include <linux/syscore_ops.h> 191609027fSChander Kashyap 201609027fSChander Kashyap #include "clk.h" 21bee4f87fSThomas Abraham #include "clk-cpu.h" 221609027fSChander Kashyap 23c898c6b7SYadwinder Singh Brar #define APLL_LOCK 0x0 24c898c6b7SYadwinder Singh Brar #define APLL_CON0 0x100 251609027fSChander Kashyap #define SRC_CPU 0x200 261609027fSChander Kashyap #define DIV_CPU0 0x500 271609027fSChander Kashyap #define DIV_CPU1 0x504 281609027fSChander Kashyap #define GATE_BUS_CPU 0x700 291609027fSChander Kashyap #define GATE_SCLK_CPU 0x800 3077342432SShaik Ameer Basha #define CLKOUT_CMU_CPU 0xa00 31e9d52956SVikas Sajjan #define SRC_MASK_CPERI 0x4300 325b73721bSNaveen Krishna Chatradhi #define GATE_IP_G2D 0x8800 33c898c6b7SYadwinder Singh Brar #define CPLL_LOCK 0x10020 34c898c6b7SYadwinder Singh Brar #define DPLL_LOCK 0x10030 35c898c6b7SYadwinder Singh Brar #define EPLL_LOCK 0x10040 36c898c6b7SYadwinder Singh Brar #define RPLL_LOCK 0x10050 37c898c6b7SYadwinder Singh Brar #define IPLL_LOCK 0x10060 38c898c6b7SYadwinder Singh Brar #define SPLL_LOCK 0x10070 3953cb6342SSachin Kamat #define VPLL_LOCK 0x10080 40c898c6b7SYadwinder Singh Brar #define MPLL_LOCK 0x10090 41c898c6b7SYadwinder Singh Brar #define CPLL_CON0 0x10120 42c898c6b7SYadwinder Singh Brar #define DPLL_CON0 0x10128 43c898c6b7SYadwinder Singh Brar #define EPLL_CON0 0x10130 4477342432SShaik Ameer Basha #define EPLL_CON1 0x10134 4577342432SShaik Ameer Basha #define EPLL_CON2 0x10138 46c898c6b7SYadwinder Singh Brar #define RPLL_CON0 0x10140 4777342432SShaik Ameer Basha #define RPLL_CON1 0x10144 4877342432SShaik Ameer Basha #define RPLL_CON2 0x10148 49c898c6b7SYadwinder Singh Brar #define IPLL_CON0 0x10150 50c898c6b7SYadwinder Singh Brar #define SPLL_CON0 0x10160 51c898c6b7SYadwinder Singh Brar #define VPLL_CON0 0x10170 52c898c6b7SYadwinder Singh Brar #define MPLL_CON0 0x10180 531609027fSChander Kashyap #define SRC_TOP0 0x10200 541609027fSChander Kashyap #define SRC_TOP1 0x10204 551609027fSChander Kashyap #define SRC_TOP2 0x10208 561609027fSChander Kashyap #define SRC_TOP3 0x1020c 571609027fSChander Kashyap #define SRC_TOP4 0x10210 581609027fSChander Kashyap #define SRC_TOP5 0x10214 591609027fSChander Kashyap #define SRC_TOP6 0x10218 601609027fSChander Kashyap #define SRC_TOP7 0x1021c 616520e968SAlim Akhtar #define SRC_TOP8 0x10220 /* 5800 specific */ 626520e968SAlim Akhtar #define SRC_TOP9 0x10224 /* 5800 specific */ 631609027fSChander Kashyap #define SRC_DISP10 0x1022c 641609027fSChander Kashyap #define SRC_MAU 0x10240 651609027fSChander Kashyap #define SRC_FSYS 0x10244 661609027fSChander Kashyap #define SRC_PERIC0 0x10250 671609027fSChander Kashyap #define SRC_PERIC1 0x10254 683a767b35SShaik Ameer Basha #define SRC_ISP 0x10270 696520e968SAlim Akhtar #define SRC_CAM 0x10274 /* 5800 specific */ 701609027fSChander Kashyap #define SRC_TOP10 0x10280 711609027fSChander Kashyap #define SRC_TOP11 0x10284 721609027fSChander Kashyap #define SRC_TOP12 0x10288 736520e968SAlim Akhtar #define SRC_TOP13 0x1028c /* 5800 specific */ 74e9d52956SVikas Sajjan #define SRC_MASK_TOP0 0x10300 75e9d52956SVikas Sajjan #define SRC_MASK_TOP1 0x10304 76424b673aSShaik Ameer Basha #define SRC_MASK_TOP2 0x10308 7731116a64SShaik Ameer Basha #define SRC_MASK_TOP7 0x1031c 781609027fSChander Kashyap #define SRC_MASK_DISP10 0x1032c 7931116a64SShaik Ameer Basha #define SRC_MASK_MAU 0x10334 801609027fSChander Kashyap #define SRC_MASK_FSYS 0x10340 811609027fSChander Kashyap #define SRC_MASK_PERIC0 0x10350 821609027fSChander Kashyap #define SRC_MASK_PERIC1 0x10354 83e9d52956SVikas Sajjan #define SRC_MASK_ISP 0x10370 841609027fSChander Kashyap #define DIV_TOP0 0x10500 851609027fSChander Kashyap #define DIV_TOP1 0x10504 861609027fSChander Kashyap #define DIV_TOP2 0x10508 876520e968SAlim Akhtar #define DIV_TOP8 0x10520 /* 5800 specific */ 886520e968SAlim Akhtar #define DIV_TOP9 0x10524 /* 5800 specific */ 891609027fSChander Kashyap #define DIV_DISP10 0x1052c 901609027fSChander Kashyap #define DIV_MAU 0x10544 911609027fSChander Kashyap #define DIV_FSYS0 0x10548 921609027fSChander Kashyap #define DIV_FSYS1 0x1054c 931609027fSChander Kashyap #define DIV_FSYS2 0x10550 941609027fSChander Kashyap #define DIV_PERIC0 0x10558 951609027fSChander Kashyap #define DIV_PERIC1 0x1055c 961609027fSChander Kashyap #define DIV_PERIC2 0x10560 971609027fSChander Kashyap #define DIV_PERIC3 0x10564 981609027fSChander Kashyap #define DIV_PERIC4 0x10568 996520e968SAlim Akhtar #define DIV_CAM 0x10574 /* 5800 specific */ 1003a767b35SShaik Ameer Basha #define SCLK_DIV_ISP0 0x10580 1013a767b35SShaik Ameer Basha #define SCLK_DIV_ISP1 0x10584 10202932381SShaik Ameer Basha #define DIV2_RATIO0 0x10590 1031d87db4dSShaik Ameer Basha #define DIV4_RATIO 0x105a0 1041609027fSChander Kashyap #define GATE_BUS_TOP 0x10700 105e9d52956SVikas Sajjan #define GATE_BUS_DISP1 0x10728 1060a22c306SShaik Ameer Basha #define GATE_BUS_GEN 0x1073c 1071609027fSChander Kashyap #define GATE_BUS_FSYS0 0x10740 1086b5ae463SShaik Ameer Basha #define GATE_BUS_FSYS2 0x10748 1091609027fSChander Kashyap #define GATE_BUS_PERIC 0x10750 1101609027fSChander Kashyap #define GATE_BUS_PERIC1 0x10754 1111609027fSChander Kashyap #define GATE_BUS_PERIS0 0x10760 1121609027fSChander Kashyap #define GATE_BUS_PERIS1 0x10764 1136575fa76SShaik Ameer Basha #define GATE_BUS_NOC 0x10770 1143a767b35SShaik Ameer Basha #define GATE_TOP_SCLK_ISP 0x10870 1151609027fSChander Kashyap #define GATE_IP_GSCL0 0x10910 1161609027fSChander Kashyap #define GATE_IP_GSCL1 0x10920 1176520e968SAlim Akhtar #define GATE_IP_CAM 0x10924 /* 5800 specific */ 1181609027fSChander Kashyap #define GATE_IP_MFC 0x1092c 1191609027fSChander Kashyap #define GATE_IP_DISP1 0x10928 1201609027fSChander Kashyap #define GATE_IP_G3D 0x10930 1211609027fSChander Kashyap #define GATE_IP_GEN 0x10934 1226b5ae463SShaik Ameer Basha #define GATE_IP_FSYS 0x10944 123faec151bSShaik Ameer Basha #define GATE_IP_PERIC 0x10950 1240a22c306SShaik Ameer Basha #define GATE_IP_PERIS 0x10960 1251609027fSChander Kashyap #define GATE_IP_MSCL 0x10970 1261609027fSChander Kashyap #define GATE_TOP_SCLK_GSCL 0x10820 1271609027fSChander Kashyap #define GATE_TOP_SCLK_DISP1 0x10828 1281609027fSChander Kashyap #define GATE_TOP_SCLK_MAU 0x1083c 1291609027fSChander Kashyap #define GATE_TOP_SCLK_FSYS 0x10840 1301609027fSChander Kashyap #define GATE_TOP_SCLK_PERIC 0x10850 131424b673aSShaik Ameer Basha #define TOP_SPARE2 0x10b08 132c898c6b7SYadwinder Singh Brar #define BPLL_LOCK 0x20010 133c898c6b7SYadwinder Singh Brar #define BPLL_CON0 0x20110 134e867e8faSChanwoo Choi #define SRC_CDREX 0x20200 135e867e8faSChanwoo Choi #define DIV_CDREX0 0x20500 136e867e8faSChanwoo Choi #define DIV_CDREX1 0x20504 137c898c6b7SYadwinder Singh Brar #define KPLL_LOCK 0x28000 138c898c6b7SYadwinder Singh Brar #define KPLL_CON0 0x28100 1391609027fSChander Kashyap #define SRC_KFC 0x28200 1401609027fSChander Kashyap #define DIV_KFC0 0x28500 1411609027fSChander Kashyap 1426520e968SAlim Akhtar /* Exynos5x SoC type */ 1436520e968SAlim Akhtar enum exynos5x_soc { 1446520e968SAlim Akhtar EXYNOS5420, 1456520e968SAlim Akhtar EXYNOS5800, 1466520e968SAlim Akhtar }; 1476520e968SAlim Akhtar 148c898c6b7SYadwinder Singh Brar /* list of PLLs */ 1496520e968SAlim Akhtar enum exynos5x_plls { 150c898c6b7SYadwinder Singh Brar apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 151c898c6b7SYadwinder Singh Brar bpll, kpll, 152c898c6b7SYadwinder Singh Brar nr_plls /* number of PLLs */ 153c898c6b7SYadwinder Singh Brar }; 154c898c6b7SYadwinder Singh Brar 155388c7885STomasz Figa static void __iomem *reg_base; 1566520e968SAlim Akhtar static enum exynos5x_soc exynos5x_soc; 157388c7885STomasz Figa 158388c7885STomasz Figa #ifdef CONFIG_PM_SLEEP 1596520e968SAlim Akhtar static struct samsung_clk_reg_dump *exynos5x_save; 1606520e968SAlim Akhtar static struct samsung_clk_reg_dump *exynos5800_save; 161388c7885STomasz Figa 1621609027fSChander Kashyap /* 1631609027fSChander Kashyap * list of controller registers to be saved and restored during a 1641609027fSChander Kashyap * suspend/resume cycle. 1651609027fSChander Kashyap */ 166ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5x_clk_regs[] __initconst = { 1671609027fSChander Kashyap SRC_CPU, 1681609027fSChander Kashyap DIV_CPU0, 1691609027fSChander Kashyap DIV_CPU1, 1701609027fSChander Kashyap GATE_BUS_CPU, 1711609027fSChander Kashyap GATE_SCLK_CPU, 17277342432SShaik Ameer Basha CLKOUT_CMU_CPU, 17377342432SShaik Ameer Basha EPLL_CON0, 17477342432SShaik Ameer Basha EPLL_CON1, 17577342432SShaik Ameer Basha EPLL_CON2, 17677342432SShaik Ameer Basha RPLL_CON0, 17777342432SShaik Ameer Basha RPLL_CON1, 17877342432SShaik Ameer Basha RPLL_CON2, 1791609027fSChander Kashyap SRC_TOP0, 1801609027fSChander Kashyap SRC_TOP1, 1811609027fSChander Kashyap SRC_TOP2, 1821609027fSChander Kashyap SRC_TOP3, 1831609027fSChander Kashyap SRC_TOP4, 1841609027fSChander Kashyap SRC_TOP5, 1851609027fSChander Kashyap SRC_TOP6, 1861609027fSChander Kashyap SRC_TOP7, 1871609027fSChander Kashyap SRC_DISP10, 1881609027fSChander Kashyap SRC_MAU, 1891609027fSChander Kashyap SRC_FSYS, 1901609027fSChander Kashyap SRC_PERIC0, 1911609027fSChander Kashyap SRC_PERIC1, 1921609027fSChander Kashyap SRC_TOP10, 1931609027fSChander Kashyap SRC_TOP11, 1941609027fSChander Kashyap SRC_TOP12, 195424b673aSShaik Ameer Basha SRC_MASK_TOP2, 19631116a64SShaik Ameer Basha SRC_MASK_TOP7, 1971609027fSChander Kashyap SRC_MASK_DISP10, 1981609027fSChander Kashyap SRC_MASK_FSYS, 1991609027fSChander Kashyap SRC_MASK_PERIC0, 2001609027fSChander Kashyap SRC_MASK_PERIC1, 201e9d52956SVikas Sajjan SRC_MASK_TOP0, 202e9d52956SVikas Sajjan SRC_MASK_TOP1, 203e9d52956SVikas Sajjan SRC_MASK_MAU, 204e9d52956SVikas Sajjan SRC_MASK_ISP, 2053a767b35SShaik Ameer Basha SRC_ISP, 2061609027fSChander Kashyap DIV_TOP0, 2071609027fSChander Kashyap DIV_TOP1, 2081609027fSChander Kashyap DIV_TOP2, 2091609027fSChander Kashyap DIV_DISP10, 2101609027fSChander Kashyap DIV_MAU, 2111609027fSChander Kashyap DIV_FSYS0, 2121609027fSChander Kashyap DIV_FSYS1, 2131609027fSChander Kashyap DIV_FSYS2, 2141609027fSChander Kashyap DIV_PERIC0, 2151609027fSChander Kashyap DIV_PERIC1, 2161609027fSChander Kashyap DIV_PERIC2, 2171609027fSChander Kashyap DIV_PERIC3, 2181609027fSChander Kashyap DIV_PERIC4, 2193a767b35SShaik Ameer Basha SCLK_DIV_ISP0, 2203a767b35SShaik Ameer Basha SCLK_DIV_ISP1, 22102932381SShaik Ameer Basha DIV2_RATIO0, 2221d87db4dSShaik Ameer Basha DIV4_RATIO, 223e9d52956SVikas Sajjan GATE_BUS_DISP1, 2241609027fSChander Kashyap GATE_BUS_TOP, 2250a22c306SShaik Ameer Basha GATE_BUS_GEN, 2261609027fSChander Kashyap GATE_BUS_FSYS0, 2276b5ae463SShaik Ameer Basha GATE_BUS_FSYS2, 2281609027fSChander Kashyap GATE_BUS_PERIC, 2291609027fSChander Kashyap GATE_BUS_PERIC1, 2301609027fSChander Kashyap GATE_BUS_PERIS0, 2311609027fSChander Kashyap GATE_BUS_PERIS1, 2326575fa76SShaik Ameer Basha GATE_BUS_NOC, 2333a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2341609027fSChander Kashyap GATE_IP_GSCL0, 2351609027fSChander Kashyap GATE_IP_GSCL1, 2361609027fSChander Kashyap GATE_IP_MFC, 2371609027fSChander Kashyap GATE_IP_DISP1, 2381609027fSChander Kashyap GATE_IP_G3D, 2391609027fSChander Kashyap GATE_IP_GEN, 2406b5ae463SShaik Ameer Basha GATE_IP_FSYS, 241faec151bSShaik Ameer Basha GATE_IP_PERIC, 2420a22c306SShaik Ameer Basha GATE_IP_PERIS, 2431609027fSChander Kashyap GATE_IP_MSCL, 2441609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 2451609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 2461609027fSChander Kashyap GATE_TOP_SCLK_MAU, 2471609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2481609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 249424b673aSShaik Ameer Basha TOP_SPARE2, 250e867e8faSChanwoo Choi SRC_CDREX, 251e867e8faSChanwoo Choi DIV_CDREX0, 252e867e8faSChanwoo Choi DIV_CDREX1, 2531609027fSChander Kashyap SRC_KFC, 2541609027fSChander Kashyap DIV_KFC0, 2551609027fSChander Kashyap }; 2561609027fSChander Kashyap 257ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5800_clk_regs[] __initconst = { 2586520e968SAlim Akhtar SRC_TOP8, 2596520e968SAlim Akhtar SRC_TOP9, 2606520e968SAlim Akhtar SRC_CAM, 2616520e968SAlim Akhtar SRC_TOP1, 2626520e968SAlim Akhtar DIV_TOP8, 2636520e968SAlim Akhtar DIV_TOP9, 2646520e968SAlim Akhtar DIV_CAM, 2656520e968SAlim Akhtar GATE_IP_CAM, 2666520e968SAlim Akhtar }; 2676520e968SAlim Akhtar 268e9d52956SVikas Sajjan static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 269e9d52956SVikas Sajjan { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 270e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 271e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 272e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 273e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 274e9d52956SVikas Sajjan { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 275e9d52956SVikas Sajjan { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 276e9d52956SVikas Sajjan { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 277e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 278e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 279e9d52956SVikas Sajjan { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 28097372e5aSJavier Martinez Canillas { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 281e9d52956SVikas Sajjan { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 282e9d52956SVikas Sajjan { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 283e9d52956SVikas Sajjan }; 284e9d52956SVikas Sajjan 285388c7885STomasz Figa static int exynos5420_clk_suspend(void) 286388c7885STomasz Figa { 2876520e968SAlim Akhtar samsung_clk_save(reg_base, exynos5x_save, 2886520e968SAlim Akhtar ARRAY_SIZE(exynos5x_clk_regs)); 2896520e968SAlim Akhtar 2906520e968SAlim Akhtar if (exynos5x_soc == EXYNOS5800) 2916520e968SAlim Akhtar samsung_clk_save(reg_base, exynos5800_save, 2926520e968SAlim Akhtar ARRAY_SIZE(exynos5800_clk_regs)); 293388c7885STomasz Figa 294e9d52956SVikas Sajjan samsung_clk_restore(reg_base, exynos5420_set_clksrc, 295e9d52956SVikas Sajjan ARRAY_SIZE(exynos5420_set_clksrc)); 296e9d52956SVikas Sajjan 297388c7885STomasz Figa return 0; 298388c7885STomasz Figa } 299388c7885STomasz Figa 300388c7885STomasz Figa static void exynos5420_clk_resume(void) 301388c7885STomasz Figa { 3026520e968SAlim Akhtar samsung_clk_restore(reg_base, exynos5x_save, 3036520e968SAlim Akhtar ARRAY_SIZE(exynos5x_clk_regs)); 3046520e968SAlim Akhtar 3056520e968SAlim Akhtar if (exynos5x_soc == EXYNOS5800) 3066520e968SAlim Akhtar samsung_clk_restore(reg_base, exynos5800_save, 3076520e968SAlim Akhtar ARRAY_SIZE(exynos5800_clk_regs)); 308388c7885STomasz Figa } 309388c7885STomasz Figa 310388c7885STomasz Figa static struct syscore_ops exynos5420_clk_syscore_ops = { 311388c7885STomasz Figa .suspend = exynos5420_clk_suspend, 312388c7885STomasz Figa .resume = exynos5420_clk_resume, 313388c7885STomasz Figa }; 314388c7885STomasz Figa 315ebd217e1SKrzysztof Kozlowski static void __init exynos5420_clk_sleep_init(void) 316388c7885STomasz Figa { 3176520e968SAlim Akhtar exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs, 3186520e968SAlim Akhtar ARRAY_SIZE(exynos5x_clk_regs)); 3196520e968SAlim Akhtar if (!exynos5x_save) { 320388c7885STomasz Figa pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 321388c7885STomasz Figa __func__); 322388c7885STomasz Figa return; 323388c7885STomasz Figa } 324388c7885STomasz Figa 3256520e968SAlim Akhtar if (exynos5x_soc == EXYNOS5800) { 3266520e968SAlim Akhtar exynos5800_save = 3276520e968SAlim Akhtar samsung_clk_alloc_reg_dump(exynos5800_clk_regs, 3286520e968SAlim Akhtar ARRAY_SIZE(exynos5800_clk_regs)); 3296520e968SAlim Akhtar if (!exynos5800_save) 3306520e968SAlim Akhtar goto err_soc; 3316520e968SAlim Akhtar } 3326520e968SAlim Akhtar 333388c7885STomasz Figa register_syscore_ops(&exynos5420_clk_syscore_ops); 3346520e968SAlim Akhtar return; 3356520e968SAlim Akhtar err_soc: 3366520e968SAlim Akhtar kfree(exynos5x_save); 3376520e968SAlim Akhtar pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 3386520e968SAlim Akhtar __func__); 3396520e968SAlim Akhtar return; 340388c7885STomasz Figa } 341388c7885STomasz Figa #else 342ebd217e1SKrzysztof Kozlowski static void __init exynos5420_clk_sleep_init(void) {} 343388c7885STomasz Figa #endif 344388c7885STomasz Figa 3451609027fSChander Kashyap /* list of all parent clocks */ 346dbd713bbSShaik Ameer Basha PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 347dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 348dbd713bbSShaik Ameer Basha PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 349dbd713bbSShaik Ameer Basha PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 350dbd713bbSShaik Ameer Basha PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 351dbd713bbSShaik Ameer Basha PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 352dbd713bbSShaik Ameer Basha PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 353dbd713bbSShaik Ameer Basha PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 354dbd713bbSShaik Ameer Basha PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 355dbd713bbSShaik Ameer Basha PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 356dbd713bbSShaik Ameer Basha PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 357dbd713bbSShaik Ameer Basha PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 358dbd713bbSShaik Ameer Basha PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 359dbd713bbSShaik Ameer Basha PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 360dbd713bbSShaik Ameer Basha PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 3611609027fSChander Kashyap 362dbd713bbSShaik Ameer Basha PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 363dbd713bbSShaik Ameer Basha "mout_sclk_mpll"}; 364dbd713bbSShaik Ameer Basha PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 365dbd713bbSShaik Ameer Basha "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 366dbd713bbSShaik Ameer Basha "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 367dbd713bbSShaik Ameer Basha PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 368dbd713bbSShaik Ameer Basha PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 369dbd713bbSShaik Ameer Basha PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 3701609027fSChander Kashyap 371424b673aSShaik Ameer Basha PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 372dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 373faec151bSShaik Ameer Basha PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 374b31ca2a0SShaik Ameer Basha PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 3751609027fSChander Kashyap 376dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 3776b5ae463SShaik Ameer Basha PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 3786b5ae463SShaik Ameer Basha PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 379dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 3801609027fSChander Kashyap 381dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 382dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 3836575fa76SShaik Ameer Basha PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 3846575fa76SShaik Ameer Basha PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 3856575fa76SShaik Ameer Basha 3866575fa76SShaik Ameer Basha PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 3876575fa76SShaik Ameer Basha PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 3886575fa76SShaik Ameer Basha PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 3896575fa76SShaik Ameer Basha 3903a767b35SShaik Ameer Basha PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 3913a767b35SShaik Ameer Basha PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 3923a767b35SShaik Ameer Basha 3933a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 3943a767b35SShaik Ameer Basha "mout_sclk_spll"}; 3953a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 3963a767b35SShaik Ameer Basha 3973a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 3983a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 3991609027fSChander Kashyap 400dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 401424b673aSShaik Ameer Basha PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 4021609027fSChander Kashyap 403dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 404dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 4051609027fSChander Kashyap 406dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 407dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 4081609027fSChander Kashyap 409dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 410dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 4111609027fSChander Kashyap 412dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 413dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 4143a767b35SShaik Ameer Basha PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 4151609027fSChander Kashyap 416dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 417dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 4181609027fSChander Kashyap 419dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 420dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 4211609027fSChander Kashyap 422dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 423424b673aSShaik Ameer Basha PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 424dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 425424b673aSShaik Ameer Basha PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 4261609027fSChander Kashyap 427dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 428dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 4291609027fSChander Kashyap 430dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 431dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 4321609027fSChander Kashyap 433dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 434dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 4351609027fSChander Kashyap 436dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 437dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 4381609027fSChander Kashyap 439dbd713bbSShaik Ameer Basha PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 440dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 441dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 442dbd713bbSShaik Ameer Basha PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 443dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 444dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 445dbd713bbSShaik Ameer Basha PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 446dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 447dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 448dbd713bbSShaik Ameer Basha PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 449dbd713bbSShaik Ameer Basha "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 450dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 451dbd713bbSShaik Ameer Basha PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 452dbd713bbSShaik Ameer Basha PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 453dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 454dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 45531116a64SShaik Ameer Basha PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 45631116a64SShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 457e867e8faSChanwoo Choi PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"}; 458e867e8faSChanwoo Choi 4596520e968SAlim Akhtar /* List of parents specific to exynos5800 */ 4606520e968SAlim Akhtar PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 4616520e968SAlim Akhtar PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4626520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4636520e968SAlim Akhtar PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4646520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4656520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 4666520e968SAlim Akhtar PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4676520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4686520e968SAlim Akhtar "mout_epll2" }; 4696520e968SAlim Akhtar PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4706520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll" }; 4716520e968SAlim Akhtar PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 4726520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4736520e968SAlim Akhtar PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4746520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll", 4756520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 476e867e8faSChanwoo Choi PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll", 477e867e8faSChanwoo Choi "mout_sclk_mpll", "ff_dout_spll2", 478e867e8faSChanwoo Choi "mout_sclk_spll", "mout_sclk_epll"}; 4796520e968SAlim Akhtar PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 4806520e968SAlim Akhtar "mout_sclk_mpll", 4816520e968SAlim Akhtar "ff_dout_spll2" }; 4826520e968SAlim Akhtar PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 4836520e968SAlim Akhtar PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 4846520e968SAlim Akhtar PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 4856520e968SAlim Akhtar PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 4866520e968SAlim Akhtar PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 4876520e968SAlim Akhtar PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 4886520e968SAlim Akhtar PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 4896520e968SAlim Akhtar PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 4908a9cf26eSSylwester Nawrocki PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; 4911609027fSChander Kashyap 4921609027fSChander Kashyap /* fixed rate clocks generated outside the soc */ 4936520e968SAlim Akhtar static struct samsung_fixed_rate_clock 4946520e968SAlim Akhtar exynos5x_fixed_rate_ext_clks[] __initdata = { 495728f288dSStephen Boyd FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 4961609027fSChander Kashyap }; 4971609027fSChander Kashyap 4981609027fSChander Kashyap /* fixed rate clocks generated inside the soc */ 499ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { 500728f288dSStephen Boyd FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 501728f288dSStephen Boyd FRATE(0, "sclk_pwi", NULL, 0, 24000000), 502728f288dSStephen Boyd FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 503728f288dSStephen Boyd FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 504728f288dSStephen Boyd FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 5051609027fSChander Kashyap }; 5061609027fSChander Kashyap 507ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 508ad98c64fSKrzysztof Kozlowski exynos5x_fixed_factor_clks[] __initconst = { 509b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 510b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 5111609027fSChander Kashyap }; 5121609027fSChander Kashyap 513ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 514ad98c64fSKrzysztof Kozlowski exynos5800_fixed_factor_clks[] __initconst = { 5156520e968SAlim Akhtar FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 5166520e968SAlim Akhtar FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 5176520e968SAlim Akhtar }; 5186520e968SAlim Akhtar 519ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 5206520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 5216520e968SAlim Akhtar MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 5226520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 5236520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 5246520e968SAlim Akhtar 5256520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 5266520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 5276520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 5286520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 5296520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 5306520e968SAlim Akhtar 5316520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 5326520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 5336520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 5346520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 5356520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 5366520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 5376520e968SAlim Akhtar 538e867e8faSChanwoo Choi MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 539e867e8faSChanwoo Choi mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), 540599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, 541599cebeaSSylwester Nawrocki SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), 5426520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 5436520e968SAlim Akhtar MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 5446520e968SAlim Akhtar 5456520e968SAlim Akhtar MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 5466520e968SAlim Akhtar MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 5476520e968SAlim Akhtar MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 5486520e968SAlim Akhtar MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 5496520e968SAlim Akhtar 550599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, 551599cebeaSSylwester Nawrocki SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0), 5526520e968SAlim Akhtar MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 5536520e968SAlim Akhtar SRC_TOP9, 16, 1), 5546520e968SAlim Akhtar MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 5556520e968SAlim Akhtar SRC_TOP9, 20, 1), 5566520e968SAlim Akhtar MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 5576520e968SAlim Akhtar SRC_TOP9, 24, 1), 5586520e968SAlim Akhtar MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 5596520e968SAlim Akhtar SRC_TOP9, 28, 1), 5606520e968SAlim Akhtar 5616520e968SAlim Akhtar MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 5626520e968SAlim Akhtar MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 5636520e968SAlim Akhtar SRC_TOP13, 20, 1), 5646520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 5656520e968SAlim Akhtar SRC_TOP13, 24, 1), 5666520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 5676520e968SAlim Akhtar SRC_TOP13, 28, 1), 5686520e968SAlim Akhtar 5696520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 5706520e968SAlim Akhtar }; 5716520e968SAlim Akhtar 572ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { 57381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 57481fed6e3SChanwoo Choi "mout_aclk400_wcore", DIV_TOP0, 16, 3), 5756520e968SAlim Akhtar DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 5766520e968SAlim Akhtar DIV_TOP8, 16, 3), 5776520e968SAlim Akhtar DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 5786520e968SAlim Akhtar DIV_TOP8, 20, 3), 5796520e968SAlim Akhtar DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 5806520e968SAlim Akhtar DIV_TOP8, 24, 3), 5816520e968SAlim Akhtar DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 5826520e968SAlim Akhtar DIV_TOP8, 28, 3), 5836520e968SAlim Akhtar 5846520e968SAlim Akhtar DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 5856520e968SAlim Akhtar DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 5866520e968SAlim Akhtar }; 5876520e968SAlim Akhtar 588ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 5896520e968SAlim Akhtar GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 5906520e968SAlim Akhtar GATE_BUS_TOP, 24, 0, 0), 5916520e968SAlim Akhtar GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 592318fa46cSMarek Szyprowski GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), 59341097f25SSylwester Nawrocki GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", 594599cebeaSSylwester Nawrocki SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 5956520e968SAlim Akhtar }; 5966520e968SAlim Akhtar 597ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 5986520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 5996520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 6006520e968SAlim Akhtar TOP_SPARE2, 4, 1), 6016520e968SAlim Akhtar 6026520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 60336ba4824SMarek Szyprowski MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2), 6046520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 6056520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 6066520e968SAlim Akhtar 6076520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 6086520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group4_p, 6096520e968SAlim Akhtar SRC_TOP1, 4, 2), 6106520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 6116520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 6126520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 6136520e968SAlim Akhtar 6146520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 6156520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 6166520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 6176520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 6186520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 6196520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 6206520e968SAlim Akhtar 621e867e8faSChanwoo Choi MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 622e867e8faSChanwoo Choi mout_group5_5800_p, SRC_TOP7, 16, 2), 6236520e968SAlim Akhtar MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2), 6246520e968SAlim Akhtar 6256520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 6266520e968SAlim Akhtar }; 6276520e968SAlim Akhtar 628ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 62981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 63081fed6e3SChanwoo Choi "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 6316520e968SAlim Akhtar }; 6326520e968SAlim Akhtar 63341097f25SSylwester Nawrocki static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { 63441097f25SSylwester Nawrocki GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 635599cebeaSSylwester Nawrocki SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 63641097f25SSylwester Nawrocki }; 63741097f25SSylwester Nawrocki 638ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 639b31ca2a0SShaik Ameer Basha MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 640b31ca2a0SShaik Ameer Basha SRC_TOP7, 4, 1), 641dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 642dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 64331116a64SShaik Ameer Basha 644bee4f87fSThomas Abraham MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 645bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 646dbd713bbSShaik Ameer Basha MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 647bee4f87fSThomas Abraham MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 648bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 649dbd713bbSShaik Ameer Basha MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 6501609027fSChander Kashyap 651dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 652dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 6536b5ae463SShaik Ameer Basha MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 654dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 6551609027fSChander Kashyap 656dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 657dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 6581609027fSChander Kashyap 659dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 6601609027fSChander Kashyap 6613a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 6623a767b35SShaik Ameer Basha SRC_TOP3, 0, 1), 663dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 6641609027fSChander Kashyap SRC_TOP3, 4, 1), 66588560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 66688560100SJavier Martinez Canillas mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 667dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 6681609027fSChander Kashyap SRC_TOP3, 12, 1), 6696575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 6706575fa76SShaik Ameer Basha SRC_TOP3, 16, 1), 6716575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 6726575fa76SShaik Ameer Basha SRC_TOP3, 20, 1), 6736b5ae463SShaik Ameer Basha MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 6746b5ae463SShaik Ameer Basha SRC_TOP3, 24, 1), 675dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 6761609027fSChander Kashyap SRC_TOP3, 28, 1), 6771609027fSChander Kashyap 678dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 6791609027fSChander Kashyap SRC_TOP4, 0, 1), 6803a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 6813a767b35SShaik Ameer Basha SRC_TOP4, 4, 1), 682faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 683faec151bSShaik Ameer Basha SRC_TOP4, 8, 1), 6843a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 6853a767b35SShaik Ameer Basha SRC_TOP4, 12, 1), 6863a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 6873a767b35SShaik Ameer Basha SRC_TOP4, 16, 1), 688dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 689dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 690c0fb262bSArun Kumar K MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 691c0fb262bSArun Kumar K SRC_TOP4, 28, 1), 6921609027fSChander Kashyap 69388560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 69488560100SJavier Martinez Canillas mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 695faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 696faec151bSShaik Ameer Basha SRC_TOP5, 4, 1), 6973fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 6983fac5941SShaik Ameer Basha SRC_TOP5, 8, 1), 6993fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 7003fac5941SShaik Ameer Basha SRC_TOP5, 12, 1), 7013fac5941SShaik Ameer Basha MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 7023fac5941SShaik Ameer Basha SRC_TOP5, 16, 1), 703dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 7041609027fSChander Kashyap SRC_TOP5, 20, 1), 70588560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 70688560100SJavier Martinez Canillas mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 707c0feb268SMarek Szyprowski MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 708c0feb268SMarek Szyprowski mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 7091609027fSChander Kashyap 710dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 711dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 712dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 713dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 714dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 715599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, 716599cebeaSSylwester Nawrocki CLK_SET_RATE_PARENT, 0), 717dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 718dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 7191609027fSChander Kashyap 7203a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 7213a767b35SShaik Ameer Basha SRC_TOP10, 0, 1), 722dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 723dbd713bbSShaik Ameer Basha SRC_TOP10, 4, 1), 72488560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 72588560100SJavier Martinez Canillas SRC_TOP10, 8, 1), 726dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 7271609027fSChander Kashyap SRC_TOP10, 12, 1), 7286575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 7296575fa76SShaik Ameer Basha SRC_TOP10, 16, 1), 7306575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 7316575fa76SShaik Ameer Basha SRC_TOP10, 20, 1), 7326b5ae463SShaik Ameer Basha MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 7336b5ae463SShaik Ameer Basha SRC_TOP10, 24, 1), 734dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 735dbd713bbSShaik Ameer Basha SRC_TOP10, 28, 1), 7363a767b35SShaik Ameer Basha 737dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 7381609027fSChander Kashyap SRC_TOP11, 0, 1), 7393a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 7403a767b35SShaik Ameer Basha SRC_TOP11, 4, 1), 741dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 7423a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 7433a767b35SShaik Ameer Basha SRC_TOP11, 12, 1), 744dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 745dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 746c0fb262bSArun Kumar K MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 747c0fb262bSArun Kumar K SRC_TOP11, 28, 1), 7481609027fSChander Kashyap 74988560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 75088560100SJavier Martinez Canillas mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 751dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 752dbd713bbSShaik Ameer Basha SRC_TOP12, 8, 1), 753dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 754dbd713bbSShaik Ameer Basha SRC_TOP12, 12, 1), 755dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 756dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 757dbd713bbSShaik Ameer Basha SRC_TOP12, 20, 1), 75888560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 75988560100SJavier Martinez Canillas mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 760c0feb268SMarek Szyprowski MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 761c0feb268SMarek Szyprowski mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 7621609027fSChander Kashyap 7631609027fSChander Kashyap /* DISP1 Block */ 764dbd713bbSShaik Ameer Basha MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 765dbd713bbSShaik Ameer Basha MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 766dbd713bbSShaik Ameer Basha MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 767dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 768424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 7696575fa76SShaik Ameer Basha 770424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 7711609027fSChander Kashyap 772e867e8faSChanwoo Choi /* CDREX block */ 773e867e8faSChanwoo Choi MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p, 774e867e8faSChanwoo Choi SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0), 775e867e8faSChanwoo Choi MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1, 776e867e8faSChanwoo Choi CLK_SET_RATE_PARENT, 0), 777e867e8faSChanwoo Choi 7781609027fSChander Kashyap /* MAU Block */ 77931116a64SShaik Ameer Basha MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 7801609027fSChander Kashyap 7811609027fSChander Kashyap /* FSYS Block */ 782dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 783dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 784dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 785dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 786dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 787dbd713bbSShaik Ameer Basha MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 7886b5ae463SShaik Ameer Basha MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 7891609027fSChander Kashyap 7901609027fSChander Kashyap /* PERIC Block */ 791dbd713bbSShaik Ameer Basha MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 792dbd713bbSShaik Ameer Basha MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 793dbd713bbSShaik Ameer Basha MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 794dbd713bbSShaik Ameer Basha MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 795dbd713bbSShaik Ameer Basha MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 796dbd713bbSShaik Ameer Basha MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 797dbd713bbSShaik Ameer Basha MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 798dbd713bbSShaik Ameer Basha MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 799dbd713bbSShaik Ameer Basha MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 800dbd713bbSShaik Ameer Basha MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 801dbd713bbSShaik Ameer Basha MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 802dbd713bbSShaik Ameer Basha MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 8033a767b35SShaik Ameer Basha 8043a767b35SShaik Ameer Basha /* ISP Block */ 8053a767b35SShaik Ameer Basha MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 8063a767b35SShaik Ameer Basha MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 8073a767b35SShaik Ameer Basha MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 8083a767b35SShaik Ameer Basha MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 8093a767b35SShaik Ameer Basha MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 8101609027fSChander Kashyap }; 8111609027fSChander Kashyap 812ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 813cba9d2faSAndrzej Hajda DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 814cba9d2faSAndrzej Hajda DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 815cba9d2faSAndrzej Hajda DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 816dbd713bbSShaik Ameer Basha DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 817cba9d2faSAndrzej Hajda DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 8181609027fSChander Kashyap 81981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 82081fed6e3SChanwoo Choi DIV_TOP0, 0, 3), 82181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 82281fed6e3SChanwoo Choi DIV_TOP0, 4, 3), 82381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 82481fed6e3SChanwoo Choi DIV_TOP0, 8, 3), 82581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 82681fed6e3SChanwoo Choi DIV_TOP0, 12, 3), 82781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 82881fed6e3SChanwoo Choi DIV_TOP0, 20, 3), 82981fed6e3SChanwoo Choi DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 83081fed6e3SChanwoo Choi DIV_TOP0, 24, 3), 83181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 83281fed6e3SChanwoo Choi DIV_TOP0, 28, 3), 83381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 83481fed6e3SChanwoo Choi "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 83581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 83681fed6e3SChanwoo Choi "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 83781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 83881fed6e3SChanwoo Choi DIV_TOP1, 8, 6), 83981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 84081fed6e3SChanwoo Choi "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 84181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 84281fed6e3SChanwoo Choi DIV_TOP1, 20, 3), 84381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 84481fed6e3SChanwoo Choi DIV_TOP1, 24, 3), 84581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 84681fed6e3SChanwoo Choi DIV_TOP1, 28, 3), 8471609027fSChander Kashyap 84881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 84981fed6e3SChanwoo Choi DIV_TOP2, 8, 3), 85081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 85181fed6e3SChanwoo Choi DIV_TOP2, 12, 3), 85281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 85381fed6e3SChanwoo Choi 16, 3), 85481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 85581fed6e3SChanwoo Choi DIV_TOP2, 20, 3), 85681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 85781fed6e3SChanwoo Choi "mout_aclk300_disp1", DIV_TOP2, 24, 3), 85881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 85981fed6e3SChanwoo Choi DIV_TOP2, 28, 3), 8601609027fSChander Kashyap 8611609027fSChander Kashyap /* DISP1 Block */ 862424b673aSShaik Ameer Basha DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 863cba9d2faSAndrzej Hajda DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 864cba9d2faSAndrzej Hajda DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 865cba9d2faSAndrzej Hajda DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 866424b673aSShaik Ameer Basha DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 86781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 86881fed6e3SChanwoo Choi "mout_aclk400_disp1", DIV_TOP2, 4, 3), 8691609027fSChander Kashyap 870e867e8faSChanwoo Choi /* CDREX Block */ 871e867e8faSChanwoo Choi DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", 872e867e8faSChanwoo Choi DIV_CDREX0, 28, 3), 873e867e8faSChanwoo Choi DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", 874e867e8faSChanwoo Choi DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), 875e867e8faSChanwoo Choi DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", 876e867e8faSChanwoo Choi DIV_CDREX0, 16, 3), 877e867e8faSChanwoo Choi DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", 878e867e8faSChanwoo Choi DIV_CDREX0, 8, 3), 879e867e8faSChanwoo Choi DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", 880e867e8faSChanwoo Choi DIV_CDREX0, 3, 5), 881e867e8faSChanwoo Choi 882e867e8faSChanwoo Choi DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", 883e867e8faSChanwoo Choi DIV_CDREX1, 8, 3), 884e867e8faSChanwoo Choi 8851609027fSChander Kashyap /* Audio Block */ 886cba9d2faSAndrzej Hajda DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 887cba9d2faSAndrzej Hajda DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 8881609027fSChander Kashyap 8891609027fSChander Kashyap /* USB3.0 */ 890cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 891cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 892cba9d2faSAndrzej Hajda DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 893cba9d2faSAndrzej Hajda DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 8941609027fSChander Kashyap 8951609027fSChander Kashyap /* MMC */ 896cba9d2faSAndrzej Hajda DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 897cba9d2faSAndrzej Hajda DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 898cba9d2faSAndrzej Hajda DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 8991609027fSChander Kashyap 900cba9d2faSAndrzej Hajda DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 9016b5ae463SShaik Ameer Basha DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 9021609027fSChander Kashyap 9031609027fSChander Kashyap /* UART and PWM */ 904cba9d2faSAndrzej Hajda DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 905cba9d2faSAndrzej Hajda DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 906cba9d2faSAndrzej Hajda DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 907cba9d2faSAndrzej Hajda DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 908cba9d2faSAndrzej Hajda DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 9091609027fSChander Kashyap 9101609027fSChander Kashyap /* SPI */ 911cba9d2faSAndrzej Hajda DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 912cba9d2faSAndrzej Hajda DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 913cba9d2faSAndrzej Hajda DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 9141609027fSChander Kashyap 9151d87db4dSShaik Ameer Basha /* Mfc Block */ 9161d87db4dSShaik Ameer Basha DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 9171d87db4dSShaik Ameer Basha 9181609027fSChander Kashyap /* PCM */ 919cba9d2faSAndrzej Hajda DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 920cba9d2faSAndrzej Hajda DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 9211609027fSChander Kashyap 9221609027fSChander Kashyap /* Audio - I2S */ 923cba9d2faSAndrzej Hajda DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 924cba9d2faSAndrzej Hajda DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 925cba9d2faSAndrzej Hajda DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 926cba9d2faSAndrzej Hajda DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 927cba9d2faSAndrzej Hajda DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 9281609027fSChander Kashyap 9291609027fSChander Kashyap /* SPI Pre-Ratio */ 930faec151bSShaik Ameer Basha DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 931faec151bSShaik Ameer Basha DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 932faec151bSShaik Ameer Basha DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 9333a767b35SShaik Ameer Basha 93402932381SShaik Ameer Basha /* GSCL Block */ 93502932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 93602932381SShaik Ameer Basha DIV2_RATIO0, 4, 2), 93702932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 93802932381SShaik Ameer Basha 9394549d93dSShaik Ameer Basha /* MSCL Block */ 9404549d93dSShaik Ameer Basha DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 9414549d93dSShaik Ameer Basha 9420a22c306SShaik Ameer Basha /* PSGEN */ 9430a22c306SShaik Ameer Basha DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 9440a22c306SShaik Ameer Basha DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 9450a22c306SShaik Ameer Basha 9463a767b35SShaik Ameer Basha /* ISP Block */ 9473a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 9483a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 9493a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 9503a767b35SShaik Ameer Basha DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 9513a767b35SShaik Ameer Basha DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 9523a767b35SShaik Ameer Basha DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 9533a767b35SShaik Ameer Basha DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 9543a767b35SShaik Ameer Basha DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 9553a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 9563a767b35SShaik Ameer Basha DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 9573a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 9581609027fSChander Kashyap }; 9591609027fSChander Kashyap 960ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 9615b73721bSNaveen Krishna Chatradhi /* G2D */ 9623fac5941SShaik Ameer Basha GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 9635b73721bSNaveen Krishna Chatradhi GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 9643fac5941SShaik Ameer Basha GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 9653fac5941SShaik Ameer Basha GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 9663fac5941SShaik Ameer Basha GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 9675b73721bSNaveen Krishna Chatradhi 9681609027fSChander Kashyap GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 969318fa46cSMarek Szyprowski GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), 9701609027fSChander Kashyap GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 9711609027fSChander Kashyap GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 9721609027fSChander Kashyap 9731609027fSChander Kashyap GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 9741609027fSChander Kashyap GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 9751609027fSChander Kashyap GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 976318fa46cSMarek Szyprowski GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), 9771609027fSChander Kashyap GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 9781609027fSChander Kashyap GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 9793a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 9803a767b35SShaik Ameer Basha GATE_BUS_TOP, 5, 0, 0), 9811609027fSChander Kashyap GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 982318fa46cSMarek Szyprowski GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), 9831609027fSChander Kashyap GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 9841609027fSChander Kashyap GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 9853a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 9863a767b35SShaik Ameer Basha GATE_BUS_TOP, 8, 0, 0), 987b31ca2a0SShaik Ameer Basha GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 9881609027fSChander Kashyap GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 989faec151bSShaik Ameer Basha GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 9901609027fSChander Kashyap GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 9913a767b35SShaik Ameer Basha GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 9923a767b35SShaik Ameer Basha GATE_BUS_TOP, 13, 0, 0), 9931609027fSChander Kashyap GATE(0, "aclk166", "mout_user_aclk166", 9941609027fSChander Kashyap GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 99534cba900SJavier Martinez Canillas GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", 996318fa46cSMarek Szyprowski GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), 9973a767b35SShaik Ameer Basha GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 9983a767b35SShaik Ameer Basha GATE_BUS_TOP, 16, 0, 0), 99902932381SShaik Ameer Basha GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 1000c07c1a0fSAndrzej Pietrasiewicz GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), 1001424b673aSShaik Ameer Basha GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 1002318fa46cSMarek Szyprowski GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), 1003b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 1004b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 28, 0, 0), 1005b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 1006b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 29, 0, 0), 1007424b673aSShaik Ameer Basha 1008424b673aSShaik Ameer Basha GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 1009318fa46cSMarek Szyprowski SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), 10101609027fSChander Kashyap 10111609027fSChander Kashyap /* sclk */ 1012cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 10131609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 1014cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 10151609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 1016cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 10171609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 1018cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 10191609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 1020faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 10211609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 1022faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 10231609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 1024faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 10251609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 1026cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 10271609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 1028cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 10291609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1030cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 10311609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 1032cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 10331609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 1034cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 10351609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 1036cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 10371609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 10381609027fSChander Kashyap 1039cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 10401609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 1041cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 10421609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 1043cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 10441609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 1045cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 10461609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 1047cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 10481609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 1049cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 10501609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 1051cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 10521609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 10531609027fSChander Kashyap 10541609027fSChander Kashyap /* Display */ 1055cba9d2faSAndrzej Hajda GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 10561609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 1057cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 10581609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 1059cba9d2faSAndrzej Hajda GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 1060424b673aSShaik Ameer Basha GATE_TOP_SCLK_DISP1, 9, 0, 0), 1061cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 10621609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 1063cba9d2faSAndrzej Hajda GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 10641609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 10651609027fSChander Kashyap 10661609027fSChander Kashyap /* Maudio Block */ 1067cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 10681609027fSChander Kashyap GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1069cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 10701609027fSChander Kashyap GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 10716b5ae463SShaik Ameer Basha 10726b5ae463SShaik Ameer Basha /* FSYS Block */ 1073cba9d2faSAndrzej Hajda GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1074cba9d2faSAndrzej Hajda GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1075cba9d2faSAndrzej Hajda GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1076cba9d2faSAndrzej Hajda GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 10776b5ae463SShaik Ameer Basha GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 10786b5ae463SShaik Ameer Basha GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 10796b5ae463SShaik Ameer Basha GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 10806b5ae463SShaik Ameer Basha GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1081cba9d2faSAndrzej Hajda GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 10826b5ae463SShaik Ameer Basha GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 10836b5ae463SShaik Ameer Basha GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 10846b5ae463SShaik Ameer Basha GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 10856b5ae463SShaik Ameer Basha GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 10866b5ae463SShaik Ameer Basha GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 10876b5ae463SShaik Ameer Basha SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 10881609027fSChander Kashyap 1089faec151bSShaik Ameer Basha /* PERIC Block */ 109044ff0254SDoug Anderson GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 109144ff0254SDoug Anderson GATE_IP_PERIC, 0, 0, 0), 109244ff0254SDoug Anderson GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 109344ff0254SDoug Anderson GATE_IP_PERIC, 1, 0, 0), 109444ff0254SDoug Anderson GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 109544ff0254SDoug Anderson GATE_IP_PERIC, 2, 0, 0), 109644ff0254SDoug Anderson GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 109744ff0254SDoug Anderson GATE_IP_PERIC, 3, 0, 0), 109844ff0254SDoug Anderson GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 109944ff0254SDoug Anderson GATE_IP_PERIC, 6, 0, 0), 110044ff0254SDoug Anderson GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 110144ff0254SDoug Anderson GATE_IP_PERIC, 7, 0, 0), 110244ff0254SDoug Anderson GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 110344ff0254SDoug Anderson GATE_IP_PERIC, 8, 0, 0), 110444ff0254SDoug Anderson GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 110544ff0254SDoug Anderson GATE_IP_PERIC, 9, 0, 0), 110644ff0254SDoug Anderson GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 110744ff0254SDoug Anderson GATE_IP_PERIC, 10, 0, 0), 110844ff0254SDoug Anderson GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 110944ff0254SDoug Anderson GATE_IP_PERIC, 11, 0, 0), 111044ff0254SDoug Anderson GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 111144ff0254SDoug Anderson GATE_IP_PERIC, 12, 0, 0), 111244ff0254SDoug Anderson GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 111344ff0254SDoug Anderson GATE_IP_PERIC, 13, 0, 0), 111444ff0254SDoug Anderson GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 111544ff0254SDoug Anderson GATE_IP_PERIC, 14, 0, 0), 111644ff0254SDoug Anderson GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 111744ff0254SDoug Anderson GATE_IP_PERIC, 15, 0, 0), 111844ff0254SDoug Anderson GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 111944ff0254SDoug Anderson GATE_IP_PERIC, 16, 0, 0), 112044ff0254SDoug Anderson GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 112144ff0254SDoug Anderson GATE_IP_PERIC, 17, 0, 0), 112244ff0254SDoug Anderson GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 112344ff0254SDoug Anderson GATE_IP_PERIC, 18, 0, 0), 112444ff0254SDoug Anderson GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 112544ff0254SDoug Anderson GATE_IP_PERIC, 20, 0, 0), 112644ff0254SDoug Anderson GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 112744ff0254SDoug Anderson GATE_IP_PERIC, 21, 0, 0), 112844ff0254SDoug Anderson GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 112944ff0254SDoug Anderson GATE_IP_PERIC, 22, 0, 0), 113044ff0254SDoug Anderson GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 113144ff0254SDoug Anderson GATE_IP_PERIC, 23, 0, 0), 113244ff0254SDoug Anderson GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 113344ff0254SDoug Anderson GATE_IP_PERIC, 24, 0, 0), 113444ff0254SDoug Anderson GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 113544ff0254SDoug Anderson GATE_IP_PERIC, 26, 0, 0), 113644ff0254SDoug Anderson GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 113744ff0254SDoug Anderson GATE_IP_PERIC, 28, 0, 0), 113844ff0254SDoug Anderson GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 113944ff0254SDoug Anderson GATE_IP_PERIC, 30, 0, 0), 114044ff0254SDoug Anderson GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 114144ff0254SDoug Anderson GATE_IP_PERIC, 31, 0, 0), 11421609027fSChander Kashyap 114344ff0254SDoug Anderson GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 114444ff0254SDoug Anderson GATE_BUS_PERIC, 22, 0, 0), 11451609027fSChander Kashyap 11460a22c306SShaik Ameer Basha /* PERIS Block */ 1147cba9d2faSAndrzej Hajda GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 11480a22c306SShaik Ameer Basha GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1149cba9d2faSAndrzej Hajda GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 11500a22c306SShaik Ameer Basha GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 11510a22c306SShaik Ameer Basha GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 11520a22c306SShaik Ameer Basha GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 11530a22c306SShaik Ameer Basha GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 11540a22c306SShaik Ameer Basha GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 11550a22c306SShaik Ameer Basha GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 11560a22c306SShaik Ameer Basha GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 11570a22c306SShaik Ameer Basha GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 11580a22c306SShaik Ameer Basha GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 11590a22c306SShaik Ameer Basha GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 11600a22c306SShaik Ameer Basha GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 11610a22c306SShaik Ameer Basha GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 11620a22c306SShaik Ameer Basha GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 11630a22c306SShaik Ameer Basha GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 11640a22c306SShaik Ameer Basha GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 11650a22c306SShaik Ameer Basha GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 11660a22c306SShaik Ameer Basha GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 11671609027fSChander Kashyap 1168cba9d2faSAndrzej Hajda GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 11690a22c306SShaik Ameer Basha 11700a22c306SShaik Ameer Basha /* GEN Block */ 11710a22c306SShaik Ameer Basha GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 11720a22c306SShaik Ameer Basha GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 11730a22c306SShaik Ameer Basha GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 11740a22c306SShaik Ameer Basha GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 11750a22c306SShaik Ameer Basha GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 11760a22c306SShaik Ameer Basha GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 11770a22c306SShaik Ameer Basha GATE_IP_GEN, 6, 0, 0), 11780a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 11790a22c306SShaik Ameer Basha GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 11800a22c306SShaik Ameer Basha GATE_IP_GEN, 9, 0, 0), 11810a22c306SShaik Ameer Basha 11820a22c306SShaik Ameer Basha /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 11830a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 11840a22c306SShaik Ameer Basha GATE_BUS_GEN, 28, 0, 0), 11850a22c306SShaik Ameer Basha GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 11861609027fSChander Kashyap 118702932381SShaik Ameer Basha /* GSCL Block */ 118802932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 118902932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 6, 0, 0), 119002932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 119102932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 7, 0, 0), 119202932381SShaik Ameer Basha 1193cba9d2faSAndrzej Hajda GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1194cba9d2faSAndrzej Hajda GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 119502932381SShaik Ameer Basha GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 119602932381SShaik Ameer Basha GATE_IP_GSCL0, 4, 0, 0), 119702932381SShaik Ameer Basha GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 119802932381SShaik Ameer Basha GATE_IP_GSCL0, 5, 0, 0), 119902932381SShaik Ameer Basha GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 120002932381SShaik Ameer Basha GATE_IP_GSCL0, 6, 0, 0), 12011609027fSChander Kashyap 120202932381SShaik Ameer Basha GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 120302932381SShaik Ameer Basha GATE_IP_GSCL1, 2, 0, 0), 120402932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 12051609027fSChander Kashyap GATE_IP_GSCL1, 3, 0, 0), 120602932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 12071609027fSChander Kashyap GATE_IP_GSCL1, 4, 0, 0), 120802932381SShaik Ameer Basha GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 120902932381SShaik Ameer Basha GATE_IP_GSCL1, 6, 0, 0), 121002932381SShaik Ameer Basha GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 121102932381SShaik Ameer Basha GATE_IP_GSCL1, 7, 0, 0), 121202932381SShaik Ameer Basha GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 121302932381SShaik Ameer Basha GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 121402932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 12151609027fSChander Kashyap GATE_IP_GSCL1, 16, 0, 0), 1216cba9d2faSAndrzej Hajda GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 12171609027fSChander Kashyap GATE_IP_GSCL1, 17, 0, 0), 12181609027fSChander Kashyap 121902932381SShaik Ameer Basha /* MSCL Block */ 122002932381SShaik Ameer Basha GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 122102932381SShaik Ameer Basha GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 122202932381SShaik Ameer Basha GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 12234549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 122402932381SShaik Ameer Basha GATE_IP_MSCL, 8, 0, 0), 12254549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 122602932381SShaik Ameer Basha GATE_IP_MSCL, 9, 0, 0), 12274549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 122802932381SShaik Ameer Basha GATE_IP_MSCL, 10, 0, 0), 122902932381SShaik Ameer Basha 1230cba9d2faSAndrzej Hajda GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1231cba9d2faSAndrzej Hajda GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1232cba9d2faSAndrzej Hajda GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1233424b673aSShaik Ameer Basha GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1234cba9d2faSAndrzej Hajda GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1235424b673aSShaik Ameer Basha GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1236424b673aSShaik Ameer Basha GATE_IP_DISP1, 7, 0, 0), 1237424b673aSShaik Ameer Basha GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1238424b673aSShaik Ameer Basha GATE_IP_DISP1, 8, 0, 0), 1239424b673aSShaik Ameer Basha GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1240424b673aSShaik Ameer Basha GATE_IP_DISP1, 9, 0, 0), 12411609027fSChander Kashyap 12423a767b35SShaik Ameer Basha /* ISP */ 12433a767b35SShaik Ameer Basha GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 12443a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 12453a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 12463a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 12473a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 12483a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 12493a767b35SShaik Ameer Basha GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 12503a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 12513a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 12523a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 12533a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 12543a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 12553a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 12563a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 12573a767b35SShaik Ameer Basha 1258cba9d2faSAndrzej Hajda GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 12591d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 12601d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 12611609027fSChander Kashyap 12623fac5941SShaik Ameer Basha GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 12631609027fSChander Kashyap }; 12641609027fSChander Kashyap 1265ebd217e1SKrzysztof Kozlowski static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { 1266ca5b4029SThomas Abraham PLL_35XX_RATE(2000000000, 250, 3, 0), 1267ca5b4029SThomas Abraham PLL_35XX_RATE(1900000000, 475, 6, 0), 1268ca5b4029SThomas Abraham PLL_35XX_RATE(1800000000, 225, 3, 0), 1269ca5b4029SThomas Abraham PLL_35XX_RATE(1700000000, 425, 6, 0), 1270ca5b4029SThomas Abraham PLL_35XX_RATE(1600000000, 200, 3, 0), 1271ca5b4029SThomas Abraham PLL_35XX_RATE(1500000000, 250, 4, 0), 1272ca5b4029SThomas Abraham PLL_35XX_RATE(1400000000, 175, 3, 0), 1273ca5b4029SThomas Abraham PLL_35XX_RATE(1300000000, 325, 6, 0), 1274ca5b4029SThomas Abraham PLL_35XX_RATE(1200000000, 200, 2, 1), 1275ca5b4029SThomas Abraham PLL_35XX_RATE(1100000000, 275, 3, 1), 1276ca5b4029SThomas Abraham PLL_35XX_RATE(1000000000, 250, 3, 1), 1277ca5b4029SThomas Abraham PLL_35XX_RATE(900000000, 150, 2, 1), 1278ca5b4029SThomas Abraham PLL_35XX_RATE(800000000, 200, 3, 1), 1279ca5b4029SThomas Abraham PLL_35XX_RATE(700000000, 175, 3, 1), 1280ca5b4029SThomas Abraham PLL_35XX_RATE(600000000, 200, 2, 2), 1281ca5b4029SThomas Abraham PLL_35XX_RATE(500000000, 250, 3, 2), 1282ca5b4029SThomas Abraham PLL_35XX_RATE(400000000, 200, 3, 2), 1283ca5b4029SThomas Abraham PLL_35XX_RATE(300000000, 200, 2, 3), 1284ca5b4029SThomas Abraham PLL_35XX_RATE(200000000, 200, 3, 3), 1285ca5b4029SThomas Abraham }; 1286ca5b4029SThomas Abraham 12879842452aSSylwester Nawrocki static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 12889842452aSSylwester Nawrocki PLL_36XX_RATE(600000000U, 100, 2, 1, 0), 12899842452aSSylwester Nawrocki PLL_36XX_RATE(400000000U, 200, 3, 2, 0), 12905b30850bSSylwester Nawrocki PLL_36XX_RATE(393216003U, 197, 3, 2, -25690), 12915b30850bSSylwester Nawrocki PLL_36XX_RATE(361267218U, 301, 5, 2, 3671), 12929842452aSSylwester Nawrocki PLL_36XX_RATE(200000000U, 200, 3, 3, 0), 12935b30850bSSylwester Nawrocki PLL_36XX_RATE(196608001U, 197, 3, 3, -25690), 12945b30850bSSylwester Nawrocki PLL_36XX_RATE(180633609U, 301, 5, 3, 3671), 12955b30850bSSylwester Nawrocki PLL_36XX_RATE(131072006U, 131, 3, 3, 4719), 12969842452aSSylwester Nawrocki PLL_36XX_RATE(100000000U, 200, 3, 4, 0), 12975b30850bSSylwester Nawrocki PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719), 12985b30850bSSylwester Nawrocki PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690), 12995b30850bSSylwester Nawrocki PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719), 13009842452aSSylwester Nawrocki }; 13019842452aSSylwester Nawrocki 13026520e968SAlim Akhtar static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1303cba9d2faSAndrzej Hajda [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 13043ff6e0d8SYadwinder Singh Brar APLL_CON0, NULL), 1305cba9d2faSAndrzej Hajda [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1306cdf64eeeSChander Kashyap CPLL_CON0, NULL), 1307cba9d2faSAndrzej Hajda [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 13083ff6e0d8SYadwinder Singh Brar DPLL_CON0, NULL), 13099842452aSSylwester Nawrocki [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 13103ff6e0d8SYadwinder Singh Brar EPLL_CON0, NULL), 1311cba9d2faSAndrzej Hajda [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 13123ff6e0d8SYadwinder Singh Brar RPLL_CON0, NULL), 1313cba9d2faSAndrzej Hajda [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 13143ff6e0d8SYadwinder Singh Brar IPLL_CON0, NULL), 1315cba9d2faSAndrzej Hajda [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 13163ff6e0d8SYadwinder Singh Brar SPLL_CON0, NULL), 1317cba9d2faSAndrzej Hajda [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 13183ff6e0d8SYadwinder Singh Brar VPLL_CON0, NULL), 1319cba9d2faSAndrzej Hajda [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 13203ff6e0d8SYadwinder Singh Brar MPLL_CON0, NULL), 1321cba9d2faSAndrzej Hajda [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 13223ff6e0d8SYadwinder Singh Brar BPLL_CON0, NULL), 1323cba9d2faSAndrzej Hajda [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 13243ff6e0d8SYadwinder Singh Brar KPLL_CON0, NULL), 1325c898c6b7SYadwinder Singh Brar }; 1326c898c6b7SYadwinder Singh Brar 1327bee4f87fSThomas Abraham #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1328bee4f87fSThomas Abraham ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1329bee4f87fSThomas Abraham ((cpud) << 4))) 1330bee4f87fSThomas Abraham 1331bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1332bee4f87fSThomas Abraham { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1333bee4f87fSThomas Abraham { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1334bee4f87fSThomas Abraham { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1335bee4f87fSThomas Abraham { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1336bee4f87fSThomas Abraham { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1337bee4f87fSThomas Abraham { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1338bee4f87fSThomas Abraham { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1339bee4f87fSThomas Abraham { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1340bee4f87fSThomas Abraham { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1341bee4f87fSThomas Abraham { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1342bee4f87fSThomas Abraham { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1343bee4f87fSThomas Abraham { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1344bee4f87fSThomas Abraham { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1345bee4f87fSThomas Abraham { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1346bee4f87fSThomas Abraham { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1347bee4f87fSThomas Abraham { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1348bee4f87fSThomas Abraham { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1349bee4f87fSThomas Abraham { 0 }, 1350bee4f87fSThomas Abraham }; 1351bee4f87fSThomas Abraham 135254abbdb4SBartlomiej Zolnierkiewicz static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 135354abbdb4SBartlomiej Zolnierkiewicz { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 135454abbdb4SBartlomiej Zolnierkiewicz { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 135554abbdb4SBartlomiej Zolnierkiewicz { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 135654abbdb4SBartlomiej Zolnierkiewicz { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 135754abbdb4SBartlomiej Zolnierkiewicz { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 135854abbdb4SBartlomiej Zolnierkiewicz { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 135954abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 136054abbdb4SBartlomiej Zolnierkiewicz { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 136154abbdb4SBartlomiej Zolnierkiewicz { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 136254abbdb4SBartlomiej Zolnierkiewicz { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 136354abbdb4SBartlomiej Zolnierkiewicz { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 136454abbdb4SBartlomiej Zolnierkiewicz { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 136554abbdb4SBartlomiej Zolnierkiewicz { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 136654abbdb4SBartlomiej Zolnierkiewicz { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 136754abbdb4SBartlomiej Zolnierkiewicz { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 136854abbdb4SBartlomiej Zolnierkiewicz { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 136954abbdb4SBartlomiej Zolnierkiewicz { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 137054abbdb4SBartlomiej Zolnierkiewicz { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 137154abbdb4SBartlomiej Zolnierkiewicz { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 137254abbdb4SBartlomiej Zolnierkiewicz { 0 }, 137354abbdb4SBartlomiej Zolnierkiewicz }; 137454abbdb4SBartlomiej Zolnierkiewicz 1375bee4f87fSThomas Abraham #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1376bee4f87fSThomas Abraham ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1377bee4f87fSThomas Abraham 1378bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 137954abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1380bee4f87fSThomas Abraham { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1381bee4f87fSThomas Abraham { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1382bee4f87fSThomas Abraham { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1383bee4f87fSThomas Abraham { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1384bee4f87fSThomas Abraham { 900000, E5420_KFC_DIV(3, 5, 2), }, 1385bee4f87fSThomas Abraham { 800000, E5420_KFC_DIV(3, 5, 2), }, 1386bee4f87fSThomas Abraham { 700000, E5420_KFC_DIV(3, 4, 2), }, 1387bee4f87fSThomas Abraham { 600000, E5420_KFC_DIV(3, 4, 2), }, 1388bee4f87fSThomas Abraham { 500000, E5420_KFC_DIV(3, 4, 2), }, 1389bee4f87fSThomas Abraham { 400000, E5420_KFC_DIV(3, 3, 2), }, 1390bee4f87fSThomas Abraham { 300000, E5420_KFC_DIV(3, 3, 2), }, 1391bee4f87fSThomas Abraham { 200000, E5420_KFC_DIV(3, 3, 2), }, 1392bee4f87fSThomas Abraham { 0 }, 1393bee4f87fSThomas Abraham }; 1394bee4f87fSThomas Abraham 1395305cfab0SKrzysztof Kozlowski static const struct of_device_id ext_clk_match[] __initconst = { 13961609027fSChander Kashyap { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 13971609027fSChander Kashyap { }, 13981609027fSChander Kashyap }; 13991609027fSChander Kashyap 14001609027fSChander Kashyap /* register exynos5420 clocks */ 14016520e968SAlim Akhtar static void __init exynos5x_clk_init(struct device_node *np, 14026520e968SAlim Akhtar enum exynos5x_soc soc) 14031609027fSChander Kashyap { 1404976face4SRahul Sharma struct samsung_clk_provider *ctx; 1405976face4SRahul Sharma 14061609027fSChander Kashyap if (np) { 14071609027fSChander Kashyap reg_base = of_iomap(np, 0); 14081609027fSChander Kashyap if (!reg_base) 14091609027fSChander Kashyap panic("%s: failed to map registers\n", __func__); 14101609027fSChander Kashyap } else { 14111609027fSChander Kashyap panic("%s: unable to determine soc\n", __func__); 14121609027fSChander Kashyap } 14131609027fSChander Kashyap 14146520e968SAlim Akhtar exynos5x_soc = soc; 14156520e968SAlim Akhtar 1416976face4SRahul Sharma ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1417976face4SRahul Sharma 14186520e968SAlim Akhtar samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 14196520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 14201609027fSChander Kashyap ext_clk_match); 1421ca5b4029SThomas Abraham 1422ca5b4029SThomas Abraham if (_get_rate("fin_pll") == 24 * MHZ) { 1423ca5b4029SThomas Abraham exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 14249842452aSSylwester Nawrocki exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; 1425ca5b4029SThomas Abraham exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1426e867e8faSChanwoo Choi exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1427ca5b4029SThomas Abraham } 1428ca5b4029SThomas Abraham 14296520e968SAlim Akhtar samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1430c898c6b7SYadwinder Singh Brar reg_base); 14316520e968SAlim Akhtar samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 14326520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_clks)); 14336520e968SAlim Akhtar samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 14346520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_factor_clks)); 14356520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5x_mux_clks, 14366520e968SAlim Akhtar ARRAY_SIZE(exynos5x_mux_clks)); 14376520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5x_div_clks, 14386520e968SAlim Akhtar ARRAY_SIZE(exynos5x_div_clks)); 14396520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5x_gate_clks, 14406520e968SAlim Akhtar ARRAY_SIZE(exynos5x_gate_clks)); 14416520e968SAlim Akhtar 14426520e968SAlim Akhtar if (soc == EXYNOS5420) { 1443976face4SRahul Sharma samsung_clk_register_mux(ctx, exynos5420_mux_clks, 14441609027fSChander Kashyap ARRAY_SIZE(exynos5420_mux_clks)); 1445976face4SRahul Sharma samsung_clk_register_div(ctx, exynos5420_div_clks, 14461609027fSChander Kashyap ARRAY_SIZE(exynos5420_div_clks)); 144741097f25SSylwester Nawrocki samsung_clk_register_gate(ctx, exynos5420_gate_clks, 144841097f25SSylwester Nawrocki ARRAY_SIZE(exynos5420_gate_clks)); 14496520e968SAlim Akhtar } else { 14506520e968SAlim Akhtar samsung_clk_register_fixed_factor( 14516520e968SAlim Akhtar ctx, exynos5800_fixed_factor_clks, 14526520e968SAlim Akhtar ARRAY_SIZE(exynos5800_fixed_factor_clks)); 14536520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5800_mux_clks, 14546520e968SAlim Akhtar ARRAY_SIZE(exynos5800_mux_clks)); 14556520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5800_div_clks, 14566520e968SAlim Akhtar ARRAY_SIZE(exynos5800_div_clks)); 14576520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5800_gate_clks, 14586520e968SAlim Akhtar ARRAY_SIZE(exynos5800_gate_clks)); 14596520e968SAlim Akhtar } 1460388c7885STomasz Figa 146154abbdb4SBartlomiej Zolnierkiewicz if (soc == EXYNOS5420) { 1462bee4f87fSThomas Abraham exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1463bee4f87fSThomas Abraham mout_cpu_p[0], mout_cpu_p[1], 0x200, 1464bee4f87fSThomas Abraham exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); 146554abbdb4SBartlomiej Zolnierkiewicz } else { 146654abbdb4SBartlomiej Zolnierkiewicz exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 146754abbdb4SBartlomiej Zolnierkiewicz mout_cpu_p[0], mout_cpu_p[1], 0x200, 146854abbdb4SBartlomiej Zolnierkiewicz exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); 146954abbdb4SBartlomiej Zolnierkiewicz } 1470bee4f87fSThomas Abraham exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", 1471bee4f87fSThomas Abraham mout_kfc_p[0], mout_kfc_p[1], 0x28200, 1472bee4f87fSThomas Abraham exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); 1473bee4f87fSThomas Abraham 1474388c7885STomasz Figa exynos5420_clk_sleep_init(); 1475d5e136a2SSylwester Nawrocki 1476d5e136a2SSylwester Nawrocki samsung_clk_of_add_provider(np, ctx); 14771609027fSChander Kashyap } 14786520e968SAlim Akhtar 14796520e968SAlim Akhtar static void __init exynos5420_clk_init(struct device_node *np) 14806520e968SAlim Akhtar { 14816520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5420); 14826520e968SAlim Akhtar } 14831609027fSChander Kashyap CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 14846520e968SAlim Akhtar 14856520e968SAlim Akhtar static void __init exynos5800_clk_init(struct device_node *np) 14866520e968SAlim Akhtar { 14876520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5800); 14886520e968SAlim Akhtar } 14896520e968SAlim Akhtar CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init); 1490