11609027fSChander Kashyap /* 21609027fSChander Kashyap * Copyright (c) 2013 Samsung Electronics Co., Ltd. 31609027fSChander Kashyap * Authors: Thomas Abraham <thomas.ab@samsung.com> 41609027fSChander Kashyap * Chander Kashyap <k.chander@samsung.com> 51609027fSChander Kashyap * 61609027fSChander Kashyap * This program is free software; you can redistribute it and/or modify 71609027fSChander Kashyap * it under the terms of the GNU General Public License version 2 as 81609027fSChander Kashyap * published by the Free Software Foundation. 91609027fSChander Kashyap * 101609027fSChander Kashyap * Common Clock Framework support for Exynos5420 SoC. 111609027fSChander Kashyap */ 121609027fSChander Kashyap 13cba9d2faSAndrzej Hajda #include <dt-bindings/clock/exynos5420.h> 146f1ed07aSStephen Boyd #include <linux/slab.h> 151609027fSChander Kashyap #include <linux/clk-provider.h> 161609027fSChander Kashyap #include <linux/of.h> 171609027fSChander Kashyap #include <linux/of_address.h> 181609027fSChander Kashyap 191609027fSChander Kashyap #include "clk.h" 20bee4f87fSThomas Abraham #include "clk-cpu.h" 21ec4016ffSMarek Szyprowski #include "clk-exynos5-subcmu.h" 221609027fSChander Kashyap 23c898c6b7SYadwinder Singh Brar #define APLL_LOCK 0x0 24c898c6b7SYadwinder Singh Brar #define APLL_CON0 0x100 251609027fSChander Kashyap #define SRC_CPU 0x200 261609027fSChander Kashyap #define DIV_CPU0 0x500 271609027fSChander Kashyap #define DIV_CPU1 0x504 281609027fSChander Kashyap #define GATE_BUS_CPU 0x700 291609027fSChander Kashyap #define GATE_SCLK_CPU 0x800 3077342432SShaik Ameer Basha #define CLKOUT_CMU_CPU 0xa00 31e9d52956SVikas Sajjan #define SRC_MASK_CPERI 0x4300 325b73721bSNaveen Krishna Chatradhi #define GATE_IP_G2D 0x8800 33c898c6b7SYadwinder Singh Brar #define CPLL_LOCK 0x10020 34c898c6b7SYadwinder Singh Brar #define DPLL_LOCK 0x10030 35c898c6b7SYadwinder Singh Brar #define EPLL_LOCK 0x10040 36c898c6b7SYadwinder Singh Brar #define RPLL_LOCK 0x10050 37c898c6b7SYadwinder Singh Brar #define IPLL_LOCK 0x10060 38c898c6b7SYadwinder Singh Brar #define SPLL_LOCK 0x10070 3953cb6342SSachin Kamat #define VPLL_LOCK 0x10080 40c898c6b7SYadwinder Singh Brar #define MPLL_LOCK 0x10090 41c898c6b7SYadwinder Singh Brar #define CPLL_CON0 0x10120 42c898c6b7SYadwinder Singh Brar #define DPLL_CON0 0x10128 43c898c6b7SYadwinder Singh Brar #define EPLL_CON0 0x10130 4477342432SShaik Ameer Basha #define EPLL_CON1 0x10134 4577342432SShaik Ameer Basha #define EPLL_CON2 0x10138 46c898c6b7SYadwinder Singh Brar #define RPLL_CON0 0x10140 4777342432SShaik Ameer Basha #define RPLL_CON1 0x10144 4877342432SShaik Ameer Basha #define RPLL_CON2 0x10148 49c898c6b7SYadwinder Singh Brar #define IPLL_CON0 0x10150 50c898c6b7SYadwinder Singh Brar #define SPLL_CON0 0x10160 51c898c6b7SYadwinder Singh Brar #define VPLL_CON0 0x10170 52c898c6b7SYadwinder Singh Brar #define MPLL_CON0 0x10180 531609027fSChander Kashyap #define SRC_TOP0 0x10200 541609027fSChander Kashyap #define SRC_TOP1 0x10204 551609027fSChander Kashyap #define SRC_TOP2 0x10208 561609027fSChander Kashyap #define SRC_TOP3 0x1020c 571609027fSChander Kashyap #define SRC_TOP4 0x10210 581609027fSChander Kashyap #define SRC_TOP5 0x10214 591609027fSChander Kashyap #define SRC_TOP6 0x10218 601609027fSChander Kashyap #define SRC_TOP7 0x1021c 616520e968SAlim Akhtar #define SRC_TOP8 0x10220 /* 5800 specific */ 626520e968SAlim Akhtar #define SRC_TOP9 0x10224 /* 5800 specific */ 631609027fSChander Kashyap #define SRC_DISP10 0x1022c 641609027fSChander Kashyap #define SRC_MAU 0x10240 651609027fSChander Kashyap #define SRC_FSYS 0x10244 661609027fSChander Kashyap #define SRC_PERIC0 0x10250 671609027fSChander Kashyap #define SRC_PERIC1 0x10254 683a767b35SShaik Ameer Basha #define SRC_ISP 0x10270 696520e968SAlim Akhtar #define SRC_CAM 0x10274 /* 5800 specific */ 701609027fSChander Kashyap #define SRC_TOP10 0x10280 711609027fSChander Kashyap #define SRC_TOP11 0x10284 721609027fSChander Kashyap #define SRC_TOP12 0x10288 736520e968SAlim Akhtar #define SRC_TOP13 0x1028c /* 5800 specific */ 74e9d52956SVikas Sajjan #define SRC_MASK_TOP0 0x10300 75e9d52956SVikas Sajjan #define SRC_MASK_TOP1 0x10304 76424b673aSShaik Ameer Basha #define SRC_MASK_TOP2 0x10308 7731116a64SShaik Ameer Basha #define SRC_MASK_TOP7 0x1031c 781609027fSChander Kashyap #define SRC_MASK_DISP10 0x1032c 7931116a64SShaik Ameer Basha #define SRC_MASK_MAU 0x10334 801609027fSChander Kashyap #define SRC_MASK_FSYS 0x10340 811609027fSChander Kashyap #define SRC_MASK_PERIC0 0x10350 821609027fSChander Kashyap #define SRC_MASK_PERIC1 0x10354 83e9d52956SVikas Sajjan #define SRC_MASK_ISP 0x10370 841609027fSChander Kashyap #define DIV_TOP0 0x10500 851609027fSChander Kashyap #define DIV_TOP1 0x10504 861609027fSChander Kashyap #define DIV_TOP2 0x10508 876520e968SAlim Akhtar #define DIV_TOP8 0x10520 /* 5800 specific */ 886520e968SAlim Akhtar #define DIV_TOP9 0x10524 /* 5800 specific */ 891609027fSChander Kashyap #define DIV_DISP10 0x1052c 901609027fSChander Kashyap #define DIV_MAU 0x10544 911609027fSChander Kashyap #define DIV_FSYS0 0x10548 921609027fSChander Kashyap #define DIV_FSYS1 0x1054c 931609027fSChander Kashyap #define DIV_FSYS2 0x10550 941609027fSChander Kashyap #define DIV_PERIC0 0x10558 951609027fSChander Kashyap #define DIV_PERIC1 0x1055c 961609027fSChander Kashyap #define DIV_PERIC2 0x10560 971609027fSChander Kashyap #define DIV_PERIC3 0x10564 981609027fSChander Kashyap #define DIV_PERIC4 0x10568 996520e968SAlim Akhtar #define DIV_CAM 0x10574 /* 5800 specific */ 1003a767b35SShaik Ameer Basha #define SCLK_DIV_ISP0 0x10580 1013a767b35SShaik Ameer Basha #define SCLK_DIV_ISP1 0x10584 10202932381SShaik Ameer Basha #define DIV2_RATIO0 0x10590 1031d87db4dSShaik Ameer Basha #define DIV4_RATIO 0x105a0 1041609027fSChander Kashyap #define GATE_BUS_TOP 0x10700 105e9d52956SVikas Sajjan #define GATE_BUS_DISP1 0x10728 1060a22c306SShaik Ameer Basha #define GATE_BUS_GEN 0x1073c 1071609027fSChander Kashyap #define GATE_BUS_FSYS0 0x10740 1086b5ae463SShaik Ameer Basha #define GATE_BUS_FSYS2 0x10748 1091609027fSChander Kashyap #define GATE_BUS_PERIC 0x10750 1101609027fSChander Kashyap #define GATE_BUS_PERIC1 0x10754 1111609027fSChander Kashyap #define GATE_BUS_PERIS0 0x10760 1121609027fSChander Kashyap #define GATE_BUS_PERIS1 0x10764 1136575fa76SShaik Ameer Basha #define GATE_BUS_NOC 0x10770 1143a767b35SShaik Ameer Basha #define GATE_TOP_SCLK_ISP 0x10870 1151609027fSChander Kashyap #define GATE_IP_GSCL0 0x10910 1161609027fSChander Kashyap #define GATE_IP_GSCL1 0x10920 1176520e968SAlim Akhtar #define GATE_IP_CAM 0x10924 /* 5800 specific */ 1181609027fSChander Kashyap #define GATE_IP_MFC 0x1092c 1191609027fSChander Kashyap #define GATE_IP_DISP1 0x10928 1201609027fSChander Kashyap #define GATE_IP_G3D 0x10930 1211609027fSChander Kashyap #define GATE_IP_GEN 0x10934 1226b5ae463SShaik Ameer Basha #define GATE_IP_FSYS 0x10944 123faec151bSShaik Ameer Basha #define GATE_IP_PERIC 0x10950 1240a22c306SShaik Ameer Basha #define GATE_IP_PERIS 0x10960 1251609027fSChander Kashyap #define GATE_IP_MSCL 0x10970 1261609027fSChander Kashyap #define GATE_TOP_SCLK_GSCL 0x10820 1271609027fSChander Kashyap #define GATE_TOP_SCLK_DISP1 0x10828 1281609027fSChander Kashyap #define GATE_TOP_SCLK_MAU 0x1083c 1291609027fSChander Kashyap #define GATE_TOP_SCLK_FSYS 0x10840 1301609027fSChander Kashyap #define GATE_TOP_SCLK_PERIC 0x10850 131424b673aSShaik Ameer Basha #define TOP_SPARE2 0x10b08 132c898c6b7SYadwinder Singh Brar #define BPLL_LOCK 0x20010 133c898c6b7SYadwinder Singh Brar #define BPLL_CON0 0x20110 134e867e8faSChanwoo Choi #define SRC_CDREX 0x20200 135e867e8faSChanwoo Choi #define DIV_CDREX0 0x20500 136e867e8faSChanwoo Choi #define DIV_CDREX1 0x20504 1372f57b95cSLukasz Luba #define GATE_BUS_CDREX0 0x20700 1382f57b95cSLukasz Luba #define GATE_BUS_CDREX1 0x20704 139c898c6b7SYadwinder Singh Brar #define KPLL_LOCK 0x28000 140c898c6b7SYadwinder Singh Brar #define KPLL_CON0 0x28100 1411609027fSChander Kashyap #define SRC_KFC 0x28200 1421609027fSChander Kashyap #define DIV_KFC0 0x28500 1431609027fSChander Kashyap 1446520e968SAlim Akhtar /* Exynos5x SoC type */ 1456520e968SAlim Akhtar enum exynos5x_soc { 1466520e968SAlim Akhtar EXYNOS5420, 1476520e968SAlim Akhtar EXYNOS5800, 1486520e968SAlim Akhtar }; 1496520e968SAlim Akhtar 150c898c6b7SYadwinder Singh Brar /* list of PLLs */ 1516520e968SAlim Akhtar enum exynos5x_plls { 152c898c6b7SYadwinder Singh Brar apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 153c898c6b7SYadwinder Singh Brar bpll, kpll, 154c898c6b7SYadwinder Singh Brar nr_plls /* number of PLLs */ 155c898c6b7SYadwinder Singh Brar }; 156c898c6b7SYadwinder Singh Brar 157388c7885STomasz Figa static void __iomem *reg_base; 1586520e968SAlim Akhtar static enum exynos5x_soc exynos5x_soc; 159388c7885STomasz Figa 1601609027fSChander Kashyap /* 1611609027fSChander Kashyap * list of controller registers to be saved and restored during a 1621609027fSChander Kashyap * suspend/resume cycle. 1631609027fSChander Kashyap */ 164ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5x_clk_regs[] __initconst = { 1651609027fSChander Kashyap SRC_CPU, 1661609027fSChander Kashyap DIV_CPU0, 1671609027fSChander Kashyap DIV_CPU1, 1681609027fSChander Kashyap GATE_BUS_CPU, 1691609027fSChander Kashyap GATE_SCLK_CPU, 17077342432SShaik Ameer Basha CLKOUT_CMU_CPU, 17177342432SShaik Ameer Basha EPLL_CON0, 17277342432SShaik Ameer Basha EPLL_CON1, 17377342432SShaik Ameer Basha EPLL_CON2, 17477342432SShaik Ameer Basha RPLL_CON0, 17577342432SShaik Ameer Basha RPLL_CON1, 17677342432SShaik Ameer Basha RPLL_CON2, 1771609027fSChander Kashyap SRC_TOP0, 1781609027fSChander Kashyap SRC_TOP1, 1791609027fSChander Kashyap SRC_TOP2, 1801609027fSChander Kashyap SRC_TOP3, 1811609027fSChander Kashyap SRC_TOP4, 1821609027fSChander Kashyap SRC_TOP5, 1831609027fSChander Kashyap SRC_TOP6, 1841609027fSChander Kashyap SRC_TOP7, 1851609027fSChander Kashyap SRC_DISP10, 1861609027fSChander Kashyap SRC_MAU, 1871609027fSChander Kashyap SRC_FSYS, 1881609027fSChander Kashyap SRC_PERIC0, 1891609027fSChander Kashyap SRC_PERIC1, 1901609027fSChander Kashyap SRC_TOP10, 1911609027fSChander Kashyap SRC_TOP11, 1921609027fSChander Kashyap SRC_TOP12, 193424b673aSShaik Ameer Basha SRC_MASK_TOP2, 19431116a64SShaik Ameer Basha SRC_MASK_TOP7, 1951609027fSChander Kashyap SRC_MASK_DISP10, 1961609027fSChander Kashyap SRC_MASK_FSYS, 1971609027fSChander Kashyap SRC_MASK_PERIC0, 1981609027fSChander Kashyap SRC_MASK_PERIC1, 199e9d52956SVikas Sajjan SRC_MASK_TOP0, 200e9d52956SVikas Sajjan SRC_MASK_TOP1, 201e9d52956SVikas Sajjan SRC_MASK_MAU, 202e9d52956SVikas Sajjan SRC_MASK_ISP, 2033a767b35SShaik Ameer Basha SRC_ISP, 2041609027fSChander Kashyap DIV_TOP0, 2051609027fSChander Kashyap DIV_TOP1, 2061609027fSChander Kashyap DIV_TOP2, 2071609027fSChander Kashyap DIV_DISP10, 2081609027fSChander Kashyap DIV_MAU, 2091609027fSChander Kashyap DIV_FSYS0, 2101609027fSChander Kashyap DIV_FSYS1, 2111609027fSChander Kashyap DIV_FSYS2, 2121609027fSChander Kashyap DIV_PERIC0, 2131609027fSChander Kashyap DIV_PERIC1, 2141609027fSChander Kashyap DIV_PERIC2, 2151609027fSChander Kashyap DIV_PERIC3, 2161609027fSChander Kashyap DIV_PERIC4, 2173a767b35SShaik Ameer Basha SCLK_DIV_ISP0, 2183a767b35SShaik Ameer Basha SCLK_DIV_ISP1, 21902932381SShaik Ameer Basha DIV2_RATIO0, 2201d87db4dSShaik Ameer Basha DIV4_RATIO, 221e9d52956SVikas Sajjan GATE_BUS_DISP1, 2221609027fSChander Kashyap GATE_BUS_TOP, 2230a22c306SShaik Ameer Basha GATE_BUS_GEN, 2241609027fSChander Kashyap GATE_BUS_FSYS0, 2256b5ae463SShaik Ameer Basha GATE_BUS_FSYS2, 2261609027fSChander Kashyap GATE_BUS_PERIC, 2271609027fSChander Kashyap GATE_BUS_PERIC1, 2281609027fSChander Kashyap GATE_BUS_PERIS0, 2291609027fSChander Kashyap GATE_BUS_PERIS1, 2306575fa76SShaik Ameer Basha GATE_BUS_NOC, 2313a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2321609027fSChander Kashyap GATE_IP_GSCL0, 2331609027fSChander Kashyap GATE_IP_GSCL1, 2341609027fSChander Kashyap GATE_IP_MFC, 2351609027fSChander Kashyap GATE_IP_DISP1, 2361609027fSChander Kashyap GATE_IP_G3D, 2371609027fSChander Kashyap GATE_IP_GEN, 2386b5ae463SShaik Ameer Basha GATE_IP_FSYS, 239faec151bSShaik Ameer Basha GATE_IP_PERIC, 2400a22c306SShaik Ameer Basha GATE_IP_PERIS, 2411609027fSChander Kashyap GATE_IP_MSCL, 2421609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 2431609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 2441609027fSChander Kashyap GATE_TOP_SCLK_MAU, 2451609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2461609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 247424b673aSShaik Ameer Basha TOP_SPARE2, 248e867e8faSChanwoo Choi SRC_CDREX, 249e867e8faSChanwoo Choi DIV_CDREX0, 250e867e8faSChanwoo Choi DIV_CDREX1, 2511609027fSChander Kashyap SRC_KFC, 2521609027fSChander Kashyap DIV_KFC0, 2532f57b95cSLukasz Luba GATE_BUS_CDREX0, 2542f57b95cSLukasz Luba GATE_BUS_CDREX1, 2551609027fSChander Kashyap }; 2561609027fSChander Kashyap 257ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5800_clk_regs[] __initconst = { 2586520e968SAlim Akhtar SRC_TOP8, 2596520e968SAlim Akhtar SRC_TOP9, 2606520e968SAlim Akhtar SRC_CAM, 2616520e968SAlim Akhtar SRC_TOP1, 2626520e968SAlim Akhtar DIV_TOP8, 2636520e968SAlim Akhtar DIV_TOP9, 2646520e968SAlim Akhtar DIV_CAM, 2656520e968SAlim Akhtar GATE_IP_CAM, 2666520e968SAlim Akhtar }; 2676520e968SAlim Akhtar 268e9d52956SVikas Sajjan static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 269e9d52956SVikas Sajjan { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 270e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 271e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 272e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 273e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 274e9d52956SVikas Sajjan { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 275e9d52956SVikas Sajjan { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 276e9d52956SVikas Sajjan { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 277e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 278e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 279e9d52956SVikas Sajjan { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 28097372e5aSJavier Martinez Canillas { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 281e9d52956SVikas Sajjan { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 282e9d52956SVikas Sajjan { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 283b3322802SMarek Szyprowski { .offset = GATE_IP_PERIS, .value = 0xffffffff, }, 284e9d52956SVikas Sajjan }; 285e9d52956SVikas Sajjan 2861609027fSChander Kashyap /* list of all parent clocks */ 287dbd713bbSShaik Ameer Basha PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 288dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 289dbd713bbSShaik Ameer Basha PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 290dbd713bbSShaik Ameer Basha PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 291dbd713bbSShaik Ameer Basha PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 292dbd713bbSShaik Ameer Basha PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 293dbd713bbSShaik Ameer Basha PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 294dbd713bbSShaik Ameer Basha PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 295dbd713bbSShaik Ameer Basha PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 296dbd713bbSShaik Ameer Basha PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 297dbd713bbSShaik Ameer Basha PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 298dbd713bbSShaik Ameer Basha PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 299dbd713bbSShaik Ameer Basha PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 300dbd713bbSShaik Ameer Basha PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 301dbd713bbSShaik Ameer Basha PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 3021609027fSChander Kashyap 303dbd713bbSShaik Ameer Basha PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 304dbd713bbSShaik Ameer Basha "mout_sclk_mpll"}; 305dbd713bbSShaik Ameer Basha PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 306dbd713bbSShaik Ameer Basha "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 307dbd713bbSShaik Ameer Basha "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 308dbd713bbSShaik Ameer Basha PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 309dbd713bbSShaik Ameer Basha PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 310dbd713bbSShaik Ameer Basha PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 3111609027fSChander Kashyap 312424b673aSShaik Ameer Basha PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 313dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 314faec151bSShaik Ameer Basha PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 315b31ca2a0SShaik Ameer Basha PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 3161609027fSChander Kashyap 317dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 3186b5ae463SShaik Ameer Basha PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 3196b5ae463SShaik Ameer Basha PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 320dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 3211609027fSChander Kashyap 322dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 323dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 3246575fa76SShaik Ameer Basha PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 3256575fa76SShaik Ameer Basha PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 3266575fa76SShaik Ameer Basha 3276575fa76SShaik Ameer Basha PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 3286575fa76SShaik Ameer Basha PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 3296575fa76SShaik Ameer Basha PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 3306575fa76SShaik Ameer Basha 3313a767b35SShaik Ameer Basha PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 3323a767b35SShaik Ameer Basha PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 3333a767b35SShaik Ameer Basha 3343a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 3353a767b35SShaik Ameer Basha "mout_sclk_spll"}; 3363a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 3373a767b35SShaik Ameer Basha 3383a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 3393a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 3401609027fSChander Kashyap 341dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 342424b673aSShaik Ameer Basha PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 3431609027fSChander Kashyap 344dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 345dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 3461609027fSChander Kashyap 347dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 348dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 3491609027fSChander Kashyap 350dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 351dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 3521609027fSChander Kashyap 353dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 354dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 3553a767b35SShaik Ameer Basha PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 3561609027fSChander Kashyap 357dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 358dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 3591609027fSChander Kashyap 360dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 361dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 3621609027fSChander Kashyap 363dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 364424b673aSShaik Ameer Basha PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 365dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 366424b673aSShaik Ameer Basha PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 3671609027fSChander Kashyap 368dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 369dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 3701609027fSChander Kashyap 371dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 372dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 3731609027fSChander Kashyap 374dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 375dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 3761609027fSChander Kashyap 377dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 378dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 3791609027fSChander Kashyap 380dbd713bbSShaik Ameer Basha PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 381dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 382dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 383dbd713bbSShaik Ameer Basha PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 384dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 385dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 386dbd713bbSShaik Ameer Basha PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 387dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 388dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 389dbd713bbSShaik Ameer Basha PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 390dbd713bbSShaik Ameer Basha "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 391dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 392dbd713bbSShaik Ameer Basha PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 393dbd713bbSShaik Ameer Basha PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 394dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 395dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 39631116a64SShaik Ameer Basha PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 39731116a64SShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 398e867e8faSChanwoo Choi PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"}; 399e867e8faSChanwoo Choi 4006520e968SAlim Akhtar /* List of parents specific to exynos5800 */ 4016520e968SAlim Akhtar PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 4026520e968SAlim Akhtar PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4036520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4046520e968SAlim Akhtar PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4056520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4066520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 4076520e968SAlim Akhtar PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4086520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4096520e968SAlim Akhtar "mout_epll2" }; 4106520e968SAlim Akhtar PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4116520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll" }; 4126520e968SAlim Akhtar PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 4136520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4146520e968SAlim Akhtar PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4156520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll", 4166520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 417e867e8faSChanwoo Choi PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll", 418e867e8faSChanwoo Choi "mout_sclk_mpll", "ff_dout_spll2", 419e867e8faSChanwoo Choi "mout_sclk_spll", "mout_sclk_epll"}; 4206520e968SAlim Akhtar PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 4216520e968SAlim Akhtar "mout_sclk_mpll", 4226520e968SAlim Akhtar "ff_dout_spll2" }; 4236520e968SAlim Akhtar PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 4246520e968SAlim Akhtar PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 4256520e968SAlim Akhtar PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 4266520e968SAlim Akhtar PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 4276520e968SAlim Akhtar PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 4286520e968SAlim Akhtar PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 4296520e968SAlim Akhtar PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 4306520e968SAlim Akhtar PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 4318a9cf26eSSylwester Nawrocki PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; 4322f57b95cSLukasz Luba PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll", 4332f57b95cSLukasz Luba "mout_sclk_mpll", "ff_dout_spll2", 4342f57b95cSLukasz Luba "mout_sclk_spll", "mout_sclk_epll"}; 4351609027fSChander Kashyap 4361609027fSChander Kashyap /* fixed rate clocks generated outside the soc */ 4376520e968SAlim Akhtar static struct samsung_fixed_rate_clock 4386520e968SAlim Akhtar exynos5x_fixed_rate_ext_clks[] __initdata = { 439728f288dSStephen Boyd FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 4401609027fSChander Kashyap }; 4411609027fSChander Kashyap 4421609027fSChander Kashyap /* fixed rate clocks generated inside the soc */ 443ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { 444728f288dSStephen Boyd FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 445728f288dSStephen Boyd FRATE(0, "sclk_pwi", NULL, 0, 24000000), 446728f288dSStephen Boyd FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 447728f288dSStephen Boyd FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 448728f288dSStephen Boyd FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 4491609027fSChander Kashyap }; 4501609027fSChander Kashyap 451ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 452ad98c64fSKrzysztof Kozlowski exynos5x_fixed_factor_clks[] __initconst = { 453b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 454b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 4551609027fSChander Kashyap }; 4561609027fSChander Kashyap 457ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 458ad98c64fSKrzysztof Kozlowski exynos5800_fixed_factor_clks[] __initconst = { 4596520e968SAlim Akhtar FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 4602f57b95cSLukasz Luba FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 4616520e968SAlim Akhtar }; 4626520e968SAlim Akhtar 463ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 4646520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 4656520e968SAlim Akhtar MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 4666520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 4676520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 4686520e968SAlim Akhtar 4696520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 4706520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 4716520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 4726520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 4736520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 4746520e968SAlim Akhtar 4756520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 4766520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 4776520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 4786520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 4796520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 4806520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 4816520e968SAlim Akhtar 4822f57b95cSLukasz Luba MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy", 4832f57b95cSLukasz Luba mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3), 4842f57b95cSLukasz Luba 485e867e8faSChanwoo Choi MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 4862f57b95cSLukasz Luba mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3), 487599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, 488599cebeaSSylwester Nawrocki SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), 4892f57b95cSLukasz Luba MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 4906520e968SAlim Akhtar MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 4916520e968SAlim Akhtar 4926520e968SAlim Akhtar MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 4936520e968SAlim Akhtar MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 4946520e968SAlim Akhtar MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 4956520e968SAlim Akhtar MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 4966520e968SAlim Akhtar 497599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, 498599cebeaSSylwester Nawrocki SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0), 4996520e968SAlim Akhtar MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 5006520e968SAlim Akhtar SRC_TOP9, 16, 1), 5016520e968SAlim Akhtar MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 5026520e968SAlim Akhtar SRC_TOP9, 20, 1), 5036520e968SAlim Akhtar MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 5046520e968SAlim Akhtar SRC_TOP9, 24, 1), 5056520e968SAlim Akhtar MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 5066520e968SAlim Akhtar SRC_TOP9, 28, 1), 5076520e968SAlim Akhtar 5086520e968SAlim Akhtar MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 5096520e968SAlim Akhtar MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 5106520e968SAlim Akhtar SRC_TOP13, 20, 1), 5116520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 5126520e968SAlim Akhtar SRC_TOP13, 24, 1), 5136520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 5146520e968SAlim Akhtar SRC_TOP13, 28, 1), 5156520e968SAlim Akhtar 5166520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 5176520e968SAlim Akhtar }; 5186520e968SAlim Akhtar 519ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { 52081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 52181fed6e3SChanwoo Choi "mout_aclk400_wcore", DIV_TOP0, 16, 3), 5226520e968SAlim Akhtar DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 5236520e968SAlim Akhtar DIV_TOP8, 16, 3), 5246520e968SAlim Akhtar DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 5256520e968SAlim Akhtar DIV_TOP8, 20, 3), 5266520e968SAlim Akhtar DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 5276520e968SAlim Akhtar DIV_TOP8, 24, 3), 5286520e968SAlim Akhtar DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 5296520e968SAlim Akhtar DIV_TOP8, 28, 3), 5306520e968SAlim Akhtar 5316520e968SAlim Akhtar DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 5326520e968SAlim Akhtar DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 5336520e968SAlim Akhtar }; 5346520e968SAlim Akhtar 535ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 5366520e968SAlim Akhtar GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 5376520e968SAlim Akhtar GATE_BUS_TOP, 24, 0, 0), 5386520e968SAlim Akhtar GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 539318fa46cSMarek Szyprowski GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), 54041097f25SSylwester Nawrocki GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", 541599cebeaSSylwester Nawrocki SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 5426520e968SAlim Akhtar }; 5436520e968SAlim Akhtar 544ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 5456520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 5466520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 5476520e968SAlim Akhtar TOP_SPARE2, 4, 1), 5486520e968SAlim Akhtar 5496520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 55036ba4824SMarek Szyprowski MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2), 5516520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 5526520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 5536520e968SAlim Akhtar 5546520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 5556520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group4_p, 5566520e968SAlim Akhtar SRC_TOP1, 4, 2), 5576520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 5586520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 5596520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 5606520e968SAlim Akhtar 5616520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 5626520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 5636520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 5646520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 5656520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 5666520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 5676520e968SAlim Akhtar 568e867e8faSChanwoo Choi MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 569e867e8faSChanwoo Choi mout_group5_5800_p, SRC_TOP7, 16, 2), 57006255a92SSylwester Nawrocki MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2, 57106255a92SSylwester Nawrocki CLK_SET_RATE_PARENT, 0), 5726520e968SAlim Akhtar 5736520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 5746520e968SAlim Akhtar }; 5756520e968SAlim Akhtar 576ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 57781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 57881fed6e3SChanwoo Choi "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 5796520e968SAlim Akhtar }; 5806520e968SAlim Akhtar 58141097f25SSylwester Nawrocki static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { 582d32dd2a1SJoonyoung Shim GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 58341097f25SSylwester Nawrocki GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 584599cebeaSSylwester Nawrocki SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 58541097f25SSylwester Nawrocki }; 58641097f25SSylwester Nawrocki 587ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 588b31ca2a0SShaik Ameer Basha MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 589b31ca2a0SShaik Ameer Basha SRC_TOP7, 4, 1), 590dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 591dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 59231116a64SShaik Ameer Basha 593bee4f87fSThomas Abraham MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 594bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 595dbd713bbSShaik Ameer Basha MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 596bee4f87fSThomas Abraham MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 597bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 598dbd713bbSShaik Ameer Basha MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 5991609027fSChander Kashyap 600dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 601dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 6026b5ae463SShaik Ameer Basha MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 603dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 6041609027fSChander Kashyap 605dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 606dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 6071609027fSChander Kashyap 608dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 6091609027fSChander Kashyap 6103a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 6113a767b35SShaik Ameer Basha SRC_TOP3, 0, 1), 612dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 6131609027fSChander Kashyap SRC_TOP3, 4, 1), 61488560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 61588560100SJavier Martinez Canillas mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 616dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 6171609027fSChander Kashyap SRC_TOP3, 12, 1), 6186575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 6196575fa76SShaik Ameer Basha SRC_TOP3, 16, 1), 6206575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 6216575fa76SShaik Ameer Basha SRC_TOP3, 20, 1), 6226b5ae463SShaik Ameer Basha MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 6236b5ae463SShaik Ameer Basha SRC_TOP3, 24, 1), 624dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 6251609027fSChander Kashyap SRC_TOP3, 28, 1), 6261609027fSChander Kashyap 627dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 6281609027fSChander Kashyap SRC_TOP4, 0, 1), 6293a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 6303a767b35SShaik Ameer Basha SRC_TOP4, 4, 1), 631faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 632faec151bSShaik Ameer Basha SRC_TOP4, 8, 1), 6333a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 6343a767b35SShaik Ameer Basha SRC_TOP4, 12, 1), 6353a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 6363a767b35SShaik Ameer Basha SRC_TOP4, 16, 1), 637dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 638dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 639c0fb262bSArun Kumar K MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 640c0fb262bSArun Kumar K SRC_TOP4, 28, 1), 6411609027fSChander Kashyap 64288560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 64388560100SJavier Martinez Canillas mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 644faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 645faec151bSShaik Ameer Basha SRC_TOP5, 4, 1), 6463fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 6473fac5941SShaik Ameer Basha SRC_TOP5, 8, 1), 6483fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 6493fac5941SShaik Ameer Basha SRC_TOP5, 12, 1), 6503fac5941SShaik Ameer Basha MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 6513fac5941SShaik Ameer Basha SRC_TOP5, 16, 1), 652dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 6531609027fSChander Kashyap SRC_TOP5, 20, 1), 65488560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 65588560100SJavier Martinez Canillas mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 656c0feb268SMarek Szyprowski MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 657c0feb268SMarek Szyprowski mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 6581609027fSChander Kashyap 659dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 660dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 6612f57b95cSLukasz Luba MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 662dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 663dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 664599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, 665599cebeaSSylwester Nawrocki CLK_SET_RATE_PARENT, 0), 666dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 667dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 6681609027fSChander Kashyap 6693a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 6703a767b35SShaik Ameer Basha SRC_TOP10, 0, 1), 671dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 672dbd713bbSShaik Ameer Basha SRC_TOP10, 4, 1), 67388560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 67488560100SJavier Martinez Canillas SRC_TOP10, 8, 1), 675dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 6761609027fSChander Kashyap SRC_TOP10, 12, 1), 6776575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 6786575fa76SShaik Ameer Basha SRC_TOP10, 16, 1), 6796575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 6806575fa76SShaik Ameer Basha SRC_TOP10, 20, 1), 6816b5ae463SShaik Ameer Basha MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 6826b5ae463SShaik Ameer Basha SRC_TOP10, 24, 1), 683dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 684dbd713bbSShaik Ameer Basha SRC_TOP10, 28, 1), 6853a767b35SShaik Ameer Basha 686dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 6871609027fSChander Kashyap SRC_TOP11, 0, 1), 6883a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 6893a767b35SShaik Ameer Basha SRC_TOP11, 4, 1), 690dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 6913a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 6923a767b35SShaik Ameer Basha SRC_TOP11, 12, 1), 693dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 694dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 695c0fb262bSArun Kumar K MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 696c0fb262bSArun Kumar K SRC_TOP11, 28, 1), 6971609027fSChander Kashyap 69888560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 69988560100SJavier Martinez Canillas mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 700dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 701dbd713bbSShaik Ameer Basha SRC_TOP12, 8, 1), 702dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 703dbd713bbSShaik Ameer Basha SRC_TOP12, 12, 1), 704dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 705dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 706dbd713bbSShaik Ameer Basha SRC_TOP12, 20, 1), 70788560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 70888560100SJavier Martinez Canillas mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 709c0feb268SMarek Szyprowski MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 710c0feb268SMarek Szyprowski mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 7111609027fSChander Kashyap 7121609027fSChander Kashyap /* DISP1 Block */ 713dbd713bbSShaik Ameer Basha MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 714dbd713bbSShaik Ameer Basha MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 715dbd713bbSShaik Ameer Basha MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 716dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 717424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 7186575fa76SShaik Ameer Basha 719424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 7201609027fSChander Kashyap 721e867e8faSChanwoo Choi /* CDREX block */ 722e867e8faSChanwoo Choi MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p, 723e867e8faSChanwoo Choi SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0), 724e867e8faSChanwoo Choi MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1, 725e867e8faSChanwoo Choi CLK_SET_RATE_PARENT, 0), 726e867e8faSChanwoo Choi 7271609027fSChander Kashyap /* MAU Block */ 72831116a64SShaik Ameer Basha MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 7291609027fSChander Kashyap 7301609027fSChander Kashyap /* FSYS Block */ 731dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 732dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 733dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 734dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 735dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 736dbd713bbSShaik Ameer Basha MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 7376b5ae463SShaik Ameer Basha MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 7381609027fSChander Kashyap 7391609027fSChander Kashyap /* PERIC Block */ 740dbd713bbSShaik Ameer Basha MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 741dbd713bbSShaik Ameer Basha MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 742dbd713bbSShaik Ameer Basha MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 743dbd713bbSShaik Ameer Basha MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 744dbd713bbSShaik Ameer Basha MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 745dbd713bbSShaik Ameer Basha MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 746dbd713bbSShaik Ameer Basha MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 747dbd713bbSShaik Ameer Basha MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 748dbd713bbSShaik Ameer Basha MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 749dbd713bbSShaik Ameer Basha MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 750dbd713bbSShaik Ameer Basha MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 751dbd713bbSShaik Ameer Basha MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 7523a767b35SShaik Ameer Basha 7533a767b35SShaik Ameer Basha /* ISP Block */ 7543a767b35SShaik Ameer Basha MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 7553a767b35SShaik Ameer Basha MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 7563a767b35SShaik Ameer Basha MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 7573a767b35SShaik Ameer Basha MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 7583a767b35SShaik Ameer Basha MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 7591609027fSChander Kashyap }; 7601609027fSChander Kashyap 761ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 762cba9d2faSAndrzej Hajda DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 763cba9d2faSAndrzej Hajda DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 764cba9d2faSAndrzej Hajda DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 765dbd713bbSShaik Ameer Basha DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 766cba9d2faSAndrzej Hajda DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 7671609027fSChander Kashyap 76881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 76981fed6e3SChanwoo Choi DIV_TOP0, 0, 3), 77081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 77181fed6e3SChanwoo Choi DIV_TOP0, 4, 3), 77281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 77381fed6e3SChanwoo Choi DIV_TOP0, 8, 3), 77481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 77581fed6e3SChanwoo Choi DIV_TOP0, 12, 3), 77681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 77781fed6e3SChanwoo Choi DIV_TOP0, 20, 3), 77881fed6e3SChanwoo Choi DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 77981fed6e3SChanwoo Choi DIV_TOP0, 24, 3), 78081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 78181fed6e3SChanwoo Choi DIV_TOP0, 28, 3), 78281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 78381fed6e3SChanwoo Choi "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 78481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 78581fed6e3SChanwoo Choi "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 78681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 78781fed6e3SChanwoo Choi DIV_TOP1, 8, 6), 78881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 78981fed6e3SChanwoo Choi "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 79081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 79181fed6e3SChanwoo Choi DIV_TOP1, 20, 3), 79281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 79381fed6e3SChanwoo Choi DIV_TOP1, 24, 3), 79481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 79581fed6e3SChanwoo Choi DIV_TOP1, 28, 3), 7961609027fSChander Kashyap 79781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 79881fed6e3SChanwoo Choi DIV_TOP2, 8, 3), 79981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 80081fed6e3SChanwoo Choi DIV_TOP2, 12, 3), 80181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 80281fed6e3SChanwoo Choi 16, 3), 80381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 80481fed6e3SChanwoo Choi DIV_TOP2, 20, 3), 80581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 80681fed6e3SChanwoo Choi "mout_aclk300_disp1", DIV_TOP2, 24, 3), 80781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 80881fed6e3SChanwoo Choi DIV_TOP2, 28, 3), 8091609027fSChander Kashyap 8101609027fSChander Kashyap /* DISP1 Block */ 811424b673aSShaik Ameer Basha DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 812cba9d2faSAndrzej Hajda DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 813cba9d2faSAndrzej Hajda DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 814cba9d2faSAndrzej Hajda DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 81581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 81681fed6e3SChanwoo Choi "mout_aclk400_disp1", DIV_TOP2, 4, 3), 8171609027fSChander Kashyap 818e867e8faSChanwoo Choi /* CDREX Block */ 8192f57b95cSLukasz Luba /* 8202f57b95cSLukasz Luba * The three clocks below are controlled using the same register and 8212f57b95cSLukasz Luba * bits. They are put into one because there is a need of 8222f57b95cSLukasz Luba * synchronization between the BUS and DREXs (two external memory 8232f57b95cSLukasz Luba * interfaces). 8242f57b95cSLukasz Luba * They are put here to show this HW assumption and for clock 8252f57b95cSLukasz Luba * information summary completeness. 8262f57b95cSLukasz Luba */ 8272f57b95cSLukasz Luba DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", 8282f57b95cSLukasz Luba DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 8292f57b95cSLukasz Luba DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0", 8302f57b95cSLukasz Luba DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 8312f57b95cSLukasz Luba DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0", 8322f57b95cSLukasz Luba DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 8332f57b95cSLukasz Luba 834e867e8faSChanwoo Choi DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", 835e867e8faSChanwoo Choi DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), 836e867e8faSChanwoo Choi DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", 837e867e8faSChanwoo Choi DIV_CDREX0, 16, 3), 838e867e8faSChanwoo Choi DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", 839e867e8faSChanwoo Choi DIV_CDREX0, 8, 3), 840e867e8faSChanwoo Choi DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", 841e867e8faSChanwoo Choi DIV_CDREX0, 3, 5), 842e867e8faSChanwoo Choi 843e867e8faSChanwoo Choi DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", 844e867e8faSChanwoo Choi DIV_CDREX1, 8, 3), 845e867e8faSChanwoo Choi 8461609027fSChander Kashyap /* Audio Block */ 847cba9d2faSAndrzej Hajda DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 848cba9d2faSAndrzej Hajda DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 8491609027fSChander Kashyap 8501609027fSChander Kashyap /* USB3.0 */ 851cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 852cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 853cba9d2faSAndrzej Hajda DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 854cba9d2faSAndrzej Hajda DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 8551609027fSChander Kashyap 8561609027fSChander Kashyap /* MMC */ 857cba9d2faSAndrzej Hajda DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 858cba9d2faSAndrzej Hajda DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 859cba9d2faSAndrzej Hajda DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 8601609027fSChander Kashyap 861cba9d2faSAndrzej Hajda DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 8626b5ae463SShaik Ameer Basha DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 8631609027fSChander Kashyap 8641609027fSChander Kashyap /* UART and PWM */ 865cba9d2faSAndrzej Hajda DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 866cba9d2faSAndrzej Hajda DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 867cba9d2faSAndrzej Hajda DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 868cba9d2faSAndrzej Hajda DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 869cba9d2faSAndrzej Hajda DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 8701609027fSChander Kashyap 8711609027fSChander Kashyap /* SPI */ 872cba9d2faSAndrzej Hajda DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 873cba9d2faSAndrzej Hajda DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 874cba9d2faSAndrzej Hajda DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 8751609027fSChander Kashyap 8761d87db4dSShaik Ameer Basha 8771609027fSChander Kashyap /* PCM */ 878cba9d2faSAndrzej Hajda DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 879cba9d2faSAndrzej Hajda DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 8801609027fSChander Kashyap 8811609027fSChander Kashyap /* Audio - I2S */ 882cba9d2faSAndrzej Hajda DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 883cba9d2faSAndrzej Hajda DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 884cba9d2faSAndrzej Hajda DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 885cba9d2faSAndrzej Hajda DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 886cba9d2faSAndrzej Hajda DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 8871609027fSChander Kashyap 8881609027fSChander Kashyap /* SPI Pre-Ratio */ 889faec151bSShaik Ameer Basha DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 890faec151bSShaik Ameer Basha DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 891faec151bSShaik Ameer Basha DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 8923a767b35SShaik Ameer Basha 89302932381SShaik Ameer Basha /* GSCL Block */ 89402932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 89502932381SShaik Ameer Basha 8964549d93dSShaik Ameer Basha /* MSCL Block */ 8974549d93dSShaik Ameer Basha DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 8984549d93dSShaik Ameer Basha 8990a22c306SShaik Ameer Basha /* PSGEN */ 9000a22c306SShaik Ameer Basha DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 9010a22c306SShaik Ameer Basha DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 9020a22c306SShaik Ameer Basha 9033a767b35SShaik Ameer Basha /* ISP Block */ 9043a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 9053a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 9063a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 9073a767b35SShaik Ameer Basha DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 9083a767b35SShaik Ameer Basha DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 9093a767b35SShaik Ameer Basha DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 9103a767b35SShaik Ameer Basha DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 9113a767b35SShaik Ameer Basha DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 9123a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 9133a767b35SShaik Ameer Basha DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 9143a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 9151609027fSChander Kashyap }; 9161609027fSChander Kashyap 917ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 9185b73721bSNaveen Krishna Chatradhi /* G2D */ 9193fac5941SShaik Ameer Basha GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 9205b73721bSNaveen Krishna Chatradhi GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 9213fac5941SShaik Ameer Basha GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 9223fac5941SShaik Ameer Basha GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 9233fac5941SShaik Ameer Basha GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 9245b73721bSNaveen Krishna Chatradhi 9251609027fSChander Kashyap GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 926318fa46cSMarek Szyprowski GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), 9271609027fSChander Kashyap GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 9281609027fSChander Kashyap GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 9291609027fSChander Kashyap 9301609027fSChander Kashyap GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 9311609027fSChander Kashyap GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 9321609027fSChander Kashyap GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 933318fa46cSMarek Szyprowski GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), 9341609027fSChander Kashyap GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 9351609027fSChander Kashyap GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 9363a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 9373a767b35SShaik Ameer Basha GATE_BUS_TOP, 5, 0, 0), 9381609027fSChander Kashyap GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 939318fa46cSMarek Szyprowski GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), 9401609027fSChander Kashyap GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 9411609027fSChander Kashyap GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 9423a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 9433a767b35SShaik Ameer Basha GATE_BUS_TOP, 8, 0, 0), 944b31ca2a0SShaik Ameer Basha GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 9451609027fSChander Kashyap GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 946faec151bSShaik Ameer Basha GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 9471609027fSChander Kashyap GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 9483a767b35SShaik Ameer Basha GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 9493a767b35SShaik Ameer Basha GATE_BUS_TOP, 13, 0, 0), 9501609027fSChander Kashyap GATE(0, "aclk166", "mout_user_aclk166", 9511609027fSChander Kashyap GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 95234cba900SJavier Martinez Canillas GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", 953318fa46cSMarek Szyprowski GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), 9543a767b35SShaik Ameer Basha GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 9553a767b35SShaik Ameer Basha GATE_BUS_TOP, 16, 0, 0), 95602932381SShaik Ameer Basha GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 957c07c1a0fSAndrzej Pietrasiewicz GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), 958424b673aSShaik Ameer Basha GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 959318fa46cSMarek Szyprowski GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), 960b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 961b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 28, 0, 0), 962b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 963b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 29, 0, 0), 964424b673aSShaik Ameer Basha 965424b673aSShaik Ameer Basha GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 966318fa46cSMarek Szyprowski SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), 9671609027fSChander Kashyap 9681609027fSChander Kashyap /* sclk */ 969cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 9701609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 971cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 9721609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 973cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 9741609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 975cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 9761609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 977faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 9781609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 979faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 9801609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 981faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 9821609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 983cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 9841609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 985cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 9861609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 987cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 9881609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 989cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 9901609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 991cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 9921609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 993cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 9941609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 9951609027fSChander Kashyap 996cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 9971609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 998cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 9991609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 1000cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 10011609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 1002cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 10031609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 1004cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 10051609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 1006cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 10071609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 1008cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 10091609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 10101609027fSChander Kashyap 10111609027fSChander Kashyap /* Display */ 1012cba9d2faSAndrzej Hajda GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 10131609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 1014cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 10151609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 1016cba9d2faSAndrzej Hajda GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 1017424b673aSShaik Ameer Basha GATE_TOP_SCLK_DISP1, 9, 0, 0), 1018cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 10191609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 1020cba9d2faSAndrzej Hajda GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 10211609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 10221609027fSChander Kashyap 10231609027fSChander Kashyap /* Maudio Block */ 1024cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 10251609027fSChander Kashyap GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1026cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 10271609027fSChander Kashyap GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 10286b5ae463SShaik Ameer Basha 10296b5ae463SShaik Ameer Basha /* FSYS Block */ 1030cba9d2faSAndrzej Hajda GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1031cba9d2faSAndrzej Hajda GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1032cba9d2faSAndrzej Hajda GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1033cba9d2faSAndrzej Hajda GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 10346b5ae463SShaik Ameer Basha GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 10356b5ae463SShaik Ameer Basha GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 10366b5ae463SShaik Ameer Basha GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 10376b5ae463SShaik Ameer Basha GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1038cba9d2faSAndrzej Hajda GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 10396b5ae463SShaik Ameer Basha GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 10406b5ae463SShaik Ameer Basha GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 10416b5ae463SShaik Ameer Basha GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 10426b5ae463SShaik Ameer Basha GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 10436b5ae463SShaik Ameer Basha GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 10446b5ae463SShaik Ameer Basha SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 10451609027fSChander Kashyap 1046faec151bSShaik Ameer Basha /* PERIC Block */ 104744ff0254SDoug Anderson GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 104844ff0254SDoug Anderson GATE_IP_PERIC, 0, 0, 0), 104944ff0254SDoug Anderson GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 105044ff0254SDoug Anderson GATE_IP_PERIC, 1, 0, 0), 105144ff0254SDoug Anderson GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 105244ff0254SDoug Anderson GATE_IP_PERIC, 2, 0, 0), 105344ff0254SDoug Anderson GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 105444ff0254SDoug Anderson GATE_IP_PERIC, 3, 0, 0), 105544ff0254SDoug Anderson GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 105644ff0254SDoug Anderson GATE_IP_PERIC, 6, 0, 0), 105744ff0254SDoug Anderson GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 105844ff0254SDoug Anderson GATE_IP_PERIC, 7, 0, 0), 105944ff0254SDoug Anderson GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 106044ff0254SDoug Anderson GATE_IP_PERIC, 8, 0, 0), 106144ff0254SDoug Anderson GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 106244ff0254SDoug Anderson GATE_IP_PERIC, 9, 0, 0), 106344ff0254SDoug Anderson GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 106444ff0254SDoug Anderson GATE_IP_PERIC, 10, 0, 0), 106544ff0254SDoug Anderson GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 106644ff0254SDoug Anderson GATE_IP_PERIC, 11, 0, 0), 106744ff0254SDoug Anderson GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 106844ff0254SDoug Anderson GATE_IP_PERIC, 12, 0, 0), 106944ff0254SDoug Anderson GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 107044ff0254SDoug Anderson GATE_IP_PERIC, 13, 0, 0), 107144ff0254SDoug Anderson GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 107244ff0254SDoug Anderson GATE_IP_PERIC, 14, 0, 0), 107344ff0254SDoug Anderson GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 107444ff0254SDoug Anderson GATE_IP_PERIC, 15, 0, 0), 107544ff0254SDoug Anderson GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 107644ff0254SDoug Anderson GATE_IP_PERIC, 16, 0, 0), 107744ff0254SDoug Anderson GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 107844ff0254SDoug Anderson GATE_IP_PERIC, 17, 0, 0), 107944ff0254SDoug Anderson GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 108044ff0254SDoug Anderson GATE_IP_PERIC, 18, 0, 0), 108144ff0254SDoug Anderson GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 108244ff0254SDoug Anderson GATE_IP_PERIC, 20, 0, 0), 108344ff0254SDoug Anderson GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 108444ff0254SDoug Anderson GATE_IP_PERIC, 21, 0, 0), 108544ff0254SDoug Anderson GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 108644ff0254SDoug Anderson GATE_IP_PERIC, 22, 0, 0), 108744ff0254SDoug Anderson GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 108844ff0254SDoug Anderson GATE_IP_PERIC, 23, 0, 0), 108944ff0254SDoug Anderson GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 109044ff0254SDoug Anderson GATE_IP_PERIC, 24, 0, 0), 109144ff0254SDoug Anderson GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 109244ff0254SDoug Anderson GATE_IP_PERIC, 26, 0, 0), 109344ff0254SDoug Anderson GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 109444ff0254SDoug Anderson GATE_IP_PERIC, 28, 0, 0), 109544ff0254SDoug Anderson GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 109644ff0254SDoug Anderson GATE_IP_PERIC, 30, 0, 0), 109744ff0254SDoug Anderson GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 109844ff0254SDoug Anderson GATE_IP_PERIC, 31, 0, 0), 10991609027fSChander Kashyap 110044ff0254SDoug Anderson GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 110144ff0254SDoug Anderson GATE_BUS_PERIC, 22, 0, 0), 11021609027fSChander Kashyap 11030a22c306SShaik Ameer Basha /* PERIS Block */ 1104cba9d2faSAndrzej Hajda GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 11050a22c306SShaik Ameer Basha GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1106cba9d2faSAndrzej Hajda GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 11070a22c306SShaik Ameer Basha GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 11080a22c306SShaik Ameer Basha GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 11090a22c306SShaik Ameer Basha GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 11100a22c306SShaik Ameer Basha GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 11110a22c306SShaik Ameer Basha GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 11120a22c306SShaik Ameer Basha GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 11130a22c306SShaik Ameer Basha GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 11140a22c306SShaik Ameer Basha GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 11150a22c306SShaik Ameer Basha GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 11160a22c306SShaik Ameer Basha GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 11170a22c306SShaik Ameer Basha GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 11180a22c306SShaik Ameer Basha GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 11190a22c306SShaik Ameer Basha GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 11200a22c306SShaik Ameer Basha GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 11210a22c306SShaik Ameer Basha GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 11220a22c306SShaik Ameer Basha GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 11230a22c306SShaik Ameer Basha GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 11241609027fSChander Kashyap 11250a22c306SShaik Ameer Basha /* GEN Block */ 11260a22c306SShaik Ameer Basha GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 11270a22c306SShaik Ameer Basha GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 11280a22c306SShaik Ameer Basha GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 11290a22c306SShaik Ameer Basha GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 11300a22c306SShaik Ameer Basha GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 11310a22c306SShaik Ameer Basha GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 11320a22c306SShaik Ameer Basha GATE_IP_GEN, 6, 0, 0), 11330a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 11340a22c306SShaik Ameer Basha GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 11350a22c306SShaik Ameer Basha GATE_IP_GEN, 9, 0, 0), 11360a22c306SShaik Ameer Basha 11370a22c306SShaik Ameer Basha /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 11380a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 11390a22c306SShaik Ameer Basha GATE_BUS_GEN, 28, 0, 0), 11400a22c306SShaik Ameer Basha GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 11411609027fSChander Kashyap 114202932381SShaik Ameer Basha /* GSCL Block */ 114302932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 114402932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 6, 0, 0), 114502932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 114602932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 7, 0, 0), 114702932381SShaik Ameer Basha 114802932381SShaik Ameer Basha GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 114902932381SShaik Ameer Basha GATE_IP_GSCL0, 4, 0, 0), 115002932381SShaik Ameer Basha GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 115102932381SShaik Ameer Basha GATE_IP_GSCL0, 5, 0, 0), 115202932381SShaik Ameer Basha GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 115302932381SShaik Ameer Basha GATE_IP_GSCL0, 6, 0, 0), 11541609027fSChander Kashyap 115502932381SShaik Ameer Basha GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 115602932381SShaik Ameer Basha GATE_IP_GSCL1, 2, 0, 0), 115702932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 11581609027fSChander Kashyap GATE_IP_GSCL1, 3, 0, 0), 115902932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 11601609027fSChander Kashyap GATE_IP_GSCL1, 4, 0, 0), 116102932381SShaik Ameer Basha GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 116202932381SShaik Ameer Basha GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 116302932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 11641609027fSChander Kashyap GATE_IP_GSCL1, 16, 0, 0), 1165cba9d2faSAndrzej Hajda GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 11661609027fSChander Kashyap GATE_IP_GSCL1, 17, 0, 0), 11671609027fSChander Kashyap 116802932381SShaik Ameer Basha /* MSCL Block */ 116902932381SShaik Ameer Basha GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 117002932381SShaik Ameer Basha GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 117102932381SShaik Ameer Basha GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 11724549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 117302932381SShaik Ameer Basha GATE_IP_MSCL, 8, 0, 0), 11744549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 117502932381SShaik Ameer Basha GATE_IP_MSCL, 9, 0, 0), 11764549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 117702932381SShaik Ameer Basha GATE_IP_MSCL, 10, 0, 0), 117802932381SShaik Ameer Basha 11793a767b35SShaik Ameer Basha /* ISP */ 11803a767b35SShaik Ameer Basha GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 11813a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 11823a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 11833a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 11843a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 11853a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 11863a767b35SShaik Ameer Basha GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 11873a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 11883a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 11893a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 11903a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 11913a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 11923a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 11933a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 11943a767b35SShaik Ameer Basha 1195ec4016ffSMarek Szyprowski GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 11962f57b95cSLukasz Luba 11972f57b95cSLukasz Luba /* CDREX */ 11982f57b95cSLukasz Luba GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", 11992f57b95cSLukasz Luba GATE_BUS_CDREX0, 0, 0, 0), 12002f57b95cSLukasz Luba GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex", 12012f57b95cSLukasz Luba GATE_BUS_CDREX0, 1, 0, 0), 12022f57b95cSLukasz Luba GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy", 12032f57b95cSLukasz Luba SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0), 12042f57b95cSLukasz Luba 12052f57b95cSLukasz Luba GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1", 12062f57b95cSLukasz Luba GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0), 12072f57b95cSLukasz Luba GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1", 12082f57b95cSLukasz Luba GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0), 12092f57b95cSLukasz Luba GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1", 12102f57b95cSLukasz Luba GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0), 12112f57b95cSLukasz Luba GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1", 12122f57b95cSLukasz Luba GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0), 12132f57b95cSLukasz Luba 12142f57b95cSLukasz Luba GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex", 12152f57b95cSLukasz Luba GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0), 12162f57b95cSLukasz Luba GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex", 12172f57b95cSLukasz Luba GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0), 12182f57b95cSLukasz Luba GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex", 12192f57b95cSLukasz Luba GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0), 12202f57b95cSLukasz Luba GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex", 12212f57b95cSLukasz Luba GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0), 1222ec4016ffSMarek Szyprowski }; 1223ec4016ffSMarek Szyprowski 1224ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { 1225ec4016ffSMarek Szyprowski DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 1226ec4016ffSMarek Szyprowski }; 1227ec4016ffSMarek Szyprowski 1228ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { 1229ec4016ffSMarek Szyprowski GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1230ec4016ffSMarek Szyprowski GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1231ec4016ffSMarek Szyprowski GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1232ec4016ffSMarek Szyprowski GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1233ec4016ffSMarek Szyprowski GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1234ec4016ffSMarek Szyprowski GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1235ec4016ffSMarek Szyprowski GATE_IP_DISP1, 7, 0, 0), 1236ec4016ffSMarek Szyprowski GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1237ec4016ffSMarek Szyprowski GATE_IP_DISP1, 8, 0, 0), 1238ec4016ffSMarek Szyprowski GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1239ec4016ffSMarek Szyprowski GATE_IP_DISP1, 9, 0, 0), 1240ec4016ffSMarek Szyprowski }; 1241ec4016ffSMarek Szyprowski 1242ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = { 1243ec4016ffSMarek Szyprowski { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ 1244ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ 1245ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ 1246ec4016ffSMarek Szyprowski { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ 1247ec4016ffSMarek Szyprowski { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ 1248ec4016ffSMarek Szyprowski }; 1249ec4016ffSMarek Szyprowski 1250ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { 1251ec4016ffSMarek Szyprowski DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 1252ec4016ffSMarek Szyprowski DIV2_RATIO0, 4, 2), 1253ec4016ffSMarek Szyprowski }; 1254ec4016ffSMarek Szyprowski 1255ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { 1256ec4016ffSMarek Szyprowski GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1257ec4016ffSMarek Szyprowski GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1258ec4016ffSMarek Szyprowski GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 1259ec4016ffSMarek Szyprowski GATE_IP_GSCL1, 6, 0, 0), 1260ec4016ffSMarek Szyprowski GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 1261ec4016ffSMarek Szyprowski GATE_IP_GSCL1, 7, 0, 0), 1262ec4016ffSMarek Szyprowski }; 1263ec4016ffSMarek Szyprowski 1264ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { 1265ec4016ffSMarek Szyprowski { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ 1266ec4016ffSMarek Szyprowski { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ 1267ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ 1268ec4016ffSMarek Szyprowski { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ 1269ec4016ffSMarek Szyprowski }; 1270ec4016ffSMarek Szyprowski 1271ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { 1272ec4016ffSMarek Szyprowski DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 1273ec4016ffSMarek Szyprowski }; 1274ec4016ffSMarek Szyprowski 1275ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { 1276cba9d2faSAndrzej Hajda GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 12771d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 12781d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 1279ec4016ffSMarek Szyprowski }; 12801609027fSChander Kashyap 1281ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { 1282ec4016ffSMarek Szyprowski { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ 1283ec4016ffSMarek Szyprowski { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ 1284ec4016ffSMarek Szyprowski { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ 1285ec4016ffSMarek Szyprowski }; 1286ec4016ffSMarek Szyprowski 1287ec4016ffSMarek Szyprowski static const struct exynos5_subcmu_info exynos5x_subcmus[] = { 1288ec4016ffSMarek Szyprowski { 1289ec4016ffSMarek Szyprowski .div_clks = exynos5x_disp_div_clks, 1290ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), 1291ec4016ffSMarek Szyprowski .gate_clks = exynos5x_disp_gate_clks, 1292ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), 1293ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_disp_suspend_regs, 1294ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), 1295ec4016ffSMarek Szyprowski .pd_name = "DISP", 1296ec4016ffSMarek Szyprowski }, { 1297ec4016ffSMarek Szyprowski .div_clks = exynos5x_gsc_div_clks, 1298ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), 1299ec4016ffSMarek Szyprowski .gate_clks = exynos5x_gsc_gate_clks, 1300ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), 1301ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_gsc_suspend_regs, 1302ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), 1303ec4016ffSMarek Szyprowski .pd_name = "GSC", 1304ec4016ffSMarek Szyprowski }, { 1305ec4016ffSMarek Szyprowski .div_clks = exynos5x_mfc_div_clks, 1306ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), 1307ec4016ffSMarek Szyprowski .gate_clks = exynos5x_mfc_gate_clks, 1308ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), 1309ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_mfc_suspend_regs, 1310ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), 1311ec4016ffSMarek Szyprowski .pd_name = "MFC", 1312ec4016ffSMarek Szyprowski }, 13131609027fSChander Kashyap }; 13141609027fSChander Kashyap 1315ebd217e1SKrzysztof Kozlowski static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { 13161d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0), 13171d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0), 13181d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0), 13191d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), 13201d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 13211d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 13221d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 13231d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 13241d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1), 13251d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), 13261d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), 13271d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1), 13281d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), 13291d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 13301d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2), 13311d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), 13321d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), 13331d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3), 13341d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), 1335ca5b4029SThomas Abraham }; 1336ca5b4029SThomas Abraham 13378b4a7acfSLukasz Luba static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { 13388b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), 13398b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), 13408b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), 13418b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), 13428b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), 13438b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), 13448b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), 13458b4a7acfSLukasz Luba PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), 13468b4a7acfSLukasz Luba }; 13478b4a7acfSLukasz Luba 13489842452aSSylwester Nawrocki static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 13491d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), 13501d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), 13511d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), 13521d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671), 13531d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0), 13541d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), 13551d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671), 13561d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719), 13571d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0), 1358948e0684SSylwester Nawrocki PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923), 1359948e0684SSylwester Nawrocki PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762), 13601d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719), 13611d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690), 1362948e0684SSylwester Nawrocki PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762), 13631d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), 13649842452aSSylwester Nawrocki }; 13659842452aSSylwester Nawrocki 13666520e968SAlim Akhtar static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1367cba9d2faSAndrzej Hajda [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 13683ff6e0d8SYadwinder Singh Brar APLL_CON0, NULL), 1369cba9d2faSAndrzej Hajda [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1370cdf64eeeSChander Kashyap CPLL_CON0, NULL), 1371cba9d2faSAndrzej Hajda [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 13723ff6e0d8SYadwinder Singh Brar DPLL_CON0, NULL), 13739842452aSSylwester Nawrocki [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 13743ff6e0d8SYadwinder Singh Brar EPLL_CON0, NULL), 1375cba9d2faSAndrzej Hajda [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 13763ff6e0d8SYadwinder Singh Brar RPLL_CON0, NULL), 1377cba9d2faSAndrzej Hajda [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 13783ff6e0d8SYadwinder Singh Brar IPLL_CON0, NULL), 1379cba9d2faSAndrzej Hajda [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 13803ff6e0d8SYadwinder Singh Brar SPLL_CON0, NULL), 1381cba9d2faSAndrzej Hajda [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 13823ff6e0d8SYadwinder Singh Brar VPLL_CON0, NULL), 1383cba9d2faSAndrzej Hajda [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 13843ff6e0d8SYadwinder Singh Brar MPLL_CON0, NULL), 1385cba9d2faSAndrzej Hajda [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 13863ff6e0d8SYadwinder Singh Brar BPLL_CON0, NULL), 1387cba9d2faSAndrzej Hajda [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 13883ff6e0d8SYadwinder Singh Brar KPLL_CON0, NULL), 1389c898c6b7SYadwinder Singh Brar }; 1390c898c6b7SYadwinder Singh Brar 1391bee4f87fSThomas Abraham #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1392bee4f87fSThomas Abraham ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1393bee4f87fSThomas Abraham ((cpud) << 4))) 1394bee4f87fSThomas Abraham 1395bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1396bee4f87fSThomas Abraham { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1397bee4f87fSThomas Abraham { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1398bee4f87fSThomas Abraham { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1399bee4f87fSThomas Abraham { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1400bee4f87fSThomas Abraham { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1401bee4f87fSThomas Abraham { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1402bee4f87fSThomas Abraham { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1403bee4f87fSThomas Abraham { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1404bee4f87fSThomas Abraham { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1405bee4f87fSThomas Abraham { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1406bee4f87fSThomas Abraham { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1407bee4f87fSThomas Abraham { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1408bee4f87fSThomas Abraham { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1409bee4f87fSThomas Abraham { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1410bee4f87fSThomas Abraham { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1411bee4f87fSThomas Abraham { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1412bee4f87fSThomas Abraham { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1413bee4f87fSThomas Abraham { 0 }, 1414bee4f87fSThomas Abraham }; 1415bee4f87fSThomas Abraham 141654abbdb4SBartlomiej Zolnierkiewicz static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 141754abbdb4SBartlomiej Zolnierkiewicz { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 141854abbdb4SBartlomiej Zolnierkiewicz { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 141954abbdb4SBartlomiej Zolnierkiewicz { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 142054abbdb4SBartlomiej Zolnierkiewicz { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 142154abbdb4SBartlomiej Zolnierkiewicz { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 142254abbdb4SBartlomiej Zolnierkiewicz { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 142354abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 142454abbdb4SBartlomiej Zolnierkiewicz { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 142554abbdb4SBartlomiej Zolnierkiewicz { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 142654abbdb4SBartlomiej Zolnierkiewicz { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 142754abbdb4SBartlomiej Zolnierkiewicz { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 142854abbdb4SBartlomiej Zolnierkiewicz { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 142954abbdb4SBartlomiej Zolnierkiewicz { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 143054abbdb4SBartlomiej Zolnierkiewicz { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 143154abbdb4SBartlomiej Zolnierkiewicz { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 143254abbdb4SBartlomiej Zolnierkiewicz { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 143354abbdb4SBartlomiej Zolnierkiewicz { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 143454abbdb4SBartlomiej Zolnierkiewicz { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 143554abbdb4SBartlomiej Zolnierkiewicz { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 143654abbdb4SBartlomiej Zolnierkiewicz { 0 }, 143754abbdb4SBartlomiej Zolnierkiewicz }; 143854abbdb4SBartlomiej Zolnierkiewicz 1439bee4f87fSThomas Abraham #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1440bee4f87fSThomas Abraham ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1441bee4f87fSThomas Abraham 1442bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 144354abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1444bee4f87fSThomas Abraham { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1445bee4f87fSThomas Abraham { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1446bee4f87fSThomas Abraham { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1447bee4f87fSThomas Abraham { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1448bee4f87fSThomas Abraham { 900000, E5420_KFC_DIV(3, 5, 2), }, 1449bee4f87fSThomas Abraham { 800000, E5420_KFC_DIV(3, 5, 2), }, 1450bee4f87fSThomas Abraham { 700000, E5420_KFC_DIV(3, 4, 2), }, 1451bee4f87fSThomas Abraham { 600000, E5420_KFC_DIV(3, 4, 2), }, 1452bee4f87fSThomas Abraham { 500000, E5420_KFC_DIV(3, 4, 2), }, 1453bee4f87fSThomas Abraham { 400000, E5420_KFC_DIV(3, 3, 2), }, 1454bee4f87fSThomas Abraham { 300000, E5420_KFC_DIV(3, 3, 2), }, 1455bee4f87fSThomas Abraham { 200000, E5420_KFC_DIV(3, 3, 2), }, 1456bee4f87fSThomas Abraham { 0 }, 1457bee4f87fSThomas Abraham }; 1458bee4f87fSThomas Abraham 1459305cfab0SKrzysztof Kozlowski static const struct of_device_id ext_clk_match[] __initconst = { 14601609027fSChander Kashyap { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 14611609027fSChander Kashyap { }, 14621609027fSChander Kashyap }; 14631609027fSChander Kashyap 14641609027fSChander Kashyap /* register exynos5420 clocks */ 14656520e968SAlim Akhtar static void __init exynos5x_clk_init(struct device_node *np, 14666520e968SAlim Akhtar enum exynos5x_soc soc) 14671609027fSChander Kashyap { 1468976face4SRahul Sharma struct samsung_clk_provider *ctx; 1469976face4SRahul Sharma 14701609027fSChander Kashyap if (np) { 14711609027fSChander Kashyap reg_base = of_iomap(np, 0); 14721609027fSChander Kashyap if (!reg_base) 14731609027fSChander Kashyap panic("%s: failed to map registers\n", __func__); 14741609027fSChander Kashyap } else { 14751609027fSChander Kashyap panic("%s: unable to determine soc\n", __func__); 14761609027fSChander Kashyap } 14771609027fSChander Kashyap 14786520e968SAlim Akhtar exynos5x_soc = soc; 14796520e968SAlim Akhtar 1480976face4SRahul Sharma ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1481976face4SRahul Sharma 14826520e968SAlim Akhtar samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 14836520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 14841609027fSChander Kashyap ext_clk_match); 1485ca5b4029SThomas Abraham 1486ca5b4029SThomas Abraham if (_get_rate("fin_pll") == 24 * MHZ) { 1487ca5b4029SThomas Abraham exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 14889842452aSSylwester Nawrocki exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; 1489ca5b4029SThomas Abraham exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1490ca5b4029SThomas Abraham } 1491ca5b4029SThomas Abraham 14928b4a7acfSLukasz Luba if (soc == EXYNOS5420) 14938b4a7acfSLukasz Luba exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 14948b4a7acfSLukasz Luba else 14958b4a7acfSLukasz Luba exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; 14968b4a7acfSLukasz Luba 14976520e968SAlim Akhtar samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1498c898c6b7SYadwinder Singh Brar reg_base); 14996520e968SAlim Akhtar samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 15006520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_clks)); 15016520e968SAlim Akhtar samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 15026520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_factor_clks)); 15036520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5x_mux_clks, 15046520e968SAlim Akhtar ARRAY_SIZE(exynos5x_mux_clks)); 15056520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5x_div_clks, 15066520e968SAlim Akhtar ARRAY_SIZE(exynos5x_div_clks)); 15076520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5x_gate_clks, 15086520e968SAlim Akhtar ARRAY_SIZE(exynos5x_gate_clks)); 15096520e968SAlim Akhtar 15106520e968SAlim Akhtar if (soc == EXYNOS5420) { 1511976face4SRahul Sharma samsung_clk_register_mux(ctx, exynos5420_mux_clks, 15121609027fSChander Kashyap ARRAY_SIZE(exynos5420_mux_clks)); 1513976face4SRahul Sharma samsung_clk_register_div(ctx, exynos5420_div_clks, 15141609027fSChander Kashyap ARRAY_SIZE(exynos5420_div_clks)); 151541097f25SSylwester Nawrocki samsung_clk_register_gate(ctx, exynos5420_gate_clks, 151641097f25SSylwester Nawrocki ARRAY_SIZE(exynos5420_gate_clks)); 15176520e968SAlim Akhtar } else { 15186520e968SAlim Akhtar samsung_clk_register_fixed_factor( 15196520e968SAlim Akhtar ctx, exynos5800_fixed_factor_clks, 15206520e968SAlim Akhtar ARRAY_SIZE(exynos5800_fixed_factor_clks)); 15216520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5800_mux_clks, 15226520e968SAlim Akhtar ARRAY_SIZE(exynos5800_mux_clks)); 15236520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5800_div_clks, 15246520e968SAlim Akhtar ARRAY_SIZE(exynos5800_div_clks)); 15256520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5800_gate_clks, 15266520e968SAlim Akhtar ARRAY_SIZE(exynos5800_gate_clks)); 15276520e968SAlim Akhtar } 1528388c7885STomasz Figa 152954abbdb4SBartlomiej Zolnierkiewicz if (soc == EXYNOS5420) { 1530bee4f87fSThomas Abraham exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1531bee4f87fSThomas Abraham mout_cpu_p[0], mout_cpu_p[1], 0x200, 1532bee4f87fSThomas Abraham exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); 153354abbdb4SBartlomiej Zolnierkiewicz } else { 153454abbdb4SBartlomiej Zolnierkiewicz exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 153554abbdb4SBartlomiej Zolnierkiewicz mout_cpu_p[0], mout_cpu_p[1], 0x200, 153654abbdb4SBartlomiej Zolnierkiewicz exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); 153754abbdb4SBartlomiej Zolnierkiewicz } 1538bee4f87fSThomas Abraham exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", 1539bee4f87fSThomas Abraham mout_kfc_p[0], mout_kfc_p[1], 0x28200, 1540bee4f87fSThomas Abraham exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); 1541bee4f87fSThomas Abraham 15422d77f77cSMarek Szyprowski samsung_clk_extended_sleep_init(reg_base, 15432d77f77cSMarek Szyprowski exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs), 15442d77f77cSMarek Szyprowski exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); 15452d77f77cSMarek Szyprowski if (soc == EXYNOS5800) 15462d77f77cSMarek Szyprowski samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, 15472d77f77cSMarek Szyprowski ARRAY_SIZE(exynos5800_clk_regs)); 1548ec4016ffSMarek Szyprowski exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), 1549ec4016ffSMarek Szyprowski exynos5x_subcmus); 1550d5e136a2SSylwester Nawrocki 1551d5e136a2SSylwester Nawrocki samsung_clk_of_add_provider(np, ctx); 15521609027fSChander Kashyap } 15536520e968SAlim Akhtar 15546520e968SAlim Akhtar static void __init exynos5420_clk_init(struct device_node *np) 15556520e968SAlim Akhtar { 15566520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5420); 15576520e968SAlim Akhtar } 1558ec4016ffSMarek Szyprowski CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", 1559ec4016ffSMarek Szyprowski exynos5420_clk_init); 15606520e968SAlim Akhtar 15616520e968SAlim Akhtar static void __init exynos5800_clk_init(struct device_node *np) 15626520e968SAlim Akhtar { 15636520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5800); 15646520e968SAlim Akhtar } 1565ec4016ffSMarek Szyprowski CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", 1566ec4016ffSMarek Szyprowski exynos5800_clk_init); 1567