11609027fSChander Kashyap /* 21609027fSChander Kashyap * Copyright (c) 2013 Samsung Electronics Co., Ltd. 31609027fSChander Kashyap * Authors: Thomas Abraham <thomas.ab@samsung.com> 41609027fSChander Kashyap * Chander Kashyap <k.chander@samsung.com> 51609027fSChander Kashyap * 61609027fSChander Kashyap * This program is free software; you can redistribute it and/or modify 71609027fSChander Kashyap * it under the terms of the GNU General Public License version 2 as 81609027fSChander Kashyap * published by the Free Software Foundation. 91609027fSChander Kashyap * 101609027fSChander Kashyap * Common Clock Framework support for Exynos5420 SoC. 111609027fSChander Kashyap */ 121609027fSChander Kashyap 13cba9d2faSAndrzej Hajda #include <dt-bindings/clock/exynos5420.h> 146f1ed07aSStephen Boyd #include <linux/slab.h> 151609027fSChander Kashyap #include <linux/clk-provider.h> 161609027fSChander Kashyap #include <linux/of.h> 171609027fSChander Kashyap #include <linux/of_address.h> 18388c7885STomasz Figa #include <linux/syscore_ops.h> 191609027fSChander Kashyap 201609027fSChander Kashyap #include "clk.h" 21bee4f87fSThomas Abraham #include "clk-cpu.h" 22ec4016ffSMarek Szyprowski #include "clk-exynos5-subcmu.h" 231609027fSChander Kashyap 24c898c6b7SYadwinder Singh Brar #define APLL_LOCK 0x0 25c898c6b7SYadwinder Singh Brar #define APLL_CON0 0x100 261609027fSChander Kashyap #define SRC_CPU 0x200 271609027fSChander Kashyap #define DIV_CPU0 0x500 281609027fSChander Kashyap #define DIV_CPU1 0x504 291609027fSChander Kashyap #define GATE_BUS_CPU 0x700 301609027fSChander Kashyap #define GATE_SCLK_CPU 0x800 3177342432SShaik Ameer Basha #define CLKOUT_CMU_CPU 0xa00 32e9d52956SVikas Sajjan #define SRC_MASK_CPERI 0x4300 335b73721bSNaveen Krishna Chatradhi #define GATE_IP_G2D 0x8800 34c898c6b7SYadwinder Singh Brar #define CPLL_LOCK 0x10020 35c898c6b7SYadwinder Singh Brar #define DPLL_LOCK 0x10030 36c898c6b7SYadwinder Singh Brar #define EPLL_LOCK 0x10040 37c898c6b7SYadwinder Singh Brar #define RPLL_LOCK 0x10050 38c898c6b7SYadwinder Singh Brar #define IPLL_LOCK 0x10060 39c898c6b7SYadwinder Singh Brar #define SPLL_LOCK 0x10070 4053cb6342SSachin Kamat #define VPLL_LOCK 0x10080 41c898c6b7SYadwinder Singh Brar #define MPLL_LOCK 0x10090 42c898c6b7SYadwinder Singh Brar #define CPLL_CON0 0x10120 43c898c6b7SYadwinder Singh Brar #define DPLL_CON0 0x10128 44c898c6b7SYadwinder Singh Brar #define EPLL_CON0 0x10130 4577342432SShaik Ameer Basha #define EPLL_CON1 0x10134 4677342432SShaik Ameer Basha #define EPLL_CON2 0x10138 47c898c6b7SYadwinder Singh Brar #define RPLL_CON0 0x10140 4877342432SShaik Ameer Basha #define RPLL_CON1 0x10144 4977342432SShaik Ameer Basha #define RPLL_CON2 0x10148 50c898c6b7SYadwinder Singh Brar #define IPLL_CON0 0x10150 51c898c6b7SYadwinder Singh Brar #define SPLL_CON0 0x10160 52c898c6b7SYadwinder Singh Brar #define VPLL_CON0 0x10170 53c898c6b7SYadwinder Singh Brar #define MPLL_CON0 0x10180 541609027fSChander Kashyap #define SRC_TOP0 0x10200 551609027fSChander Kashyap #define SRC_TOP1 0x10204 561609027fSChander Kashyap #define SRC_TOP2 0x10208 571609027fSChander Kashyap #define SRC_TOP3 0x1020c 581609027fSChander Kashyap #define SRC_TOP4 0x10210 591609027fSChander Kashyap #define SRC_TOP5 0x10214 601609027fSChander Kashyap #define SRC_TOP6 0x10218 611609027fSChander Kashyap #define SRC_TOP7 0x1021c 626520e968SAlim Akhtar #define SRC_TOP8 0x10220 /* 5800 specific */ 636520e968SAlim Akhtar #define SRC_TOP9 0x10224 /* 5800 specific */ 641609027fSChander Kashyap #define SRC_DISP10 0x1022c 651609027fSChander Kashyap #define SRC_MAU 0x10240 661609027fSChander Kashyap #define SRC_FSYS 0x10244 671609027fSChander Kashyap #define SRC_PERIC0 0x10250 681609027fSChander Kashyap #define SRC_PERIC1 0x10254 693a767b35SShaik Ameer Basha #define SRC_ISP 0x10270 706520e968SAlim Akhtar #define SRC_CAM 0x10274 /* 5800 specific */ 711609027fSChander Kashyap #define SRC_TOP10 0x10280 721609027fSChander Kashyap #define SRC_TOP11 0x10284 731609027fSChander Kashyap #define SRC_TOP12 0x10288 746520e968SAlim Akhtar #define SRC_TOP13 0x1028c /* 5800 specific */ 75e9d52956SVikas Sajjan #define SRC_MASK_TOP0 0x10300 76e9d52956SVikas Sajjan #define SRC_MASK_TOP1 0x10304 77424b673aSShaik Ameer Basha #define SRC_MASK_TOP2 0x10308 7831116a64SShaik Ameer Basha #define SRC_MASK_TOP7 0x1031c 791609027fSChander Kashyap #define SRC_MASK_DISP10 0x1032c 8031116a64SShaik Ameer Basha #define SRC_MASK_MAU 0x10334 811609027fSChander Kashyap #define SRC_MASK_FSYS 0x10340 821609027fSChander Kashyap #define SRC_MASK_PERIC0 0x10350 831609027fSChander Kashyap #define SRC_MASK_PERIC1 0x10354 84e9d52956SVikas Sajjan #define SRC_MASK_ISP 0x10370 851609027fSChander Kashyap #define DIV_TOP0 0x10500 861609027fSChander Kashyap #define DIV_TOP1 0x10504 871609027fSChander Kashyap #define DIV_TOP2 0x10508 886520e968SAlim Akhtar #define DIV_TOP8 0x10520 /* 5800 specific */ 896520e968SAlim Akhtar #define DIV_TOP9 0x10524 /* 5800 specific */ 901609027fSChander Kashyap #define DIV_DISP10 0x1052c 911609027fSChander Kashyap #define DIV_MAU 0x10544 921609027fSChander Kashyap #define DIV_FSYS0 0x10548 931609027fSChander Kashyap #define DIV_FSYS1 0x1054c 941609027fSChander Kashyap #define DIV_FSYS2 0x10550 951609027fSChander Kashyap #define DIV_PERIC0 0x10558 961609027fSChander Kashyap #define DIV_PERIC1 0x1055c 971609027fSChander Kashyap #define DIV_PERIC2 0x10560 981609027fSChander Kashyap #define DIV_PERIC3 0x10564 991609027fSChander Kashyap #define DIV_PERIC4 0x10568 1006520e968SAlim Akhtar #define DIV_CAM 0x10574 /* 5800 specific */ 1013a767b35SShaik Ameer Basha #define SCLK_DIV_ISP0 0x10580 1023a767b35SShaik Ameer Basha #define SCLK_DIV_ISP1 0x10584 10302932381SShaik Ameer Basha #define DIV2_RATIO0 0x10590 1041d87db4dSShaik Ameer Basha #define DIV4_RATIO 0x105a0 1051609027fSChander Kashyap #define GATE_BUS_TOP 0x10700 106e9d52956SVikas Sajjan #define GATE_BUS_DISP1 0x10728 1070a22c306SShaik Ameer Basha #define GATE_BUS_GEN 0x1073c 1081609027fSChander Kashyap #define GATE_BUS_FSYS0 0x10740 1096b5ae463SShaik Ameer Basha #define GATE_BUS_FSYS2 0x10748 1101609027fSChander Kashyap #define GATE_BUS_PERIC 0x10750 1111609027fSChander Kashyap #define GATE_BUS_PERIC1 0x10754 1121609027fSChander Kashyap #define GATE_BUS_PERIS0 0x10760 1131609027fSChander Kashyap #define GATE_BUS_PERIS1 0x10764 1146575fa76SShaik Ameer Basha #define GATE_BUS_NOC 0x10770 1153a767b35SShaik Ameer Basha #define GATE_TOP_SCLK_ISP 0x10870 1161609027fSChander Kashyap #define GATE_IP_GSCL0 0x10910 1171609027fSChander Kashyap #define GATE_IP_GSCL1 0x10920 1186520e968SAlim Akhtar #define GATE_IP_CAM 0x10924 /* 5800 specific */ 1191609027fSChander Kashyap #define GATE_IP_MFC 0x1092c 1201609027fSChander Kashyap #define GATE_IP_DISP1 0x10928 1211609027fSChander Kashyap #define GATE_IP_G3D 0x10930 1221609027fSChander Kashyap #define GATE_IP_GEN 0x10934 1236b5ae463SShaik Ameer Basha #define GATE_IP_FSYS 0x10944 124faec151bSShaik Ameer Basha #define GATE_IP_PERIC 0x10950 1250a22c306SShaik Ameer Basha #define GATE_IP_PERIS 0x10960 1261609027fSChander Kashyap #define GATE_IP_MSCL 0x10970 1271609027fSChander Kashyap #define GATE_TOP_SCLK_GSCL 0x10820 1281609027fSChander Kashyap #define GATE_TOP_SCLK_DISP1 0x10828 1291609027fSChander Kashyap #define GATE_TOP_SCLK_MAU 0x1083c 1301609027fSChander Kashyap #define GATE_TOP_SCLK_FSYS 0x10840 1311609027fSChander Kashyap #define GATE_TOP_SCLK_PERIC 0x10850 132424b673aSShaik Ameer Basha #define TOP_SPARE2 0x10b08 133c898c6b7SYadwinder Singh Brar #define BPLL_LOCK 0x20010 134c898c6b7SYadwinder Singh Brar #define BPLL_CON0 0x20110 135e867e8faSChanwoo Choi #define SRC_CDREX 0x20200 136e867e8faSChanwoo Choi #define DIV_CDREX0 0x20500 137e867e8faSChanwoo Choi #define DIV_CDREX1 0x20504 138c898c6b7SYadwinder Singh Brar #define KPLL_LOCK 0x28000 139c898c6b7SYadwinder Singh Brar #define KPLL_CON0 0x28100 1401609027fSChander Kashyap #define SRC_KFC 0x28200 1411609027fSChander Kashyap #define DIV_KFC0 0x28500 1421609027fSChander Kashyap 1436520e968SAlim Akhtar /* Exynos5x SoC type */ 1446520e968SAlim Akhtar enum exynos5x_soc { 1456520e968SAlim Akhtar EXYNOS5420, 1466520e968SAlim Akhtar EXYNOS5800, 1476520e968SAlim Akhtar }; 1486520e968SAlim Akhtar 149c898c6b7SYadwinder Singh Brar /* list of PLLs */ 1506520e968SAlim Akhtar enum exynos5x_plls { 151c898c6b7SYadwinder Singh Brar apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 152c898c6b7SYadwinder Singh Brar bpll, kpll, 153c898c6b7SYadwinder Singh Brar nr_plls /* number of PLLs */ 154c898c6b7SYadwinder Singh Brar }; 155c898c6b7SYadwinder Singh Brar 156388c7885STomasz Figa static void __iomem *reg_base; 1576520e968SAlim Akhtar static enum exynos5x_soc exynos5x_soc; 158388c7885STomasz Figa 159388c7885STomasz Figa #ifdef CONFIG_PM_SLEEP 1606520e968SAlim Akhtar static struct samsung_clk_reg_dump *exynos5x_save; 1616520e968SAlim Akhtar static struct samsung_clk_reg_dump *exynos5800_save; 162388c7885STomasz Figa 1631609027fSChander Kashyap /* 1641609027fSChander Kashyap * list of controller registers to be saved and restored during a 1651609027fSChander Kashyap * suspend/resume cycle. 1661609027fSChander Kashyap */ 167ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5x_clk_regs[] __initconst = { 1681609027fSChander Kashyap SRC_CPU, 1691609027fSChander Kashyap DIV_CPU0, 1701609027fSChander Kashyap DIV_CPU1, 1711609027fSChander Kashyap GATE_BUS_CPU, 1721609027fSChander Kashyap GATE_SCLK_CPU, 17377342432SShaik Ameer Basha CLKOUT_CMU_CPU, 17477342432SShaik Ameer Basha EPLL_CON0, 17577342432SShaik Ameer Basha EPLL_CON1, 17677342432SShaik Ameer Basha EPLL_CON2, 17777342432SShaik Ameer Basha RPLL_CON0, 17877342432SShaik Ameer Basha RPLL_CON1, 17977342432SShaik Ameer Basha RPLL_CON2, 1801609027fSChander Kashyap SRC_TOP0, 1811609027fSChander Kashyap SRC_TOP1, 1821609027fSChander Kashyap SRC_TOP2, 1831609027fSChander Kashyap SRC_TOP3, 1841609027fSChander Kashyap SRC_TOP4, 1851609027fSChander Kashyap SRC_TOP5, 1861609027fSChander Kashyap SRC_TOP6, 1871609027fSChander Kashyap SRC_TOP7, 1881609027fSChander Kashyap SRC_DISP10, 1891609027fSChander Kashyap SRC_MAU, 1901609027fSChander Kashyap SRC_FSYS, 1911609027fSChander Kashyap SRC_PERIC0, 1921609027fSChander Kashyap SRC_PERIC1, 1931609027fSChander Kashyap SRC_TOP10, 1941609027fSChander Kashyap SRC_TOP11, 1951609027fSChander Kashyap SRC_TOP12, 196424b673aSShaik Ameer Basha SRC_MASK_TOP2, 19731116a64SShaik Ameer Basha SRC_MASK_TOP7, 1981609027fSChander Kashyap SRC_MASK_DISP10, 1991609027fSChander Kashyap SRC_MASK_FSYS, 2001609027fSChander Kashyap SRC_MASK_PERIC0, 2011609027fSChander Kashyap SRC_MASK_PERIC1, 202e9d52956SVikas Sajjan SRC_MASK_TOP0, 203e9d52956SVikas Sajjan SRC_MASK_TOP1, 204e9d52956SVikas Sajjan SRC_MASK_MAU, 205e9d52956SVikas Sajjan SRC_MASK_ISP, 2063a767b35SShaik Ameer Basha SRC_ISP, 2071609027fSChander Kashyap DIV_TOP0, 2081609027fSChander Kashyap DIV_TOP1, 2091609027fSChander Kashyap DIV_TOP2, 2101609027fSChander Kashyap DIV_DISP10, 2111609027fSChander Kashyap DIV_MAU, 2121609027fSChander Kashyap DIV_FSYS0, 2131609027fSChander Kashyap DIV_FSYS1, 2141609027fSChander Kashyap DIV_FSYS2, 2151609027fSChander Kashyap DIV_PERIC0, 2161609027fSChander Kashyap DIV_PERIC1, 2171609027fSChander Kashyap DIV_PERIC2, 2181609027fSChander Kashyap DIV_PERIC3, 2191609027fSChander Kashyap DIV_PERIC4, 2203a767b35SShaik Ameer Basha SCLK_DIV_ISP0, 2213a767b35SShaik Ameer Basha SCLK_DIV_ISP1, 22202932381SShaik Ameer Basha DIV2_RATIO0, 2231d87db4dSShaik Ameer Basha DIV4_RATIO, 224e9d52956SVikas Sajjan GATE_BUS_DISP1, 2251609027fSChander Kashyap GATE_BUS_TOP, 2260a22c306SShaik Ameer Basha GATE_BUS_GEN, 2271609027fSChander Kashyap GATE_BUS_FSYS0, 2286b5ae463SShaik Ameer Basha GATE_BUS_FSYS2, 2291609027fSChander Kashyap GATE_BUS_PERIC, 2301609027fSChander Kashyap GATE_BUS_PERIC1, 2311609027fSChander Kashyap GATE_BUS_PERIS0, 2321609027fSChander Kashyap GATE_BUS_PERIS1, 2336575fa76SShaik Ameer Basha GATE_BUS_NOC, 2343a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2351609027fSChander Kashyap GATE_IP_GSCL0, 2361609027fSChander Kashyap GATE_IP_GSCL1, 2371609027fSChander Kashyap GATE_IP_MFC, 2381609027fSChander Kashyap GATE_IP_DISP1, 2391609027fSChander Kashyap GATE_IP_G3D, 2401609027fSChander Kashyap GATE_IP_GEN, 2416b5ae463SShaik Ameer Basha GATE_IP_FSYS, 242faec151bSShaik Ameer Basha GATE_IP_PERIC, 2430a22c306SShaik Ameer Basha GATE_IP_PERIS, 2441609027fSChander Kashyap GATE_IP_MSCL, 2451609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 2461609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 2471609027fSChander Kashyap GATE_TOP_SCLK_MAU, 2481609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2491609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 250424b673aSShaik Ameer Basha TOP_SPARE2, 251e867e8faSChanwoo Choi SRC_CDREX, 252e867e8faSChanwoo Choi DIV_CDREX0, 253e867e8faSChanwoo Choi DIV_CDREX1, 2541609027fSChander Kashyap SRC_KFC, 2551609027fSChander Kashyap DIV_KFC0, 2561609027fSChander Kashyap }; 2571609027fSChander Kashyap 258ad98c64fSKrzysztof Kozlowski static const unsigned long exynos5800_clk_regs[] __initconst = { 2596520e968SAlim Akhtar SRC_TOP8, 2606520e968SAlim Akhtar SRC_TOP9, 2616520e968SAlim Akhtar SRC_CAM, 2626520e968SAlim Akhtar SRC_TOP1, 2636520e968SAlim Akhtar DIV_TOP8, 2646520e968SAlim Akhtar DIV_TOP9, 2656520e968SAlim Akhtar DIV_CAM, 2666520e968SAlim Akhtar GATE_IP_CAM, 2676520e968SAlim Akhtar }; 2686520e968SAlim Akhtar 269e9d52956SVikas Sajjan static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 270e9d52956SVikas Sajjan { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 271e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 272e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 273e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 274e9d52956SVikas Sajjan { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 275e9d52956SVikas Sajjan { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 276e9d52956SVikas Sajjan { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 277e9d52956SVikas Sajjan { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 278e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 279e9d52956SVikas Sajjan { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 280e9d52956SVikas Sajjan { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 28197372e5aSJavier Martinez Canillas { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 282e9d52956SVikas Sajjan { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 283e9d52956SVikas Sajjan { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 284e9d52956SVikas Sajjan }; 285e9d52956SVikas Sajjan 286388c7885STomasz Figa static int exynos5420_clk_suspend(void) 287388c7885STomasz Figa { 2886520e968SAlim Akhtar samsung_clk_save(reg_base, exynos5x_save, 2896520e968SAlim Akhtar ARRAY_SIZE(exynos5x_clk_regs)); 2906520e968SAlim Akhtar 2916520e968SAlim Akhtar if (exynos5x_soc == EXYNOS5800) 2926520e968SAlim Akhtar samsung_clk_save(reg_base, exynos5800_save, 2936520e968SAlim Akhtar ARRAY_SIZE(exynos5800_clk_regs)); 294388c7885STomasz Figa 295e9d52956SVikas Sajjan samsung_clk_restore(reg_base, exynos5420_set_clksrc, 296e9d52956SVikas Sajjan ARRAY_SIZE(exynos5420_set_clksrc)); 297e9d52956SVikas Sajjan 298388c7885STomasz Figa return 0; 299388c7885STomasz Figa } 300388c7885STomasz Figa 301388c7885STomasz Figa static void exynos5420_clk_resume(void) 302388c7885STomasz Figa { 3036520e968SAlim Akhtar samsung_clk_restore(reg_base, exynos5x_save, 3046520e968SAlim Akhtar ARRAY_SIZE(exynos5x_clk_regs)); 3056520e968SAlim Akhtar 3066520e968SAlim Akhtar if (exynos5x_soc == EXYNOS5800) 3076520e968SAlim Akhtar samsung_clk_restore(reg_base, exynos5800_save, 3086520e968SAlim Akhtar ARRAY_SIZE(exynos5800_clk_regs)); 309388c7885STomasz Figa } 310388c7885STomasz Figa 311388c7885STomasz Figa static struct syscore_ops exynos5420_clk_syscore_ops = { 312388c7885STomasz Figa .suspend = exynos5420_clk_suspend, 313388c7885STomasz Figa .resume = exynos5420_clk_resume, 314388c7885STomasz Figa }; 315388c7885STomasz Figa 316ebd217e1SKrzysztof Kozlowski static void __init exynos5420_clk_sleep_init(void) 317388c7885STomasz Figa { 3186520e968SAlim Akhtar exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs, 3196520e968SAlim Akhtar ARRAY_SIZE(exynos5x_clk_regs)); 3206520e968SAlim Akhtar if (!exynos5x_save) { 321388c7885STomasz Figa pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 322388c7885STomasz Figa __func__); 323388c7885STomasz Figa return; 324388c7885STomasz Figa } 325388c7885STomasz Figa 3266520e968SAlim Akhtar if (exynos5x_soc == EXYNOS5800) { 3276520e968SAlim Akhtar exynos5800_save = 3286520e968SAlim Akhtar samsung_clk_alloc_reg_dump(exynos5800_clk_regs, 3296520e968SAlim Akhtar ARRAY_SIZE(exynos5800_clk_regs)); 3306520e968SAlim Akhtar if (!exynos5800_save) 3316520e968SAlim Akhtar goto err_soc; 3326520e968SAlim Akhtar } 3336520e968SAlim Akhtar 334388c7885STomasz Figa register_syscore_ops(&exynos5420_clk_syscore_ops); 3356520e968SAlim Akhtar return; 3366520e968SAlim Akhtar err_soc: 3376520e968SAlim Akhtar kfree(exynos5x_save); 3386520e968SAlim Akhtar pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 3396520e968SAlim Akhtar __func__); 3406520e968SAlim Akhtar return; 341388c7885STomasz Figa } 342388c7885STomasz Figa #else 343ebd217e1SKrzysztof Kozlowski static void __init exynos5420_clk_sleep_init(void) {} 344388c7885STomasz Figa #endif 345388c7885STomasz Figa 3461609027fSChander Kashyap /* list of all parent clocks */ 347dbd713bbSShaik Ameer Basha PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 348dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 349dbd713bbSShaik Ameer Basha PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 350dbd713bbSShaik Ameer Basha PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 351dbd713bbSShaik Ameer Basha PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 352dbd713bbSShaik Ameer Basha PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 353dbd713bbSShaik Ameer Basha PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 354dbd713bbSShaik Ameer Basha PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 355dbd713bbSShaik Ameer Basha PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 356dbd713bbSShaik Ameer Basha PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 357dbd713bbSShaik Ameer Basha PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 358dbd713bbSShaik Ameer Basha PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 359dbd713bbSShaik Ameer Basha PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 360dbd713bbSShaik Ameer Basha PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 361dbd713bbSShaik Ameer Basha PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 3621609027fSChander Kashyap 363dbd713bbSShaik Ameer Basha PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 364dbd713bbSShaik Ameer Basha "mout_sclk_mpll"}; 365dbd713bbSShaik Ameer Basha PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 366dbd713bbSShaik Ameer Basha "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 367dbd713bbSShaik Ameer Basha "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 368dbd713bbSShaik Ameer Basha PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 369dbd713bbSShaik Ameer Basha PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 370dbd713bbSShaik Ameer Basha PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 3711609027fSChander Kashyap 372424b673aSShaik Ameer Basha PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 373dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 374faec151bSShaik Ameer Basha PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 375b31ca2a0SShaik Ameer Basha PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 3761609027fSChander Kashyap 377dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 3786b5ae463SShaik Ameer Basha PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 3796b5ae463SShaik Ameer Basha PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 380dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 3811609027fSChander Kashyap 382dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 383dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 3846575fa76SShaik Ameer Basha PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 3856575fa76SShaik Ameer Basha PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 3866575fa76SShaik Ameer Basha 3876575fa76SShaik Ameer Basha PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 3886575fa76SShaik Ameer Basha PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 3896575fa76SShaik Ameer Basha PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 3906575fa76SShaik Ameer Basha 3913a767b35SShaik Ameer Basha PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 3923a767b35SShaik Ameer Basha PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 3933a767b35SShaik Ameer Basha 3943a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 3953a767b35SShaik Ameer Basha "mout_sclk_spll"}; 3963a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 3973a767b35SShaik Ameer Basha 3983a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 3993a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 4001609027fSChander Kashyap 401dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 402424b673aSShaik Ameer Basha PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 4031609027fSChander Kashyap 404dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 405dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 4061609027fSChander Kashyap 407dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 408dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 4091609027fSChander Kashyap 410dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 411dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 4121609027fSChander Kashyap 413dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 414dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 4153a767b35SShaik Ameer Basha PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 4161609027fSChander Kashyap 417dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 418dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 4191609027fSChander Kashyap 420dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 421dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 4221609027fSChander Kashyap 423dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 424424b673aSShaik Ameer Basha PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 425dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 426424b673aSShaik Ameer Basha PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 4271609027fSChander Kashyap 428dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 429dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 4301609027fSChander Kashyap 431dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 432dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 4331609027fSChander Kashyap 434dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 435dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 4361609027fSChander Kashyap 437dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 438dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 4391609027fSChander Kashyap 440dbd713bbSShaik Ameer Basha PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 441dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 442dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 443dbd713bbSShaik Ameer Basha PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 444dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 445dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 446dbd713bbSShaik Ameer Basha PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 447dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 448dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 449dbd713bbSShaik Ameer Basha PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 450dbd713bbSShaik Ameer Basha "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 451dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 452dbd713bbSShaik Ameer Basha PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 453dbd713bbSShaik Ameer Basha PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 454dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 455dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 45631116a64SShaik Ameer Basha PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 45731116a64SShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 458e867e8faSChanwoo Choi PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"}; 459e867e8faSChanwoo Choi 4606520e968SAlim Akhtar /* List of parents specific to exynos5800 */ 4616520e968SAlim Akhtar PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 4626520e968SAlim Akhtar PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4636520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4646520e968SAlim Akhtar PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4656520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4666520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 4676520e968SAlim Akhtar PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4686520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2", 4696520e968SAlim Akhtar "mout_epll2" }; 4706520e968SAlim Akhtar PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4716520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll" }; 4726520e968SAlim Akhtar PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 4736520e968SAlim Akhtar "mout_sclk_mpll", "ff_dout_spll2" }; 4746520e968SAlim Akhtar PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 4756520e968SAlim Akhtar "mout_sclk_mpll", "mout_sclk_spll", 4766520e968SAlim Akhtar "mout_epll2", "mout_sclk_ipll" }; 477e867e8faSChanwoo Choi PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll", 478e867e8faSChanwoo Choi "mout_sclk_mpll", "ff_dout_spll2", 479e867e8faSChanwoo Choi "mout_sclk_spll", "mout_sclk_epll"}; 4806520e968SAlim Akhtar PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 4816520e968SAlim Akhtar "mout_sclk_mpll", 4826520e968SAlim Akhtar "ff_dout_spll2" }; 4836520e968SAlim Akhtar PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 4846520e968SAlim Akhtar PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 4856520e968SAlim Akhtar PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 4866520e968SAlim Akhtar PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 4876520e968SAlim Akhtar PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 4886520e968SAlim Akhtar PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 4896520e968SAlim Akhtar PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 4906520e968SAlim Akhtar PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 4918a9cf26eSSylwester Nawrocki PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; 4921609027fSChander Kashyap 4931609027fSChander Kashyap /* fixed rate clocks generated outside the soc */ 4946520e968SAlim Akhtar static struct samsung_fixed_rate_clock 4956520e968SAlim Akhtar exynos5x_fixed_rate_ext_clks[] __initdata = { 496728f288dSStephen Boyd FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 4971609027fSChander Kashyap }; 4981609027fSChander Kashyap 4991609027fSChander Kashyap /* fixed rate clocks generated inside the soc */ 500ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { 501728f288dSStephen Boyd FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 502728f288dSStephen Boyd FRATE(0, "sclk_pwi", NULL, 0, 24000000), 503728f288dSStephen Boyd FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 504728f288dSStephen Boyd FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 505728f288dSStephen Boyd FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 5061609027fSChander Kashyap }; 5071609027fSChander Kashyap 508ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 509ad98c64fSKrzysztof Kozlowski exynos5x_fixed_factor_clks[] __initconst = { 510b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 511b31ca2a0SShaik Ameer Basha FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 5121609027fSChander Kashyap }; 5131609027fSChander Kashyap 514ad98c64fSKrzysztof Kozlowski static const struct samsung_fixed_factor_clock 515ad98c64fSKrzysztof Kozlowski exynos5800_fixed_factor_clks[] __initconst = { 5166520e968SAlim Akhtar FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 5176520e968SAlim Akhtar FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 5186520e968SAlim Akhtar }; 5196520e968SAlim Akhtar 520ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 5216520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 5226520e968SAlim Akhtar MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 5236520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 5246520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 5256520e968SAlim Akhtar 5266520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 5276520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 5286520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 5296520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 5306520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 5316520e968SAlim Akhtar 5326520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 5336520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 5346520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 5356520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 5366520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 5376520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 5386520e968SAlim Akhtar 539e867e8faSChanwoo Choi MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 540e867e8faSChanwoo Choi mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), 541599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, 542599cebeaSSylwester Nawrocki SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), 5436520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 5446520e968SAlim Akhtar MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 5456520e968SAlim Akhtar 5466520e968SAlim Akhtar MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 5476520e968SAlim Akhtar MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 5486520e968SAlim Akhtar MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 5496520e968SAlim Akhtar MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 5506520e968SAlim Akhtar 551599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, 552599cebeaSSylwester Nawrocki SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0), 5536520e968SAlim Akhtar MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 5546520e968SAlim Akhtar SRC_TOP9, 16, 1), 5556520e968SAlim Akhtar MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 5566520e968SAlim Akhtar SRC_TOP9, 20, 1), 5576520e968SAlim Akhtar MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 5586520e968SAlim Akhtar SRC_TOP9, 24, 1), 5596520e968SAlim Akhtar MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 5606520e968SAlim Akhtar SRC_TOP9, 28, 1), 5616520e968SAlim Akhtar 5626520e968SAlim Akhtar MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 5636520e968SAlim Akhtar MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 5646520e968SAlim Akhtar SRC_TOP13, 20, 1), 5656520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 5666520e968SAlim Akhtar SRC_TOP13, 24, 1), 5676520e968SAlim Akhtar MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 5686520e968SAlim Akhtar SRC_TOP13, 28, 1), 5696520e968SAlim Akhtar 5706520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 5716520e968SAlim Akhtar }; 5726520e968SAlim Akhtar 573ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { 57481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 57581fed6e3SChanwoo Choi "mout_aclk400_wcore", DIV_TOP0, 16, 3), 5766520e968SAlim Akhtar DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 5776520e968SAlim Akhtar DIV_TOP8, 16, 3), 5786520e968SAlim Akhtar DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 5796520e968SAlim Akhtar DIV_TOP8, 20, 3), 5806520e968SAlim Akhtar DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 5816520e968SAlim Akhtar DIV_TOP8, 24, 3), 5826520e968SAlim Akhtar DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 5836520e968SAlim Akhtar DIV_TOP8, 28, 3), 5846520e968SAlim Akhtar 5856520e968SAlim Akhtar DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 5866520e968SAlim Akhtar DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 5876520e968SAlim Akhtar }; 5886520e968SAlim Akhtar 589ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 5906520e968SAlim Akhtar GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 5916520e968SAlim Akhtar GATE_BUS_TOP, 24, 0, 0), 5926520e968SAlim Akhtar GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 593318fa46cSMarek Szyprowski GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), 59441097f25SSylwester Nawrocki GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", 595599cebeaSSylwester Nawrocki SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 5966520e968SAlim Akhtar }; 5976520e968SAlim Akhtar 598ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 5996520e968SAlim Akhtar MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 6006520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 6016520e968SAlim Akhtar TOP_SPARE2, 4, 1), 6026520e968SAlim Akhtar 6036520e968SAlim Akhtar MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 60436ba4824SMarek Szyprowski MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2), 6056520e968SAlim Akhtar MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 6066520e968SAlim Akhtar MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 6076520e968SAlim Akhtar 6086520e968SAlim Akhtar MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 6096520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp", mout_group4_p, 6106520e968SAlim Akhtar SRC_TOP1, 4, 2), 6116520e968SAlim Akhtar MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 6126520e968SAlim Akhtar MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 6136520e968SAlim Akhtar MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 6146520e968SAlim Akhtar 6156520e968SAlim Akhtar MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 6166520e968SAlim Akhtar MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 6176520e968SAlim Akhtar MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 6186520e968SAlim Akhtar MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 6196520e968SAlim Akhtar MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 6206520e968SAlim Akhtar MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 6216520e968SAlim Akhtar 622e867e8faSChanwoo Choi MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 623e867e8faSChanwoo Choi mout_group5_5800_p, SRC_TOP7, 16, 2), 62406255a92SSylwester Nawrocki MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2, 62506255a92SSylwester Nawrocki CLK_SET_RATE_PARENT, 0), 6266520e968SAlim Akhtar 6276520e968SAlim Akhtar MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 6286520e968SAlim Akhtar }; 6296520e968SAlim Akhtar 630ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 63181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 63281fed6e3SChanwoo Choi "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 6336520e968SAlim Akhtar }; 6346520e968SAlim Akhtar 63541097f25SSylwester Nawrocki static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { 63641097f25SSylwester Nawrocki GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 637599cebeaSSylwester Nawrocki SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 63841097f25SSylwester Nawrocki }; 63941097f25SSylwester Nawrocki 640ad98c64fSKrzysztof Kozlowski static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 641b31ca2a0SShaik Ameer Basha MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 642b31ca2a0SShaik Ameer Basha SRC_TOP7, 4, 1), 643dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 644dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 64531116a64SShaik Ameer Basha 646bee4f87fSThomas Abraham MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 647bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 648dbd713bbSShaik Ameer Basha MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 649bee4f87fSThomas Abraham MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 650bee4f87fSThomas Abraham CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 651dbd713bbSShaik Ameer Basha MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 6521609027fSChander Kashyap 653dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 654dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 6556b5ae463SShaik Ameer Basha MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 656dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 6571609027fSChander Kashyap 658dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 659dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 6601609027fSChander Kashyap 661dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 6621609027fSChander Kashyap 6633a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 6643a767b35SShaik Ameer Basha SRC_TOP3, 0, 1), 665dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 6661609027fSChander Kashyap SRC_TOP3, 4, 1), 66788560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 66888560100SJavier Martinez Canillas mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 669dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 6701609027fSChander Kashyap SRC_TOP3, 12, 1), 6716575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 6726575fa76SShaik Ameer Basha SRC_TOP3, 16, 1), 6736575fa76SShaik Ameer Basha MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 6746575fa76SShaik Ameer Basha SRC_TOP3, 20, 1), 6756b5ae463SShaik Ameer Basha MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 6766b5ae463SShaik Ameer Basha SRC_TOP3, 24, 1), 677dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 6781609027fSChander Kashyap SRC_TOP3, 28, 1), 6791609027fSChander Kashyap 680dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 6811609027fSChander Kashyap SRC_TOP4, 0, 1), 6823a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 6833a767b35SShaik Ameer Basha SRC_TOP4, 4, 1), 684faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 685faec151bSShaik Ameer Basha SRC_TOP4, 8, 1), 6863a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 6873a767b35SShaik Ameer Basha SRC_TOP4, 12, 1), 6883a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 6893a767b35SShaik Ameer Basha SRC_TOP4, 16, 1), 690dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 691dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 692c0fb262bSArun Kumar K MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 693c0fb262bSArun Kumar K SRC_TOP4, 28, 1), 6941609027fSChander Kashyap 69588560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 69688560100SJavier Martinez Canillas mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 697faec151bSShaik Ameer Basha MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 698faec151bSShaik Ameer Basha SRC_TOP5, 4, 1), 6993fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 7003fac5941SShaik Ameer Basha SRC_TOP5, 8, 1), 7013fac5941SShaik Ameer Basha MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 7023fac5941SShaik Ameer Basha SRC_TOP5, 12, 1), 7033fac5941SShaik Ameer Basha MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 7043fac5941SShaik Ameer Basha SRC_TOP5, 16, 1), 705dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 7061609027fSChander Kashyap SRC_TOP5, 20, 1), 70788560100SJavier Martinez Canillas MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 70888560100SJavier Martinez Canillas mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 709c0feb268SMarek Szyprowski MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 710c0feb268SMarek Szyprowski mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 7111609027fSChander Kashyap 712dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 713dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 714dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 715dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 716dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 717599cebeaSSylwester Nawrocki MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, 718599cebeaSSylwester Nawrocki CLK_SET_RATE_PARENT, 0), 719dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 720dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 7211609027fSChander Kashyap 7223a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 7233a767b35SShaik Ameer Basha SRC_TOP10, 0, 1), 724dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 725dbd713bbSShaik Ameer Basha SRC_TOP10, 4, 1), 72688560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 72788560100SJavier Martinez Canillas SRC_TOP10, 8, 1), 728dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 7291609027fSChander Kashyap SRC_TOP10, 12, 1), 7306575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 7316575fa76SShaik Ameer Basha SRC_TOP10, 16, 1), 7326575fa76SShaik Ameer Basha MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 7336575fa76SShaik Ameer Basha SRC_TOP10, 20, 1), 7346b5ae463SShaik Ameer Basha MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 7356b5ae463SShaik Ameer Basha SRC_TOP10, 24, 1), 736dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 737dbd713bbSShaik Ameer Basha SRC_TOP10, 28, 1), 7383a767b35SShaik Ameer Basha 739dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 7401609027fSChander Kashyap SRC_TOP11, 0, 1), 7413a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 7423a767b35SShaik Ameer Basha SRC_TOP11, 4, 1), 743dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 7443a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 7453a767b35SShaik Ameer Basha SRC_TOP11, 12, 1), 746dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 747dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 748c0fb262bSArun Kumar K MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 749c0fb262bSArun Kumar K SRC_TOP11, 28, 1), 7501609027fSChander Kashyap 75188560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 75288560100SJavier Martinez Canillas mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 753dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 754dbd713bbSShaik Ameer Basha SRC_TOP12, 8, 1), 755dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 756dbd713bbSShaik Ameer Basha SRC_TOP12, 12, 1), 757dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 758dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 759dbd713bbSShaik Ameer Basha SRC_TOP12, 20, 1), 76088560100SJavier Martinez Canillas MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 76188560100SJavier Martinez Canillas mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 762c0feb268SMarek Szyprowski MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 763c0feb268SMarek Szyprowski mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 7641609027fSChander Kashyap 7651609027fSChander Kashyap /* DISP1 Block */ 766dbd713bbSShaik Ameer Basha MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 767dbd713bbSShaik Ameer Basha MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 768dbd713bbSShaik Ameer Basha MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 769dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 770424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 7716575fa76SShaik Ameer Basha 772424b673aSShaik Ameer Basha MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 7731609027fSChander Kashyap 774e867e8faSChanwoo Choi /* CDREX block */ 775e867e8faSChanwoo Choi MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p, 776e867e8faSChanwoo Choi SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0), 777e867e8faSChanwoo Choi MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1, 778e867e8faSChanwoo Choi CLK_SET_RATE_PARENT, 0), 779e867e8faSChanwoo Choi 7801609027fSChander Kashyap /* MAU Block */ 78131116a64SShaik Ameer Basha MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 7821609027fSChander Kashyap 7831609027fSChander Kashyap /* FSYS Block */ 784dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 785dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 786dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 787dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 788dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 789dbd713bbSShaik Ameer Basha MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 7906b5ae463SShaik Ameer Basha MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 7911609027fSChander Kashyap 7921609027fSChander Kashyap /* PERIC Block */ 793dbd713bbSShaik Ameer Basha MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 794dbd713bbSShaik Ameer Basha MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 795dbd713bbSShaik Ameer Basha MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 796dbd713bbSShaik Ameer Basha MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 797dbd713bbSShaik Ameer Basha MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 798dbd713bbSShaik Ameer Basha MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 799dbd713bbSShaik Ameer Basha MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 800dbd713bbSShaik Ameer Basha MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 801dbd713bbSShaik Ameer Basha MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 802dbd713bbSShaik Ameer Basha MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 803dbd713bbSShaik Ameer Basha MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 804dbd713bbSShaik Ameer Basha MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 8053a767b35SShaik Ameer Basha 8063a767b35SShaik Ameer Basha /* ISP Block */ 8073a767b35SShaik Ameer Basha MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 8083a767b35SShaik Ameer Basha MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 8093a767b35SShaik Ameer Basha MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 8103a767b35SShaik Ameer Basha MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 8113a767b35SShaik Ameer Basha MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 8121609027fSChander Kashyap }; 8131609027fSChander Kashyap 814ad98c64fSKrzysztof Kozlowski static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 815cba9d2faSAndrzej Hajda DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 816cba9d2faSAndrzej Hajda DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 817cba9d2faSAndrzej Hajda DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 818dbd713bbSShaik Ameer Basha DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 819cba9d2faSAndrzej Hajda DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 8201609027fSChander Kashyap 82181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 82281fed6e3SChanwoo Choi DIV_TOP0, 0, 3), 82381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 82481fed6e3SChanwoo Choi DIV_TOP0, 4, 3), 82581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 82681fed6e3SChanwoo Choi DIV_TOP0, 8, 3), 82781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 82881fed6e3SChanwoo Choi DIV_TOP0, 12, 3), 82981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 83081fed6e3SChanwoo Choi DIV_TOP0, 20, 3), 83181fed6e3SChanwoo Choi DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 83281fed6e3SChanwoo Choi DIV_TOP0, 24, 3), 83381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 83481fed6e3SChanwoo Choi DIV_TOP0, 28, 3), 83581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 83681fed6e3SChanwoo Choi "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 83781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 83881fed6e3SChanwoo Choi "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 83981fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 84081fed6e3SChanwoo Choi DIV_TOP1, 8, 6), 84181fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 84281fed6e3SChanwoo Choi "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 84381fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 84481fed6e3SChanwoo Choi DIV_TOP1, 20, 3), 84581fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 84681fed6e3SChanwoo Choi DIV_TOP1, 24, 3), 84781fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 84881fed6e3SChanwoo Choi DIV_TOP1, 28, 3), 8491609027fSChander Kashyap 85081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 85181fed6e3SChanwoo Choi DIV_TOP2, 8, 3), 85281fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 85381fed6e3SChanwoo Choi DIV_TOP2, 12, 3), 85481fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 85581fed6e3SChanwoo Choi 16, 3), 85681fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 85781fed6e3SChanwoo Choi DIV_TOP2, 20, 3), 85881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 85981fed6e3SChanwoo Choi "mout_aclk300_disp1", DIV_TOP2, 24, 3), 86081fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 86181fed6e3SChanwoo Choi DIV_TOP2, 28, 3), 8621609027fSChander Kashyap 8631609027fSChander Kashyap /* DISP1 Block */ 864424b673aSShaik Ameer Basha DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 865cba9d2faSAndrzej Hajda DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 866cba9d2faSAndrzej Hajda DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 867cba9d2faSAndrzej Hajda DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 86881fed6e3SChanwoo Choi DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 86981fed6e3SChanwoo Choi "mout_aclk400_disp1", DIV_TOP2, 4, 3), 8701609027fSChander Kashyap 871e867e8faSChanwoo Choi /* CDREX Block */ 872e867e8faSChanwoo Choi DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", 873e867e8faSChanwoo Choi DIV_CDREX0, 28, 3), 874e867e8faSChanwoo Choi DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", 875e867e8faSChanwoo Choi DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), 876e867e8faSChanwoo Choi DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", 877e867e8faSChanwoo Choi DIV_CDREX0, 16, 3), 878e867e8faSChanwoo Choi DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", 879e867e8faSChanwoo Choi DIV_CDREX0, 8, 3), 880e867e8faSChanwoo Choi DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", 881e867e8faSChanwoo Choi DIV_CDREX0, 3, 5), 882e867e8faSChanwoo Choi 883e867e8faSChanwoo Choi DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", 884e867e8faSChanwoo Choi DIV_CDREX1, 8, 3), 885e867e8faSChanwoo Choi 8861609027fSChander Kashyap /* Audio Block */ 887cba9d2faSAndrzej Hajda DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 888cba9d2faSAndrzej Hajda DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 8891609027fSChander Kashyap 8901609027fSChander Kashyap /* USB3.0 */ 891cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 892cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 893cba9d2faSAndrzej Hajda DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 894cba9d2faSAndrzej Hajda DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 8951609027fSChander Kashyap 8961609027fSChander Kashyap /* MMC */ 897cba9d2faSAndrzej Hajda DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 898cba9d2faSAndrzej Hajda DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 899cba9d2faSAndrzej Hajda DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 9001609027fSChander Kashyap 901cba9d2faSAndrzej Hajda DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 9026b5ae463SShaik Ameer Basha DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 9031609027fSChander Kashyap 9041609027fSChander Kashyap /* UART and PWM */ 905cba9d2faSAndrzej Hajda DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 906cba9d2faSAndrzej Hajda DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 907cba9d2faSAndrzej Hajda DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 908cba9d2faSAndrzej Hajda DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 909cba9d2faSAndrzej Hajda DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 9101609027fSChander Kashyap 9111609027fSChander Kashyap /* SPI */ 912cba9d2faSAndrzej Hajda DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 913cba9d2faSAndrzej Hajda DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 914cba9d2faSAndrzej Hajda DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 9151609027fSChander Kashyap 9161d87db4dSShaik Ameer Basha 9171609027fSChander Kashyap /* PCM */ 918cba9d2faSAndrzej Hajda DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 919cba9d2faSAndrzej Hajda DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 9201609027fSChander Kashyap 9211609027fSChander Kashyap /* Audio - I2S */ 922cba9d2faSAndrzej Hajda DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 923cba9d2faSAndrzej Hajda DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 924cba9d2faSAndrzej Hajda DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 925cba9d2faSAndrzej Hajda DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 926cba9d2faSAndrzej Hajda DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 9271609027fSChander Kashyap 9281609027fSChander Kashyap /* SPI Pre-Ratio */ 929faec151bSShaik Ameer Basha DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 930faec151bSShaik Ameer Basha DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 931faec151bSShaik Ameer Basha DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 9323a767b35SShaik Ameer Basha 93302932381SShaik Ameer Basha /* GSCL Block */ 93402932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 93502932381SShaik Ameer Basha 9364549d93dSShaik Ameer Basha /* MSCL Block */ 9374549d93dSShaik Ameer Basha DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 9384549d93dSShaik Ameer Basha 9390a22c306SShaik Ameer Basha /* PSGEN */ 9400a22c306SShaik Ameer Basha DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 9410a22c306SShaik Ameer Basha DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 9420a22c306SShaik Ameer Basha 9433a767b35SShaik Ameer Basha /* ISP Block */ 9443a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 9453a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 9463a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 9473a767b35SShaik Ameer Basha DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 9483a767b35SShaik Ameer Basha DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 9493a767b35SShaik Ameer Basha DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 9503a767b35SShaik Ameer Basha DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 9513a767b35SShaik Ameer Basha DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 9523a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 9533a767b35SShaik Ameer Basha DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 9543a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 9551609027fSChander Kashyap }; 9561609027fSChander Kashyap 957ad98c64fSKrzysztof Kozlowski static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 9585b73721bSNaveen Krishna Chatradhi /* G2D */ 9593fac5941SShaik Ameer Basha GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 9605b73721bSNaveen Krishna Chatradhi GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 9613fac5941SShaik Ameer Basha GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 9623fac5941SShaik Ameer Basha GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 9633fac5941SShaik Ameer Basha GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 9645b73721bSNaveen Krishna Chatradhi 9651609027fSChander Kashyap GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 966318fa46cSMarek Szyprowski GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), 9671609027fSChander Kashyap GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 9681609027fSChander Kashyap GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 9691609027fSChander Kashyap 9701609027fSChander Kashyap GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 9711609027fSChander Kashyap GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 9721609027fSChander Kashyap GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 973318fa46cSMarek Szyprowski GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), 9741609027fSChander Kashyap GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 9751609027fSChander Kashyap GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 9763a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 9773a767b35SShaik Ameer Basha GATE_BUS_TOP, 5, 0, 0), 9781609027fSChander Kashyap GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 979318fa46cSMarek Szyprowski GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), 9801609027fSChander Kashyap GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 9811609027fSChander Kashyap GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 9823a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 9833a767b35SShaik Ameer Basha GATE_BUS_TOP, 8, 0, 0), 984b31ca2a0SShaik Ameer Basha GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 9851609027fSChander Kashyap GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 986faec151bSShaik Ameer Basha GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 9871609027fSChander Kashyap GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 9883a767b35SShaik Ameer Basha GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 9893a767b35SShaik Ameer Basha GATE_BUS_TOP, 13, 0, 0), 9901609027fSChander Kashyap GATE(0, "aclk166", "mout_user_aclk166", 9911609027fSChander Kashyap GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 99234cba900SJavier Martinez Canillas GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", 993318fa46cSMarek Szyprowski GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), 9943a767b35SShaik Ameer Basha GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 9953a767b35SShaik Ameer Basha GATE_BUS_TOP, 16, 0, 0), 99602932381SShaik Ameer Basha GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 997c07c1a0fSAndrzej Pietrasiewicz GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), 998424b673aSShaik Ameer Basha GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 999318fa46cSMarek Szyprowski GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), 1000b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 1001b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 28, 0, 0), 1002b31ca2a0SShaik Ameer Basha GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 1003b31ca2a0SShaik Ameer Basha GATE_BUS_TOP, 29, 0, 0), 1004424b673aSShaik Ameer Basha 1005424b673aSShaik Ameer Basha GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 1006318fa46cSMarek Szyprowski SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), 10071609027fSChander Kashyap 10081609027fSChander Kashyap /* sclk */ 1009cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 10101609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 1011cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 10121609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 1013cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 10141609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 1015cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 10161609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 1017faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 10181609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 1019faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 10201609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 1021faec151bSShaik Ameer Basha GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 10221609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 1023cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 10241609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 1025cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 10261609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1027cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 10281609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 1029cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 10301609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 1031cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 10321609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 1033cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 10341609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 10351609027fSChander Kashyap 1036cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 10371609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 1038cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 10391609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 1040cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 10411609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 1042cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 10431609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 1044cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 10451609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 1046cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 10471609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 1048cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 10491609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 10501609027fSChander Kashyap 10511609027fSChander Kashyap /* Display */ 1052cba9d2faSAndrzej Hajda GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 10531609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 1054cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 10551609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 1056cba9d2faSAndrzej Hajda GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 1057424b673aSShaik Ameer Basha GATE_TOP_SCLK_DISP1, 9, 0, 0), 1058cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 10591609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 1060cba9d2faSAndrzej Hajda GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 10611609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 10621609027fSChander Kashyap 10631609027fSChander Kashyap /* Maudio Block */ 1064cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 10651609027fSChander Kashyap GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1066cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 10671609027fSChander Kashyap GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 10686b5ae463SShaik Ameer Basha 10696b5ae463SShaik Ameer Basha /* FSYS Block */ 1070cba9d2faSAndrzej Hajda GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1071cba9d2faSAndrzej Hajda GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1072cba9d2faSAndrzej Hajda GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1073cba9d2faSAndrzej Hajda GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 10746b5ae463SShaik Ameer Basha GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 10756b5ae463SShaik Ameer Basha GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 10766b5ae463SShaik Ameer Basha GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 10776b5ae463SShaik Ameer Basha GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1078cba9d2faSAndrzej Hajda GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 10796b5ae463SShaik Ameer Basha GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 10806b5ae463SShaik Ameer Basha GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 10816b5ae463SShaik Ameer Basha GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 10826b5ae463SShaik Ameer Basha GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 10836b5ae463SShaik Ameer Basha GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 10846b5ae463SShaik Ameer Basha SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 10851609027fSChander Kashyap 1086faec151bSShaik Ameer Basha /* PERIC Block */ 108744ff0254SDoug Anderson GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 108844ff0254SDoug Anderson GATE_IP_PERIC, 0, 0, 0), 108944ff0254SDoug Anderson GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 109044ff0254SDoug Anderson GATE_IP_PERIC, 1, 0, 0), 109144ff0254SDoug Anderson GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 109244ff0254SDoug Anderson GATE_IP_PERIC, 2, 0, 0), 109344ff0254SDoug Anderson GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 109444ff0254SDoug Anderson GATE_IP_PERIC, 3, 0, 0), 109544ff0254SDoug Anderson GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 109644ff0254SDoug Anderson GATE_IP_PERIC, 6, 0, 0), 109744ff0254SDoug Anderson GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 109844ff0254SDoug Anderson GATE_IP_PERIC, 7, 0, 0), 109944ff0254SDoug Anderson GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 110044ff0254SDoug Anderson GATE_IP_PERIC, 8, 0, 0), 110144ff0254SDoug Anderson GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 110244ff0254SDoug Anderson GATE_IP_PERIC, 9, 0, 0), 110344ff0254SDoug Anderson GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 110444ff0254SDoug Anderson GATE_IP_PERIC, 10, 0, 0), 110544ff0254SDoug Anderson GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 110644ff0254SDoug Anderson GATE_IP_PERIC, 11, 0, 0), 110744ff0254SDoug Anderson GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 110844ff0254SDoug Anderson GATE_IP_PERIC, 12, 0, 0), 110944ff0254SDoug Anderson GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 111044ff0254SDoug Anderson GATE_IP_PERIC, 13, 0, 0), 111144ff0254SDoug Anderson GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 111244ff0254SDoug Anderson GATE_IP_PERIC, 14, 0, 0), 111344ff0254SDoug Anderson GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 111444ff0254SDoug Anderson GATE_IP_PERIC, 15, 0, 0), 111544ff0254SDoug Anderson GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 111644ff0254SDoug Anderson GATE_IP_PERIC, 16, 0, 0), 111744ff0254SDoug Anderson GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 111844ff0254SDoug Anderson GATE_IP_PERIC, 17, 0, 0), 111944ff0254SDoug Anderson GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 112044ff0254SDoug Anderson GATE_IP_PERIC, 18, 0, 0), 112144ff0254SDoug Anderson GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 112244ff0254SDoug Anderson GATE_IP_PERIC, 20, 0, 0), 112344ff0254SDoug Anderson GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 112444ff0254SDoug Anderson GATE_IP_PERIC, 21, 0, 0), 112544ff0254SDoug Anderson GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 112644ff0254SDoug Anderson GATE_IP_PERIC, 22, 0, 0), 112744ff0254SDoug Anderson GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 112844ff0254SDoug Anderson GATE_IP_PERIC, 23, 0, 0), 112944ff0254SDoug Anderson GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 113044ff0254SDoug Anderson GATE_IP_PERIC, 24, 0, 0), 113144ff0254SDoug Anderson GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 113244ff0254SDoug Anderson GATE_IP_PERIC, 26, 0, 0), 113344ff0254SDoug Anderson GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 113444ff0254SDoug Anderson GATE_IP_PERIC, 28, 0, 0), 113544ff0254SDoug Anderson GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 113644ff0254SDoug Anderson GATE_IP_PERIC, 30, 0, 0), 113744ff0254SDoug Anderson GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 113844ff0254SDoug Anderson GATE_IP_PERIC, 31, 0, 0), 11391609027fSChander Kashyap 114044ff0254SDoug Anderson GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 114144ff0254SDoug Anderson GATE_BUS_PERIC, 22, 0, 0), 11421609027fSChander Kashyap 11430a22c306SShaik Ameer Basha /* PERIS Block */ 1144cba9d2faSAndrzej Hajda GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 11450a22c306SShaik Ameer Basha GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1146cba9d2faSAndrzej Hajda GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 11470a22c306SShaik Ameer Basha GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 11480a22c306SShaik Ameer Basha GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 11490a22c306SShaik Ameer Basha GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 11500a22c306SShaik Ameer Basha GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 11510a22c306SShaik Ameer Basha GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 11520a22c306SShaik Ameer Basha GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 11530a22c306SShaik Ameer Basha GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 11540a22c306SShaik Ameer Basha GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 11550a22c306SShaik Ameer Basha GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 11560a22c306SShaik Ameer Basha GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 11570a22c306SShaik Ameer Basha GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 11580a22c306SShaik Ameer Basha GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 11590a22c306SShaik Ameer Basha GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 11600a22c306SShaik Ameer Basha GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 11610a22c306SShaik Ameer Basha GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 11620a22c306SShaik Ameer Basha GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 11630a22c306SShaik Ameer Basha GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 11641609027fSChander Kashyap 1165cba9d2faSAndrzej Hajda GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 11660a22c306SShaik Ameer Basha 11670a22c306SShaik Ameer Basha /* GEN Block */ 11680a22c306SShaik Ameer Basha GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 11690a22c306SShaik Ameer Basha GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 11700a22c306SShaik Ameer Basha GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 11710a22c306SShaik Ameer Basha GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 11720a22c306SShaik Ameer Basha GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 11730a22c306SShaik Ameer Basha GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 11740a22c306SShaik Ameer Basha GATE_IP_GEN, 6, 0, 0), 11750a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 11760a22c306SShaik Ameer Basha GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 11770a22c306SShaik Ameer Basha GATE_IP_GEN, 9, 0, 0), 11780a22c306SShaik Ameer Basha 11790a22c306SShaik Ameer Basha /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 11800a22c306SShaik Ameer Basha GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 11810a22c306SShaik Ameer Basha GATE_BUS_GEN, 28, 0, 0), 11820a22c306SShaik Ameer Basha GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 11831609027fSChander Kashyap 118402932381SShaik Ameer Basha /* GSCL Block */ 118502932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 118602932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 6, 0, 0), 118702932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 118802932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 7, 0, 0), 118902932381SShaik Ameer Basha 119002932381SShaik Ameer Basha GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 119102932381SShaik Ameer Basha GATE_IP_GSCL0, 4, 0, 0), 119202932381SShaik Ameer Basha GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 119302932381SShaik Ameer Basha GATE_IP_GSCL0, 5, 0, 0), 119402932381SShaik Ameer Basha GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 119502932381SShaik Ameer Basha GATE_IP_GSCL0, 6, 0, 0), 11961609027fSChander Kashyap 119702932381SShaik Ameer Basha GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 119802932381SShaik Ameer Basha GATE_IP_GSCL1, 2, 0, 0), 119902932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 12001609027fSChander Kashyap GATE_IP_GSCL1, 3, 0, 0), 120102932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 12021609027fSChander Kashyap GATE_IP_GSCL1, 4, 0, 0), 120302932381SShaik Ameer Basha GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 120402932381SShaik Ameer Basha GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 120502932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 12061609027fSChander Kashyap GATE_IP_GSCL1, 16, 0, 0), 1207cba9d2faSAndrzej Hajda GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 12081609027fSChander Kashyap GATE_IP_GSCL1, 17, 0, 0), 12091609027fSChander Kashyap 121002932381SShaik Ameer Basha /* MSCL Block */ 121102932381SShaik Ameer Basha GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 121202932381SShaik Ameer Basha GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 121302932381SShaik Ameer Basha GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 12144549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 121502932381SShaik Ameer Basha GATE_IP_MSCL, 8, 0, 0), 12164549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 121702932381SShaik Ameer Basha GATE_IP_MSCL, 9, 0, 0), 12184549d93dSShaik Ameer Basha GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 121902932381SShaik Ameer Basha GATE_IP_MSCL, 10, 0, 0), 122002932381SShaik Ameer Basha 12213a767b35SShaik Ameer Basha /* ISP */ 12223a767b35SShaik Ameer Basha GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 12233a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 12243a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 12253a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 12263a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 12273a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 12283a767b35SShaik Ameer Basha GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 12293a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 12303a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 12313a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 12323a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 12333a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 12343a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 12353a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 12363a767b35SShaik Ameer Basha 1237ec4016ffSMarek Szyprowski GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 1238ec4016ffSMarek Szyprowski }; 1239ec4016ffSMarek Szyprowski 1240ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { 1241ec4016ffSMarek Szyprowski DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 1242ec4016ffSMarek Szyprowski }; 1243ec4016ffSMarek Szyprowski 1244ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { 1245ec4016ffSMarek Szyprowski GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1246ec4016ffSMarek Szyprowski GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1247ec4016ffSMarek Szyprowski GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1248ec4016ffSMarek Szyprowski GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1249ec4016ffSMarek Szyprowski GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1250ec4016ffSMarek Szyprowski GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1251ec4016ffSMarek Szyprowski GATE_IP_DISP1, 7, 0, 0), 1252ec4016ffSMarek Szyprowski GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1253ec4016ffSMarek Szyprowski GATE_IP_DISP1, 8, 0, 0), 1254ec4016ffSMarek Szyprowski GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1255ec4016ffSMarek Szyprowski GATE_IP_DISP1, 9, 0, 0), 1256ec4016ffSMarek Szyprowski }; 1257ec4016ffSMarek Szyprowski 1258ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = { 1259ec4016ffSMarek Szyprowski { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ 1260ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ 1261ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ 1262ec4016ffSMarek Szyprowski { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ 1263ec4016ffSMarek Szyprowski { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ 1264ec4016ffSMarek Szyprowski }; 1265ec4016ffSMarek Szyprowski 1266ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { 1267ec4016ffSMarek Szyprowski DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 1268ec4016ffSMarek Szyprowski DIV2_RATIO0, 4, 2), 1269ec4016ffSMarek Szyprowski }; 1270ec4016ffSMarek Szyprowski 1271ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { 1272ec4016ffSMarek Szyprowski GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1273ec4016ffSMarek Szyprowski GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1274ec4016ffSMarek Szyprowski GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 1275ec4016ffSMarek Szyprowski GATE_IP_GSCL1, 6, 0, 0), 1276ec4016ffSMarek Szyprowski GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 1277ec4016ffSMarek Szyprowski GATE_IP_GSCL1, 7, 0, 0), 1278ec4016ffSMarek Szyprowski }; 1279ec4016ffSMarek Szyprowski 1280ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { 1281ec4016ffSMarek Szyprowski { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ 1282ec4016ffSMarek Szyprowski { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ 1283ec4016ffSMarek Szyprowski { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ 1284ec4016ffSMarek Szyprowski { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ 1285ec4016ffSMarek Szyprowski }; 1286ec4016ffSMarek Szyprowski 1287ec4016ffSMarek Szyprowski static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { 1288ec4016ffSMarek Szyprowski DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 1289ec4016ffSMarek Szyprowski }; 1290ec4016ffSMarek Szyprowski 1291ec4016ffSMarek Szyprowski static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { 1292cba9d2faSAndrzej Hajda GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 12931d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 12941d87db4dSShaik Ameer Basha GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 1295ec4016ffSMarek Szyprowski }; 12961609027fSChander Kashyap 1297ec4016ffSMarek Szyprowski static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { 1298ec4016ffSMarek Szyprowski { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ 1299ec4016ffSMarek Szyprowski { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ 1300ec4016ffSMarek Szyprowski { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ 1301ec4016ffSMarek Szyprowski }; 1302ec4016ffSMarek Szyprowski 1303ec4016ffSMarek Szyprowski static const struct exynos5_subcmu_info exynos5x_subcmus[] = { 1304ec4016ffSMarek Szyprowski { 1305ec4016ffSMarek Szyprowski .div_clks = exynos5x_disp_div_clks, 1306ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), 1307ec4016ffSMarek Szyprowski .gate_clks = exynos5x_disp_gate_clks, 1308ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), 1309ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_disp_suspend_regs, 1310ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), 1311ec4016ffSMarek Szyprowski .pd_name = "DISP", 1312ec4016ffSMarek Szyprowski }, { 1313ec4016ffSMarek Szyprowski .div_clks = exynos5x_gsc_div_clks, 1314ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), 1315ec4016ffSMarek Szyprowski .gate_clks = exynos5x_gsc_gate_clks, 1316ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), 1317ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_gsc_suspend_regs, 1318ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), 1319ec4016ffSMarek Szyprowski .pd_name = "GSC", 1320ec4016ffSMarek Szyprowski }, { 1321ec4016ffSMarek Szyprowski .div_clks = exynos5x_mfc_div_clks, 1322ec4016ffSMarek Szyprowski .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), 1323ec4016ffSMarek Szyprowski .gate_clks = exynos5x_mfc_gate_clks, 1324ec4016ffSMarek Szyprowski .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), 1325ec4016ffSMarek Szyprowski .suspend_regs = exynos5x_mfc_suspend_regs, 1326ec4016ffSMarek Szyprowski .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), 1327ec4016ffSMarek Szyprowski .pd_name = "MFC", 1328ec4016ffSMarek Szyprowski }, 13291609027fSChander Kashyap }; 13301609027fSChander Kashyap 1331ebd217e1SKrzysztof Kozlowski static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { 13321d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0), 13331d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0), 13341d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0), 13351d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), 13361d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 13371d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 13381d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 13391d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 13401d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1), 13411d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), 13421d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), 13431d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1), 13441d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), 13451d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 13461d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2), 13471d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), 13481d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), 13491d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3), 13501d5013f1SAndrzej Hajda PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), 1351ca5b4029SThomas Abraham }; 1352ca5b4029SThomas Abraham 13539842452aSSylwester Nawrocki static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 13541d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), 13551d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), 13561d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), 13571d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671), 13581d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0), 13591d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), 13601d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671), 13611d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719), 13621d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0), 13631d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719), 13641d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690), 13651d5013f1SAndrzej Hajda PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), 13669842452aSSylwester Nawrocki }; 13679842452aSSylwester Nawrocki 13686520e968SAlim Akhtar static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1369cba9d2faSAndrzej Hajda [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 13703ff6e0d8SYadwinder Singh Brar APLL_CON0, NULL), 1371cba9d2faSAndrzej Hajda [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1372cdf64eeeSChander Kashyap CPLL_CON0, NULL), 1373cba9d2faSAndrzej Hajda [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 13743ff6e0d8SYadwinder Singh Brar DPLL_CON0, NULL), 13759842452aSSylwester Nawrocki [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 13763ff6e0d8SYadwinder Singh Brar EPLL_CON0, NULL), 1377cba9d2faSAndrzej Hajda [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 13783ff6e0d8SYadwinder Singh Brar RPLL_CON0, NULL), 1379cba9d2faSAndrzej Hajda [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 13803ff6e0d8SYadwinder Singh Brar IPLL_CON0, NULL), 1381cba9d2faSAndrzej Hajda [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 13823ff6e0d8SYadwinder Singh Brar SPLL_CON0, NULL), 1383cba9d2faSAndrzej Hajda [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 13843ff6e0d8SYadwinder Singh Brar VPLL_CON0, NULL), 1385cba9d2faSAndrzej Hajda [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 13863ff6e0d8SYadwinder Singh Brar MPLL_CON0, NULL), 1387cba9d2faSAndrzej Hajda [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 13883ff6e0d8SYadwinder Singh Brar BPLL_CON0, NULL), 1389cba9d2faSAndrzej Hajda [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 13903ff6e0d8SYadwinder Singh Brar KPLL_CON0, NULL), 1391c898c6b7SYadwinder Singh Brar }; 1392c898c6b7SYadwinder Singh Brar 1393bee4f87fSThomas Abraham #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1394bee4f87fSThomas Abraham ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1395bee4f87fSThomas Abraham ((cpud) << 4))) 1396bee4f87fSThomas Abraham 1397bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1398bee4f87fSThomas Abraham { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1399bee4f87fSThomas Abraham { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1400bee4f87fSThomas Abraham { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1401bee4f87fSThomas Abraham { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1402bee4f87fSThomas Abraham { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1403bee4f87fSThomas Abraham { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1404bee4f87fSThomas Abraham { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1405bee4f87fSThomas Abraham { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1406bee4f87fSThomas Abraham { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1407bee4f87fSThomas Abraham { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1408bee4f87fSThomas Abraham { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1409bee4f87fSThomas Abraham { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1410bee4f87fSThomas Abraham { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1411bee4f87fSThomas Abraham { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1412bee4f87fSThomas Abraham { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1413bee4f87fSThomas Abraham { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1414bee4f87fSThomas Abraham { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1415bee4f87fSThomas Abraham { 0 }, 1416bee4f87fSThomas Abraham }; 1417bee4f87fSThomas Abraham 141854abbdb4SBartlomiej Zolnierkiewicz static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 141954abbdb4SBartlomiej Zolnierkiewicz { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 142054abbdb4SBartlomiej Zolnierkiewicz { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 142154abbdb4SBartlomiej Zolnierkiewicz { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 142254abbdb4SBartlomiej Zolnierkiewicz { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 142354abbdb4SBartlomiej Zolnierkiewicz { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 142454abbdb4SBartlomiej Zolnierkiewicz { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 142554abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 142654abbdb4SBartlomiej Zolnierkiewicz { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 142754abbdb4SBartlomiej Zolnierkiewicz { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 142854abbdb4SBartlomiej Zolnierkiewicz { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 142954abbdb4SBartlomiej Zolnierkiewicz { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 143054abbdb4SBartlomiej Zolnierkiewicz { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 143154abbdb4SBartlomiej Zolnierkiewicz { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 143254abbdb4SBartlomiej Zolnierkiewicz { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 143354abbdb4SBartlomiej Zolnierkiewicz { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 143454abbdb4SBartlomiej Zolnierkiewicz { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 143554abbdb4SBartlomiej Zolnierkiewicz { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 143654abbdb4SBartlomiej Zolnierkiewicz { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 143754abbdb4SBartlomiej Zolnierkiewicz { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 143854abbdb4SBartlomiej Zolnierkiewicz { 0 }, 143954abbdb4SBartlomiej Zolnierkiewicz }; 144054abbdb4SBartlomiej Zolnierkiewicz 1441bee4f87fSThomas Abraham #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1442bee4f87fSThomas Abraham ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1443bee4f87fSThomas Abraham 1444bee4f87fSThomas Abraham static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 144554abbdb4SBartlomiej Zolnierkiewicz { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1446bee4f87fSThomas Abraham { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1447bee4f87fSThomas Abraham { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1448bee4f87fSThomas Abraham { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1449bee4f87fSThomas Abraham { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1450bee4f87fSThomas Abraham { 900000, E5420_KFC_DIV(3, 5, 2), }, 1451bee4f87fSThomas Abraham { 800000, E5420_KFC_DIV(3, 5, 2), }, 1452bee4f87fSThomas Abraham { 700000, E5420_KFC_DIV(3, 4, 2), }, 1453bee4f87fSThomas Abraham { 600000, E5420_KFC_DIV(3, 4, 2), }, 1454bee4f87fSThomas Abraham { 500000, E5420_KFC_DIV(3, 4, 2), }, 1455bee4f87fSThomas Abraham { 400000, E5420_KFC_DIV(3, 3, 2), }, 1456bee4f87fSThomas Abraham { 300000, E5420_KFC_DIV(3, 3, 2), }, 1457bee4f87fSThomas Abraham { 200000, E5420_KFC_DIV(3, 3, 2), }, 1458bee4f87fSThomas Abraham { 0 }, 1459bee4f87fSThomas Abraham }; 1460bee4f87fSThomas Abraham 1461305cfab0SKrzysztof Kozlowski static const struct of_device_id ext_clk_match[] __initconst = { 14621609027fSChander Kashyap { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 14631609027fSChander Kashyap { }, 14641609027fSChander Kashyap }; 14651609027fSChander Kashyap 14661609027fSChander Kashyap /* register exynos5420 clocks */ 14676520e968SAlim Akhtar static void __init exynos5x_clk_init(struct device_node *np, 14686520e968SAlim Akhtar enum exynos5x_soc soc) 14691609027fSChander Kashyap { 1470976face4SRahul Sharma struct samsung_clk_provider *ctx; 1471976face4SRahul Sharma 14721609027fSChander Kashyap if (np) { 14731609027fSChander Kashyap reg_base = of_iomap(np, 0); 14741609027fSChander Kashyap if (!reg_base) 14751609027fSChander Kashyap panic("%s: failed to map registers\n", __func__); 14761609027fSChander Kashyap } else { 14771609027fSChander Kashyap panic("%s: unable to determine soc\n", __func__); 14781609027fSChander Kashyap } 14791609027fSChander Kashyap 14806520e968SAlim Akhtar exynos5x_soc = soc; 14816520e968SAlim Akhtar 1482976face4SRahul Sharma ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1483976face4SRahul Sharma 14846520e968SAlim Akhtar samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 14856520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 14861609027fSChander Kashyap ext_clk_match); 1487ca5b4029SThomas Abraham 1488ca5b4029SThomas Abraham if (_get_rate("fin_pll") == 24 * MHZ) { 1489ca5b4029SThomas Abraham exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 14909842452aSSylwester Nawrocki exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; 1491ca5b4029SThomas Abraham exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1492e867e8faSChanwoo Choi exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1493ca5b4029SThomas Abraham } 1494ca5b4029SThomas Abraham 14956520e968SAlim Akhtar samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1496c898c6b7SYadwinder Singh Brar reg_base); 14976520e968SAlim Akhtar samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 14986520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_rate_clks)); 14996520e968SAlim Akhtar samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 15006520e968SAlim Akhtar ARRAY_SIZE(exynos5x_fixed_factor_clks)); 15016520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5x_mux_clks, 15026520e968SAlim Akhtar ARRAY_SIZE(exynos5x_mux_clks)); 15036520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5x_div_clks, 15046520e968SAlim Akhtar ARRAY_SIZE(exynos5x_div_clks)); 15056520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5x_gate_clks, 15066520e968SAlim Akhtar ARRAY_SIZE(exynos5x_gate_clks)); 15076520e968SAlim Akhtar 15086520e968SAlim Akhtar if (soc == EXYNOS5420) { 1509976face4SRahul Sharma samsung_clk_register_mux(ctx, exynos5420_mux_clks, 15101609027fSChander Kashyap ARRAY_SIZE(exynos5420_mux_clks)); 1511976face4SRahul Sharma samsung_clk_register_div(ctx, exynos5420_div_clks, 15121609027fSChander Kashyap ARRAY_SIZE(exynos5420_div_clks)); 151341097f25SSylwester Nawrocki samsung_clk_register_gate(ctx, exynos5420_gate_clks, 151441097f25SSylwester Nawrocki ARRAY_SIZE(exynos5420_gate_clks)); 15156520e968SAlim Akhtar } else { 15166520e968SAlim Akhtar samsung_clk_register_fixed_factor( 15176520e968SAlim Akhtar ctx, exynos5800_fixed_factor_clks, 15186520e968SAlim Akhtar ARRAY_SIZE(exynos5800_fixed_factor_clks)); 15196520e968SAlim Akhtar samsung_clk_register_mux(ctx, exynos5800_mux_clks, 15206520e968SAlim Akhtar ARRAY_SIZE(exynos5800_mux_clks)); 15216520e968SAlim Akhtar samsung_clk_register_div(ctx, exynos5800_div_clks, 15226520e968SAlim Akhtar ARRAY_SIZE(exynos5800_div_clks)); 15236520e968SAlim Akhtar samsung_clk_register_gate(ctx, exynos5800_gate_clks, 15246520e968SAlim Akhtar ARRAY_SIZE(exynos5800_gate_clks)); 15256520e968SAlim Akhtar } 1526388c7885STomasz Figa 152754abbdb4SBartlomiej Zolnierkiewicz if (soc == EXYNOS5420) { 1528bee4f87fSThomas Abraham exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1529bee4f87fSThomas Abraham mout_cpu_p[0], mout_cpu_p[1], 0x200, 1530bee4f87fSThomas Abraham exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); 153154abbdb4SBartlomiej Zolnierkiewicz } else { 153254abbdb4SBartlomiej Zolnierkiewicz exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 153354abbdb4SBartlomiej Zolnierkiewicz mout_cpu_p[0], mout_cpu_p[1], 0x200, 153454abbdb4SBartlomiej Zolnierkiewicz exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); 153554abbdb4SBartlomiej Zolnierkiewicz } 1536bee4f87fSThomas Abraham exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", 1537bee4f87fSThomas Abraham mout_kfc_p[0], mout_kfc_p[1], 0x28200, 1538bee4f87fSThomas Abraham exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); 1539bee4f87fSThomas Abraham 1540388c7885STomasz Figa exynos5420_clk_sleep_init(); 1541ec4016ffSMarek Szyprowski exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), 1542ec4016ffSMarek Szyprowski exynos5x_subcmus); 1543d5e136a2SSylwester Nawrocki 1544d5e136a2SSylwester Nawrocki samsung_clk_of_add_provider(np, ctx); 15451609027fSChander Kashyap } 15466520e968SAlim Akhtar 15476520e968SAlim Akhtar static void __init exynos5420_clk_init(struct device_node *np) 15486520e968SAlim Akhtar { 15496520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5420); 15506520e968SAlim Akhtar } 1551ec4016ffSMarek Szyprowski CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", 1552ec4016ffSMarek Szyprowski exynos5420_clk_init); 15536520e968SAlim Akhtar 15546520e968SAlim Akhtar static void __init exynos5800_clk_init(struct device_node *np) 15556520e968SAlim Akhtar { 15566520e968SAlim Akhtar exynos5x_clk_init(np, EXYNOS5800); 15576520e968SAlim Akhtar } 1558ec4016ffSMarek Szyprowski CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", 1559ec4016ffSMarek Szyprowski exynos5800_clk_init); 1560