11609027fSChander Kashyap /* 21609027fSChander Kashyap * Copyright (c) 2013 Samsung Electronics Co., Ltd. 31609027fSChander Kashyap * Authors: Thomas Abraham <thomas.ab@samsung.com> 41609027fSChander Kashyap * Chander Kashyap <k.chander@samsung.com> 51609027fSChander Kashyap * 61609027fSChander Kashyap * This program is free software; you can redistribute it and/or modify 71609027fSChander Kashyap * it under the terms of the GNU General Public License version 2 as 81609027fSChander Kashyap * published by the Free Software Foundation. 91609027fSChander Kashyap * 101609027fSChander Kashyap * Common Clock Framework support for Exynos5420 SoC. 111609027fSChander Kashyap */ 121609027fSChander Kashyap 13cba9d2faSAndrzej Hajda #include <dt-bindings/clock/exynos5420.h> 141609027fSChander Kashyap #include <linux/clk.h> 151609027fSChander Kashyap #include <linux/clkdev.h> 161609027fSChander Kashyap #include <linux/clk-provider.h> 171609027fSChander Kashyap #include <linux/of.h> 181609027fSChander Kashyap #include <linux/of_address.h> 19388c7885STomasz Figa #include <linux/syscore_ops.h> 201609027fSChander Kashyap 211609027fSChander Kashyap #include "clk.h" 221609027fSChander Kashyap 23c898c6b7SYadwinder Singh Brar #define APLL_LOCK 0x0 24c898c6b7SYadwinder Singh Brar #define APLL_CON0 0x100 251609027fSChander Kashyap #define SRC_CPU 0x200 261609027fSChander Kashyap #define DIV_CPU0 0x500 271609027fSChander Kashyap #define DIV_CPU1 0x504 281609027fSChander Kashyap #define GATE_BUS_CPU 0x700 291609027fSChander Kashyap #define GATE_SCLK_CPU 0x800 305b73721bSNaveen Krishna Chatradhi #define GATE_IP_G2D 0x8800 31c898c6b7SYadwinder Singh Brar #define CPLL_LOCK 0x10020 32c898c6b7SYadwinder Singh Brar #define DPLL_LOCK 0x10030 33c898c6b7SYadwinder Singh Brar #define EPLL_LOCK 0x10040 34c898c6b7SYadwinder Singh Brar #define RPLL_LOCK 0x10050 35c898c6b7SYadwinder Singh Brar #define IPLL_LOCK 0x10060 36c898c6b7SYadwinder Singh Brar #define SPLL_LOCK 0x10070 3753cb6342SSachin Kamat #define VPLL_LOCK 0x10080 38c898c6b7SYadwinder Singh Brar #define MPLL_LOCK 0x10090 39c898c6b7SYadwinder Singh Brar #define CPLL_CON0 0x10120 40c898c6b7SYadwinder Singh Brar #define DPLL_CON0 0x10128 41c898c6b7SYadwinder Singh Brar #define EPLL_CON0 0x10130 42c898c6b7SYadwinder Singh Brar #define RPLL_CON0 0x10140 43c898c6b7SYadwinder Singh Brar #define IPLL_CON0 0x10150 44c898c6b7SYadwinder Singh Brar #define SPLL_CON0 0x10160 45c898c6b7SYadwinder Singh Brar #define VPLL_CON0 0x10170 46c898c6b7SYadwinder Singh Brar #define MPLL_CON0 0x10180 471609027fSChander Kashyap #define SRC_TOP0 0x10200 481609027fSChander Kashyap #define SRC_TOP1 0x10204 491609027fSChander Kashyap #define SRC_TOP2 0x10208 501609027fSChander Kashyap #define SRC_TOP3 0x1020c 511609027fSChander Kashyap #define SRC_TOP4 0x10210 521609027fSChander Kashyap #define SRC_TOP5 0x10214 531609027fSChander Kashyap #define SRC_TOP6 0x10218 541609027fSChander Kashyap #define SRC_TOP7 0x1021c 551609027fSChander Kashyap #define SRC_DISP10 0x1022c 561609027fSChander Kashyap #define SRC_MAU 0x10240 571609027fSChander Kashyap #define SRC_FSYS 0x10244 581609027fSChander Kashyap #define SRC_PERIC0 0x10250 591609027fSChander Kashyap #define SRC_PERIC1 0x10254 603a767b35SShaik Ameer Basha #define SRC_ISP 0x10270 611609027fSChander Kashyap #define SRC_TOP10 0x10280 621609027fSChander Kashyap #define SRC_TOP11 0x10284 631609027fSChander Kashyap #define SRC_TOP12 0x10288 641609027fSChander Kashyap #define SRC_MASK_DISP10 0x1032c 651609027fSChander Kashyap #define SRC_MASK_FSYS 0x10340 661609027fSChander Kashyap #define SRC_MASK_PERIC0 0x10350 671609027fSChander Kashyap #define SRC_MASK_PERIC1 0x10354 681609027fSChander Kashyap #define DIV_TOP0 0x10500 691609027fSChander Kashyap #define DIV_TOP1 0x10504 701609027fSChander Kashyap #define DIV_TOP2 0x10508 711609027fSChander Kashyap #define DIV_DISP10 0x1052c 721609027fSChander Kashyap #define DIV_MAU 0x10544 731609027fSChander Kashyap #define DIV_FSYS0 0x10548 741609027fSChander Kashyap #define DIV_FSYS1 0x1054c 751609027fSChander Kashyap #define DIV_FSYS2 0x10550 761609027fSChander Kashyap #define DIV_PERIC0 0x10558 771609027fSChander Kashyap #define DIV_PERIC1 0x1055c 781609027fSChander Kashyap #define DIV_PERIC2 0x10560 791609027fSChander Kashyap #define DIV_PERIC3 0x10564 801609027fSChander Kashyap #define DIV_PERIC4 0x10568 813a767b35SShaik Ameer Basha #define SCLK_DIV_ISP0 0x10580 823a767b35SShaik Ameer Basha #define SCLK_DIV_ISP1 0x10584 8302932381SShaik Ameer Basha #define DIV2_RATIO0 0x10590 841609027fSChander Kashyap #define GATE_BUS_TOP 0x10700 851609027fSChander Kashyap #define GATE_BUS_FSYS0 0x10740 861609027fSChander Kashyap #define GATE_BUS_PERIC 0x10750 871609027fSChander Kashyap #define GATE_BUS_PERIC1 0x10754 881609027fSChander Kashyap #define GATE_BUS_PERIS0 0x10760 891609027fSChander Kashyap #define GATE_BUS_PERIS1 0x10764 903a767b35SShaik Ameer Basha #define GATE_TOP_SCLK_ISP 0x10870 911609027fSChander Kashyap #define GATE_IP_GSCL0 0x10910 921609027fSChander Kashyap #define GATE_IP_GSCL1 0x10920 931609027fSChander Kashyap #define GATE_IP_MFC 0x1092c 941609027fSChander Kashyap #define GATE_IP_DISP1 0x10928 951609027fSChander Kashyap #define GATE_IP_G3D 0x10930 961609027fSChander Kashyap #define GATE_IP_GEN 0x10934 971609027fSChander Kashyap #define GATE_IP_MSCL 0x10970 981609027fSChander Kashyap #define GATE_TOP_SCLK_GSCL 0x10820 991609027fSChander Kashyap #define GATE_TOP_SCLK_DISP1 0x10828 1001609027fSChander Kashyap #define GATE_TOP_SCLK_MAU 0x1083c 1011609027fSChander Kashyap #define GATE_TOP_SCLK_FSYS 0x10840 1021609027fSChander Kashyap #define GATE_TOP_SCLK_PERIC 0x10850 103c898c6b7SYadwinder Singh Brar #define BPLL_LOCK 0x20010 104c898c6b7SYadwinder Singh Brar #define BPLL_CON0 0x20110 1051609027fSChander Kashyap #define SRC_CDREX 0x20200 106c898c6b7SYadwinder Singh Brar #define KPLL_LOCK 0x28000 107c898c6b7SYadwinder Singh Brar #define KPLL_CON0 0x28100 1081609027fSChander Kashyap #define SRC_KFC 0x28200 1091609027fSChander Kashyap #define DIV_KFC0 0x28500 1101609027fSChander Kashyap 111c898c6b7SYadwinder Singh Brar /* list of PLLs */ 112c898c6b7SYadwinder Singh Brar enum exynos5420_plls { 113c898c6b7SYadwinder Singh Brar apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 114c898c6b7SYadwinder Singh Brar bpll, kpll, 115c898c6b7SYadwinder Singh Brar nr_plls /* number of PLLs */ 116c898c6b7SYadwinder Singh Brar }; 117c898c6b7SYadwinder Singh Brar 118388c7885STomasz Figa static void __iomem *reg_base; 119388c7885STomasz Figa 120388c7885STomasz Figa #ifdef CONFIG_PM_SLEEP 121388c7885STomasz Figa static struct samsung_clk_reg_dump *exynos5420_save; 122388c7885STomasz Figa 1231609027fSChander Kashyap /* 1241609027fSChander Kashyap * list of controller registers to be saved and restored during a 1251609027fSChander Kashyap * suspend/resume cycle. 1261609027fSChander Kashyap */ 127202e5ae9SSachin Kamat static unsigned long exynos5420_clk_regs[] __initdata = { 1281609027fSChander Kashyap SRC_CPU, 1291609027fSChander Kashyap DIV_CPU0, 1301609027fSChander Kashyap DIV_CPU1, 1311609027fSChander Kashyap GATE_BUS_CPU, 1321609027fSChander Kashyap GATE_SCLK_CPU, 1331609027fSChander Kashyap SRC_TOP0, 1341609027fSChander Kashyap SRC_TOP1, 1351609027fSChander Kashyap SRC_TOP2, 1361609027fSChander Kashyap SRC_TOP3, 1371609027fSChander Kashyap SRC_TOP4, 1381609027fSChander Kashyap SRC_TOP5, 1391609027fSChander Kashyap SRC_TOP6, 1401609027fSChander Kashyap SRC_TOP7, 1411609027fSChander Kashyap SRC_DISP10, 1421609027fSChander Kashyap SRC_MAU, 1431609027fSChander Kashyap SRC_FSYS, 1441609027fSChander Kashyap SRC_PERIC0, 1451609027fSChander Kashyap SRC_PERIC1, 1461609027fSChander Kashyap SRC_TOP10, 1471609027fSChander Kashyap SRC_TOP11, 1481609027fSChander Kashyap SRC_TOP12, 1491609027fSChander Kashyap SRC_MASK_DISP10, 1501609027fSChander Kashyap SRC_MASK_FSYS, 1511609027fSChander Kashyap SRC_MASK_PERIC0, 1521609027fSChander Kashyap SRC_MASK_PERIC1, 1533a767b35SShaik Ameer Basha SRC_ISP, 1541609027fSChander Kashyap DIV_TOP0, 1551609027fSChander Kashyap DIV_TOP1, 1561609027fSChander Kashyap DIV_TOP2, 1571609027fSChander Kashyap DIV_DISP10, 1581609027fSChander Kashyap DIV_MAU, 1591609027fSChander Kashyap DIV_FSYS0, 1601609027fSChander Kashyap DIV_FSYS1, 1611609027fSChander Kashyap DIV_FSYS2, 1621609027fSChander Kashyap DIV_PERIC0, 1631609027fSChander Kashyap DIV_PERIC1, 1641609027fSChander Kashyap DIV_PERIC2, 1651609027fSChander Kashyap DIV_PERIC3, 1661609027fSChander Kashyap DIV_PERIC4, 1673a767b35SShaik Ameer Basha SCLK_DIV_ISP0, 1683a767b35SShaik Ameer Basha SCLK_DIV_ISP1, 16902932381SShaik Ameer Basha DIV2_RATIO0, 1701609027fSChander Kashyap GATE_BUS_TOP, 1711609027fSChander Kashyap GATE_BUS_FSYS0, 1721609027fSChander Kashyap GATE_BUS_PERIC, 1731609027fSChander Kashyap GATE_BUS_PERIC1, 1741609027fSChander Kashyap GATE_BUS_PERIS0, 1751609027fSChander Kashyap GATE_BUS_PERIS1, 1763a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 1771609027fSChander Kashyap GATE_IP_GSCL0, 1781609027fSChander Kashyap GATE_IP_GSCL1, 1791609027fSChander Kashyap GATE_IP_MFC, 1801609027fSChander Kashyap GATE_IP_DISP1, 1811609027fSChander Kashyap GATE_IP_G3D, 1821609027fSChander Kashyap GATE_IP_GEN, 1831609027fSChander Kashyap GATE_IP_MSCL, 1841609027fSChander Kashyap GATE_TOP_SCLK_GSCL, 1851609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 1861609027fSChander Kashyap GATE_TOP_SCLK_MAU, 1871609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1881609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1891609027fSChander Kashyap SRC_CDREX, 1901609027fSChander Kashyap SRC_KFC, 1911609027fSChander Kashyap DIV_KFC0, 1921609027fSChander Kashyap }; 1931609027fSChander Kashyap 194388c7885STomasz Figa static int exynos5420_clk_suspend(void) 195388c7885STomasz Figa { 196388c7885STomasz Figa samsung_clk_save(reg_base, exynos5420_save, 197388c7885STomasz Figa ARRAY_SIZE(exynos5420_clk_regs)); 198388c7885STomasz Figa 199388c7885STomasz Figa return 0; 200388c7885STomasz Figa } 201388c7885STomasz Figa 202388c7885STomasz Figa static void exynos5420_clk_resume(void) 203388c7885STomasz Figa { 204388c7885STomasz Figa samsung_clk_restore(reg_base, exynos5420_save, 205388c7885STomasz Figa ARRAY_SIZE(exynos5420_clk_regs)); 206388c7885STomasz Figa } 207388c7885STomasz Figa 208388c7885STomasz Figa static struct syscore_ops exynos5420_clk_syscore_ops = { 209388c7885STomasz Figa .suspend = exynos5420_clk_suspend, 210388c7885STomasz Figa .resume = exynos5420_clk_resume, 211388c7885STomasz Figa }; 212388c7885STomasz Figa 213388c7885STomasz Figa static void exynos5420_clk_sleep_init(void) 214388c7885STomasz Figa { 215388c7885STomasz Figa exynos5420_save = samsung_clk_alloc_reg_dump(exynos5420_clk_regs, 216388c7885STomasz Figa ARRAY_SIZE(exynos5420_clk_regs)); 217388c7885STomasz Figa if (!exynos5420_save) { 218388c7885STomasz Figa pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 219388c7885STomasz Figa __func__); 220388c7885STomasz Figa return; 221388c7885STomasz Figa } 222388c7885STomasz Figa 223388c7885STomasz Figa register_syscore_ops(&exynos5420_clk_syscore_ops); 224388c7885STomasz Figa } 225388c7885STomasz Figa #else 226388c7885STomasz Figa static void exynos5420_clk_sleep_init(void) {} 227388c7885STomasz Figa #endif 228388c7885STomasz Figa 2291609027fSChander Kashyap /* list of all parent clocks */ 230dbd713bbSShaik Ameer Basha PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 231dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll"}; 232dbd713bbSShaik Ameer Basha PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 233dbd713bbSShaik Ameer Basha PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 234dbd713bbSShaik Ameer Basha PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 235dbd713bbSShaik Ameer Basha PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 236dbd713bbSShaik Ameer Basha PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 237dbd713bbSShaik Ameer Basha PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 238dbd713bbSShaik Ameer Basha PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 239dbd713bbSShaik Ameer Basha PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 240dbd713bbSShaik Ameer Basha PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 241dbd713bbSShaik Ameer Basha PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 242dbd713bbSShaik Ameer Basha PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 243dbd713bbSShaik Ameer Basha PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 244dbd713bbSShaik Ameer Basha PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 2451609027fSChander Kashyap 246dbd713bbSShaik Ameer Basha PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 247dbd713bbSShaik Ameer Basha "mout_sclk_mpll"}; 248dbd713bbSShaik Ameer Basha PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 249dbd713bbSShaik Ameer Basha "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 250dbd713bbSShaik Ameer Basha "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 251dbd713bbSShaik Ameer Basha PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 252dbd713bbSShaik Ameer Basha PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 253dbd713bbSShaik Ameer Basha PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 2541609027fSChander Kashyap 255dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 256dbd713bbSShaik Ameer Basha PNAME(mout_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" }; 2571609027fSChander Kashyap 258dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 259dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 2601609027fSChander Kashyap 261dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 262dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 2633a767b35SShaik Ameer Basha PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 2643a767b35SShaik Ameer Basha PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 2653a767b35SShaik Ameer Basha 2663a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 2673a767b35SShaik Ameer Basha "mout_sclk_spll"}; 2683a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 2693a767b35SShaik Ameer Basha 2703a767b35SShaik Ameer Basha PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 2713a767b35SShaik Ameer Basha PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 2721609027fSChander Kashyap 273dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 274dbd713bbSShaik Ameer Basha PNAME(mout_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 2751609027fSChander Kashyap 276dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 277dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 2781609027fSChander Kashyap 279dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 280dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 2811609027fSChander Kashyap 282dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 283dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 2841609027fSChander Kashyap 285dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 286dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 2873a767b35SShaik Ameer Basha PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 2881609027fSChander Kashyap 289dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 290dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 2911609027fSChander Kashyap 292dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 293dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 2941609027fSChander Kashyap 295dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 296dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 2971609027fSChander Kashyap 298dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 299dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 3001609027fSChander Kashyap 301dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 302dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 3031609027fSChander Kashyap 304dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 305dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 3061609027fSChander Kashyap 307dbd713bbSShaik Ameer Basha PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 308dbd713bbSShaik Ameer Basha PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 3091609027fSChander Kashyap 310dbd713bbSShaik Ameer Basha PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 311dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 312dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 313dbd713bbSShaik Ameer Basha PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 314dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 315dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 316dbd713bbSShaik Ameer Basha PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 317dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 318dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 319dbd713bbSShaik Ameer Basha PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 320dbd713bbSShaik Ameer Basha "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 321dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 322dbd713bbSShaik Ameer Basha PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 323dbd713bbSShaik Ameer Basha PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 324dbd713bbSShaik Ameer Basha "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 325dbd713bbSShaik Ameer Basha "mout_sclk_epll", "mout_sclk_rpll"}; 3261609027fSChander Kashyap 3271609027fSChander Kashyap /* fixed rate clocks generated outside the soc */ 328c7306229SSachin Kamat static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 329cba9d2faSAndrzej Hajda FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 3301609027fSChander Kashyap }; 3311609027fSChander Kashyap 3321609027fSChander Kashyap /* fixed rate clocks generated inside the soc */ 333c7306229SSachin Kamat static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { 334cba9d2faSAndrzej Hajda FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 335cba9d2faSAndrzej Hajda FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 336cba9d2faSAndrzej Hajda FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 337cba9d2faSAndrzej Hajda FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), 338cba9d2faSAndrzej Hajda FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 3391609027fSChander Kashyap }; 3401609027fSChander Kashyap 341c7306229SSachin Kamat static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 342cba9d2faSAndrzej Hajda FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0), 3431609027fSChander Kashyap }; 3441609027fSChander Kashyap 345c7306229SSachin Kamat static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 346dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 347dbd713bbSShaik Ameer Basha MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 348dbd713bbSShaik Ameer Basha MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), 349dbd713bbSShaik Ameer Basha MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 350dbd713bbSShaik Ameer Basha MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1), 351dbd713bbSShaik Ameer Basha MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 3521609027fSChander Kashyap 353dbd713bbSShaik Ameer Basha MUX(0, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 3541609027fSChander Kashyap 3553a767b35SShaik Ameer Basha MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 356dbd713bbSShaik Ameer Basha MUX_A(0, "mout_aclk400_mscl", mout_group1_p, 3571609027fSChander Kashyap SRC_TOP0, 4, 2, "aclk400_mscl"), 358dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 359dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 360dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 3611609027fSChander Kashyap 362dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 3633a767b35SShaik Ameer Basha MUX(0, "mout_aclk333_432_isp", mout_group4_p, 3643a767b35SShaik Ameer Basha SRC_TOP1, 4, 2), 365dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 3663a767b35SShaik Ameer Basha MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 367dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 368dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 369dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 3701609027fSChander Kashyap 371dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 372dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 373dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 374dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 375dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 376dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 3771609027fSChander Kashyap 3783a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 3793a767b35SShaik Ameer Basha SRC_TOP3, 0, 1), 380dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 3811609027fSChander Kashyap SRC_TOP3, 4, 1), 382dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk200_disp1", mout_aclk200_disp1_p, SRC_TOP3, 8, 1), 383dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 3841609027fSChander Kashyap SRC_TOP3, 12, 1), 385dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 3861609027fSChander Kashyap SRC_TOP3, 28, 1), 3871609027fSChander Kashyap 388dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 3891609027fSChander Kashyap SRC_TOP4, 0, 1), 3903a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 3913a767b35SShaik Ameer Basha SRC_TOP4, 4, 1), 392dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66_peric", mout_aclk66_peric_p, SRC_TOP4, 8, 1), 3933a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 3943a767b35SShaik Ameer Basha SRC_TOP4, 12, 1), 3953a767b35SShaik Ameer Basha MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 3963a767b35SShaik Ameer Basha SRC_TOP4, 16, 1), 397dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 398dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 399dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1), 4001609027fSChander Kashyap 401dbd713bbSShaik Ameer Basha MUX(0, "mout_aclk66_psgen", mout_aclk66_peric_p, SRC_TOP5, 4, 1), 402dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, SRC_TOP5, 403dbd713bbSShaik Ameer Basha 8, 1), 404dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, SRC_TOP5, 405dbd713bbSShaik Ameer Basha 12, 1), 406dbd713bbSShaik Ameer Basha MUX_A(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 4071609027fSChander Kashyap SRC_TOP5, 16, 1, "aclkg3d"), 408dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 4091609027fSChander Kashyap SRC_TOP5, 20, 1), 410dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p, 4111609027fSChander Kashyap SRC_TOP5, 24, 1), 412dbd713bbSShaik Ameer Basha MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p, 4131609027fSChander Kashyap SRC_TOP5, 28, 1), 4141609027fSChander Kashyap 415dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 416dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 417dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 418dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 419dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 420dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1), 421dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 422dbd713bbSShaik Ameer Basha MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 4231609027fSChander Kashyap 4243a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 4253a767b35SShaik Ameer Basha SRC_TOP10, 0, 1), 426dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 427dbd713bbSShaik Ameer Basha SRC_TOP10, 4, 1), 428dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1), 429dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 4301609027fSChander Kashyap SRC_TOP10, 12, 1), 431dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 432dbd713bbSShaik Ameer Basha SRC_TOP10, 28, 1), 4333a767b35SShaik Ameer Basha 434dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 4351609027fSChander Kashyap SRC_TOP11, 0, 1), 4363a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 4373a767b35SShaik Ameer Basha SRC_TOP11, 4, 1), 438dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 4393a767b35SShaik Ameer Basha MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 4403a767b35SShaik Ameer Basha SRC_TOP11, 12, 1), 441dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 442dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 443dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1), 4441609027fSChander Kashyap 445dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 446dbd713bbSShaik Ameer Basha SRC_TOP12, 8, 1), 447dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 448dbd713bbSShaik Ameer Basha SRC_TOP12, 12, 1), 449dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 450dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 451dbd713bbSShaik Ameer Basha SRC_TOP12, 20, 1), 452dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p, 4531609027fSChander Kashyap SRC_TOP12, 24, 1), 454dbd713bbSShaik Ameer Basha MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p, 455dbd713bbSShaik Ameer Basha SRC_TOP12, 28, 1), 4561609027fSChander Kashyap 4571609027fSChander Kashyap /* DISP1 Block */ 458dbd713bbSShaik Ameer Basha MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 459dbd713bbSShaik Ameer Basha MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 460dbd713bbSShaik Ameer Basha MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 461dbd713bbSShaik Ameer Basha MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 462dbd713bbSShaik Ameer Basha MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 4631609027fSChander Kashyap 4641609027fSChander Kashyap /* MAU Block */ 465dbd713bbSShaik Ameer Basha MUX(0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 4661609027fSChander Kashyap 4671609027fSChander Kashyap /* FSYS Block */ 468dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 469dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 470dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 471dbd713bbSShaik Ameer Basha MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 472dbd713bbSShaik Ameer Basha MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 473dbd713bbSShaik Ameer Basha MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 4741609027fSChander Kashyap 4751609027fSChander Kashyap /* PERIC Block */ 476dbd713bbSShaik Ameer Basha MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 477dbd713bbSShaik Ameer Basha MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 478dbd713bbSShaik Ameer Basha MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 479dbd713bbSShaik Ameer Basha MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 480dbd713bbSShaik Ameer Basha MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 481dbd713bbSShaik Ameer Basha MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 482dbd713bbSShaik Ameer Basha MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 483dbd713bbSShaik Ameer Basha MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 484dbd713bbSShaik Ameer Basha MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 485dbd713bbSShaik Ameer Basha MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 486dbd713bbSShaik Ameer Basha MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 487dbd713bbSShaik Ameer Basha MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 4883a767b35SShaik Ameer Basha 4893a767b35SShaik Ameer Basha /* ISP Block */ 4903a767b35SShaik Ameer Basha MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 4913a767b35SShaik Ameer Basha MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 4923a767b35SShaik Ameer Basha MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 4933a767b35SShaik Ameer Basha MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 4943a767b35SShaik Ameer Basha MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 4951609027fSChander Kashyap }; 4961609027fSChander Kashyap 497c7306229SSachin Kamat static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 498cba9d2faSAndrzej Hajda DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 499cba9d2faSAndrzej Hajda DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 500cba9d2faSAndrzej Hajda DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 501dbd713bbSShaik Ameer Basha DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 502cba9d2faSAndrzej Hajda DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 5031609027fSChander Kashyap 5043a767b35SShaik Ameer Basha DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3), 505cba9d2faSAndrzej Hajda DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 506cba9d2faSAndrzej Hajda DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 507cba9d2faSAndrzej Hajda DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 508cba9d2faSAndrzej Hajda DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 509cba9d2faSAndrzej Hajda DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 5101609027fSChander Kashyap 511cba9d2faSAndrzej Hajda DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 5121609027fSChander Kashyap DIV_TOP1, 0, 3), 5133a767b35SShaik Ameer Basha DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp", 5143a767b35SShaik Ameer Basha DIV_TOP1, 4, 3), 515cba9d2faSAndrzej Hajda DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 5163a767b35SShaik Ameer Basha DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0", 5173a767b35SShaik Ameer Basha DIV_TOP1, 16, 3), 518cba9d2faSAndrzej Hajda DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 519cba9d2faSAndrzej Hajda DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 520cba9d2faSAndrzej Hajda DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 5211609027fSChander Kashyap 522cba9d2faSAndrzej Hajda DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), 523cba9d2faSAndrzej Hajda DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 524cba9d2faSAndrzej Hajda DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 525cba9d2faSAndrzej Hajda DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 526cba9d2faSAndrzej Hajda DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1", 5271609027fSChander Kashyap DIV_TOP2, 24, 3, "aclk300_disp1"), 528cba9d2faSAndrzej Hajda DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 5291609027fSChander Kashyap 5301609027fSChander Kashyap /* DISP1 Block */ 531cba9d2faSAndrzej Hajda DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), 532cba9d2faSAndrzej Hajda DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 533cba9d2faSAndrzej Hajda DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 534cba9d2faSAndrzej Hajda DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 5351609027fSChander Kashyap 5361609027fSChander Kashyap /* Audio Block */ 537cba9d2faSAndrzej Hajda DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 538cba9d2faSAndrzej Hajda DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 5391609027fSChander Kashyap 5401609027fSChander Kashyap /* USB3.0 */ 541cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 542cba9d2faSAndrzej Hajda DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 543cba9d2faSAndrzej Hajda DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 544cba9d2faSAndrzej Hajda DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 5451609027fSChander Kashyap 5461609027fSChander Kashyap /* MMC */ 547cba9d2faSAndrzej Hajda DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 548cba9d2faSAndrzej Hajda DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 549cba9d2faSAndrzej Hajda DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 5501609027fSChander Kashyap 551cba9d2faSAndrzej Hajda DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 5521609027fSChander Kashyap 5531609027fSChander Kashyap /* UART and PWM */ 554cba9d2faSAndrzej Hajda DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 555cba9d2faSAndrzej Hajda DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 556cba9d2faSAndrzej Hajda DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 557cba9d2faSAndrzej Hajda DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 558cba9d2faSAndrzej Hajda DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 5591609027fSChander Kashyap 5601609027fSChander Kashyap /* SPI */ 561cba9d2faSAndrzej Hajda DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 562cba9d2faSAndrzej Hajda DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 563cba9d2faSAndrzej Hajda DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 5641609027fSChander Kashyap 5651609027fSChander Kashyap /* PCM */ 566cba9d2faSAndrzej Hajda DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 567cba9d2faSAndrzej Hajda DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 5681609027fSChander Kashyap 5691609027fSChander Kashyap /* Audio - I2S */ 570cba9d2faSAndrzej Hajda DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 571cba9d2faSAndrzej Hajda DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 572cba9d2faSAndrzej Hajda DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 573cba9d2faSAndrzej Hajda DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 574cba9d2faSAndrzej Hajda DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 5751609027fSChander Kashyap 5761609027fSChander Kashyap /* SPI Pre-Ratio */ 577cba9d2faSAndrzej Hajda DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), 578cba9d2faSAndrzej Hajda DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), 579cba9d2faSAndrzej Hajda DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), 5803a767b35SShaik Ameer Basha 58102932381SShaik Ameer Basha /* GSCL Block */ 58202932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 58302932381SShaik Ameer Basha DIV2_RATIO0, 4, 2), 58402932381SShaik Ameer Basha DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 58502932381SShaik Ameer Basha 5863a767b35SShaik Ameer Basha /* ISP Block */ 5873a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 5883a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 5893a767b35SShaik Ameer Basha DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 5903a767b35SShaik Ameer Basha DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 5913a767b35SShaik Ameer Basha DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 5923a767b35SShaik Ameer Basha DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 5933a767b35SShaik Ameer Basha DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 5943a767b35SShaik Ameer Basha DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 5953a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 5963a767b35SShaik Ameer Basha DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 5973a767b35SShaik Ameer Basha CLK_SET_RATE_PARENT, 0), 5981609027fSChander Kashyap }; 5991609027fSChander Kashyap 600c7306229SSachin Kamat static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 6015b73721bSNaveen Krishna Chatradhi /* G2D */ 6025b73721bSNaveen Krishna Chatradhi GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 6035b73721bSNaveen Krishna Chatradhi 6041609027fSChander Kashyap /* TODO: Re-verify the CG bits for all the gate clocks */ 605cba9d2faSAndrzej Hajda GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, 606cba9d2faSAndrzej Hajda "mct"), 6071609027fSChander Kashyap 6081609027fSChander Kashyap GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 6091609027fSChander Kashyap GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 6101609027fSChander Kashyap GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 6111609027fSChander Kashyap GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 6121609027fSChander Kashyap 6131609027fSChander Kashyap GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 6141609027fSChander Kashyap GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 6151609027fSChander Kashyap GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 6161609027fSChander Kashyap GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), 6171609027fSChander Kashyap GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 6181609027fSChander Kashyap GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 6193a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 6203a767b35SShaik Ameer Basha GATE_BUS_TOP, 5, 0, 0), 6211609027fSChander Kashyap GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 6221609027fSChander Kashyap GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), 6231609027fSChander Kashyap GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 6241609027fSChander Kashyap GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 6253a767b35SShaik Ameer Basha GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 6263a767b35SShaik Ameer Basha GATE_BUS_TOP, 8, 0, 0), 6271609027fSChander Kashyap GATE(0, "pclk66_gpio", "mout_sw_aclk66", 6281609027fSChander Kashyap GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 6291609027fSChander Kashyap GATE(0, "aclk66_psgen", "mout_aclk66_psgen", 6301609027fSChander Kashyap GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 6311609027fSChander Kashyap GATE(0, "aclk66_peric", "mout_aclk66_peric", 6321609027fSChander Kashyap GATE_BUS_TOP, 11, 0, 0), 6333a767b35SShaik Ameer Basha GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 6343a767b35SShaik Ameer Basha GATE_BUS_TOP, 13, 0, 0), 6351609027fSChander Kashyap GATE(0, "aclk166", "mout_user_aclk166", 6361609027fSChander Kashyap GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 6371609027fSChander Kashyap GATE(0, "aclk333", "mout_aclk333", 6381609027fSChander Kashyap GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 6393a767b35SShaik Ameer Basha GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 6403a767b35SShaik Ameer Basha GATE_BUS_TOP, 16, 0, 0), 64102932381SShaik Ameer Basha GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 64202932381SShaik Ameer Basha GATE_BUS_TOP, 17, 0, 0), 6431609027fSChander Kashyap 6441609027fSChander Kashyap /* sclk */ 645cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 6461609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 647cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 6481609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 649cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 6501609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 651cba9d2faSAndrzej Hajda GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 6521609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 653cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0", 6541609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 655cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1", 6561609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 657cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2", 6581609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 659cba9d2faSAndrzej Hajda GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 6601609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 661cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 6621609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 663cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 6641609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 665cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 6661609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 667cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 6681609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 669cba9d2faSAndrzej Hajda GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 6701609027fSChander Kashyap GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 6711609027fSChander Kashyap 672cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 6731609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 674cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 6751609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 676cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 6771609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 678cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 6791609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 680cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 6811609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 682cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 6831609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 684cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 6851609027fSChander Kashyap GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 6861609027fSChander Kashyap 687cba9d2faSAndrzej Hajda GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro", 6881609027fSChander Kashyap SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 6891609027fSChander Kashyap 6901609027fSChander Kashyap /* Display */ 691cba9d2faSAndrzej Hajda GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 6921609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 693cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 6941609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 695cba9d2faSAndrzej Hajda GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 6961609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), 697cba9d2faSAndrzej Hajda GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 6981609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 699cba9d2faSAndrzej Hajda GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 7001609027fSChander Kashyap GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 7011609027fSChander Kashyap 7021609027fSChander Kashyap /* Maudio Block */ 703cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 7041609027fSChander Kashyap GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 705cba9d2faSAndrzej Hajda GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 7061609027fSChander Kashyap GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 7071609027fSChander Kashyap /* FSYS */ 708cba9d2faSAndrzej Hajda GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 709cba9d2faSAndrzej Hajda GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 710cba9d2faSAndrzej Hajda GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 711cba9d2faSAndrzej Hajda GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 712cba9d2faSAndrzej Hajda GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), 713cba9d2faSAndrzej Hajda GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), 714cba9d2faSAndrzej Hajda GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), 715cba9d2faSAndrzej Hajda GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), 716cba9d2faSAndrzej Hajda GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 7171609027fSChander Kashyap GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), 718cba9d2faSAndrzej Hajda GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), 719cba9d2faSAndrzej Hajda GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), 720cba9d2faSAndrzej Hajda GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), 7211609027fSChander Kashyap 7221609027fSChander Kashyap /* UART */ 723cba9d2faSAndrzej Hajda GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0), 724cba9d2faSAndrzej Hajda GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0), 725cba9d2faSAndrzej Hajda GATE_A(CLK_UART2, "uart2", "aclk66_peric", 7261609027fSChander Kashyap GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"), 727cba9d2faSAndrzej Hajda GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0), 7281609027fSChander Kashyap /* I2C */ 729cba9d2faSAndrzej Hajda GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0), 730cba9d2faSAndrzej Hajda GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0), 731cba9d2faSAndrzej Hajda GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0), 732cba9d2faSAndrzej Hajda GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0), 733cba9d2faSAndrzej Hajda GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0), 734cba9d2faSAndrzej Hajda GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0), 735cba9d2faSAndrzej Hajda GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0), 736cba9d2faSAndrzej Hajda GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0), 737cba9d2faSAndrzej Hajda GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 738cba9d2faSAndrzej Hajda 0), 739cba9d2faSAndrzej Hajda GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0), 7401609027fSChander Kashyap /* SPI */ 741cba9d2faSAndrzej Hajda GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0), 742cba9d2faSAndrzej Hajda GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0), 743cba9d2faSAndrzej Hajda GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0), 744cba9d2faSAndrzej Hajda GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0), 7451609027fSChander Kashyap /* I2S */ 746cba9d2faSAndrzej Hajda GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0), 747cba9d2faSAndrzej Hajda GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0), 7481609027fSChander Kashyap /* PCM */ 749cba9d2faSAndrzej Hajda GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0), 750cba9d2faSAndrzej Hajda GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0), 7511609027fSChander Kashyap /* PWM */ 752cba9d2faSAndrzej Hajda GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0), 7531609027fSChander Kashyap /* SPDIF */ 754cba9d2faSAndrzej Hajda GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0), 7551609027fSChander Kashyap 756cba9d2faSAndrzej Hajda GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0), 757cba9d2faSAndrzej Hajda GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0), 758cba9d2faSAndrzej Hajda GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0), 7591609027fSChander Kashyap 760cba9d2faSAndrzej Hajda GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 7611609027fSChander Kashyap GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0), 762cba9d2faSAndrzej Hajda GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 7631609027fSChander Kashyap GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0), 764cba9d2faSAndrzej Hajda GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0), 765cba9d2faSAndrzej Hajda GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0), 766cba9d2faSAndrzej Hajda GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0), 767cba9d2faSAndrzej Hajda GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0), 768cba9d2faSAndrzej Hajda GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0), 769cba9d2faSAndrzej Hajda GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0), 770cba9d2faSAndrzej Hajda GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0), 771cba9d2faSAndrzej Hajda GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0), 772cba9d2faSAndrzej Hajda GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0), 773cba9d2faSAndrzej Hajda GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0), 7741609027fSChander Kashyap 775cba9d2faSAndrzej Hajda GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 776cba9d2faSAndrzej Hajda 0), 777cba9d2faSAndrzej Hajda GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 778cba9d2faSAndrzej Hajda GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0), 779cba9d2faSAndrzej Hajda GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0), 780cba9d2faSAndrzej Hajda GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0), 781cba9d2faSAndrzej Hajda GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0), 7821609027fSChander Kashyap 78302932381SShaik Ameer Basha /* GSCL Block */ 78402932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 78502932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 6, 0, 0), 78602932381SShaik Ameer Basha GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 78702932381SShaik Ameer Basha GATE_TOP_SCLK_GSCL, 7, 0, 0), 78802932381SShaik Ameer Basha 789cba9d2faSAndrzej Hajda GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 790cba9d2faSAndrzej Hajda GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 79102932381SShaik Ameer Basha GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 79202932381SShaik Ameer Basha GATE_IP_GSCL0, 4, 0, 0), 79302932381SShaik Ameer Basha GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 79402932381SShaik Ameer Basha GATE_IP_GSCL0, 5, 0, 0), 79502932381SShaik Ameer Basha GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 79602932381SShaik Ameer Basha GATE_IP_GSCL0, 6, 0, 0), 7971609027fSChander Kashyap 79802932381SShaik Ameer Basha GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 79902932381SShaik Ameer Basha GATE_IP_GSCL1, 2, 0, 0), 80002932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 8011609027fSChander Kashyap GATE_IP_GSCL1, 3, 0, 0), 80202932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 8031609027fSChander Kashyap GATE_IP_GSCL1, 4, 0, 0), 80402932381SShaik Ameer Basha GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 80502932381SShaik Ameer Basha GATE_IP_GSCL1, 6, 0, 0), 80602932381SShaik Ameer Basha GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 80702932381SShaik Ameer Basha GATE_IP_GSCL1, 7, 0, 0), 80802932381SShaik Ameer Basha GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 80902932381SShaik Ameer Basha GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 81002932381SShaik Ameer Basha GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 8111609027fSChander Kashyap GATE_IP_GSCL1, 16, 0, 0), 812cba9d2faSAndrzej Hajda GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 8131609027fSChander Kashyap GATE_IP_GSCL1, 17, 0, 0), 8141609027fSChander Kashyap 81502932381SShaik Ameer Basha /* MSCL Block */ 81602932381SShaik Ameer Basha GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 81702932381SShaik Ameer Basha GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 81802932381SShaik Ameer Basha GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 81902932381SShaik Ameer Basha GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", 82002932381SShaik Ameer Basha GATE_IP_MSCL, 8, 0, 0), 82102932381SShaik Ameer Basha GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", 82202932381SShaik Ameer Basha GATE_IP_MSCL, 9, 0, 0), 82302932381SShaik Ameer Basha GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", 82402932381SShaik Ameer Basha GATE_IP_MSCL, 10, 0, 0), 82502932381SShaik Ameer Basha 826cba9d2faSAndrzej Hajda GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 827cba9d2faSAndrzej Hajda GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 828cba9d2faSAndrzej Hajda GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 829cba9d2faSAndrzej Hajda GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0), 830cba9d2faSAndrzej Hajda GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 831cba9d2faSAndrzej Hajda GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 832cba9d2faSAndrzej Hajda 0), 8331609027fSChander Kashyap 8343a767b35SShaik Ameer Basha /* ISP */ 8353a767b35SShaik Ameer Basha GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 8363a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 8373a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 8383a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 8393a767b35SShaik Ameer Basha GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 8403a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 8413a767b35SShaik Ameer Basha GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 8423a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 8433a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 8443a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 8453a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 8463a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 8473a767b35SShaik Ameer Basha GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 8483a767b35SShaik Ameer Basha GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 8493a767b35SShaik Ameer Basha 850cba9d2faSAndrzej Hajda GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 851cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 852cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 8531609027fSChander Kashyap 854cba9d2faSAndrzej Hajda GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0), 8551609027fSChander Kashyap 856cba9d2faSAndrzej Hajda GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 857cba9d2faSAndrzej Hajda GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 858cba9d2faSAndrzej Hajda GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 859cba9d2faSAndrzej Hajda GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), 860cba9d2faSAndrzej Hajda GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), 861cba9d2faSAndrzej Hajda GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0), 862cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0), 8631609027fSChander Kashyap 864cba9d2faSAndrzej Hajda GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 865cba9d2faSAndrzej Hajda 0), 8661609027fSChander Kashyap }; 8671609027fSChander Kashyap 868202e5ae9SSachin Kamat static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { 869cba9d2faSAndrzej Hajda [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 8703ff6e0d8SYadwinder Singh Brar APLL_CON0, NULL), 871cba9d2faSAndrzej Hajda [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 872cdf64eeeSChander Kashyap CPLL_CON0, NULL), 873cba9d2faSAndrzej Hajda [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 8743ff6e0d8SYadwinder Singh Brar DPLL_CON0, NULL), 875cba9d2faSAndrzej Hajda [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 8763ff6e0d8SYadwinder Singh Brar EPLL_CON0, NULL), 877cba9d2faSAndrzej Hajda [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 8783ff6e0d8SYadwinder Singh Brar RPLL_CON0, NULL), 879cba9d2faSAndrzej Hajda [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 8803ff6e0d8SYadwinder Singh Brar IPLL_CON0, NULL), 881cba9d2faSAndrzej Hajda [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 8823ff6e0d8SYadwinder Singh Brar SPLL_CON0, NULL), 883cba9d2faSAndrzej Hajda [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 8843ff6e0d8SYadwinder Singh Brar VPLL_CON0, NULL), 885cba9d2faSAndrzej Hajda [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 8863ff6e0d8SYadwinder Singh Brar MPLL_CON0, NULL), 887cba9d2faSAndrzej Hajda [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 8883ff6e0d8SYadwinder Singh Brar BPLL_CON0, NULL), 889cba9d2faSAndrzej Hajda [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 8903ff6e0d8SYadwinder Singh Brar KPLL_CON0, NULL), 891c898c6b7SYadwinder Singh Brar }; 892c898c6b7SYadwinder Singh Brar 893202e5ae9SSachin Kamat static struct of_device_id ext_clk_match[] __initdata = { 8941609027fSChander Kashyap { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 8951609027fSChander Kashyap { }, 8961609027fSChander Kashyap }; 8971609027fSChander Kashyap 8981609027fSChander Kashyap /* register exynos5420 clocks */ 899c7306229SSachin Kamat static void __init exynos5420_clk_init(struct device_node *np) 9001609027fSChander Kashyap { 901976face4SRahul Sharma struct samsung_clk_provider *ctx; 902976face4SRahul Sharma 9031609027fSChander Kashyap if (np) { 9041609027fSChander Kashyap reg_base = of_iomap(np, 0); 9051609027fSChander Kashyap if (!reg_base) 9061609027fSChander Kashyap panic("%s: failed to map registers\n", __func__); 9071609027fSChander Kashyap } else { 9081609027fSChander Kashyap panic("%s: unable to determine soc\n", __func__); 9091609027fSChander Kashyap } 9101609027fSChander Kashyap 911976face4SRahul Sharma ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 912976face4SRahul Sharma if (!ctx) 913976face4SRahul Sharma panic("%s: unable to allocate context.\n", __func__); 914976face4SRahul Sharma 915976face4SRahul Sharma samsung_clk_of_register_fixed_ext(ctx, exynos5420_fixed_rate_ext_clks, 9161609027fSChander Kashyap ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), 9171609027fSChander Kashyap ext_clk_match); 918976face4SRahul Sharma samsung_clk_register_pll(ctx, exynos5420_plls, 919976face4SRahul Sharma ARRAY_SIZE(exynos5420_plls), 920c898c6b7SYadwinder Singh Brar reg_base); 921976face4SRahul Sharma samsung_clk_register_fixed_rate(ctx, exynos5420_fixed_rate_clks, 9221609027fSChander Kashyap ARRAY_SIZE(exynos5420_fixed_rate_clks)); 923976face4SRahul Sharma samsung_clk_register_fixed_factor(ctx, exynos5420_fixed_factor_clks, 9241609027fSChander Kashyap ARRAY_SIZE(exynos5420_fixed_factor_clks)); 925976face4SRahul Sharma samsung_clk_register_mux(ctx, exynos5420_mux_clks, 9261609027fSChander Kashyap ARRAY_SIZE(exynos5420_mux_clks)); 927976face4SRahul Sharma samsung_clk_register_div(ctx, exynos5420_div_clks, 9281609027fSChander Kashyap ARRAY_SIZE(exynos5420_div_clks)); 929976face4SRahul Sharma samsung_clk_register_gate(ctx, exynos5420_gate_clks, 9301609027fSChander Kashyap ARRAY_SIZE(exynos5420_gate_clks)); 931388c7885STomasz Figa 932388c7885STomasz Figa exynos5420_clk_sleep_init(); 9331609027fSChander Kashyap } 9341609027fSChander Kashyap CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 935