1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Author: Tarek Dakhran <t.dakhran@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Common Clock Framework support for Exynos5410 SoC. 10 */ 11 12 #include <dt-bindings/clock/exynos5410.h> 13 14 #include <linux/clk-provider.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 18 #include "clk.h" 19 20 #define APLL_LOCK 0x0 21 #define APLL_CON0 0x100 22 #define CPLL_LOCK 0x10020 23 #define CPLL_CON0 0x10120 24 #define MPLL_LOCK 0x4000 25 #define MPLL_CON0 0x4100 26 #define BPLL_LOCK 0x20010 27 #define BPLL_CON0 0x20110 28 #define KPLL_LOCK 0x28000 29 #define KPLL_CON0 0x28100 30 31 #define SRC_CPU 0x200 32 #define DIV_CPU0 0x500 33 #define SRC_CPERI1 0x4204 34 #define DIV_TOP0 0x10510 35 #define DIV_TOP1 0x10514 36 #define DIV_FSYS0 0x10548 37 #define DIV_FSYS1 0x1054c 38 #define DIV_FSYS2 0x10550 39 #define DIV_PERIC0 0x10558 40 #define DIV_PERIC3 0x10564 41 #define SRC_TOP0 0x10210 42 #define SRC_TOP1 0x10214 43 #define SRC_TOP2 0x10218 44 #define SRC_FSYS 0x10244 45 #define SRC_PERIC0 0x10250 46 #define SRC_MASK_FSYS 0x10340 47 #define SRC_MASK_PERIC0 0x10350 48 #define GATE_BUS_FSYS0 0x10740 49 #define GATE_TOP_SCLK_FSYS 0x10840 50 #define GATE_TOP_SCLK_PERIC 0x10850 51 #define GATE_IP_FSYS 0x10944 52 #define GATE_IP_PERIC 0x10950 53 #define GATE_IP_PERIS 0x10960 54 #define SRC_CDREX 0x20200 55 #define SRC_KFC 0x28200 56 #define DIV_KFC0 0x28500 57 58 /* list of PLLs */ 59 enum exynos5410_plls { 60 apll, cpll, mpll, 61 bpll, kpll, 62 nr_plls /* number of PLLs */ 63 }; 64 65 /* list of all parent clocks */ 66 PNAME(apll_p) = { "fin_pll", "fout_apll", }; 67 PNAME(bpll_p) = { "fin_pll", "fout_bpll", }; 68 PNAME(cpll_p) = { "fin_pll", "fout_cpll" }; 69 PNAME(mpll_p) = { "fin_pll", "fout_mpll", }; 70 PNAME(kpll_p) = { "fin_pll", "fout_kpll", }; 71 72 PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", }; 73 PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", }; 74 75 PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", }; 76 PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", }; 77 PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", }; 78 PNAME(sclk_mpll_bpll_p) = { "sclk_mpll_bpll", "fin_pll", }; 79 80 PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none", 81 "none", "none", "sclk_mpll_bpll", 82 "none", "none", "sclk_cpll" }; 83 84 static const struct samsung_mux_clock exynos5410_mux_clks[] __initconst = { 85 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1), 86 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 87 88 MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1), 89 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 90 91 MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1), 92 MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1), 93 94 MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), 95 MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1), 96 97 MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1), 98 99 MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1), 100 101 MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4), 102 MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4), 103 MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4), 104 MUX(0, "mout_usbd300", sclk_mpll_bpll_p, SRC_FSYS, 28, 1), 105 MUX(0, "mout_usbd301", sclk_mpll_bpll_p, SRC_FSYS, 29, 1), 106 107 MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4), 108 MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4), 109 MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4), 110 MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 12, 4), 111 MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 4), 112 113 MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1), 114 MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1), 115 }; 116 117 static const struct samsung_div_clock exynos5410_div_clks[] __initconst = { 118 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 119 DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3), 120 121 DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3), 122 DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3), 123 DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3), 124 DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3), 125 126 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 127 DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3), 128 DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3), 129 130 DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3), 131 DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3), 132 133 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 134 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 20, 4), 135 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 136 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 28, 4), 137 138 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 139 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 140 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 141 142 DIV_F(0, "div_mmc_pre0", "div_mmc0", 143 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0), 144 DIV_F(0, "div_mmc_pre1", "div_mmc1", 145 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0), 146 DIV_F(0, "div_mmc_pre2", "div_mmc2", 147 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0), 148 149 DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), 150 DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), 151 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), 152 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), 153 154 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4), 155 156 DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3), 157 DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3), 158 }; 159 160 static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { 161 GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0), 162 GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0), 163 GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0), 164 165 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", 166 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 167 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", 168 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 169 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", 170 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 171 172 GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0), 173 GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0), 174 GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0), 175 176 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 177 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 178 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 179 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 180 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 181 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 182 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 183 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 184 185 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 186 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 187 188 GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0), 189 GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0), 190 GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0), 191 GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0), 192 GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0), 193 GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0), 194 GATE(CLK_I2C2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0), 195 GATE(CLK_I2C3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0), 196 GATE(CLK_USI0, "usi0", "aclk66", GATE_IP_PERIC, 10, 0, 0), 197 GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0), 198 GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0), 199 GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0), 200 GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), 201 202 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", 203 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0), 204 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", 205 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 206 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", 207 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 208 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3", 209 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0), 210 211 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 212 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 213 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 214 }; 215 216 static const struct samsung_pll_clock exynos5410_plls[nr_plls] __initconst = { 217 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 218 APLL_CON0, NULL), 219 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 220 CPLL_CON0, NULL), 221 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 222 MPLL_CON0, NULL), 223 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 224 BPLL_CON0, NULL), 225 [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 226 KPLL_CON0, NULL), 227 }; 228 229 /* register exynos5410 clocks */ 230 static void __init exynos5410_clk_init(struct device_node *np) 231 { 232 struct samsung_clk_provider *ctx; 233 void __iomem *reg_base; 234 235 reg_base = of_iomap(np, 0); 236 if (!reg_base) 237 panic("%s: failed to map registers\n", __func__); 238 239 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 240 241 samsung_clk_register_pll(ctx, exynos5410_plls, 242 ARRAY_SIZE(exynos5410_plls), reg_base); 243 244 samsung_clk_register_mux(ctx, exynos5410_mux_clks, 245 ARRAY_SIZE(exynos5410_mux_clks)); 246 samsung_clk_register_div(ctx, exynos5410_div_clks, 247 ARRAY_SIZE(exynos5410_div_clks)); 248 samsung_clk_register_gate(ctx, exynos5410_gate_clks, 249 ARRAY_SIZE(exynos5410_gate_clks)); 250 251 samsung_clk_of_add_provider(np, ctx); 252 253 pr_debug("Exynos5410: clock setup completed.\n"); 254 } 255 CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init); 256