1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2013 Linaro Ltd. 4 * Author: Thomas Abraham <thomas.ab@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for Exynos5250 SoC. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clkdev.h> 15 #include <linux/clk-provider.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 19 #include "clk.h" 20 21 #define APLL_LOCK 0x0 22 #define APLL_CON0 0x100 23 #define SRC_CPU 0x200 24 #define DIV_CPU0 0x500 25 #define MPLL_LOCK 0x4000 26 #define MPLL_CON0 0x4100 27 #define SRC_CORE1 0x4204 28 #define CPLL_LOCK 0x10020 29 #define EPLL_LOCK 0x10030 30 #define VPLL_LOCK 0x10040 31 #define GPLL_LOCK 0x10050 32 #define CPLL_CON0 0x10120 33 #define EPLL_CON0 0x10130 34 #define VPLL_CON0 0x10140 35 #define GPLL_CON0 0x10150 36 #define SRC_TOP0 0x10210 37 #define SRC_TOP2 0x10218 38 #define SRC_GSCL 0x10220 39 #define SRC_DISP1_0 0x1022c 40 #define SRC_MAU 0x10240 41 #define SRC_FSYS 0x10244 42 #define SRC_GEN 0x10248 43 #define SRC_PERIC0 0x10250 44 #define SRC_PERIC1 0x10254 45 #define SRC_MASK_GSCL 0x10320 46 #define SRC_MASK_DISP1_0 0x1032c 47 #define SRC_MASK_MAU 0x10334 48 #define SRC_MASK_FSYS 0x10340 49 #define SRC_MASK_GEN 0x10344 50 #define SRC_MASK_PERIC0 0x10350 51 #define SRC_MASK_PERIC1 0x10354 52 #define DIV_TOP0 0x10510 53 #define DIV_TOP1 0x10514 54 #define DIV_GSCL 0x10520 55 #define DIV_DISP1_0 0x1052c 56 #define DIV_GEN 0x1053c 57 #define DIV_MAU 0x10544 58 #define DIV_FSYS0 0x10548 59 #define DIV_FSYS1 0x1054c 60 #define DIV_FSYS2 0x10550 61 #define DIV_PERIC0 0x10558 62 #define DIV_PERIC1 0x1055c 63 #define DIV_PERIC2 0x10560 64 #define DIV_PERIC3 0x10564 65 #define DIV_PERIC4 0x10568 66 #define DIV_PERIC5 0x1056c 67 #define GATE_IP_GSCL 0x10920 68 #define GATE_IP_MFC 0x1092c 69 #define GATE_IP_GEN 0x10934 70 #define GATE_IP_FSYS 0x10944 71 #define GATE_IP_PERIC 0x10950 72 #define GATE_IP_PERIS 0x10960 73 #define BPLL_LOCK 0x20010 74 #define BPLL_CON0 0x20110 75 #define SRC_CDREX 0x20200 76 #define PLL_DIV2_SEL 0x20a24 77 #define GATE_IP_DISP1 0x10928 78 #define GATE_IP_ACP 0x10000 79 80 /* list of PLLs to be registered */ 81 enum exynos5250_plls { 82 apll, mpll, cpll, epll, vpll, gpll, bpll, 83 nr_plls /* number of PLLs */ 84 }; 85 86 /* 87 * Let each supported clock get a unique id. This id is used to lookup the clock 88 * for device tree based platforms. The clocks are categorized into three 89 * sections: core, sclk gate and bus interface gate clocks. 90 * 91 * When adding a new clock to this list, it is advised to choose a clock 92 * category and add it to the end of that category. That is because the the 93 * device tree source file is referring to these ids and any change in the 94 * sequence number of existing clocks will require corresponding change in the 95 * device tree files. This limitation would go away when pre-processor support 96 * for dtc would be available. 97 */ 98 enum exynos5250_clks { 99 none, 100 101 /* core clocks */ 102 fin_pll, fout_apll, fout_mpll, fout_bpll, fout_gpll, fout_cpll, 103 fout_epll, fout_vpll, 104 105 /* gate for special clocks (sclk) */ 106 sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb, 107 sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0, 108 sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3, 109 sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm, 110 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, 111 div_i2s1, div_i2s2, sclk_hdmiphy, 112 113 /* gate clocks */ 114 gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0, 115 smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator, 116 jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata, 117 usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3, 118 sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0, 119 i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1, 120 spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2, 121 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1, 122 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct, 123 wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, 124 125 /* mux clocks */ 126 mout_hdmi = 1024, 127 128 nr_clks, 129 }; 130 131 /* 132 * list of controller registers to be saved and restored during a 133 * suspend/resume cycle. 134 */ 135 static unsigned long exynos5250_clk_regs[] __initdata = { 136 SRC_CPU, 137 DIV_CPU0, 138 SRC_CORE1, 139 SRC_TOP0, 140 SRC_TOP2, 141 SRC_GSCL, 142 SRC_DISP1_0, 143 SRC_MAU, 144 SRC_FSYS, 145 SRC_GEN, 146 SRC_PERIC0, 147 SRC_PERIC1, 148 SRC_MASK_GSCL, 149 SRC_MASK_DISP1_0, 150 SRC_MASK_MAU, 151 SRC_MASK_FSYS, 152 SRC_MASK_GEN, 153 SRC_MASK_PERIC0, 154 SRC_MASK_PERIC1, 155 DIV_TOP0, 156 DIV_TOP1, 157 DIV_GSCL, 158 DIV_DISP1_0, 159 DIV_GEN, 160 DIV_MAU, 161 DIV_FSYS0, 162 DIV_FSYS1, 163 DIV_FSYS2, 164 DIV_PERIC0, 165 DIV_PERIC1, 166 DIV_PERIC2, 167 DIV_PERIC3, 168 DIV_PERIC4, 169 DIV_PERIC5, 170 GATE_IP_GSCL, 171 GATE_IP_MFC, 172 GATE_IP_GEN, 173 GATE_IP_FSYS, 174 GATE_IP_PERIC, 175 GATE_IP_PERIS, 176 SRC_CDREX, 177 PLL_DIV2_SEL, 178 GATE_IP_DISP1, 179 GATE_IP_ACP, 180 }; 181 182 /* list of all parent clock list */ 183 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 184 PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", }; 185 PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" }; 186 PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" }; 187 PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" }; 188 PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" }; 189 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" }; 190 PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" }; 191 PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" }; 192 PNAME(mout_epll_p) = { "fin_pll", "fout_epll" }; 193 PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" }; 194 PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" }; 195 PNAME(mout_aclk166_p) = { "sclk_cpll", "sclk_mpll_user" }; 196 PNAME(mout_aclk200_p) = { "sclk_mpll_user", "sclk_bpll_user" }; 197 PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; 198 PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" }; 199 PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", 200 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", 201 "sclk_mpll_user", "sclk_epll", "sclk_vpll", 202 "sclk_cpll" }; 203 PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 204 "sclk_uhostphy", "sclk_hdmiphy", 205 "sclk_mpll_user", "sclk_epll", "sclk_vpll", 206 "sclk_cpll" }; 207 PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 208 "sclk_uhostphy", "sclk_hdmiphy", 209 "sclk_mpll_user", "sclk_epll", "sclk_vpll", 210 "sclk_cpll" }; 211 PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 212 "sclk_uhostphy", "sclk_hdmiphy", 213 "sclk_mpll_user", "sclk_epll", "sclk_vpll", 214 "sclk_cpll" }; 215 PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", 216 "spdif_extclk" }; 217 218 /* fixed rate clocks generated outside the soc */ 219 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = { 220 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), 221 }; 222 223 /* fixed rate clocks generated inside the soc */ 224 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { 225 FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 226 FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), 227 FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000), 228 FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000), 229 }; 230 231 static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { 232 FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0), 233 FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0), 234 }; 235 236 static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { 237 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), 238 }; 239 240 static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 241 MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"), 242 MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), 243 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), 244 MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), 245 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), 246 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 247 MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1), 248 MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1), 249 MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1), 250 MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), 251 MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), 252 MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), 253 MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), 254 MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), 255 MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), 256 MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), 257 MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), 258 MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4), 259 MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4), 260 MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4), 261 MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4), 262 MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4), 263 MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), 264 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4), 265 MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4), 266 MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4), 267 MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4), 268 MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4), 269 MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1), 270 MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1), 271 MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4), 272 MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4), 273 MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4), 274 MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4), 275 MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4), 276 MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4), 277 MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4), 278 MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4), 279 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2), 280 MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4), 281 MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4), 282 MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4), 283 }; 284 285 static struct samsung_div_clock exynos5250_div_clks[] __initdata = { 286 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 287 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 288 DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3), 289 DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3), 290 DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3), 291 DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3), 292 DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3), 293 DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3), 294 DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4), 295 DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4), 296 DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4), 297 DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4), 298 DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4), 299 DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4), 300 DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4), 301 DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4), 302 DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4), 303 DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4), 304 DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), 305 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 306 DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), 307 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 308 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 309 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 310 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 311 DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), 312 DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), 313 DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), 314 DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), 315 DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4), 316 DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4), 317 DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4), 318 DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4), 319 DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4), 320 DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8), 321 DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4), 322 DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8), 323 DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6), 324 DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6), 325 DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4), 326 DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"), 327 DIV_F(none, "div_mipi1_pre", "div_mipi1", 328 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0), 329 DIV_F(none, "div_mmc_pre0", "div_mmc0", 330 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0), 331 DIV_F(none, "div_mmc_pre1", "div_mmc1", 332 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0), 333 DIV_F(none, "div_mmc_pre2", "div_mmc2", 334 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0), 335 DIV_F(none, "div_mmc_pre3", "div_mmc3", 336 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0), 337 DIV_F(none, "div_spi_pre0", "div_spi0", 338 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0), 339 DIV_F(none, "div_spi_pre1", "div_spi1", 340 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0), 341 DIV_F(none, "div_spi_pre2", "div_spi2", 342 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0), 343 }; 344 345 static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 346 GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0), 347 GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0), 348 GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0), 349 GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0), 350 GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), 351 GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), 352 GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0), 353 GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0), 354 GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0), 355 GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0), 356 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 357 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 358 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 359 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 360 GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0), 361 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), 362 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), 363 GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0), 364 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0), 365 GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0), 366 GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0), 367 GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0), 368 GATE(usbotg, "usbotg", "aclk200", GATE_IP_FSYS, 7, 0, 0), 369 GATE(mipi_hsi, "mipi_hsi", "aclk200", GATE_IP_FSYS, 8, 0, 0), 370 GATE(sdmmc0, "sdmmc0", "aclk200", GATE_IP_FSYS, 12, 0, 0), 371 GATE(sdmmc1, "sdmmc1", "aclk200", GATE_IP_FSYS, 13, 0, 0), 372 GATE(sdmmc2, "sdmmc2", "aclk200", GATE_IP_FSYS, 14, 0, 0), 373 GATE(sdmmc3, "sdmmc3", "aclk200", GATE_IP_FSYS, 15, 0, 0), 374 GATE(sromc, "sromc", "aclk200", GATE_IP_FSYS, 17, 0, 0), 375 GATE(usb2, "usb2", "aclk200", GATE_IP_FSYS, 18, 0, 0), 376 GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0), 377 GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0), 378 GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0), 379 GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0), 380 GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0), 381 GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0), 382 GATE(uart3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0), 383 GATE(uart4, "uart4", "aclk66", GATE_IP_PERIC, 4, 0, 0), 384 GATE(i2c0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0), 385 GATE(i2c1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0), 386 GATE(i2c2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0), 387 GATE(i2c3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0), 388 GATE(i2c4, "i2c4", "aclk66", GATE_IP_PERIC, 10, 0, 0), 389 GATE(i2c5, "i2c5", "aclk66", GATE_IP_PERIC, 11, 0, 0), 390 GATE(i2c6, "i2c6", "aclk66", GATE_IP_PERIC, 12, 0, 0), 391 GATE(i2c7, "i2c7", "aclk66", GATE_IP_PERIC, 13, 0, 0), 392 GATE(i2c_hdmi, "i2c_hdmi", "aclk66", GATE_IP_PERIC, 14, 0, 0), 393 GATE(adc, "adc", "aclk66", GATE_IP_PERIC, 15, 0, 0), 394 GATE(spi0, "spi0", "aclk66", GATE_IP_PERIC, 16, 0, 0), 395 GATE(spi1, "spi1", "aclk66", GATE_IP_PERIC, 17, 0, 0), 396 GATE(spi2, "spi2", "aclk66", GATE_IP_PERIC, 18, 0, 0), 397 GATE(i2s1, "i2s1", "aclk66", GATE_IP_PERIC, 20, 0, 0), 398 GATE(i2s2, "i2s2", "aclk66", GATE_IP_PERIC, 21, 0, 0), 399 GATE(pcm1, "pcm1", "aclk66", GATE_IP_PERIC, 22, 0, 0), 400 GATE(pcm2, "pcm2", "aclk66", GATE_IP_PERIC, 23, 0, 0), 401 GATE(pwm, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), 402 GATE(spdif, "spdif", "aclk66", GATE_IP_PERIC, 26, 0, 0), 403 GATE(ac97, "ac97", "aclk66", GATE_IP_PERIC, 27, 0, 0), 404 GATE(hsi2c0, "hsi2c0", "aclk66", GATE_IP_PERIC, 28, 0, 0), 405 GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0), 406 GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0), 407 GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0), 408 GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0), 409 GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0), 410 GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0), 411 GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0), 412 GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0), 413 GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0), 414 GATE(tzpc3, "tzpc3", "aclk66", GATE_IP_PERIS, 9, 0, 0), 415 GATE(tzpc4, "tzpc4", "aclk66", GATE_IP_PERIS, 10, 0, 0), 416 GATE(tzpc5, "tzpc5", "aclk66", GATE_IP_PERIS, 11, 0, 0), 417 GATE(tzpc6, "tzpc6", "aclk66", GATE_IP_PERIS, 12, 0, 0), 418 GATE(tzpc7, "tzpc7", "aclk66", GATE_IP_PERIS, 13, 0, 0), 419 GATE(tzpc8, "tzpc8", "aclk66", GATE_IP_PERIS, 14, 0, 0), 420 GATE(tzpc9, "tzpc9", "aclk66", GATE_IP_PERIS, 15, 0, 0), 421 GATE(hdmi_cec, "hdmi_cec", "aclk66", GATE_IP_PERIS, 16, 0, 0), 422 GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0), 423 GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0), 424 GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0), 425 GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0), 426 GATE(cmu_top, "cmu_top", "aclk66", 427 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0), 428 GATE(cmu_core, "cmu_core", "aclk66", 429 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0), 430 GATE(cmu_mem, "cmu_mem", "aclk66", 431 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0), 432 GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer", 433 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0), 434 GATE(sclk_cam0, "sclk_cam0", "div_cam0", 435 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0), 436 GATE(sclk_cam1, "sclk_cam1", "div_cam1", 437 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0), 438 GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa", 439 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0), 440 GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb", 441 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0), 442 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1", 443 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0), 444 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1", 445 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0), 446 GATE(sclk_dp, "sclk_dp", "div_dp", 447 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0), 448 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", 449 SRC_MASK_DISP1_0, 20, 0, 0), 450 GATE(sclk_audio0, "sclk_audio0", "div_audio0", 451 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0), 452 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0", 453 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 454 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1", 455 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 456 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2", 457 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 458 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3", 459 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0), 460 GATE(sclk_sata, "sclk_sata", "div_sata", 461 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 462 GATE(sclk_usb3, "sclk_usb3", "div_usb3", 463 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0), 464 GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg", 465 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0), 466 GATE(sclk_uart0, "sclk_uart0", "div_uart0", 467 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0), 468 GATE(sclk_uart1, "sclk_uart1", "div_uart1", 469 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 470 GATE(sclk_uart2, "sclk_uart2", "div_uart2", 471 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 472 GATE(sclk_uart3, "sclk_uart3", "div_uart3", 473 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0), 474 GATE(sclk_pwm, "sclk_pwm", "div_pwm", 475 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0), 476 GATE(sclk_audio1, "sclk_audio1", "div_audio1", 477 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 478 GATE(sclk_audio2, "sclk_audio2", "div_audio2", 479 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 480 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 481 SRC_MASK_PERIC1, 4, 0, 0), 482 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0", 483 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0), 484 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1", 485 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 486 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", 487 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0), 488 GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0), 489 GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0), 490 GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0), 491 GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0), 492 GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 493 GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 494 GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), 495 }; 496 497 static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { 498 /* sorted in descending order */ 499 /* PLL_36XX_RATE(rate, m, p, s, k) */ 500 PLL_36XX_RATE(266000000, 266, 3, 3, 0), 501 /* Not in UM, but need for eDP on snow */ 502 PLL_36XX_RATE(70500000, 94, 2, 4, 0), 503 { }, 504 }; 505 506 static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { 507 /* sorted in descending order */ 508 /* PLL_36XX_RATE(rate, m, p, s, k) */ 509 PLL_36XX_RATE(192000000, 64, 2, 2, 0), 510 PLL_36XX_RATE(180633600, 90, 3, 2, 20762), 511 PLL_36XX_RATE(180000000, 90, 3, 2, 0), 512 PLL_36XX_RATE(73728000, 98, 2, 4, 19923), 513 PLL_36XX_RATE(67737600, 90, 2, 4, 20762), 514 PLL_36XX_RATE(49152000, 98, 3, 4, 19923), 515 PLL_36XX_RATE(45158400, 90, 3, 4, 20762), 516 PLL_36XX_RATE(32768000, 131, 3, 5, 4719), 517 { }, 518 }; 519 520 static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { 521 [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, 522 APLL_CON0, "fout_apll", NULL), 523 [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, 524 MPLL_CON0, "fout_mpll", NULL), 525 [bpll] = PLL(pll_35xx, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK, 526 BPLL_CON0, NULL), 527 [gpll] = PLL(pll_35xx, fout_gpll, "fout_gpll", "fin_pll", GPLL_LOCK, 528 GPLL_CON0, NULL), 529 [cpll] = PLL(pll_35xx, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK, 530 CPLL_CON0, NULL), 531 [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, 532 EPLL_CON0, NULL), 533 [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "mout_vpllsrc", 534 VPLL_LOCK, VPLL_CON0, NULL), 535 }; 536 537 static struct of_device_id ext_clk_match[] __initdata = { 538 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 539 { }, 540 }; 541 542 /* register exynox5250 clocks */ 543 static void __init exynos5250_clk_init(struct device_node *np) 544 { 545 void __iomem *reg_base; 546 547 if (np) { 548 reg_base = of_iomap(np, 0); 549 if (!reg_base) 550 panic("%s: failed to map registers\n", __func__); 551 } else { 552 panic("%s: unable to determine soc\n", __func__); 553 } 554 555 samsung_clk_init(np, reg_base, nr_clks, 556 exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs), 557 NULL, 0); 558 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks, 559 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), 560 ext_clk_match); 561 samsung_clk_register_mux(exynos5250_pll_pmux_clks, 562 ARRAY_SIZE(exynos5250_pll_pmux_clks)); 563 564 if (_get_rate("fin_pll") == 24 * MHZ) 565 exynos5250_plls[epll].rate_table = epll_24mhz_tbl; 566 567 if (_get_rate("mout_vpllsrc") == 24 * MHZ) 568 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; 569 570 samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls), 571 reg_base); 572 samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks, 573 ARRAY_SIZE(exynos5250_fixed_rate_clks)); 574 samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks, 575 ARRAY_SIZE(exynos5250_fixed_factor_clks)); 576 samsung_clk_register_mux(exynos5250_mux_clks, 577 ARRAY_SIZE(exynos5250_mux_clks)); 578 samsung_clk_register_div(exynos5250_div_clks, 579 ARRAY_SIZE(exynos5250_div_clks)); 580 samsung_clk_register_gate(exynos5250_gate_clks, 581 ARRAY_SIZE(exynos5250_gate_clks)); 582 583 pr_info("Exynos5250: clock setup completed, armclk=%ld\n", 584 _get_rate("armclk")); 585 } 586 CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); 587