1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2013 Linaro Ltd. 4 * Author: Thomas Abraham <thomas.ab@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for Exynos5250 SoC. 11 */ 12 13 #include <dt-bindings/clock/exynos5250.h> 14 #include <linux/clk.h> 15 #include <linux/clkdev.h> 16 #include <linux/clk-provider.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 20 #include "clk.h" 21 22 #define APLL_LOCK 0x0 23 #define APLL_CON0 0x100 24 #define SRC_CPU 0x200 25 #define DIV_CPU0 0x500 26 #define MPLL_LOCK 0x4000 27 #define MPLL_CON0 0x4100 28 #define SRC_CORE1 0x4204 29 #define GATE_IP_ACP 0x8800 30 #define CPLL_LOCK 0x10020 31 #define EPLL_LOCK 0x10030 32 #define VPLL_LOCK 0x10040 33 #define GPLL_LOCK 0x10050 34 #define CPLL_CON0 0x10120 35 #define EPLL_CON0 0x10130 36 #define VPLL_CON0 0x10140 37 #define GPLL_CON0 0x10150 38 #define SRC_TOP0 0x10210 39 #define SRC_TOP2 0x10218 40 #define SRC_TOP3 0x1021c 41 #define SRC_GSCL 0x10220 42 #define SRC_DISP1_0 0x1022c 43 #define SRC_MAU 0x10240 44 #define SRC_FSYS 0x10244 45 #define SRC_GEN 0x10248 46 #define SRC_PERIC0 0x10250 47 #define SRC_PERIC1 0x10254 48 #define SRC_MASK_GSCL 0x10320 49 #define SRC_MASK_DISP1_0 0x1032c 50 #define SRC_MASK_MAU 0x10334 51 #define SRC_MASK_FSYS 0x10340 52 #define SRC_MASK_GEN 0x10344 53 #define SRC_MASK_PERIC0 0x10350 54 #define SRC_MASK_PERIC1 0x10354 55 #define DIV_TOP0 0x10510 56 #define DIV_TOP1 0x10514 57 #define DIV_GSCL 0x10520 58 #define DIV_DISP1_0 0x1052c 59 #define DIV_GEN 0x1053c 60 #define DIV_MAU 0x10544 61 #define DIV_FSYS0 0x10548 62 #define DIV_FSYS1 0x1054c 63 #define DIV_FSYS2 0x10550 64 #define DIV_PERIC0 0x10558 65 #define DIV_PERIC1 0x1055c 66 #define DIV_PERIC2 0x10560 67 #define DIV_PERIC3 0x10564 68 #define DIV_PERIC4 0x10568 69 #define DIV_PERIC5 0x1056c 70 #define GATE_IP_GSCL 0x10920 71 #define GATE_IP_DISP1 0x10928 72 #define GATE_IP_MFC 0x1092c 73 #define GATE_IP_GEN 0x10934 74 #define GATE_IP_FSYS 0x10944 75 #define GATE_IP_PERIC 0x10950 76 #define GATE_IP_PERIS 0x10960 77 #define BPLL_LOCK 0x20010 78 #define BPLL_CON0 0x20110 79 #define SRC_CDREX 0x20200 80 #define PLL_DIV2_SEL 0x20a24 81 82 /* list of PLLs to be registered */ 83 enum exynos5250_plls { 84 apll, mpll, cpll, epll, vpll, gpll, bpll, 85 nr_plls /* number of PLLs */ 86 }; 87 88 /* 89 * list of controller registers to be saved and restored during a 90 * suspend/resume cycle. 91 */ 92 static unsigned long exynos5250_clk_regs[] __initdata = { 93 SRC_CPU, 94 DIV_CPU0, 95 SRC_CORE1, 96 SRC_TOP0, 97 SRC_TOP2, 98 SRC_TOP3, 99 SRC_GSCL, 100 SRC_DISP1_0, 101 SRC_MAU, 102 SRC_FSYS, 103 SRC_GEN, 104 SRC_PERIC0, 105 SRC_PERIC1, 106 SRC_MASK_GSCL, 107 SRC_MASK_DISP1_0, 108 SRC_MASK_MAU, 109 SRC_MASK_FSYS, 110 SRC_MASK_GEN, 111 SRC_MASK_PERIC0, 112 SRC_MASK_PERIC1, 113 DIV_TOP0, 114 DIV_TOP1, 115 DIV_GSCL, 116 DIV_DISP1_0, 117 DIV_GEN, 118 DIV_MAU, 119 DIV_FSYS0, 120 DIV_FSYS1, 121 DIV_FSYS2, 122 DIV_PERIC0, 123 DIV_PERIC1, 124 DIV_PERIC2, 125 DIV_PERIC3, 126 DIV_PERIC4, 127 DIV_PERIC5, 128 GATE_IP_GSCL, 129 GATE_IP_MFC, 130 GATE_IP_GEN, 131 GATE_IP_FSYS, 132 GATE_IP_PERIC, 133 GATE_IP_PERIS, 134 SRC_CDREX, 135 PLL_DIV2_SEL, 136 GATE_IP_DISP1, 137 GATE_IP_ACP, 138 }; 139 140 /* list of all parent clock list */ 141 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 142 PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", }; 143 PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" }; 144 PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" }; 145 PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" }; 146 PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" }; 147 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" }; 148 PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" }; 149 PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" }; 150 PNAME(mout_epll_p) = { "fin_pll", "fout_epll" }; 151 PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" }; 152 PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" }; 153 PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" }; 154 PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" }; 155 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" }; 156 PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; 157 PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" }; 158 PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; 159 PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" }; 160 PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", 161 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", 162 "mout_mpll_user", "mout_epll", "mout_vpll", 163 "mout_cpll", "none", "none", 164 "none", "none", "none", 165 "none" }; 166 PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 167 "sclk_uhostphy", "fin_pll", 168 "mout_mpll_user", "mout_epll", "mout_vpll", 169 "mout_cpll", "none", "none", 170 "none", "none", "none", 171 "none" }; 172 PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 173 "sclk_uhostphy", "fin_pll", 174 "mout_mpll_user", "mout_epll", "mout_vpll", 175 "mout_cpll", "none", "none", 176 "none", "none", "none", 177 "none" }; 178 PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 179 "sclk_uhostphy", "fin_pll", 180 "mout_mpll_user", "mout_epll", "mout_vpll", 181 "mout_cpll", "none", "none", 182 "none", "none", "none", 183 "none" }; 184 PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", 185 "spdif_extclk" }; 186 187 /* fixed rate clocks generated outside the soc */ 188 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = { 189 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 190 }; 191 192 /* fixed rate clocks generated inside the soc */ 193 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { 194 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 195 FRATE(0, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), 196 FRATE(0, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000), 197 FRATE(0, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000), 198 }; 199 200 static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { 201 FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0), 202 FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0), 203 }; 204 205 static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { 206 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), 207 }; 208 209 static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 210 /* 211 * NOTE: Following table is sorted by (clock domain, register address, 212 * bitfield shift) triplet in ascending order. When adding new entries, 213 * please make sure that the order is kept, to avoid merge conflicts 214 * and make further work with defined data easier. 215 */ 216 217 /* 218 * CMU_CPU 219 */ 220 MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 221 CLK_SET_RATE_PARENT, 0, "mout_apll"), 222 MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), 223 224 /* 225 * CMU_CORE 226 */ 227 MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), 228 229 /* 230 * CMU_TOP 231 */ 232 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), 233 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), 234 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), 235 236 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1), 237 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1), 238 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1), 239 MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), 240 MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), 241 242 MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1), 243 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1), 244 MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1), 245 246 MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), 247 MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), 248 MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), 249 MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4), 250 MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4), 251 252 MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4), 253 MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4), 254 MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4), 255 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), 256 257 MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4), 258 259 MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4), 260 MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4), 261 MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4), 262 MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4), 263 MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1), 264 MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1), 265 266 MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4), 267 268 MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4), 269 MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4), 270 MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4), 271 MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4), 272 MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4), 273 274 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4), 275 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4), 276 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2), 277 MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4), 278 MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4), 279 MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4), 280 281 /* 282 * CMU_CDREX 283 */ 284 MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 285 286 MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), 287 MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), 288 }; 289 290 static struct samsung_div_clock exynos5250_div_clks[] __initdata = { 291 /* 292 * NOTE: Following table is sorted by (clock domain, register address, 293 * bitfield shift) triplet in ascending order. When adding new entries, 294 * please make sure that the order is kept, to avoid merge conflicts 295 * and make further work with defined data easier. 296 */ 297 298 /* 299 * CMU_CPU 300 */ 301 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 302 DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3), 303 DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"), 304 305 /* 306 * CMU_TOP 307 */ 308 DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3), 309 DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3), 310 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3), 311 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3), 312 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3), 313 314 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3), 315 316 DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4), 317 DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4), 318 DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4), 319 DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4), 320 DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4), 321 322 DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4), 323 DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4), 324 DIV_F(0, "div_mipi1_pre", "div_mipi1", 325 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0), 326 DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4), 327 DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4), 328 329 DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4), 330 331 DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4), 332 DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), 333 334 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 335 DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), 336 337 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 338 DIV_F(0, "div_mmc_pre0", "div_mmc0", 339 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0), 340 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 341 DIV_F(0, "div_mmc_pre1", "div_mmc1", 342 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0), 343 344 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 345 DIV_F(0, "div_mmc_pre2", "div_mmc2", 346 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0), 347 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 348 DIV_F(0, "div_mmc_pre3", "div_mmc3", 349 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0), 350 351 DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), 352 DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), 353 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), 354 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), 355 356 DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4), 357 DIV_F(0, "div_spi_pre0", "div_spi0", 358 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0), 359 DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4), 360 DIV_F(0, "div_spi_pre1", "div_spi1", 361 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0), 362 363 DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4), 364 DIV_F(0, "div_spi_pre2", "div_spi2", 365 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0), 366 367 DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4), 368 369 DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4), 370 DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8), 371 DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4), 372 DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8), 373 374 DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6), 375 DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6), 376 }; 377 378 static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 379 /* 380 * NOTE: Following table is sorted by (clock domain, register address, 381 * bitfield shift) triplet in ascending order. When adding new entries, 382 * please make sure that the order is kept, to avoid merge conflicts 383 * and make further work with defined data easier. 384 */ 385 386 /* 387 * CMU_ACP 388 */ 389 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0), 390 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0), 391 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0), 392 393 /* 394 * CMU_TOP 395 */ 396 GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer", 397 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0), 398 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", 399 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0), 400 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", 401 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0), 402 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa", 403 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0), 404 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb", 405 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0), 406 407 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", 408 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0), 409 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1", 410 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0), 411 GATE(CLK_SCLK_DP, "sclk_dp", "div_dp", 412 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0), 413 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 414 SRC_MASK_DISP1_0, 20, 0, 0), 415 416 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", 417 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0), 418 419 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", 420 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 421 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", 422 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 423 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", 424 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 425 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", 426 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0), 427 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata", 428 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 429 GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3", 430 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0), 431 432 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg", 433 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0), 434 435 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", 436 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0), 437 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", 438 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 439 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", 440 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 441 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3", 442 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0), 443 GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm", 444 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0), 445 446 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", 447 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 448 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", 449 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 450 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 451 SRC_MASK_PERIC1, 4, 0, 0), 452 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", 453 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0), 454 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", 455 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 456 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", 457 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0), 458 459 GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0, 460 0), 461 GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0, 462 0), 463 GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0, 464 0), 465 GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0, 466 0), 467 GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), 468 GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), 469 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub", 470 GATE_IP_GSCL, 7, 0, 0), 471 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub", 472 GATE_IP_GSCL, 8, 0, 0), 473 GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub", 474 GATE_IP_GSCL, 9, 0, 0), 475 GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub", 476 GATE_IP_GSCL, 10, 0, 0), 477 478 GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, 479 0), 480 GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0, 481 0), 482 GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0, 483 0), 484 GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0), 485 GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, 486 0), 487 GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, 488 0), 489 490 GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0), 491 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0, 492 0), 493 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0, 494 0), 495 496 GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0), 497 GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0), 498 GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0), 499 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0, 500 0), 501 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0), 502 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0), 503 504 GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0), 505 GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0), 506 GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0), 507 GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0), 508 GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0), 509 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0), 510 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0), 511 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0), 512 GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0), 513 GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0), 514 GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0), 515 GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0), 516 GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200", 517 GATE_IP_FSYS, 24, 0, 0), 518 GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0, 519 0), 520 521 GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0), 522 GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0), 523 GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0), 524 GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0), 525 GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0), 526 GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0), 527 GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0), 528 GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0), 529 GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0), 530 GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0), 531 GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0), 532 GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0), 533 GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0), 534 GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0), 535 GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0), 536 GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0), 537 GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0), 538 GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0), 539 GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0), 540 GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0), 541 GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0), 542 GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0), 543 GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0), 544 GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0), 545 GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0), 546 GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0), 547 GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0), 548 GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0), 549 GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0), 550 551 GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0), 552 GATE(CLK_SYSREG, "sysreg", "div_aclk66", 553 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 554 GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 555 0), 556 GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66", 557 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0), 558 GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66", 559 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0), 560 GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66", 561 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0), 562 GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0), 563 GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0), 564 GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0), 565 GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0), 566 GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0), 567 GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0), 568 GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0), 569 GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0), 570 GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0), 571 GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0), 572 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0), 573 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0), 574 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0), 575 GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0), 576 GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0), 577 }; 578 579 static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { 580 /* sorted in descending order */ 581 /* PLL_36XX_RATE(rate, m, p, s, k) */ 582 PLL_36XX_RATE(266000000, 266, 3, 3, 0), 583 /* Not in UM, but need for eDP on snow */ 584 PLL_36XX_RATE(70500000, 94, 2, 4, 0), 585 { }, 586 }; 587 588 static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { 589 /* sorted in descending order */ 590 /* PLL_36XX_RATE(rate, m, p, s, k) */ 591 PLL_36XX_RATE(192000000, 64, 2, 2, 0), 592 PLL_36XX_RATE(180633600, 90, 3, 2, 20762), 593 PLL_36XX_RATE(180000000, 90, 3, 2, 0), 594 PLL_36XX_RATE(73728000, 98, 2, 4, 19923), 595 PLL_36XX_RATE(67737600, 90, 2, 4, 20762), 596 PLL_36XX_RATE(49152000, 98, 3, 4, 19923), 597 PLL_36XX_RATE(45158400, 90, 3, 4, 20762), 598 PLL_36XX_RATE(32768000, 131, 3, 5, 4719), 599 { }, 600 }; 601 602 static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = { 603 /* sorted in descending order */ 604 /* PLL_35XX_RATE(rate, m, p, s) */ 605 PLL_35XX_RATE(1700000000, 425, 6, 0), 606 PLL_35XX_RATE(1600000000, 200, 3, 0), 607 PLL_35XX_RATE(1500000000, 250, 4, 0), 608 PLL_35XX_RATE(1400000000, 175, 3, 0), 609 PLL_35XX_RATE(1300000000, 325, 6, 0), 610 PLL_35XX_RATE(1200000000, 200, 4, 0), 611 PLL_35XX_RATE(1100000000, 275, 6, 0), 612 PLL_35XX_RATE(1000000000, 125, 3, 0), 613 PLL_35XX_RATE(900000000, 150, 4, 0), 614 PLL_35XX_RATE(800000000, 100, 3, 0), 615 PLL_35XX_RATE(700000000, 175, 3, 1), 616 PLL_35XX_RATE(600000000, 200, 4, 1), 617 PLL_35XX_RATE(500000000, 125, 3, 1), 618 PLL_35XX_RATE(400000000, 100, 3, 1), 619 PLL_35XX_RATE(300000000, 200, 4, 2), 620 PLL_35XX_RATE(200000000, 100, 3, 2), 621 }; 622 623 static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { 624 [apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 625 APLL_LOCK, APLL_CON0, "fout_apll", NULL), 626 [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 627 MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL), 628 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 629 BPLL_CON0, NULL), 630 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK, 631 GPLL_CON0, NULL), 632 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 633 CPLL_CON0, NULL), 634 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 635 EPLL_CON0, NULL), 636 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc", 637 VPLL_LOCK, VPLL_CON0, NULL), 638 }; 639 640 static struct of_device_id ext_clk_match[] __initdata = { 641 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 642 { }, 643 }; 644 645 /* register exynox5250 clocks */ 646 static void __init exynos5250_clk_init(struct device_node *np) 647 { 648 void __iomem *reg_base; 649 650 if (np) { 651 reg_base = of_iomap(np, 0); 652 if (!reg_base) 653 panic("%s: failed to map registers\n", __func__); 654 } else { 655 panic("%s: unable to determine soc\n", __func__); 656 } 657 658 samsung_clk_init(np, reg_base, CLK_NR_CLKS, 659 exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs), 660 NULL, 0); 661 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks, 662 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), 663 ext_clk_match); 664 samsung_clk_register_mux(exynos5250_pll_pmux_clks, 665 ARRAY_SIZE(exynos5250_pll_pmux_clks)); 666 667 if (_get_rate("fin_pll") == 24 * MHZ) { 668 exynos5250_plls[epll].rate_table = epll_24mhz_tbl; 669 exynos5250_plls[apll].rate_table = apll_24mhz_tbl; 670 } 671 672 if (_get_rate("mout_vpllsrc") == 24 * MHZ) 673 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; 674 675 samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls), 676 reg_base); 677 samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks, 678 ARRAY_SIZE(exynos5250_fixed_rate_clks)); 679 samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks, 680 ARRAY_SIZE(exynos5250_fixed_factor_clks)); 681 samsung_clk_register_mux(exynos5250_mux_clks, 682 ARRAY_SIZE(exynos5250_mux_clks)); 683 samsung_clk_register_div(exynos5250_div_clks, 684 ARRAY_SIZE(exynos5250_div_clks)); 685 samsung_clk_register_gate(exynos5250_gate_clks, 686 ARRAY_SIZE(exynos5250_gate_clks)); 687 688 pr_info("Exynos5250: clock setup completed, armclk=%ld\n", 689 _get_rate("div_arm2")); 690 } 691 CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); 692