1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4  * Copyright (c) 2013 Linaro Ltd.
5  * Author: Thomas Abraham <thomas.ab@samsung.com>
6  *
7  * Common Clock Framework support for Exynos5250 SoC.
8 */
9 
10 #include <dt-bindings/clock/exynos5250.h>
11 #include <linux/clk-provider.h>
12 #include <linux/io.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 
16 #include "clk.h"
17 #include "clk-cpu.h"
18 #include "clk-exynos5-subcmu.h"
19 
20 #define APLL_LOCK		0x0
21 #define APLL_CON0		0x100
22 #define SRC_CPU			0x200
23 #define DIV_CPU0		0x500
24 #define PWR_CTRL1		0x1020
25 #define PWR_CTRL2		0x1024
26 #define MPLL_LOCK		0x4000
27 #define MPLL_CON0		0x4100
28 #define SRC_CORE1		0x4204
29 #define GATE_IP_ACP		0x8800
30 #define GATE_IP_ISP0		0xc800
31 #define GATE_IP_ISP1		0xc804
32 #define CPLL_LOCK		0x10020
33 #define EPLL_LOCK		0x10030
34 #define VPLL_LOCK		0x10040
35 #define GPLL_LOCK		0x10050
36 #define CPLL_CON0		0x10120
37 #define EPLL_CON0		0x10130
38 #define VPLL_CON0		0x10140
39 #define GPLL_CON0		0x10150
40 #define SRC_TOP0		0x10210
41 #define SRC_TOP1		0x10214
42 #define SRC_TOP2		0x10218
43 #define SRC_TOP3		0x1021c
44 #define SRC_GSCL		0x10220
45 #define SRC_DISP1_0		0x1022c
46 #define SRC_MAU			0x10240
47 #define SRC_FSYS		0x10244
48 #define SRC_GEN			0x10248
49 #define SRC_PERIC0		0x10250
50 #define SRC_PERIC1		0x10254
51 #define SRC_MASK_GSCL		0x10320
52 #define SRC_MASK_DISP1_0	0x1032c
53 #define SRC_MASK_MAU		0x10334
54 #define SRC_MASK_FSYS		0x10340
55 #define SRC_MASK_GEN		0x10344
56 #define SRC_MASK_PERIC0		0x10350
57 #define SRC_MASK_PERIC1		0x10354
58 #define DIV_TOP0		0x10510
59 #define DIV_TOP1		0x10514
60 #define DIV_GSCL		0x10520
61 #define DIV_DISP1_0		0x1052c
62 #define DIV_GEN			0x1053c
63 #define DIV_MAU			0x10544
64 #define DIV_FSYS0		0x10548
65 #define DIV_FSYS1		0x1054c
66 #define DIV_FSYS2		0x10550
67 #define DIV_PERIC0		0x10558
68 #define DIV_PERIC1		0x1055c
69 #define DIV_PERIC2		0x10560
70 #define DIV_PERIC3		0x10564
71 #define DIV_PERIC4		0x10568
72 #define DIV_PERIC5		0x1056c
73 #define GATE_IP_GSCL		0x10920
74 #define GATE_IP_DISP1		0x10928
75 #define GATE_IP_MFC		0x1092c
76 #define GATE_IP_G3D		0x10930
77 #define GATE_IP_GEN		0x10934
78 #define GATE_IP_FSYS		0x10944
79 #define GATE_IP_PERIC		0x10950
80 #define GATE_IP_PERIS		0x10960
81 #define BPLL_LOCK		0x20010
82 #define BPLL_CON0		0x20110
83 #define SRC_CDREX		0x20200
84 #define PLL_DIV2_SEL		0x20a24
85 
86 /*Below definitions are used for PWR_CTRL settings*/
87 #define PWR_CTRL1_CORE2_DOWN_RATIO		(7 << 28)
88 #define PWR_CTRL1_CORE1_DOWN_RATIO		(7 << 16)
89 #define PWR_CTRL1_DIV2_DOWN_EN			(1 << 9)
90 #define PWR_CTRL1_DIV1_DOWN_EN			(1 << 8)
91 #define PWR_CTRL1_USE_CORE1_WFE			(1 << 5)
92 #define PWR_CTRL1_USE_CORE0_WFE			(1 << 4)
93 #define PWR_CTRL1_USE_CORE1_WFI			(1 << 1)
94 #define PWR_CTRL1_USE_CORE0_WFI			(1 << 0)
95 
96 #define PWR_CTRL2_DIV2_UP_EN			(1 << 25)
97 #define PWR_CTRL2_DIV1_UP_EN			(1 << 24)
98 #define PWR_CTRL2_DUR_STANDBY2_VAL		(1 << 16)
99 #define PWR_CTRL2_DUR_STANDBY1_VAL		(1 << 8)
100 #define PWR_CTRL2_CORE2_UP_RATIO		(1 << 4)
101 #define PWR_CTRL2_CORE1_UP_RATIO		(1 << 0)
102 
103 /* list of PLLs to be registered */
104 enum exynos5250_plls {
105 	apll, mpll, cpll, epll, vpll, gpll, bpll,
106 	nr_plls			/* number of PLLs */
107 };
108 
109 static void __iomem *reg_base;
110 
111 /*
112  * list of controller registers to be saved and restored during a
113  * suspend/resume cycle.
114  */
115 static const unsigned long exynos5250_clk_regs[] __initconst = {
116 	SRC_CPU,
117 	DIV_CPU0,
118 	PWR_CTRL1,
119 	PWR_CTRL2,
120 	SRC_CORE1,
121 	SRC_TOP0,
122 	SRC_TOP1,
123 	SRC_TOP2,
124 	SRC_TOP3,
125 	SRC_GSCL,
126 	SRC_DISP1_0,
127 	SRC_MAU,
128 	SRC_FSYS,
129 	SRC_GEN,
130 	SRC_PERIC0,
131 	SRC_PERIC1,
132 	SRC_MASK_GSCL,
133 	SRC_MASK_DISP1_0,
134 	SRC_MASK_MAU,
135 	SRC_MASK_FSYS,
136 	SRC_MASK_GEN,
137 	SRC_MASK_PERIC0,
138 	SRC_MASK_PERIC1,
139 	DIV_TOP0,
140 	DIV_TOP1,
141 	DIV_GSCL,
142 	DIV_DISP1_0,
143 	DIV_GEN,
144 	DIV_MAU,
145 	DIV_FSYS0,
146 	DIV_FSYS1,
147 	DIV_FSYS2,
148 	DIV_PERIC0,
149 	DIV_PERIC1,
150 	DIV_PERIC2,
151 	DIV_PERIC3,
152 	DIV_PERIC4,
153 	DIV_PERIC5,
154 	GATE_IP_GSCL,
155 	GATE_IP_MFC,
156 	GATE_IP_G3D,
157 	GATE_IP_GEN,
158 	GATE_IP_FSYS,
159 	GATE_IP_PERIC,
160 	GATE_IP_PERIS,
161 	SRC_CDREX,
162 	PLL_DIV2_SEL,
163 	GATE_IP_DISP1,
164 	GATE_IP_ACP,
165 	GATE_IP_ISP0,
166 	GATE_IP_ISP1,
167 };
168 
169 /* list of all parent clock list */
170 PNAME(mout_apll_p)	= { "fin_pll", "fout_apll", };
171 PNAME(mout_cpu_p)	= { "mout_apll", "mout_mpll", };
172 PNAME(mout_mpll_fout_p)	= { "fout_mplldiv2", "fout_mpll" };
173 PNAME(mout_mpll_p)	= { "fin_pll", "mout_mpll_fout" };
174 PNAME(mout_bpll_fout_p)	= { "fout_bplldiv2", "fout_bpll" };
175 PNAME(mout_bpll_p)	= { "fin_pll", "mout_bpll_fout" };
176 PNAME(mout_vpllsrc_p)	= { "fin_pll", "sclk_hdmi27m" };
177 PNAME(mout_vpll_p)	= { "mout_vpllsrc", "fout_vpll" };
178 PNAME(mout_cpll_p)	= { "fin_pll", "fout_cpll" };
179 PNAME(mout_epll_p)	= { "fin_pll", "fout_epll" };
180 PNAME(mout_gpll_p)	= { "fin_pll", "fout_gpll" };
181 PNAME(mout_mpll_user_p)	= { "fin_pll", "mout_mpll" };
182 PNAME(mout_bpll_user_p)	= { "fin_pll", "mout_bpll" };
183 PNAME(mout_aclk166_p)	= { "mout_cpll", "mout_mpll_user" };
184 PNAME(mout_aclk200_p)	= { "mout_mpll_user", "mout_bpll_user" };
185 PNAME(mout_aclk300_p)	= { "mout_aclk300_disp1_mid",
186 			    "mout_aclk300_disp1_mid1" };
187 PNAME(mout_aclk400_p)	= { "mout_aclk400_g3d_mid", "mout_gpll" };
188 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
189 PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
190 PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" };
191 PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" };
192 PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
193 PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
194 PNAME(mout_hdmi_p)	= { "div_hdmi_pixel", "sclk_hdmiphy" };
195 PNAME(mout_usb3_p)	= { "mout_mpll_user", "mout_cpll" };
196 PNAME(mout_group1_p)	= { "fin_pll", "fin_pll", "sclk_hdmi27m",
197 				"sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
198 				"mout_mpll_user", "mout_epll", "mout_vpll",
199 				"mout_cpll", "none", "none",
200 				"none", "none", "none",
201 				"none" };
202 PNAME(mout_audio0_p)	= { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
203 				"sclk_uhostphy", "fin_pll",
204 				"mout_mpll_user", "mout_epll", "mout_vpll",
205 				"mout_cpll", "none", "none",
206 				"none", "none", "none",
207 				"none" };
208 PNAME(mout_audio1_p)	= { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
209 				"sclk_uhostphy", "fin_pll",
210 				"mout_mpll_user", "mout_epll", "mout_vpll",
211 				"mout_cpll", "none", "none",
212 				"none", "none", "none",
213 				"none" };
214 PNAME(mout_audio2_p)	= { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
215 				"sclk_uhostphy", "fin_pll",
216 				"mout_mpll_user", "mout_epll", "mout_vpll",
217 				"mout_cpll", "none", "none",
218 				"none", "none", "none",
219 				"none" };
220 PNAME(mout_spdif_p)	= { "sclk_audio0", "sclk_audio1", "sclk_audio2",
221 				"spdif_extclk" };
222 
223 /* fixed rate clocks generated outside the soc */
224 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
225 	FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
226 };
227 
228 /* fixed rate clocks generated inside the soc */
229 static const struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initconst = {
230 	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
231 	FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000),
232 	FRATE(0, "sclk_dptxphy", NULL, 0, 24000000),
233 	FRATE(0, "sclk_uhostphy", NULL, 0, 48000000),
234 };
235 
236 static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initconst = {
237 	FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
238 	FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
239 };
240 
241 static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {
242 	MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
243 };
244 
245 static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
246 	/*
247 	 * NOTE: Following table is sorted by (clock domain, register address,
248 	 * bitfield shift) triplet in ascending order. When adding new entries,
249 	 * please make sure that the order is kept, to avoid merge conflicts
250 	 * and make further work with defined data easier.
251 	 */
252 
253 	/*
254 	 * CMU_CPU
255 	 */
256 	MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
257 					CLK_SET_RATE_PARENT, 0),
258 	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
259 
260 	/*
261 	 * CMU_CORE
262 	 */
263 	MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
264 
265 	/*
266 	 * CMU_TOP
267 	 */
268 	MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
269 	MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
270 	MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
271 	MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
272 	MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
273 	MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
274 
275 	MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
276 		8, 1),
277 	MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
278 	MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
279 
280 	MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
281 	MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
282 	MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
283 	MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
284 	MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
285 	MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
286 
287 	MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub",
288 		mout_aclk200_sub_p, SRC_TOP3, 4, 1),
289 	MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub",
290 		mout_aclk300_sub_p, SRC_TOP3, 6, 1),
291 	MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
292 	MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
293 	MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
294 			SRC_TOP3, 20, 1),
295 	MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
296 
297 	MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
298 	MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
299 	MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
300 	MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
301 	MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
302 
303 	MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
304 	MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
305 	MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
306 	MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
307 
308 	MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
309 
310 	MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
311 	MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
312 	MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
313 	MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
314 	MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
315 	MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
316 
317 	MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
318 
319 	MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
320 	MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
321 	MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
322 	MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
323 	MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
324 
325 	MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
326 	MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
327 	MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
328 	MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
329 	MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
330 	MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
331 
332 	/*
333 	 * CMU_CDREX
334 	 */
335 	MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
336 
337 	MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
338 	MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
339 };
340 
341 static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
342 	/*
343 	 * NOTE: Following table is sorted by (clock domain, register address,
344 	 * bitfield shift) triplet in ascending order. When adding new entries,
345 	 * please make sure that the order is kept, to avoid merge conflicts
346 	 * and make further work with defined data easier.
347 	 */
348 
349 	/*
350 	 * CMU_CPU
351 	 */
352 	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
353 	DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
354 	DIV(CLK_DIV_ARM2, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
355 
356 	/*
357 	 * CMU_TOP
358 	 */
359 	DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
360 	DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
361 	DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
362 	DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
363 	DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
364 	DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
365 							24, 3),
366 	DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3),
367 
368 	DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
369 	DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
370 
371 	DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
372 	DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
373 	DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
374 	DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
375 	DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
376 
377 	DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
378 	DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
379 	DIV_F(0, "div_mipi1_pre", "div_mipi1",
380 			DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
381 	DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
382 	DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
383 
384 	DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
385 
386 	DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
387 	DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
388 
389 	DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
390 	DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
391 
392 	DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
393 	DIV_F(0, "div_mmc_pre0", "div_mmc0",
394 			DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
395 	DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
396 	DIV_F(0, "div_mmc_pre1", "div_mmc1",
397 			DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
398 
399 	DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
400 	DIV_F(0, "div_mmc_pre2", "div_mmc2",
401 			DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
402 	DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
403 	DIV_F(0, "div_mmc_pre3", "div_mmc3",
404 			DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
405 
406 	DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
407 	DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
408 	DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
409 	DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
410 
411 	DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
412 	DIV_F(0, "div_spi_pre0", "div_spi0",
413 			DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
414 	DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
415 	DIV_F(0, "div_spi_pre1", "div_spi1",
416 			DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
417 
418 	DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
419 	DIV_F(0, "div_spi_pre2", "div_spi2",
420 			DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
421 
422 	DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
423 
424 	DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
425 	DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
426 	DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
427 	DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
428 
429 	DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
430 	DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
431 };
432 
433 static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = {
434 	/*
435 	 * NOTE: Following table is sorted by (clock domain, register address,
436 	 * bitfield shift) triplet in ascending order. When adding new entries,
437 	 * please make sure that the order is kept, to avoid merge conflicts
438 	 * and make further work with defined data easier.
439 	 */
440 
441 	/*
442 	 * CMU_ACP
443 	 */
444 	GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
445 	GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
446 	GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
447 	GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
448 
449 	/*
450 	 * CMU_TOP
451 	 */
452 	GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
453 			SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
454 	GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
455 			SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
456 	GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
457 			SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
458 	GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
459 			SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
460 	GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
461 			SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
462 
463 	GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
464 			SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
465 	GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
466 			SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
467 	GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
468 			SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
469 	GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
470 			SRC_MASK_DISP1_0, 20, 0, 0),
471 
472 	GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
473 			SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
474 
475 	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
476 			SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
477 	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
478 			SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
479 	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
480 			SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
481 	GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
482 			SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
483 	GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
484 			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
485 	GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
486 			SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
487 
488 	GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
489 			SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
490 
491 	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
492 			SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
493 	GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
494 			SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
495 	GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
496 			SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
497 	GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
498 			SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
499 	GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
500 			SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
501 
502 	GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
503 			SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
504 	GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
505 			SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
506 	GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
507 			SRC_MASK_PERIC1, 4, 0, 0),
508 	GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
509 			SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
510 	GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
511 			SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
512 	GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
513 			SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
514 
515 	GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
516 		0),
517 	GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
518 		0),
519 	GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
520 		0),
521 	GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
522 		0),
523 	GATE(CLK_CAMIF_TOP, "camif_top", "mout_aclk266_gscl_sub",
524 			GATE_IP_GSCL, 4, 0, 0),
525 	GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
526 	GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
527 	GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
528 			GATE_IP_GSCL, 7, 0, 0),
529 	GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
530 			GATE_IP_GSCL, 8, 0, 0),
531 	GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
532 			GATE_IP_GSCL, 9, 0, 0),
533 	GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
534 			GATE_IP_GSCL, 10, 0, 0),
535 	GATE(CLK_SMMU_FIMC_LITE0, "smmu_fimc_lite0", "mout_aclk266_gscl_sub",
536 			GATE_IP_GSCL, 11, 0, 0),
537 	GATE(CLK_SMMU_FIMC_LITE1, "smmu_fimc_lite1", "mout_aclk266_gscl_sub",
538 			GATE_IP_GSCL, 12, 0, 0),
539 
540 
541 	GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
542 	GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
543 		0),
544 	GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
545 		0),
546 	GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
547 					CLK_SET_RATE_PARENT, 0),
548 	GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
549 	GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
550 	GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
551 	GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
552 		0),
553 	GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
554 	GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
555 
556 	GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
557 	GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
558 	GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
559 	GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
560 	GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
561 	GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
562 	GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
563 	GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
564 	GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
565 	GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
566 	GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
567 	GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
568 	GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
569 			GATE_IP_FSYS, 24, 0, 0),
570 	GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
571 		0),
572 
573 	GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
574 	GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
575 	GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
576 	GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
577 	GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
578 	GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
579 	GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
580 	GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
581 	GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
582 	GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
583 	GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
584 	GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
585 	GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
586 	GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
587 	GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
588 	GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
589 	GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
590 	GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
591 	GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
592 	GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
593 	GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
594 	GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
595 	GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
596 	GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
597 	GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
598 	GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
599 	GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
600 	GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
601 	GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
602 
603 	GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
604 	GATE(CLK_SYSREG, "sysreg", "div_aclk66",
605 			GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
606 	GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
607 		0),
608 	GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
609 			GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
610 	GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
611 			GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
612 	GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
613 			GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
614 	GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
615 	GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
616 	GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
617 	GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
618 	GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
619 	GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
620 	GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
621 	GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
622 	GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
623 	GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
624 	GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
625 	GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
626 	GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
627 	GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
628 	GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
629 	GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
630 	GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
631 			GATE_IP_ISP0, 8, 0, 0),
632 	GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
633 			GATE_IP_ISP0, 9, 0, 0),
634 	GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
635 			GATE_IP_ISP0, 10, 0, 0),
636 	GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",
637 			GATE_IP_ISP0, 11, 0, 0),
638 	GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub",
639 			GATE_IP_ISP0, 12, 0, 0),
640 	GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub",
641 			GATE_IP_ISP0, 13, 0, 0),
642 	GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub",
643 			GATE_IP_ISP1, 4, 0, 0),
644 	GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
645 			GATE_IP_ISP1, 5, 0, 0),
646 	GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
647 			GATE_IP_ISP1, 6, 0, 0),
648 	GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
649 			GATE_IP_ISP1, 7, 0, 0),
650 };
651 
652 static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = {
653 	GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
654 		0),
655 	GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
656 		0),
657 	GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
658 		0),
659 	GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
660 	GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
661 		0),
662 	GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
663 		0),
664 	GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
665 			GATE_IP_DISP1, 9, 0, 0),
666 	GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
667 			GATE_IP_DISP1, 8, 0, 0),
668 };
669 
670 static struct exynos5_subcmu_reg_dump exynos5250_disp_suspend_regs[] = {
671 	{ GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
672 	{ SRC_TOP3, 0, BIT(4) },	/* MUX mout_aclk200_disp1_sub */
673 	{ SRC_TOP3, 0, BIT(6) },	/* MUX mout_aclk300_disp1_sub */
674 };
675 
676 static const struct exynos5_subcmu_info exynos5250_disp_subcmu = {
677 	.gate_clks	= exynos5250_disp_gate_clks,
678 	.nr_gate_clks	= ARRAY_SIZE(exynos5250_disp_gate_clks),
679 	.suspend_regs	= exynos5250_disp_suspend_regs,
680 	.nr_suspend_regs = ARRAY_SIZE(exynos5250_disp_suspend_regs),
681 	.pd_name	= "DISP1",
682 };
683 
684 static const struct exynos5_subcmu_info *exynos5250_subcmus[] = {
685 	&exynos5250_disp_subcmu,
686 };
687 
688 static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
689 	/* sorted in descending order */
690 	/* PLL_36XX_RATE(rate, m, p, s, k) */
691 	PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
692 	/* Not in UM, but need for eDP on snow */
693 	PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
694 	{ },
695 };
696 
697 static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {
698 	/* sorted in descending order */
699 	/* PLL_36XX_RATE(rate, m, p, s, k) */
700 	PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
701 	PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
702 	PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
703 	PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
704 	PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
705 	PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
706 	PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
707 	PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
708 	{ },
709 };
710 
711 static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
712 	/* sorted in descending order */
713 	/* PLL_35XX_RATE(fin, rate, m, p, s) */
714 	PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
715 	PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
716 	PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
717 	PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
718 	PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
719 	PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
720 	PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
721 	PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
722 	PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
723 	PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
724 	PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
725 	PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
726 	PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
727 	PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
728 	PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
729 	PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
730 };
731 
732 static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
733 	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
734 		APLL_CON0, NULL),
735 	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
736 		MPLL_CON0, NULL),
737 	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
738 		BPLL_CON0, NULL),
739 	[gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
740 		GPLL_CON0, NULL),
741 	[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
742 		CPLL_CON0, NULL),
743 	[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
744 		EPLL_CON0, NULL),
745 	[vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
746 		VPLL_LOCK, VPLL_CON0, NULL),
747 };
748 
749 #define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud)		\
750 		((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) |	\
751 		 ((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
752 #define E5250_CPU_DIV1(hpm, copy)					\
753 		(((hpm) << 4) | (copy))
754 
755 static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
756 	{ 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
757 	{ 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
758 	{ 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
759 	{ 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
760 	{ 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
761 	{ 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
762 	{ 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
763 	{ 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
764 	{  900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
765 	{  800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
766 	{  700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
767 	{  600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
768 	{  500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
769 	{  400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
770 	{  300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
771 	{  200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
772 	{  0 },
773 };
774 
775 static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = {
776 	CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL, CLK_CPU_HAS_DIV1, 0x200,
777 			exynos5250_armclk_d),
778 };
779 
780 static const struct of_device_id ext_clk_match[] __initconst = {
781 	{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
782 	{ },
783 };
784 
785 /* register exynox5250 clocks */
786 static void __init exynos5250_clk_init(struct device_node *np)
787 {
788 	struct samsung_clk_provider *ctx;
789 	unsigned int tmp;
790 	struct clk_hw **hws;
791 
792 	if (np) {
793 		reg_base = of_iomap(np, 0);
794 		if (!reg_base)
795 			panic("%s: failed to map registers\n", __func__);
796 	} else {
797 		panic("%s: unable to determine soc\n", __func__);
798 	}
799 
800 	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
801 	hws = ctx->clk_data.hws;
802 
803 	samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
804 			ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
805 			ext_clk_match);
806 	samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
807 				ARRAY_SIZE(exynos5250_pll_pmux_clks));
808 
809 	if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
810 		exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
811 		exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
812 	}
813 
814 	if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ)
815 		exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;
816 
817 	samsung_clk_register_pll(ctx, exynos5250_plls,
818 			ARRAY_SIZE(exynos5250_plls),
819 			reg_base);
820 	samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
821 			ARRAY_SIZE(exynos5250_fixed_rate_clks));
822 	samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
823 			ARRAY_SIZE(exynos5250_fixed_factor_clks));
824 	samsung_clk_register_mux(ctx, exynos5250_mux_clks,
825 			ARRAY_SIZE(exynos5250_mux_clks));
826 	samsung_clk_register_div(ctx, exynos5250_div_clks,
827 			ARRAY_SIZE(exynos5250_div_clks));
828 	samsung_clk_register_gate(ctx, exynos5250_gate_clks,
829 			ARRAY_SIZE(exynos5250_gate_clks));
830 	samsung_clk_register_cpu(ctx, exynos5250_cpu_clks,
831 			ARRAY_SIZE(exynos5250_cpu_clks));
832 
833 	/*
834 	 * Enable arm clock down (in idle) and set arm divider
835 	 * ratios in WFI/WFE state.
836 	 */
837 	tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
838 		PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
839 		PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
840 		PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
841 	__raw_writel(tmp, reg_base + PWR_CTRL1);
842 
843 	/*
844 	 * Enable arm clock up (on exiting idle). Set arm divider
845 	 * ratios when not in idle along with the standby duration
846 	 * ratios.
847 	 */
848 	tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
849 		PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
850 		PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
851 	__raw_writel(tmp, reg_base + PWR_CTRL2);
852 
853 	samsung_clk_sleep_init(reg_base, exynos5250_clk_regs,
854 			       ARRAY_SIZE(exynos5250_clk_regs));
855 	exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus),
856 			     exynos5250_subcmus);
857 
858 	samsung_clk_of_add_provider(np, ctx);
859 
860 	pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
861 		clk_hw_get_rate(hws[CLK_DIV_ARM2]));
862 }
863 CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
864