1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2013 Linaro Ltd. 4 * Author: Thomas Abraham <thomas.ab@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for all Exynos4 SoCs. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clkdev.h> 15 #include <linux/clk-provider.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 19 #include "clk.h" 20 #include "clk-pll.h" 21 22 /* Exynos4 clock controller register offsets */ 23 #define SRC_LEFTBUS 0x4200 24 #define DIV_LEFTBUS 0x4500 25 #define GATE_IP_LEFTBUS 0x4800 26 #define E4X12_GATE_IP_IMAGE 0x4930 27 #define SRC_RIGHTBUS 0x8200 28 #define DIV_RIGHTBUS 0x8500 29 #define GATE_IP_RIGHTBUS 0x8800 30 #define E4X12_GATE_IP_PERIR 0x8960 31 #define EPLL_LOCK 0xc010 32 #define VPLL_LOCK 0xc020 33 #define EPLL_CON0 0xc110 34 #define EPLL_CON1 0xc114 35 #define EPLL_CON2 0xc118 36 #define VPLL_CON0 0xc120 37 #define VPLL_CON1 0xc124 38 #define VPLL_CON2 0xc128 39 #define SRC_TOP0 0xc210 40 #define SRC_TOP1 0xc214 41 #define SRC_CAM 0xc220 42 #define SRC_TV 0xc224 43 #define SRC_MFC 0xcc28 44 #define SRC_G3D 0xc22c 45 #define E4210_SRC_IMAGE 0xc230 46 #define SRC_LCD0 0xc234 47 #define E4210_SRC_LCD1 0xc238 48 #define E4X12_SRC_ISP 0xc238 49 #define SRC_MAUDIO 0xc23c 50 #define SRC_FSYS 0xc240 51 #define SRC_PERIL0 0xc250 52 #define SRC_PERIL1 0xc254 53 #define E4X12_SRC_CAM1 0xc258 54 #define SRC_MASK_TOP 0xc310 55 #define SRC_MASK_CAM 0xc320 56 #define SRC_MASK_TV 0xc324 57 #define SRC_MASK_LCD0 0xc334 58 #define E4210_SRC_MASK_LCD1 0xc338 59 #define E4X12_SRC_MASK_ISP 0xc338 60 #define SRC_MASK_MAUDIO 0xc33c 61 #define SRC_MASK_FSYS 0xc340 62 #define SRC_MASK_PERIL0 0xc350 63 #define SRC_MASK_PERIL1 0xc354 64 #define DIV_TOP 0xc510 65 #define DIV_CAM 0xc520 66 #define DIV_TV 0xc524 67 #define DIV_MFC 0xc528 68 #define DIV_G3D 0xc52c 69 #define DIV_IMAGE 0xc530 70 #define DIV_LCD0 0xc534 71 #define E4210_DIV_LCD1 0xc538 72 #define E4X12_DIV_ISP 0xc538 73 #define DIV_MAUDIO 0xc53c 74 #define DIV_FSYS0 0xc540 75 #define DIV_FSYS1 0xc544 76 #define DIV_FSYS2 0xc548 77 #define DIV_FSYS3 0xc54c 78 #define DIV_PERIL0 0xc550 79 #define DIV_PERIL1 0xc554 80 #define DIV_PERIL2 0xc558 81 #define DIV_PERIL3 0xc55c 82 #define DIV_PERIL4 0xc560 83 #define DIV_PERIL5 0xc564 84 #define E4X12_DIV_CAM1 0xc568 85 #define GATE_SCLK_CAM 0xc820 86 #define GATE_IP_CAM 0xc920 87 #define GATE_IP_TV 0xc924 88 #define GATE_IP_MFC 0xc928 89 #define GATE_IP_G3D 0xc92c 90 #define E4210_GATE_IP_IMAGE 0xc930 91 #define GATE_IP_LCD0 0xc934 92 #define E4210_GATE_IP_LCD1 0xc938 93 #define E4X12_GATE_IP_ISP 0xc938 94 #define E4X12_GATE_IP_MAUDIO 0xc93c 95 #define GATE_IP_FSYS 0xc940 96 #define GATE_IP_GPS 0xc94c 97 #define GATE_IP_PERIL 0xc950 98 #define E4210_GATE_IP_PERIR 0xc960 99 #define GATE_BLOCK 0xc970 100 #define E4X12_MPLL_CON0 0x10108 101 #define SRC_DMC 0x10200 102 #define SRC_MASK_DMC 0x10300 103 #define DIV_DMC0 0x10500 104 #define DIV_DMC1 0x10504 105 #define GATE_IP_DMC 0x10900 106 #define APLL_CON0 0x14100 107 #define E4210_MPLL_CON0 0x14108 108 #define SRC_CPU 0x14200 109 #define DIV_CPU0 0x14500 110 #define DIV_CPU1 0x14504 111 #define GATE_SCLK_CPU 0x14800 112 #define GATE_IP_CPU 0x14900 113 #define E4X12_DIV_ISP0 0x18300 114 #define E4X12_DIV_ISP1 0x18304 115 #define E4X12_GATE_ISP0 0x18800 116 #define E4X12_GATE_ISP1 0x18804 117 118 /* the exynos4 soc type */ 119 enum exynos4_soc { 120 EXYNOS4210, 121 EXYNOS4X12, 122 }; 123 124 /* 125 * Let each supported clock get a unique id. This id is used to lookup the clock 126 * for device tree based platforms. The clocks are categorized into three 127 * sections: core, sclk gate and bus interface gate clocks. 128 * 129 * When adding a new clock to this list, it is advised to choose a clock 130 * category and add it to the end of that category. That is because the the 131 * device tree source file is referring to these ids and any change in the 132 * sequence number of existing clocks will require corresponding change in the 133 * device tree files. This limitation would go away when pre-processor support 134 * for dtc would be available. 135 */ 136 enum exynos4_clks { 137 none, 138 139 /* core clocks */ 140 xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll, 141 sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100, 142 aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core, 143 mout_apll, /* 20 */ 144 145 /* gate for special clocks (sclk) */ 146 sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0, 147 sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac, 148 sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0, 149 sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4, 150 sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4, 151 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, 152 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1, 153 sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp, 154 sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d, 155 156 /* gate clocks */ 157 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0, 158 smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi, 159 smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d, 160 smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1, 161 mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0, 162 sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie, 163 onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3, 164 uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, 165 spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus, 166 spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif, 167 audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0, 168 fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp, 169 gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp, 170 mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp, 171 asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk, 172 spi1_isp_sclk, uart_isp_sclk, 173 174 /* mux clocks */ 175 mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0, 176 mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d, 177 aclk400_mcuisp, 178 179 /* div clocks */ 180 div_isp0 = 450, div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200, 181 div_aclk400_mcuisp, 182 183 nr_clks, 184 }; 185 186 /* 187 * list of controller registers to be saved and restored during a 188 * suspend/resume cycle. 189 */ 190 static __initdata unsigned long exynos4210_clk_save[] = { 191 E4210_SRC_IMAGE, 192 E4210_SRC_LCD1, 193 E4210_SRC_MASK_LCD1, 194 E4210_DIV_LCD1, 195 E4210_GATE_IP_IMAGE, 196 E4210_GATE_IP_LCD1, 197 E4210_GATE_IP_PERIR, 198 E4210_MPLL_CON0, 199 }; 200 201 static __initdata unsigned long exynos4x12_clk_save[] = { 202 E4X12_GATE_IP_IMAGE, 203 E4X12_GATE_IP_PERIR, 204 E4X12_SRC_CAM1, 205 E4X12_DIV_ISP, 206 E4X12_DIV_CAM1, 207 E4X12_MPLL_CON0, 208 }; 209 210 static __initdata unsigned long exynos4_clk_regs[] = { 211 SRC_LEFTBUS, 212 DIV_LEFTBUS, 213 GATE_IP_LEFTBUS, 214 SRC_RIGHTBUS, 215 DIV_RIGHTBUS, 216 GATE_IP_RIGHTBUS, 217 EPLL_CON0, 218 EPLL_CON1, 219 EPLL_CON2, 220 VPLL_CON0, 221 VPLL_CON1, 222 VPLL_CON2, 223 SRC_TOP0, 224 SRC_TOP1, 225 SRC_CAM, 226 SRC_TV, 227 SRC_MFC, 228 SRC_G3D, 229 SRC_LCD0, 230 SRC_MAUDIO, 231 SRC_FSYS, 232 SRC_PERIL0, 233 SRC_PERIL1, 234 SRC_MASK_TOP, 235 SRC_MASK_CAM, 236 SRC_MASK_TV, 237 SRC_MASK_LCD0, 238 SRC_MASK_MAUDIO, 239 SRC_MASK_FSYS, 240 SRC_MASK_PERIL0, 241 SRC_MASK_PERIL1, 242 DIV_TOP, 243 DIV_CAM, 244 DIV_TV, 245 DIV_MFC, 246 DIV_G3D, 247 DIV_IMAGE, 248 DIV_LCD0, 249 DIV_MAUDIO, 250 DIV_FSYS0, 251 DIV_FSYS1, 252 DIV_FSYS2, 253 DIV_FSYS3, 254 DIV_PERIL0, 255 DIV_PERIL1, 256 DIV_PERIL2, 257 DIV_PERIL3, 258 DIV_PERIL4, 259 DIV_PERIL5, 260 GATE_SCLK_CAM, 261 GATE_IP_CAM, 262 GATE_IP_TV, 263 GATE_IP_MFC, 264 GATE_IP_G3D, 265 GATE_IP_LCD0, 266 GATE_IP_FSYS, 267 GATE_IP_GPS, 268 GATE_IP_PERIL, 269 GATE_BLOCK, 270 SRC_MASK_DMC, 271 SRC_DMC, 272 DIV_DMC0, 273 DIV_DMC1, 274 GATE_IP_DMC, 275 APLL_CON0, 276 SRC_CPU, 277 DIV_CPU0, 278 DIV_CPU1, 279 GATE_SCLK_CPU, 280 GATE_IP_CPU, 281 }; 282 283 /* list of all parent clock list */ 284 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 285 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; 286 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; 287 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", }; 288 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", }; 289 PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", }; 290 PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", }; 291 PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", }; 292 PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", }; 293 PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", }; 294 PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", }; 295 PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", 296 "spdif_extclk", }; 297 PNAME(mout_onenand_p) = {"aclk133", "aclk160", }; 298 PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", }; 299 300 /* Exynos 4210-specific parent groups */ 301 PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", }; 302 PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", }; 303 PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", }; 304 PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", 305 "sclk_usbphy0", "none", "sclk_hdmiphy", 306 "sclk_mpll", "sclk_epll", "sclk_vpll", }; 307 PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m", 308 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 309 "sclk_epll", "sclk_vpll" }; 310 PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m", 311 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 312 "sclk_epll", "sclk_vpll", }; 313 PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m", 314 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 315 "sclk_epll", "sclk_vpll", }; 316 PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", }; 317 PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", }; 318 319 /* Exynos 4x12-specific parent groups */ 320 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", }; 321 PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", }; 322 PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", }; 323 PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", 324 "none", "sclk_hdmiphy", "mout_mpll_user_t", 325 "sclk_epll", "sclk_vpll", }; 326 PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m", 327 "sclk_usbphy0", "xxti", "xusbxti", 328 "mout_mpll_user_t", "sclk_epll", "sclk_vpll" }; 329 PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m", 330 "sclk_usbphy0", "xxti", "xusbxti", 331 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; 332 PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m", 333 "sclk_usbphy0", "xxti", "xusbxti", 334 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; 335 PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", }; 336 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", }; 337 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", }; 338 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; 339 340 /* fixed rate clocks generated outside the soc */ 341 struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { 342 FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0), 343 FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0), 344 }; 345 346 /* fixed rate clocks generated inside the soc */ 347 struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { 348 FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), 349 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 350 FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 351 }; 352 353 struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { 354 FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), 355 }; 356 357 /* list of mux clocks supported in all exynos4 soc's */ 358 struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 359 MUX_FA(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 360 CLK_SET_RATE_PARENT, 0, "mout_apll"), 361 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), 362 MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), 363 MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), 364 MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, 365 CLK_SET_RATE_PARENT, 0), 366 MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, 367 CLK_SET_RATE_PARENT, 0), 368 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), 369 MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), 370 MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"), 371 MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), 372 }; 373 374 /* list of mux clocks supported in exynos4210 soc */ 375 struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 376 MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), 377 MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), 378 MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), 379 MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), 380 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), 381 MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), 382 MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), 383 MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), 384 MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), 385 MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), 386 MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), 387 MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), 388 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "mout_mpll"), 389 MUX_A(mout_core, "mout_core", mout_core_p4210, 390 SRC_CPU, 16, 1, "moutcore"), 391 MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, 392 SRC_TOP0, 8, 1, "sclk_vpll"), 393 MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), 394 MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), 395 MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), 396 MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), 397 MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), 398 MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), 399 MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), 400 MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), 401 MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), 402 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, 403 CLK_SET_RATE_PARENT, 0), 404 MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), 405 MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), 406 MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), 407 MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), 408 MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), 409 MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), 410 MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), 411 MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), 412 MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), 413 MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), 414 MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), 415 MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), 416 MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), 417 MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), 418 MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), 419 MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), 420 MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), 421 MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), 422 MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), 423 }; 424 425 /* list of mux clocks supported in exynos4x12 soc */ 426 struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 427 MUX_A(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, 428 SRC_CPU, 24, 1, "mout_mpll"), 429 MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), 430 MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), 431 MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12, 432 SRC_TOP1, 12, 1), 433 MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, 434 SRC_TOP1, 16, 1), 435 MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), 436 MUX(aclk400_mcuisp, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12, 437 SRC_TOP1, 24, 1), 438 MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), 439 MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), 440 MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), 441 MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), 442 MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), 443 MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), 444 MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), 445 MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), 446 MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), 447 MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), 448 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, 449 SRC_DMC, 12, 1, "sclk_mpll"), 450 MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p, 451 SRC_TOP0, 8, 1, "sclk_vpll"), 452 MUX_A(mout_core, "mout_core", mout_core_p4x12, 453 SRC_CPU, 16, 1, "moutcore"), 454 MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), 455 MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), 456 MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), 457 MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), 458 MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), 459 MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), 460 MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), 461 MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), 462 MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), 463 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, 464 CLK_SET_RATE_PARENT, 0), 465 MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), 466 MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), 467 MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), 468 MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), 469 MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), 470 MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), 471 MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), 472 MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), 473 MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), 474 MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), 475 MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), 476 MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), 477 MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), 478 MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), 479 MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), 480 MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), 481 MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), 482 MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), 483 MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), 484 MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), 485 MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), 486 MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), 487 MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), 488 MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), 489 MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), 490 MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), 491 }; 492 493 /* list of divider clocks supported in all exynos4 soc's */ 494 struct samsung_div_clock exynos4_div_clks[] __initdata = { 495 DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3), 496 DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3), 497 DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), 498 DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), 499 DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), 500 DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), 501 DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), 502 DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), 503 DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), 504 DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), 505 DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), 506 DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4, 507 CLK_SET_RATE_PARENT, 0), 508 DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), 509 DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), 510 DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), 511 DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), 512 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 513 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 514 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 515 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 516 DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), 517 DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), 518 DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), 519 DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), 520 DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), 521 DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), 522 DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), 523 DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), 524 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), 525 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), 526 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), 527 DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8), 528 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 529 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 530 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), 531 DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), 532 DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), 533 DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), 534 DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), 535 DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), 536 DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), 537 DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), 538 DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), 539 DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), 540 DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), 541 DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "armclk"), 542 DIV_A(sclk_apll, "sclk_apll", "mout_apll", 543 DIV_CPU0, 24, 3, "sclk_apll"), 544 DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, 545 CLK_SET_RATE_PARENT, 0), 546 DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, 547 CLK_SET_RATE_PARENT, 0), 548 DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, 549 CLK_SET_RATE_PARENT, 0), 550 DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, 551 CLK_SET_RATE_PARENT, 0), 552 DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, 553 CLK_SET_RATE_PARENT, 0), 554 }; 555 556 /* list of divider clocks supported in exynos4210 soc */ 557 struct samsung_div_clock exynos4210_div_clks[] __initdata = { 558 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), 559 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), 560 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), 561 DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), 562 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 563 DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, 564 CLK_SET_RATE_PARENT, 0), 565 }; 566 567 /* list of divider clocks supported in exynos4x12 soc */ 568 struct samsung_div_clock exynos4x12_div_clks[] __initdata = { 569 DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), 570 DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), 571 DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), 572 DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), 573 DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), 574 DIV(div_aclk200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), 575 DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), 576 DIV(div_aclk400_mcuisp, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", 577 DIV_TOP, 24, 3), 578 DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), 579 DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), 580 DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), 581 DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), 582 DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), 583 DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), 584 DIV_F(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, 585 CLK_GET_RATE_NOCACHE, 0), 586 DIV_F(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, 587 CLK_GET_RATE_NOCACHE, 0), 588 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), 589 DIV_F(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 590 4, 3, CLK_GET_RATE_NOCACHE, 0), 591 DIV_F(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 592 8, 3, CLK_GET_RATE_NOCACHE, 0), 593 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 594 }; 595 596 /* list of gate clocks supported in all exynos4 soc's */ 597 struct samsung_gate_clock exynos4_gate_clks[] __initdata = { 598 /* 599 * After all Exynos4 based platforms are migrated to use device tree, 600 * the device name and clock alias names specified below for some 601 * of the clocks can be removed. 602 */ 603 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), 604 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0), 605 GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), 606 GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), 607 GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), 608 GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), 609 GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), 610 GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), 611 GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0), 612 GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), 613 GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), 614 GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, 615 CLK_SET_RATE_PARENT, 0), 616 GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), 617 GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), 618 GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), 619 GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), 620 GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), 621 GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), 622 GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, 623 CLK_SET_RATE_PARENT, 0), 624 GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, 625 CLK_SET_RATE_PARENT, 0), 626 GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0", 627 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), 628 GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, 629 CLK_SET_RATE_PARENT, 0), 630 GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, 631 CLK_SET_RATE_PARENT, 0), 632 GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0), 633 GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), 634 GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), 635 GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"), 636 GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"), 637 GATE_A(usb_host, "usb_host", "aclk133", 638 GATE_IP_FSYS, 12, 0, 0, "usbhost"), 639 GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0", 640 SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), 641 GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1", 642 SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), 643 GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2", 644 SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), 645 GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3", 646 SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), 647 GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0", 648 SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"), 649 GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1", 650 SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"), 651 GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0", 652 SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), 653 GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0", 654 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0, 655 "mmc_busclk.2"), 656 GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1", 657 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0, 658 "mmc_busclk.2"), 659 GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2", 660 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0, 661 "mmc_busclk.2"), 662 GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3", 663 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0, 664 "mmc_busclk.2"), 665 GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4", 666 SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"), 667 GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0", 668 SRC_MASK_PERIL0, 0, CLK_SET_RATE_PARENT, 669 0, "clk_uart_baud0"), 670 GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1", 671 SRC_MASK_PERIL0, 4, CLK_SET_RATE_PARENT, 672 0, "clk_uart_baud0"), 673 GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2", 674 SRC_MASK_PERIL0, 8, CLK_SET_RATE_PARENT, 675 0, "clk_uart_baud0"), 676 GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3", 677 SRC_MASK_PERIL0, 12, CLK_SET_RATE_PARENT, 678 0, "clk_uart_baud0"), 679 GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4", 680 SRC_MASK_PERIL0, 16, CLK_SET_RATE_PARENT, 681 0, "clk_uart_baud0"), 682 GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, 683 CLK_SET_RATE_PARENT, 0), 684 GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0", 685 SRC_MASK_PERIL1, 16, CLK_SET_RATE_PARENT, 686 0, "spi_busclk0"), 687 GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1", 688 SRC_MASK_PERIL1, 20, CLK_SET_RATE_PARENT, 689 0, "spi_busclk0"), 690 GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2", 691 SRC_MASK_PERIL1, 24, CLK_SET_RATE_PARENT, 692 0, "spi_busclk0"), 693 GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160", 694 GATE_IP_CAM, 0, 0, 0, "fimc"), 695 GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160", 696 GATE_IP_CAM, 1, 0, 0, "fimc"), 697 GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160", 698 GATE_IP_CAM, 2, 0, 0, "fimc"), 699 GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160", 700 GATE_IP_CAM, 3, 0, 0, "fimc"), 701 GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160", 702 GATE_IP_CAM, 4, 0, 0, "fimc"), 703 GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160", 704 GATE_IP_CAM, 5, 0, 0, "fimc"), 705 GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160", 706 GATE_IP_CAM, 7, 0, 0, "sysmmu"), 707 GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160", 708 GATE_IP_CAM, 8, 0, 0, "sysmmu"), 709 GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160", 710 GATE_IP_CAM, 9, 0, 0, "sysmmu"), 711 GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160", 712 GATE_IP_CAM, 10, 0, 0, "sysmmu"), 713 GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160", 714 GATE_IP_CAM, 11, 0, 0, "sysmmu"), 715 GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), 716 GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), 717 GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160", 718 GATE_IP_TV, 4, 0, 0, "sysmmu"), 719 GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"), 720 GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100", 721 GATE_IP_MFC, 1, 0, 0, "sysmmu"), 722 GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100", 723 GATE_IP_MFC, 2, 0, 0, "sysmmu"), 724 GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160", 725 GATE_IP_LCD0, 0, 0, 0, "fimd"), 726 GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160", 727 GATE_IP_LCD0, 4, 0, 0, "sysmmu"), 728 GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133", 729 GATE_IP_FSYS, 0, 0, 0, "dma"), 730 GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133", 731 GATE_IP_FSYS, 1, 0, 0, "dma"), 732 GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133", 733 GATE_IP_FSYS, 5, 0, 0, "hsmmc"), 734 GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133", 735 GATE_IP_FSYS, 6, 0, 0, "hsmmc"), 736 GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133", 737 GATE_IP_FSYS, 7, 0, 0, "hsmmc"), 738 GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133", 739 GATE_IP_FSYS, 8, 0, 0, "hsmmc"), 740 GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100", 741 GATE_IP_PERIL, 0, 0, 0, "uart"), 742 GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100", 743 GATE_IP_PERIL, 1, 0, 0, "uart"), 744 GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100", 745 GATE_IP_PERIL, 2, 0, 0, "uart"), 746 GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100", 747 GATE_IP_PERIL, 3, 0, 0, "uart"), 748 GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100", 749 GATE_IP_PERIL, 4, 0, 0, "uart"), 750 GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100", 751 GATE_IP_PERIL, 6, 0, 0, "i2c"), 752 GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100", 753 GATE_IP_PERIL, 7, 0, 0, "i2c"), 754 GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100", 755 GATE_IP_PERIL, 8, 0, 0, "i2c"), 756 GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100", 757 GATE_IP_PERIL, 9, 0, 0, "i2c"), 758 GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100", 759 GATE_IP_PERIL, 10, 0, 0, "i2c"), 760 GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100", 761 GATE_IP_PERIL, 11, 0, 0, "i2c"), 762 GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100", 763 GATE_IP_PERIL, 12, 0, 0, "i2c"), 764 GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100", 765 GATE_IP_PERIL, 13, 0, 0, "i2c"), 766 GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100", 767 GATE_IP_PERIL, 14, 0, 0, "i2c"), 768 GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100", 769 GATE_IP_PERIL, 16, 0, 0, "spi"), 770 GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100", 771 GATE_IP_PERIL, 17, 0, 0, "spi"), 772 GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100", 773 GATE_IP_PERIL, 18, 0, 0, "spi"), 774 GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100", 775 GATE_IP_PERIL, 20, 0, 0, "iis"), 776 GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100", 777 GATE_IP_PERIL, 21, 0, 0, "iis"), 778 GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100", 779 GATE_IP_PERIL, 22, 0, 0, "pcm"), 780 GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100", 781 GATE_IP_PERIL, 23, 0, 0, "pcm"), 782 GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100", 783 GATE_IP_PERIL, 26, 0, 0, "spdif"), 784 GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100", 785 GATE_IP_PERIL, 27, 0, 0, "ac97"), 786 }; 787 788 /* list of gate clocks supported in exynos4210 soc */ 789 struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 790 GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), 791 GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), 792 GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), 793 GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), 794 GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), 795 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0), 796 GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), 797 GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), 798 GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), 799 GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), 800 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), 801 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), 802 GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), 803 GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 804 CLK_IGNORE_UNUSED, 0), 805 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0), 806 GATE(smmu_rotator, "smmu_rotator", "aclk200", 807 E4210_GATE_IP_IMAGE, 4, 0, 0), 808 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1", 809 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), 810 GATE(sclk_sata, "sclk_sata", "div_sata", 811 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 812 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), 813 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), 814 GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"), 815 GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"), 816 GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"), 817 GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"), 818 GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"), 819 GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1", 820 E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), 821 }; 822 823 /* list of gate clocks supported in exynos4x12 soc */ 824 struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 825 GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), 826 GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), 827 GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), 828 GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), 829 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0), 830 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 831 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), 832 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 833 CLK_IGNORE_UNUSED, 0), 834 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0), 835 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0", 836 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), 837 GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", 838 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), 839 GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi", 840 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 841 GATE(smmu_rotator, "smmu_rotator", "aclk200", 842 E4X12_GATE_IP_IMAGE, 4, 0, 0), 843 GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"), 844 GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"), 845 GATE_A(keyif, "keyif", "aclk100", 846 E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"), 847 GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp", 848 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0), 849 GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre", 850 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0), 851 GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre", 852 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0), 853 GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp", 854 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0), 855 GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp", 856 E4X12_GATE_IP_ISP, 0, 0, 0), 857 GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp", 858 E4X12_GATE_IP_ISP, 1, 0, 0), 859 GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp", 860 E4X12_GATE_IP_ISP, 2, 0, 0), 861 GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp", 862 E4X12_GATE_IP_ISP, 3, 0, 0), 863 GATE_A(wdt, "watchdog", "aclk100", 864 E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"), 865 GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100", 866 E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"), 867 GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100", 868 E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"), 869 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0, 870 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 871 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1, 872 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 873 GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2, 874 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 875 GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 876 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 877 GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 878 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 879 GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 880 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 881 GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 882 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 883 GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 884 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 885 GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 886 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 887 GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 888 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 889 GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, 890 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 891 GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, 892 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 893 GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, 894 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 895 GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, 896 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 897 GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, 898 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 899 GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, 900 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 901 GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, 902 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 903 GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, 904 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 905 GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, 906 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 907 GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 908 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 909 GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 910 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 911 GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, 912 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 913 GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, 914 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 915 GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, 916 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 917 GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, 918 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 919 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 920 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 921 GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), 922 }; 923 924 /* 925 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit 926 * resides in chipid register space, outside of the clock controller memory 927 * mapped space. So to determine the parent of fin_pll clock, the chipid 928 * controller is first remapped and the value of XOM[0] bit is read to 929 * determine the parent clock. 930 */ 931 static unsigned long exynos4_get_xom(void) 932 { 933 unsigned long xom = 0; 934 void __iomem *chipid_base; 935 struct device_node *np; 936 937 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid"); 938 if (np) { 939 chipid_base = of_iomap(np, 0); 940 941 if (chipid_base) 942 xom = readl(chipid_base + 8); 943 944 iounmap(chipid_base); 945 } 946 947 return xom; 948 } 949 950 static void __init exynos4_clk_register_finpll(unsigned long xom) 951 { 952 struct samsung_fixed_rate_clock fclk; 953 struct clk *clk; 954 unsigned long finpll_f = 24000000; 955 char *parent_name; 956 957 parent_name = xom & 1 ? "xusbxti" : "xxti"; 958 clk = clk_get(NULL, parent_name); 959 if (IS_ERR(clk)) { 960 pr_err("%s: failed to lookup parent clock %s, assuming " 961 "fin_pll clock frequency is 24MHz\n", __func__, 962 parent_name); 963 } else { 964 finpll_f = clk_get_rate(clk); 965 } 966 967 fclk.id = fin_pll; 968 fclk.name = "fin_pll"; 969 fclk.parent_name = NULL; 970 fclk.flags = CLK_IS_ROOT; 971 fclk.fixed_rate = finpll_f; 972 samsung_clk_register_fixed_rate(&fclk, 1); 973 974 } 975 976 /* 977 * This function allows non-dt platforms to specify the clock speed of the 978 * xxti and xusbxti clocks. These clocks are then registered with the specified 979 * clock speed. 980 */ 981 void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f, 982 unsigned long xusbxti_f) 983 { 984 exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f; 985 exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f; 986 samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks, 987 ARRAY_SIZE(exynos4_fixed_rate_ext_clks)); 988 } 989 990 static __initdata struct of_device_id ext_clk_match[] = { 991 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 992 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, 993 {}, 994 }; 995 996 /* register exynos4 clocks */ 997 void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_soc, void __iomem *reg_base, unsigned long xom) 998 { 999 struct clk *apll, *mpll, *epll, *vpll; 1000 1001 if (np) { 1002 reg_base = of_iomap(np, 0); 1003 if (!reg_base) 1004 panic("%s: failed to map registers\n", __func__); 1005 } 1006 1007 if (exynos4_soc == EXYNOS4210) 1008 samsung_clk_init(np, reg_base, nr_clks, 1009 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), 1010 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save)); 1011 else 1012 samsung_clk_init(np, reg_base, nr_clks, 1013 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), 1014 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save)); 1015 1016 if (np) 1017 samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks, 1018 ARRAY_SIZE(exynos4_fixed_rate_ext_clks), 1019 ext_clk_match); 1020 1021 exynos4_clk_register_finpll(xom); 1022 1023 if (exynos4_soc == EXYNOS4210) { 1024 apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll", 1025 reg_base + APLL_CON0, pll_4508); 1026 mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll", 1027 reg_base + E4210_MPLL_CON0, pll_4508); 1028 epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll", 1029 reg_base + EPLL_CON0, pll_4600); 1030 vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc", 1031 reg_base + VPLL_CON0, pll_4650c); 1032 } else { 1033 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", 1034 reg_base + APLL_CON0); 1035 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", 1036 reg_base + E4X12_MPLL_CON0); 1037 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", 1038 reg_base + EPLL_CON0); 1039 vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll", 1040 reg_base + VPLL_CON0); 1041 } 1042 1043 samsung_clk_add_lookup(apll, fout_apll); 1044 samsung_clk_add_lookup(mpll, fout_mpll); 1045 samsung_clk_add_lookup(epll, fout_epll); 1046 samsung_clk_add_lookup(vpll, fout_vpll); 1047 1048 samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks, 1049 ARRAY_SIZE(exynos4_fixed_rate_clks)); 1050 samsung_clk_register_mux(exynos4_mux_clks, 1051 ARRAY_SIZE(exynos4_mux_clks)); 1052 samsung_clk_register_div(exynos4_div_clks, 1053 ARRAY_SIZE(exynos4_div_clks)); 1054 samsung_clk_register_gate(exynos4_gate_clks, 1055 ARRAY_SIZE(exynos4_gate_clks)); 1056 1057 if (exynos4_soc == EXYNOS4210) { 1058 samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks, 1059 ARRAY_SIZE(exynos4210_fixed_rate_clks)); 1060 samsung_clk_register_mux(exynos4210_mux_clks, 1061 ARRAY_SIZE(exynos4210_mux_clks)); 1062 samsung_clk_register_div(exynos4210_div_clks, 1063 ARRAY_SIZE(exynos4210_div_clks)); 1064 samsung_clk_register_gate(exynos4210_gate_clks, 1065 ARRAY_SIZE(exynos4210_gate_clks)); 1066 } else { 1067 samsung_clk_register_mux(exynos4x12_mux_clks, 1068 ARRAY_SIZE(exynos4x12_mux_clks)); 1069 samsung_clk_register_div(exynos4x12_div_clks, 1070 ARRAY_SIZE(exynos4x12_div_clks)); 1071 samsung_clk_register_gate(exynos4x12_gate_clks, 1072 ARRAY_SIZE(exynos4x12_gate_clks)); 1073 } 1074 1075 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" 1076 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", 1077 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", 1078 _get_rate("sclk_apll"), _get_rate("mout_mpll"), 1079 _get_rate("sclk_epll"), _get_rate("sclk_vpll"), 1080 _get_rate("armclk")); 1081 } 1082 1083 1084 static void __init exynos4210_clk_init(struct device_node *np) 1085 { 1086 exynos4_clk_init(np, EXYNOS4210, NULL, exynos4_get_xom()); 1087 } 1088 CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init); 1089 1090 static void __init exynos4412_clk_init(struct device_node *np) 1091 { 1092 exynos4_clk_init(np, EXYNOS4X12, NULL, exynos4_get_xom()); 1093 } 1094 CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init); 1095