1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2013 Linaro Ltd. 4 * Author: Thomas Abraham <thomas.ab@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for all Exynos4 SoCs. 11 */ 12 13 #include <dt-bindings/clock/exynos4.h> 14 #include <linux/clk.h> 15 #include <linux/clkdev.h> 16 #include <linux/clk-provider.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/syscore_ops.h> 20 21 #include "clk.h" 22 #include "clk-cpu.h" 23 24 /* Exynos4 clock controller register offsets */ 25 #define SRC_LEFTBUS 0x4200 26 #define DIV_LEFTBUS 0x4500 27 #define GATE_IP_LEFTBUS 0x4800 28 #define E4X12_GATE_IP_IMAGE 0x4930 29 #define CLKOUT_CMU_LEFTBUS 0x4a00 30 #define SRC_RIGHTBUS 0x8200 31 #define DIV_RIGHTBUS 0x8500 32 #define GATE_IP_RIGHTBUS 0x8800 33 #define E4X12_GATE_IP_PERIR 0x8960 34 #define CLKOUT_CMU_RIGHTBUS 0x8a00 35 #define EPLL_LOCK 0xc010 36 #define VPLL_LOCK 0xc020 37 #define EPLL_CON0 0xc110 38 #define EPLL_CON1 0xc114 39 #define EPLL_CON2 0xc118 40 #define VPLL_CON0 0xc120 41 #define VPLL_CON1 0xc124 42 #define VPLL_CON2 0xc128 43 #define SRC_TOP0 0xc210 44 #define SRC_TOP1 0xc214 45 #define SRC_CAM 0xc220 46 #define SRC_TV 0xc224 47 #define SRC_MFC 0xc228 48 #define SRC_G3D 0xc22c 49 #define E4210_SRC_IMAGE 0xc230 50 #define SRC_LCD0 0xc234 51 #define E4210_SRC_LCD1 0xc238 52 #define E4X12_SRC_ISP 0xc238 53 #define SRC_MAUDIO 0xc23c 54 #define SRC_FSYS 0xc240 55 #define SRC_PERIL0 0xc250 56 #define SRC_PERIL1 0xc254 57 #define E4X12_SRC_CAM1 0xc258 58 #define SRC_MASK_TOP 0xc310 59 #define SRC_MASK_CAM 0xc320 60 #define SRC_MASK_TV 0xc324 61 #define SRC_MASK_LCD0 0xc334 62 #define E4210_SRC_MASK_LCD1 0xc338 63 #define E4X12_SRC_MASK_ISP 0xc338 64 #define SRC_MASK_MAUDIO 0xc33c 65 #define SRC_MASK_FSYS 0xc340 66 #define SRC_MASK_PERIL0 0xc350 67 #define SRC_MASK_PERIL1 0xc354 68 #define DIV_TOP 0xc510 69 #define DIV_CAM 0xc520 70 #define DIV_TV 0xc524 71 #define DIV_MFC 0xc528 72 #define DIV_G3D 0xc52c 73 #define DIV_IMAGE 0xc530 74 #define DIV_LCD0 0xc534 75 #define E4210_DIV_LCD1 0xc538 76 #define E4X12_DIV_ISP 0xc538 77 #define DIV_MAUDIO 0xc53c 78 #define DIV_FSYS0 0xc540 79 #define DIV_FSYS1 0xc544 80 #define DIV_FSYS2 0xc548 81 #define DIV_FSYS3 0xc54c 82 #define DIV_PERIL0 0xc550 83 #define DIV_PERIL1 0xc554 84 #define DIV_PERIL2 0xc558 85 #define DIV_PERIL3 0xc55c 86 #define DIV_PERIL4 0xc560 87 #define DIV_PERIL5 0xc564 88 #define E4X12_DIV_CAM1 0xc568 89 #define GATE_SCLK_CAM 0xc820 90 #define GATE_IP_CAM 0xc920 91 #define GATE_IP_TV 0xc924 92 #define GATE_IP_MFC 0xc928 93 #define GATE_IP_G3D 0xc92c 94 #define E4210_GATE_IP_IMAGE 0xc930 95 #define GATE_IP_LCD0 0xc934 96 #define E4210_GATE_IP_LCD1 0xc938 97 #define E4X12_GATE_IP_ISP 0xc938 98 #define E4X12_GATE_IP_MAUDIO 0xc93c 99 #define GATE_IP_FSYS 0xc940 100 #define GATE_IP_GPS 0xc94c 101 #define GATE_IP_PERIL 0xc950 102 #define E4210_GATE_IP_PERIR 0xc960 103 #define GATE_BLOCK 0xc970 104 #define CLKOUT_CMU_TOP 0xca00 105 #define E4X12_MPLL_LOCK 0x10008 106 #define E4X12_MPLL_CON0 0x10108 107 #define SRC_DMC 0x10200 108 #define SRC_MASK_DMC 0x10300 109 #define DIV_DMC0 0x10500 110 #define DIV_DMC1 0x10504 111 #define GATE_IP_DMC 0x10900 112 #define CLKOUT_CMU_DMC 0x10a00 113 #define APLL_LOCK 0x14000 114 #define E4210_MPLL_LOCK 0x14008 115 #define APLL_CON0 0x14100 116 #define E4210_MPLL_CON0 0x14108 117 #define SRC_CPU 0x14200 118 #define DIV_CPU0 0x14500 119 #define DIV_CPU1 0x14504 120 #define GATE_SCLK_CPU 0x14800 121 #define GATE_IP_CPU 0x14900 122 #define CLKOUT_CMU_CPU 0x14a00 123 #define PWR_CTRL1 0x15020 124 #define E4X12_PWR_CTRL2 0x15024 125 #define E4X12_DIV_ISP0 0x18300 126 #define E4X12_DIV_ISP1 0x18304 127 #define E4X12_GATE_ISP0 0x18800 128 #define E4X12_GATE_ISP1 0x18804 129 130 /* Below definitions are used for PWR_CTRL settings */ 131 #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28) 132 #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16) 133 #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) 134 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) 135 #define PWR_CTRL1_USE_CORE3_WFE (1 << 7) 136 #define PWR_CTRL1_USE_CORE2_WFE (1 << 6) 137 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5) 138 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4) 139 #define PWR_CTRL1_USE_CORE3_WFI (1 << 3) 140 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2) 141 #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) 142 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) 143 144 /* the exynos4 soc type */ 145 enum exynos4_soc { 146 EXYNOS4210, 147 EXYNOS4X12, 148 }; 149 150 /* list of PLLs to be registered */ 151 enum exynos4_plls { 152 apll, mpll, epll, vpll, 153 nr_plls /* number of PLLs */ 154 }; 155 156 static void __iomem *reg_base; 157 static enum exynos4_soc exynos4_soc; 158 159 /* 160 * Support for CMU save/restore across system suspends 161 */ 162 #ifdef CONFIG_PM_SLEEP 163 static struct samsung_clk_reg_dump *exynos4_save_common; 164 static struct samsung_clk_reg_dump *exynos4_save_soc; 165 static struct samsung_clk_reg_dump *exynos4_save_pll; 166 167 /* 168 * list of controller registers to be saved and restored during a 169 * suspend/resume cycle. 170 */ 171 static unsigned long exynos4210_clk_save[] __initdata = { 172 E4210_SRC_IMAGE, 173 E4210_SRC_LCD1, 174 E4210_SRC_MASK_LCD1, 175 E4210_DIV_LCD1, 176 E4210_GATE_IP_IMAGE, 177 E4210_GATE_IP_LCD1, 178 E4210_GATE_IP_PERIR, 179 E4210_MPLL_CON0, 180 PWR_CTRL1, 181 }; 182 183 static unsigned long exynos4x12_clk_save[] __initdata = { 184 E4X12_GATE_IP_IMAGE, 185 E4X12_GATE_IP_PERIR, 186 E4X12_SRC_CAM1, 187 E4X12_DIV_ISP, 188 E4X12_DIV_CAM1, 189 E4X12_MPLL_CON0, 190 PWR_CTRL1, 191 E4X12_PWR_CTRL2, 192 }; 193 194 static unsigned long exynos4_clk_pll_regs[] __initdata = { 195 EPLL_LOCK, 196 VPLL_LOCK, 197 EPLL_CON0, 198 EPLL_CON1, 199 EPLL_CON2, 200 VPLL_CON0, 201 VPLL_CON1, 202 VPLL_CON2, 203 }; 204 205 static unsigned long exynos4_clk_regs[] __initdata = { 206 SRC_LEFTBUS, 207 DIV_LEFTBUS, 208 GATE_IP_LEFTBUS, 209 SRC_RIGHTBUS, 210 DIV_RIGHTBUS, 211 GATE_IP_RIGHTBUS, 212 SRC_TOP0, 213 SRC_TOP1, 214 SRC_CAM, 215 SRC_TV, 216 SRC_MFC, 217 SRC_G3D, 218 SRC_LCD0, 219 SRC_MAUDIO, 220 SRC_FSYS, 221 SRC_PERIL0, 222 SRC_PERIL1, 223 SRC_MASK_TOP, 224 SRC_MASK_CAM, 225 SRC_MASK_TV, 226 SRC_MASK_LCD0, 227 SRC_MASK_MAUDIO, 228 SRC_MASK_FSYS, 229 SRC_MASK_PERIL0, 230 SRC_MASK_PERIL1, 231 DIV_TOP, 232 DIV_CAM, 233 DIV_TV, 234 DIV_MFC, 235 DIV_G3D, 236 DIV_IMAGE, 237 DIV_LCD0, 238 DIV_MAUDIO, 239 DIV_FSYS0, 240 DIV_FSYS1, 241 DIV_FSYS2, 242 DIV_FSYS3, 243 DIV_PERIL0, 244 DIV_PERIL1, 245 DIV_PERIL2, 246 DIV_PERIL3, 247 DIV_PERIL4, 248 DIV_PERIL5, 249 GATE_SCLK_CAM, 250 GATE_IP_CAM, 251 GATE_IP_TV, 252 GATE_IP_MFC, 253 GATE_IP_G3D, 254 GATE_IP_LCD0, 255 GATE_IP_FSYS, 256 GATE_IP_GPS, 257 GATE_IP_PERIL, 258 GATE_BLOCK, 259 SRC_MASK_DMC, 260 SRC_DMC, 261 DIV_DMC0, 262 DIV_DMC1, 263 GATE_IP_DMC, 264 APLL_CON0, 265 SRC_CPU, 266 DIV_CPU0, 267 DIV_CPU1, 268 GATE_SCLK_CPU, 269 GATE_IP_CPU, 270 CLKOUT_CMU_LEFTBUS, 271 CLKOUT_CMU_RIGHTBUS, 272 CLKOUT_CMU_TOP, 273 CLKOUT_CMU_DMC, 274 CLKOUT_CMU_CPU, 275 }; 276 277 static const struct samsung_clk_reg_dump src_mask_suspend[] = { 278 { .offset = SRC_MASK_TOP, .value = 0x00000001, }, 279 { .offset = SRC_MASK_CAM, .value = 0x11111111, }, 280 { .offset = SRC_MASK_TV, .value = 0x00000111, }, 281 { .offset = SRC_MASK_LCD0, .value = 0x00001111, }, 282 { .offset = SRC_MASK_MAUDIO, .value = 0x00000001, }, 283 { .offset = SRC_MASK_FSYS, .value = 0x01011111, }, 284 { .offset = SRC_MASK_PERIL0, .value = 0x01111111, }, 285 { .offset = SRC_MASK_PERIL1, .value = 0x01110111, }, 286 { .offset = SRC_MASK_DMC, .value = 0x00010000, }, 287 }; 288 289 static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { 290 { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, }, 291 }; 292 293 #define PLL_ENABLED (1 << 31) 294 #define PLL_LOCKED (1 << 29) 295 296 static void exynos4_clk_wait_for_pll(u32 reg) 297 { 298 u32 pll_con; 299 300 pll_con = readl(reg_base + reg); 301 if (!(pll_con & PLL_ENABLED)) 302 return; 303 304 while (!(pll_con & PLL_LOCKED)) { 305 cpu_relax(); 306 pll_con = readl(reg_base + reg); 307 } 308 } 309 310 static int exynos4_clk_suspend(void) 311 { 312 samsung_clk_save(reg_base, exynos4_save_common, 313 ARRAY_SIZE(exynos4_clk_regs)); 314 samsung_clk_save(reg_base, exynos4_save_pll, 315 ARRAY_SIZE(exynos4_clk_pll_regs)); 316 317 if (exynos4_soc == EXYNOS4210) { 318 samsung_clk_save(reg_base, exynos4_save_soc, 319 ARRAY_SIZE(exynos4210_clk_save)); 320 samsung_clk_restore(reg_base, src_mask_suspend_e4210, 321 ARRAY_SIZE(src_mask_suspend_e4210)); 322 } else { 323 samsung_clk_save(reg_base, exynos4_save_soc, 324 ARRAY_SIZE(exynos4x12_clk_save)); 325 } 326 327 samsung_clk_restore(reg_base, src_mask_suspend, 328 ARRAY_SIZE(src_mask_suspend)); 329 330 return 0; 331 } 332 333 static void exynos4_clk_resume(void) 334 { 335 samsung_clk_restore(reg_base, exynos4_save_pll, 336 ARRAY_SIZE(exynos4_clk_pll_regs)); 337 338 exynos4_clk_wait_for_pll(EPLL_CON0); 339 exynos4_clk_wait_for_pll(VPLL_CON0); 340 341 samsung_clk_restore(reg_base, exynos4_save_common, 342 ARRAY_SIZE(exynos4_clk_regs)); 343 344 if (exynos4_soc == EXYNOS4210) 345 samsung_clk_restore(reg_base, exynos4_save_soc, 346 ARRAY_SIZE(exynos4210_clk_save)); 347 else 348 samsung_clk_restore(reg_base, exynos4_save_soc, 349 ARRAY_SIZE(exynos4x12_clk_save)); 350 } 351 352 static struct syscore_ops exynos4_clk_syscore_ops = { 353 .suspend = exynos4_clk_suspend, 354 .resume = exynos4_clk_resume, 355 }; 356 357 static void __init exynos4_clk_sleep_init(void) 358 { 359 exynos4_save_common = samsung_clk_alloc_reg_dump(exynos4_clk_regs, 360 ARRAY_SIZE(exynos4_clk_regs)); 361 if (!exynos4_save_common) 362 goto err_warn; 363 364 if (exynos4_soc == EXYNOS4210) 365 exynos4_save_soc = samsung_clk_alloc_reg_dump( 366 exynos4210_clk_save, 367 ARRAY_SIZE(exynos4210_clk_save)); 368 else 369 exynos4_save_soc = samsung_clk_alloc_reg_dump( 370 exynos4x12_clk_save, 371 ARRAY_SIZE(exynos4x12_clk_save)); 372 if (!exynos4_save_soc) 373 goto err_common; 374 375 exynos4_save_pll = samsung_clk_alloc_reg_dump(exynos4_clk_pll_regs, 376 ARRAY_SIZE(exynos4_clk_pll_regs)); 377 if (!exynos4_save_pll) 378 goto err_soc; 379 380 register_syscore_ops(&exynos4_clk_syscore_ops); 381 return; 382 383 err_soc: 384 kfree(exynos4_save_soc); 385 err_common: 386 kfree(exynos4_save_common); 387 err_warn: 388 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 389 __func__); 390 } 391 #else 392 static void __init exynos4_clk_sleep_init(void) {} 393 #endif 394 395 /* list of all parent clock list */ 396 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 397 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; 398 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; 399 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", }; 400 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", }; 401 PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", }; 402 PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", }; 403 PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", }; 404 PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", }; 405 PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", }; 406 PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", }; 407 PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", 408 "spdif_extclk", }; 409 PNAME(mout_onenand_p) = {"aclk133", "aclk160", }; 410 PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", }; 411 412 /* Exynos 4210-specific parent groups */ 413 PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", }; 414 PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", }; 415 PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", }; 416 PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", 417 "sclk_usbphy0", "none", "sclk_hdmiphy", 418 "sclk_mpll", "sclk_epll", "sclk_vpll", }; 419 PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m", 420 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 421 "sclk_epll", "sclk_vpll" }; 422 PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m", 423 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 424 "sclk_epll", "sclk_vpll", }; 425 PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m", 426 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 427 "sclk_epll", "sclk_vpll", }; 428 PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", }; 429 PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", }; 430 PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", 431 "sclk_usbphy1", "sclk_hdmiphy", "none", 432 "sclk_epll", "sclk_vpll" }; 433 PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2", 434 "div_gdl", "div_gpl" }; 435 PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2", 436 "div_gdr", "div_gpr" }; 437 PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m", 438 "sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy", 439 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk", 440 "aclk160", "aclk133", "aclk200", "aclk100", 441 "sclk_mfc", "sclk_g3d", "sclk_g2d", 442 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l", 443 "s_rxbyteclkhs0_4l" }; 444 PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc", 445 "div_dphy", "none", "div_pwi" }; 446 PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2", 447 "none", "arm_clk_div_2", "div_corem0", 448 "div_corem1", "div_corem0", "div_atb", 449 "div_periph", "div_pclk_dbg", "div_hpm" }; 450 451 /* Exynos 4x12-specific parent groups */ 452 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", }; 453 PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", }; 454 PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", }; 455 PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", }; 456 PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", }; 457 PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", 458 "none", "sclk_hdmiphy", "mout_mpll_user_t", 459 "sclk_epll", "sclk_vpll", }; 460 PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m", 461 "sclk_usbphy0", "xxti", "xusbxti", 462 "mout_mpll_user_t", "sclk_epll", "sclk_vpll" }; 463 PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m", 464 "sclk_usbphy0", "xxti", "xusbxti", 465 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; 466 PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m", 467 "sclk_usbphy0", "xxti", "xusbxti", 468 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; 469 PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", }; 470 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", }; 471 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", }; 472 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; 473 PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", 474 "none", "sclk_hdmiphy", "sclk_mpll", 475 "sclk_epll", "sclk_vpll" }; 476 PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2", 477 "div_gdl", "div_gpl" }; 478 PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2", 479 "div_gdr", "div_gpr" }; 480 PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m", 481 "sclk_usbphy0", "none", "sclk_hdmiphy", 482 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk", 483 "aclk160", "aclk133", "aclk200", "aclk100", 484 "sclk_mfc", "sclk_g3d", "aclk400_mcuisp", 485 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l", 486 "s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0", 487 "rx_half_byte_clk_csis1", "div_jpeg", 488 "sclk_pwm_isp", "sclk_spi0_isp", 489 "sclk_spi1_isp", "sclk_uart_isp", 490 "sclk_mipihsi", "sclk_hdmi", "sclk_fimd0", 491 "sclk_pcm0" }; 492 PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk", 493 "div_dmc", "div_dphy", "fout_mpll_div_2", 494 "div_pwi", "none", "div_c2c", "div_c2c_aclk" }; 495 PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none", 496 "arm_clk_div_2", "div_corem0", "div_corem1", 497 "div_cores", "div_atb", "div_periph", 498 "div_pclk_dbg", "div_hpm" }; 499 500 /* fixed rate clocks generated outside the soc */ 501 static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { 502 FRATE(CLK_XXTI, "xxti", NULL, CLK_IS_ROOT, 0), 503 FRATE(CLK_XUSBXTI, "xusbxti", NULL, CLK_IS_ROOT, 0), 504 }; 505 506 /* fixed rate clocks generated inside the soc */ 507 static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { 508 FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), 509 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000), 510 FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 511 }; 512 513 static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { 514 FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), 515 }; 516 517 static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata = { 518 FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0), 519 FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0), 520 FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0), 521 FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0), 522 }; 523 524 static struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initdata = { 525 FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0), 526 }; 527 528 static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initdata = { 529 FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0), 530 FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0), 531 FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0), 532 FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0), 533 }; 534 535 /* list of mux clocks supported in all exynos4 soc's */ 536 static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 537 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 538 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0, 539 "mout_apll"), 540 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), 541 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), 542 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), 543 MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, 544 CLK_SET_RATE_PARENT, 0), 545 MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, 546 CLK_SET_RATE_PARENT, 0), 547 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), 548 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), 549 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1), 550 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), 551 552 MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1), 553 MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1), 554 }; 555 556 /* list of mux clocks supported in exynos4210 soc */ 557 static struct samsung_mux_clock exynos4210_mux_early[] __initdata = { 558 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), 559 }; 560 561 static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 562 MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1), 563 MUX(0, "mout_clkout_leftbus", clkout_left_p4210, 564 CLKOUT_CMU_LEFTBUS, 0, 5), 565 566 MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1), 567 MUX(0, "mout_clkout_rightbus", clkout_right_p4210, 568 CLKOUT_CMU_RIGHTBUS, 0, 5), 569 570 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), 571 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), 572 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), 573 MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), 574 MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), 575 MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), 576 MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), 577 MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), 578 MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), 579 MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), 580 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), 581 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), 582 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), 583 MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1), 584 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), 585 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), 586 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), 587 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), 588 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), 589 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), 590 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), 591 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), 592 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), 593 MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), 594 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, 595 CLK_SET_RATE_PARENT, 0), 596 MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), 597 MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), 598 MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), 599 MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), 600 MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), 601 MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), 602 MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), 603 MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), 604 MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), 605 MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), 606 MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), 607 MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), 608 MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), 609 MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), 610 MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), 611 MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), 612 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), 613 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), 614 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), 615 MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5), 616 617 MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4), 618 MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5), 619 620 MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5), 621 }; 622 623 /* list of mux clocks supported in exynos4x12 soc */ 624 static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 625 MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1), 626 MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1), 627 MUX(0, "mout_clkout_leftbus", clkout_left_p4x12, 628 CLKOUT_CMU_LEFTBUS, 0, 5), 629 630 MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1), 631 MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1), 632 MUX(0, "mout_clkout_rightbus", clkout_right_p4x12, 633 CLKOUT_CMU_RIGHTBUS, 0, 5), 634 635 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12, 636 SRC_CPU, 24, 1), 637 MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5), 638 639 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), 640 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), 641 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12, 642 SRC_TOP1, 12, 1), 643 MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, 644 SRC_TOP1, 16, 1), 645 MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), 646 MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp", 647 mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1), 648 MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), 649 MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), 650 MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), 651 MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), 652 MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), 653 MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), 654 MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), 655 MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), 656 MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), 657 MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), 658 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), 659 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1), 660 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), 661 MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1), 662 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), 663 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), 664 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), 665 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), 666 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), 667 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), 668 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), 669 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), 670 MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), 671 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, 672 CLK_SET_RATE_PARENT, 0), 673 MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), 674 MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), 675 MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), 676 MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), 677 MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), 678 MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), 679 MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), 680 MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), 681 MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), 682 MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), 683 MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), 684 MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), 685 MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), 686 MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), 687 MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), 688 MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), 689 MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), 690 MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), 691 MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), 692 MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), 693 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), 694 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), 695 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), 696 MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5), 697 698 MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1), 699 MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4), 700 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), 701 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), 702 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), 703 MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5), 704 }; 705 706 /* list of divider clocks supported in all exynos4 soc's */ 707 static struct samsung_div_clock exynos4_div_clks[] __initdata = { 708 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3), 709 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3), 710 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus", 711 CLKOUT_CMU_LEFTBUS, 8, 6), 712 713 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3), 714 DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3), 715 DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus", 716 CLKOUT_CMU_RIGHTBUS, 8, 6), 717 718 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3), 719 DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3), 720 DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3), 721 DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3), 722 DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3), 723 DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3), 724 DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3), 725 DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), 726 DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3), 727 DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6), 728 729 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), 730 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), 731 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), 732 DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), 733 DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), 734 DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), 735 DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), 736 DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), 737 DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), 738 DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4), 739 DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), 740 DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), 741 DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), 742 DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), 743 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 744 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 745 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 746 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 747 DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), 748 DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), 749 DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), 750 DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), 751 DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), 752 DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), 753 DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), 754 DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), 755 DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), 756 DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), 757 DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), 758 DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8, 759 CLK_SET_RATE_PARENT, 0), 760 DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 761 DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 762 DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), 763 DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), 764 DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), 765 DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), 766 DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), 767 DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), 768 DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), 769 DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), 770 DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), 771 DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), 772 DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), 773 DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 774 DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, 775 CLK_SET_RATE_PARENT, 0), 776 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, 777 CLK_SET_RATE_PARENT, 0), 778 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, 779 CLK_SET_RATE_PARENT, 0), 780 DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, 781 CLK_SET_RATE_PARENT, 0), 782 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, 783 CLK_SET_RATE_PARENT, 0), 784 DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6), 785 786 DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3), 787 DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3), 788 DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3), 789 DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3), 790 DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3), 791 DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3), 792 DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4), 793 DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6), 794 }; 795 796 /* list of divider clocks supported in exynos4210 soc */ 797 static struct samsung_div_clock exynos4210_div_clks[] __initdata = { 798 DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), 799 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), 800 DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), 801 DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), 802 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 803 DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, 804 CLK_SET_RATE_PARENT, 0), 805 }; 806 807 /* list of divider clocks supported in exynos4x12 soc */ 808 static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { 809 DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), 810 DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), 811 DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), 812 DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), 813 DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), 814 DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), 815 DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), 816 DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", 817 DIV_TOP, 24, 3), 818 DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), 819 DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), 820 DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), 821 DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), 822 DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), 823 DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), 824 DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, 825 CLK_GET_RATE_NOCACHE, 0), 826 DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, 827 CLK_GET_RATE_NOCACHE, 0), 828 DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), 829 DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 830 4, 3, CLK_GET_RATE_NOCACHE, 0), 831 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 832 8, 3, CLK_GET_RATE_NOCACHE, 0), 833 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 834 DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), 835 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), 836 }; 837 838 /* list of gate clocks supported in all exynos4 soc's */ 839 static struct samsung_gate_clock exynos4_gate_clks[] __initdata = { 840 /* 841 * After all Exynos4 based platforms are migrated to use device tree, 842 * the device name and clock alias names specified below for some 843 * of the clocks can be removed. 844 */ 845 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0), 846 GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0), 847 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), 848 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 849 0), 850 GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), 851 GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), 852 GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), 853 GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), 854 GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), 855 GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), 856 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 857 0), 858 GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), 859 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), 860 GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0), 861 GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0), 862 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), 863 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), 864 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), 865 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), 866 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), 867 GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0), 868 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), 869 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, 870 CLK_SET_RATE_PARENT, 0), 871 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, 872 CLK_SET_RATE_PARENT, 0), 873 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0", 874 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), 875 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, 876 CLK_SET_RATE_PARENT, 0), 877 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, 878 CLK_SET_RATE_PARENT, 0), 879 GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0), 880 GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), 881 GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), 882 GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0), 883 GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0), 884 GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0), 885 GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0, 886 CLK_SET_RATE_PARENT, 0), 887 GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4, 888 CLK_SET_RATE_PARENT, 0), 889 GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8, 890 CLK_SET_RATE_PARENT, 0), 891 GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12, 892 CLK_SET_RATE_PARENT, 0), 893 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24, 894 CLK_SET_RATE_PARENT, 0), 895 GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28, 896 CLK_SET_RATE_PARENT, 0), 897 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0, 898 CLK_SET_RATE_PARENT, 0), 899 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, 900 CLK_SET_RATE_PARENT, 0), 901 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4, 902 CLK_SET_RATE_PARENT, 0), 903 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8, 904 CLK_SET_RATE_PARENT, 0), 905 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12, 906 CLK_SET_RATE_PARENT, 0), 907 GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16, 908 CLK_SET_RATE_PARENT, 0), 909 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0, 910 CLK_SET_RATE_PARENT, 0), 911 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4, 912 CLK_SET_RATE_PARENT, 0), 913 GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8, 914 CLK_SET_RATE_PARENT, 0), 915 GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12, 916 CLK_SET_RATE_PARENT, 0), 917 GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16, 918 CLK_SET_RATE_PARENT, 0), 919 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, 920 CLK_SET_RATE_PARENT, 0), 921 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16, 922 CLK_SET_RATE_PARENT, 0), 923 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20, 924 CLK_SET_RATE_PARENT, 0), 925 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24, 926 CLK_SET_RATE_PARENT, 0), 927 GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0, 928 0, 0), 929 GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1, 930 0, 0), 931 GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2, 932 0, 0), 933 GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3, 934 0, 0), 935 GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4, 936 0, 0), 937 GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5, 938 0, 0), 939 GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7, 940 0, 0), 941 GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8, 942 0, 0), 943 GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9, 944 0, 0), 945 GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10, 946 0, 0), 947 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, 948 0, 0), 949 GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0), 950 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), 951 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), 952 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4, 953 0, 0), 954 GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0), 955 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0), 956 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1, 957 0, 0), 958 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2, 959 0, 0), 960 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0), 961 GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0), 962 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0, 963 0, 0), 964 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4, 965 0, 0), 966 GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0), 967 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0, 968 0, 0), 969 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1, 970 0, 0), 971 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5, 972 0, 0), 973 GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6, 974 0, 0), 975 GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7, 976 0, 0), 977 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8, 978 0, 0), 979 GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0), 980 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0, 981 0, 0), 982 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1, 983 0, 0), 984 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2, 985 0, 0), 986 GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3, 987 0, 0), 988 GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4, 989 0, 0), 990 GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6, 991 0, 0), 992 GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7, 993 0, 0), 994 GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8, 995 0, 0), 996 GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9, 997 0, 0), 998 GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10, 999 0, 0), 1000 GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11, 1001 0, 0), 1002 GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12, 1003 0, 0), 1004 GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13, 1005 0, 0), 1006 GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14, 1007 0, 0), 1008 GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16, 1009 0, 0), 1010 GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17, 1011 0, 0), 1012 GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18, 1013 0, 0), 1014 GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20, 1015 0, 0), 1016 GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21, 1017 0, 0), 1018 GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22, 1019 0, 0), 1020 GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23, 1021 0, 0), 1022 GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26, 1023 0, 0), 1024 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27, 1025 0, 0), 1026 GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0), 1027 GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0), 1028 GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0), 1029 GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0), 1030 1031 GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus", 1032 CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0), 1033 GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus", 1034 CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0), 1035 GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top", 1036 CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0), 1037 GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc", 1038 CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0), 1039 GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu", 1040 CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0), 1041 }; 1042 1043 /* list of gate clocks supported in exynos4210 soc */ 1044 static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 1045 GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), 1046 GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), 1047 GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), 1048 GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), 1049 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), 1050 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 1051 0), 1052 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0, 1053 0), 1054 GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0), 1055 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), 1056 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), 1057 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), 1058 GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), 1059 GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), 1060 GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), 1061 GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), 1062 GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 1063 CLK_IGNORE_UNUSED, 0), 1064 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 1065 0), 1066 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200", 1067 E4210_GATE_IP_IMAGE, 4, 0, 0), 1068 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1", 1069 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), 1070 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata", 1071 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 1072 GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), 1073 GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), 1074 GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15, 1075 0, 0), 1076 GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 1077 0, 0), 1078 GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 1079 0, 0), 1080 GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 1081 0, 0), 1082 GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 1083 0, 0), 1084 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, 1085 CLK_SET_RATE_PARENT, 0), 1086 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 1087 0), 1088 }; 1089 1090 /* list of gate clocks supported in exynos4x12 soc */ 1091 static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 1092 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), 1093 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), 1094 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), 1095 GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), 1096 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 1097 0), 1098 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0, 1099 0), 1100 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 1101 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), 1102 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 1103 CLK_IGNORE_UNUSED, 0), 1104 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 1105 0), 1106 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0", 1107 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), 1108 GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", 1109 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), 1110 GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi", 1111 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 1112 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200", 1113 E4X12_GATE_IP_IMAGE, 4, 0, 0), 1114 GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 1115 0, 0), 1116 GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 1117 0, 0), 1118 GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0), 1119 GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp", 1120 E4X12_GATE_IP_ISP, 0, 0, 0), 1121 GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre", 1122 E4X12_GATE_IP_ISP, 1, 0, 0), 1123 GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre", 1124 E4X12_GATE_IP_ISP, 2, 0, 0), 1125 GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp", 1126 E4X12_GATE_IP_ISP, 3, 0, 0), 1127 GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0), 1128 GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2, 1129 0, 0), 1130 GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 1131 0, 0), 1132 GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 1133 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1134 GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 1135 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1136 GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 1137 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1138 GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 1139 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1140 GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 1141 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1142 GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 1143 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1144 GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 1145 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1146 GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 1147 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1148 GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 1149 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1150 GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 1151 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1152 GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, 1153 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1154 GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, 1155 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1156 GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, 1157 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1158 GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, 1159 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1160 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, 1161 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1162 GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, 1163 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1164 GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, 1165 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1166 GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, 1167 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1168 GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, 1169 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1170 GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 1171 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1172 GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 1173 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1174 GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, 1175 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1176 GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, 1177 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1178 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, 1179 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1180 GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, 1181 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1182 GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 1183 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1184 GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), 1185 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0), 1186 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 1187 0), 1188 }; 1189 1190 static struct samsung_clock_alias exynos4_aliases[] __initdata = { 1191 ALIAS(CLK_MOUT_CORE, NULL, "moutcore"), 1192 ALIAS(CLK_ARM_CLK, NULL, "armclk"), 1193 ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"), 1194 }; 1195 1196 static struct samsung_clock_alias exynos4210_aliases[] __initdata = { 1197 ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"), 1198 }; 1199 1200 static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { 1201 ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"), 1202 }; 1203 1204 /* 1205 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit 1206 * resides in chipid register space, outside of the clock controller memory 1207 * mapped space. So to determine the parent of fin_pll clock, the chipid 1208 * controller is first remapped and the value of XOM[0] bit is read to 1209 * determine the parent clock. 1210 */ 1211 static unsigned long exynos4_get_xom(void) 1212 { 1213 unsigned long xom = 0; 1214 void __iomem *chipid_base; 1215 struct device_node *np; 1216 1217 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid"); 1218 if (np) { 1219 chipid_base = of_iomap(np, 0); 1220 1221 if (chipid_base) 1222 xom = readl(chipid_base + 8); 1223 1224 iounmap(chipid_base); 1225 } 1226 1227 return xom; 1228 } 1229 1230 static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) 1231 { 1232 struct samsung_fixed_rate_clock fclk; 1233 struct clk *clk; 1234 unsigned long finpll_f = 24000000; 1235 char *parent_name; 1236 unsigned int xom = exynos4_get_xom(); 1237 1238 parent_name = xom & 1 ? "xusbxti" : "xxti"; 1239 clk = clk_get(NULL, parent_name); 1240 if (IS_ERR(clk)) { 1241 pr_err("%s: failed to lookup parent clock %s, assuming " 1242 "fin_pll clock frequency is 24MHz\n", __func__, 1243 parent_name); 1244 } else { 1245 finpll_f = clk_get_rate(clk); 1246 } 1247 1248 fclk.id = CLK_FIN_PLL; 1249 fclk.name = "fin_pll"; 1250 fclk.parent_name = NULL; 1251 fclk.flags = CLK_IS_ROOT; 1252 fclk.fixed_rate = finpll_f; 1253 samsung_clk_register_fixed_rate(ctx, &fclk, 1); 1254 1255 } 1256 1257 static const struct of_device_id ext_clk_match[] __initconst = { 1258 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 1259 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, 1260 {}, 1261 }; 1262 1263 /* PLLs PMS values */ 1264 static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = { 1265 PLL_45XX_RATE(1200000000, 150, 3, 1, 28), 1266 PLL_45XX_RATE(1000000000, 250, 6, 1, 28), 1267 PLL_45XX_RATE( 800000000, 200, 6, 1, 28), 1268 PLL_45XX_RATE( 666857142, 389, 14, 1, 13), 1269 PLL_45XX_RATE( 600000000, 100, 4, 1, 13), 1270 PLL_45XX_RATE( 533000000, 533, 24, 1, 5), 1271 PLL_45XX_RATE( 500000000, 250, 6, 2, 28), 1272 PLL_45XX_RATE( 400000000, 200, 6, 2, 28), 1273 PLL_45XX_RATE( 200000000, 200, 6, 3, 28), 1274 { /* sentinel */ } 1275 }; 1276 1277 static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = { 1278 PLL_4600_RATE(192000000, 48, 3, 1, 0, 0), 1279 PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0), 1280 PLL_4600_RATE(180000000, 45, 3, 1, 0, 0), 1281 PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1), 1282 PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1), 1283 PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0), 1284 PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0), 1285 { /* sentinel */ } 1286 }; 1287 1288 static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = { 1289 PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0), 1290 PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1), 1291 PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1), 1292 PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0), 1293 PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0), 1294 { /* sentinel */ } 1295 }; 1296 1297 static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = { 1298 PLL_35XX_RATE(1500000000, 250, 4, 0), 1299 PLL_35XX_RATE(1400000000, 175, 3, 0), 1300 PLL_35XX_RATE(1300000000, 325, 6, 0), 1301 PLL_35XX_RATE(1200000000, 200, 4, 0), 1302 PLL_35XX_RATE(1100000000, 275, 6, 0), 1303 PLL_35XX_RATE(1000000000, 125, 3, 0), 1304 PLL_35XX_RATE( 900000000, 150, 4, 0), 1305 PLL_35XX_RATE( 800000000, 100, 3, 0), 1306 PLL_35XX_RATE( 700000000, 175, 3, 1), 1307 PLL_35XX_RATE( 600000000, 200, 4, 1), 1308 PLL_35XX_RATE( 500000000, 125, 3, 1), 1309 PLL_35XX_RATE( 400000000, 100, 3, 1), 1310 PLL_35XX_RATE( 300000000, 200, 4, 2), 1311 PLL_35XX_RATE( 200000000, 100, 3, 2), 1312 { /* sentinel */ } 1313 }; 1314 1315 static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = { 1316 PLL_36XX_RATE(192000000, 48, 3, 1, 0), 1317 PLL_36XX_RATE(180633605, 45, 3, 1, 10381), 1318 PLL_36XX_RATE(180000000, 45, 3, 1, 0), 1319 PLL_36XX_RATE( 73727996, 73, 3, 3, 47710), 1320 PLL_36XX_RATE( 67737602, 90, 4, 3, 20762), 1321 PLL_36XX_RATE( 49151992, 49, 3, 3, 9961), 1322 PLL_36XX_RATE( 45158401, 45, 3, 3, 10381), 1323 { /* sentinel */ } 1324 }; 1325 1326 static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = { 1327 PLL_36XX_RATE(533000000, 133, 3, 1, 16384), 1328 PLL_36XX_RATE(440000000, 110, 3, 1, 0), 1329 PLL_36XX_RATE(350000000, 175, 3, 2, 0), 1330 PLL_36XX_RATE(266000000, 133, 3, 2, 0), 1331 PLL_36XX_RATE(160000000, 160, 3, 3, 0), 1332 PLL_36XX_RATE(106031250, 53, 3, 2, 1024), 1333 PLL_36XX_RATE( 53015625, 53, 3, 3, 1024), 1334 { /* sentinel */ } 1335 }; 1336 1337 static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { 1338 [apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll", 1339 APLL_LOCK, APLL_CON0, "fout_apll", NULL), 1340 [mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 1341 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL), 1342 [epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 1343 EPLL_LOCK, EPLL_CON0, "fout_epll", NULL), 1344 [vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc", 1345 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL), 1346 }; 1347 1348 static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { 1349 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 1350 APLL_LOCK, APLL_CON0, NULL), 1351 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 1352 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL), 1353 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 1354 EPLL_LOCK, EPLL_CON0, NULL), 1355 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", 1356 VPLL_LOCK, VPLL_CON0, NULL), 1357 }; 1358 1359 static void __init exynos4x12_core_down_clock(void) 1360 { 1361 unsigned int tmp; 1362 1363 /* 1364 * Enable arm clock down (in idle) and set arm divider 1365 * ratios in WFI/WFE state. 1366 */ 1367 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) | 1368 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN | 1369 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE | 1370 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI); 1371 /* On Exynos4412 enable it also on core 2 and 3 */ 1372 if (num_possible_cpus() == 4) 1373 tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE | 1374 PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI; 1375 __raw_writel(tmp, reg_base + PWR_CTRL1); 1376 1377 /* 1378 * Disable the clock up feature in case it was enabled by bootloader. 1379 */ 1380 __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2); 1381 } 1382 1383 #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \ 1384 (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1385 ((periph) << 12) | ((corem1) << 8) | ((corem0) << 4)) 1386 #define E4210_CPU_DIV1(hpm, copy) \ 1387 (((hpm) << 4) | ((copy) << 0)) 1388 1389 static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { 1390 { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), }, 1391 { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), }, 1392 { 800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, 1393 { 500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, 1394 { 400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, 1395 { 200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), }, 1396 { 0 }, 1397 }; 1398 1399 /* register exynos4 clocks */ 1400 static void __init exynos4_clk_init(struct device_node *np, 1401 enum exynos4_soc soc) 1402 { 1403 struct samsung_clk_provider *ctx; 1404 exynos4_soc = soc; 1405 1406 reg_base = of_iomap(np, 0); 1407 if (!reg_base) 1408 panic("%s: failed to map registers\n", __func__); 1409 1410 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1411 if (!ctx) 1412 panic("%s: unable to allocate context.\n", __func__); 1413 1414 samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks, 1415 ARRAY_SIZE(exynos4_fixed_rate_ext_clks), 1416 ext_clk_match); 1417 1418 exynos4_clk_register_finpll(ctx); 1419 1420 if (exynos4_soc == EXYNOS4210) { 1421 samsung_clk_register_mux(ctx, exynos4210_mux_early, 1422 ARRAY_SIZE(exynos4210_mux_early)); 1423 1424 if (_get_rate("fin_pll") == 24000000) { 1425 exynos4210_plls[apll].rate_table = 1426 exynos4210_apll_rates; 1427 exynos4210_plls[epll].rate_table = 1428 exynos4210_epll_rates; 1429 } 1430 1431 if (_get_rate("mout_vpllsrc") == 24000000) 1432 exynos4210_plls[vpll].rate_table = 1433 exynos4210_vpll_rates; 1434 1435 samsung_clk_register_pll(ctx, exynos4210_plls, 1436 ARRAY_SIZE(exynos4210_plls), reg_base); 1437 } else { 1438 if (_get_rate("fin_pll") == 24000000) { 1439 exynos4x12_plls[apll].rate_table = 1440 exynos4x12_apll_rates; 1441 exynos4x12_plls[epll].rate_table = 1442 exynos4x12_epll_rates; 1443 exynos4x12_plls[vpll].rate_table = 1444 exynos4x12_vpll_rates; 1445 } 1446 1447 samsung_clk_register_pll(ctx, exynos4x12_plls, 1448 ARRAY_SIZE(exynos4x12_plls), reg_base); 1449 } 1450 1451 samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks, 1452 ARRAY_SIZE(exynos4_fixed_rate_clks)); 1453 samsung_clk_register_mux(ctx, exynos4_mux_clks, 1454 ARRAY_SIZE(exynos4_mux_clks)); 1455 samsung_clk_register_div(ctx, exynos4_div_clks, 1456 ARRAY_SIZE(exynos4_div_clks)); 1457 samsung_clk_register_gate(ctx, exynos4_gate_clks, 1458 ARRAY_SIZE(exynos4_gate_clks)); 1459 samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks, 1460 ARRAY_SIZE(exynos4_fixed_factor_clks)); 1461 1462 if (exynos4_soc == EXYNOS4210) { 1463 samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks, 1464 ARRAY_SIZE(exynos4210_fixed_rate_clks)); 1465 samsung_clk_register_mux(ctx, exynos4210_mux_clks, 1466 ARRAY_SIZE(exynos4210_mux_clks)); 1467 samsung_clk_register_div(ctx, exynos4210_div_clks, 1468 ARRAY_SIZE(exynos4210_div_clks)); 1469 samsung_clk_register_gate(ctx, exynos4210_gate_clks, 1470 ARRAY_SIZE(exynos4210_gate_clks)); 1471 samsung_clk_register_alias(ctx, exynos4210_aliases, 1472 ARRAY_SIZE(exynos4210_aliases)); 1473 samsung_clk_register_fixed_factor(ctx, 1474 exynos4210_fixed_factor_clks, 1475 ARRAY_SIZE(exynos4210_fixed_factor_clks)); 1476 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1477 mout_core_p4210[0], mout_core_p4210[1], 0x14200, 1478 e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), 1479 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); 1480 } else { 1481 samsung_clk_register_mux(ctx, exynos4x12_mux_clks, 1482 ARRAY_SIZE(exynos4x12_mux_clks)); 1483 samsung_clk_register_div(ctx, exynos4x12_div_clks, 1484 ARRAY_SIZE(exynos4x12_div_clks)); 1485 samsung_clk_register_gate(ctx, exynos4x12_gate_clks, 1486 ARRAY_SIZE(exynos4x12_gate_clks)); 1487 samsung_clk_register_alias(ctx, exynos4x12_aliases, 1488 ARRAY_SIZE(exynos4x12_aliases)); 1489 samsung_clk_register_fixed_factor(ctx, 1490 exynos4x12_fixed_factor_clks, 1491 ARRAY_SIZE(exynos4x12_fixed_factor_clks)); 1492 } 1493 1494 samsung_clk_register_alias(ctx, exynos4_aliases, 1495 ARRAY_SIZE(exynos4_aliases)); 1496 1497 if (soc == EXYNOS4X12) 1498 exynos4x12_core_down_clock(); 1499 exynos4_clk_sleep_init(); 1500 1501 samsung_clk_of_add_provider(np, ctx); 1502 1503 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" 1504 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", 1505 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", 1506 _get_rate("sclk_apll"), _get_rate("sclk_mpll"), 1507 _get_rate("sclk_epll"), _get_rate("sclk_vpll"), 1508 _get_rate("div_core2")); 1509 } 1510 1511 1512 static void __init exynos4210_clk_init(struct device_node *np) 1513 { 1514 exynos4_clk_init(np, EXYNOS4210); 1515 } 1516 CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init); 1517 1518 static void __init exynos4412_clk_init(struct device_node *np) 1519 { 1520 exynos4_clk_init(np, EXYNOS4X12); 1521 } 1522 CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init); 1523