1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2013 Linaro Ltd. 4 * Author: Thomas Abraham <thomas.ab@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for all Exynos4 SoCs. 11 */ 12 13 #include <dt-bindings/clock/exynos4.h> 14 #include <linux/clk.h> 15 #include <linux/clkdev.h> 16 #include <linux/clk-provider.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/syscore_ops.h> 20 21 #include "clk.h" 22 23 /* Exynos4 clock controller register offsets */ 24 #define SRC_LEFTBUS 0x4200 25 #define DIV_LEFTBUS 0x4500 26 #define GATE_IP_LEFTBUS 0x4800 27 #define E4X12_GATE_IP_IMAGE 0x4930 28 #define SRC_RIGHTBUS 0x8200 29 #define DIV_RIGHTBUS 0x8500 30 #define GATE_IP_RIGHTBUS 0x8800 31 #define E4X12_GATE_IP_PERIR 0x8960 32 #define EPLL_LOCK 0xc010 33 #define VPLL_LOCK 0xc020 34 #define EPLL_CON0 0xc110 35 #define EPLL_CON1 0xc114 36 #define EPLL_CON2 0xc118 37 #define VPLL_CON0 0xc120 38 #define VPLL_CON1 0xc124 39 #define VPLL_CON2 0xc128 40 #define SRC_TOP0 0xc210 41 #define SRC_TOP1 0xc214 42 #define SRC_CAM 0xc220 43 #define SRC_TV 0xc224 44 #define SRC_MFC 0xc228 45 #define SRC_G3D 0xc22c 46 #define E4210_SRC_IMAGE 0xc230 47 #define SRC_LCD0 0xc234 48 #define E4210_SRC_LCD1 0xc238 49 #define E4X12_SRC_ISP 0xc238 50 #define SRC_MAUDIO 0xc23c 51 #define SRC_FSYS 0xc240 52 #define SRC_PERIL0 0xc250 53 #define SRC_PERIL1 0xc254 54 #define E4X12_SRC_CAM1 0xc258 55 #define SRC_MASK_TOP 0xc310 56 #define SRC_MASK_CAM 0xc320 57 #define SRC_MASK_TV 0xc324 58 #define SRC_MASK_LCD0 0xc334 59 #define E4210_SRC_MASK_LCD1 0xc338 60 #define E4X12_SRC_MASK_ISP 0xc338 61 #define SRC_MASK_MAUDIO 0xc33c 62 #define SRC_MASK_FSYS 0xc340 63 #define SRC_MASK_PERIL0 0xc350 64 #define SRC_MASK_PERIL1 0xc354 65 #define DIV_TOP 0xc510 66 #define DIV_CAM 0xc520 67 #define DIV_TV 0xc524 68 #define DIV_MFC 0xc528 69 #define DIV_G3D 0xc52c 70 #define DIV_IMAGE 0xc530 71 #define DIV_LCD0 0xc534 72 #define E4210_DIV_LCD1 0xc538 73 #define E4X12_DIV_ISP 0xc538 74 #define DIV_MAUDIO 0xc53c 75 #define DIV_FSYS0 0xc540 76 #define DIV_FSYS1 0xc544 77 #define DIV_FSYS2 0xc548 78 #define DIV_FSYS3 0xc54c 79 #define DIV_PERIL0 0xc550 80 #define DIV_PERIL1 0xc554 81 #define DIV_PERIL2 0xc558 82 #define DIV_PERIL3 0xc55c 83 #define DIV_PERIL4 0xc560 84 #define DIV_PERIL5 0xc564 85 #define E4X12_DIV_CAM1 0xc568 86 #define GATE_SCLK_CAM 0xc820 87 #define GATE_IP_CAM 0xc920 88 #define GATE_IP_TV 0xc924 89 #define GATE_IP_MFC 0xc928 90 #define GATE_IP_G3D 0xc92c 91 #define E4210_GATE_IP_IMAGE 0xc930 92 #define GATE_IP_LCD0 0xc934 93 #define E4210_GATE_IP_LCD1 0xc938 94 #define E4X12_GATE_IP_ISP 0xc938 95 #define E4X12_GATE_IP_MAUDIO 0xc93c 96 #define GATE_IP_FSYS 0xc940 97 #define GATE_IP_GPS 0xc94c 98 #define GATE_IP_PERIL 0xc950 99 #define E4210_GATE_IP_PERIR 0xc960 100 #define GATE_BLOCK 0xc970 101 #define E4X12_MPLL_LOCK 0x10008 102 #define E4X12_MPLL_CON0 0x10108 103 #define SRC_DMC 0x10200 104 #define SRC_MASK_DMC 0x10300 105 #define DIV_DMC0 0x10500 106 #define DIV_DMC1 0x10504 107 #define GATE_IP_DMC 0x10900 108 #define APLL_LOCK 0x14000 109 #define E4210_MPLL_LOCK 0x14008 110 #define APLL_CON0 0x14100 111 #define E4210_MPLL_CON0 0x14108 112 #define SRC_CPU 0x14200 113 #define DIV_CPU0 0x14500 114 #define DIV_CPU1 0x14504 115 #define GATE_SCLK_CPU 0x14800 116 #define GATE_IP_CPU 0x14900 117 #define E4X12_DIV_ISP0 0x18300 118 #define E4X12_DIV_ISP1 0x18304 119 #define E4X12_GATE_ISP0 0x18800 120 #define E4X12_GATE_ISP1 0x18804 121 122 /* the exynos4 soc type */ 123 enum exynos4_soc { 124 EXYNOS4210, 125 EXYNOS4X12, 126 }; 127 128 /* list of PLLs to be registered */ 129 enum exynos4_plls { 130 apll, mpll, epll, vpll, 131 nr_plls /* number of PLLs */ 132 }; 133 134 static void __iomem *reg_base; 135 static enum exynos4_soc exynos4_soc; 136 137 /* 138 * Support for CMU save/restore across system suspends 139 */ 140 #ifdef CONFIG_PM_SLEEP 141 static struct samsung_clk_reg_dump *exynos4_save_common; 142 static struct samsung_clk_reg_dump *exynos4_save_soc; 143 static struct samsung_clk_reg_dump *exynos4_save_pll; 144 145 /* 146 * list of controller registers to be saved and restored during a 147 * suspend/resume cycle. 148 */ 149 static unsigned long exynos4210_clk_save[] __initdata = { 150 E4210_SRC_IMAGE, 151 E4210_SRC_LCD1, 152 E4210_SRC_MASK_LCD1, 153 E4210_DIV_LCD1, 154 E4210_GATE_IP_IMAGE, 155 E4210_GATE_IP_LCD1, 156 E4210_GATE_IP_PERIR, 157 E4210_MPLL_CON0, 158 }; 159 160 static unsigned long exynos4x12_clk_save[] __initdata = { 161 E4X12_GATE_IP_IMAGE, 162 E4X12_GATE_IP_PERIR, 163 E4X12_SRC_CAM1, 164 E4X12_DIV_ISP, 165 E4X12_DIV_CAM1, 166 E4X12_MPLL_CON0, 167 }; 168 169 static unsigned long exynos4_clk_pll_regs[] __initdata = { 170 EPLL_LOCK, 171 VPLL_LOCK, 172 EPLL_CON0, 173 EPLL_CON1, 174 EPLL_CON2, 175 VPLL_CON0, 176 VPLL_CON1, 177 VPLL_CON2, 178 }; 179 180 static unsigned long exynos4_clk_regs[] __initdata = { 181 SRC_LEFTBUS, 182 DIV_LEFTBUS, 183 GATE_IP_LEFTBUS, 184 SRC_RIGHTBUS, 185 DIV_RIGHTBUS, 186 GATE_IP_RIGHTBUS, 187 SRC_TOP0, 188 SRC_TOP1, 189 SRC_CAM, 190 SRC_TV, 191 SRC_MFC, 192 SRC_G3D, 193 SRC_LCD0, 194 SRC_MAUDIO, 195 SRC_FSYS, 196 SRC_PERIL0, 197 SRC_PERIL1, 198 SRC_MASK_TOP, 199 SRC_MASK_CAM, 200 SRC_MASK_TV, 201 SRC_MASK_LCD0, 202 SRC_MASK_MAUDIO, 203 SRC_MASK_FSYS, 204 SRC_MASK_PERIL0, 205 SRC_MASK_PERIL1, 206 DIV_TOP, 207 DIV_CAM, 208 DIV_TV, 209 DIV_MFC, 210 DIV_G3D, 211 DIV_IMAGE, 212 DIV_LCD0, 213 DIV_MAUDIO, 214 DIV_FSYS0, 215 DIV_FSYS1, 216 DIV_FSYS2, 217 DIV_FSYS3, 218 DIV_PERIL0, 219 DIV_PERIL1, 220 DIV_PERIL2, 221 DIV_PERIL3, 222 DIV_PERIL4, 223 DIV_PERIL5, 224 GATE_SCLK_CAM, 225 GATE_IP_CAM, 226 GATE_IP_TV, 227 GATE_IP_MFC, 228 GATE_IP_G3D, 229 GATE_IP_LCD0, 230 GATE_IP_FSYS, 231 GATE_IP_GPS, 232 GATE_IP_PERIL, 233 GATE_BLOCK, 234 SRC_MASK_DMC, 235 SRC_DMC, 236 DIV_DMC0, 237 DIV_DMC1, 238 GATE_IP_DMC, 239 APLL_CON0, 240 SRC_CPU, 241 DIV_CPU0, 242 DIV_CPU1, 243 GATE_SCLK_CPU, 244 GATE_IP_CPU, 245 }; 246 247 static const struct samsung_clk_reg_dump src_mask_suspend[] = { 248 { .offset = SRC_MASK_TOP, .value = 0x00000001, }, 249 { .offset = SRC_MASK_CAM, .value = 0x11111111, }, 250 { .offset = SRC_MASK_TV, .value = 0x00000111, }, 251 { .offset = SRC_MASK_LCD0, .value = 0x00001111, }, 252 { .offset = SRC_MASK_MAUDIO, .value = 0x00000001, }, 253 { .offset = SRC_MASK_FSYS, .value = 0x01011111, }, 254 { .offset = SRC_MASK_PERIL0, .value = 0x01111111, }, 255 { .offset = SRC_MASK_PERIL1, .value = 0x01110111, }, 256 { .offset = SRC_MASK_DMC, .value = 0x00010000, }, 257 }; 258 259 static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { 260 { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, }, 261 }; 262 263 #define PLL_ENABLED (1 << 31) 264 #define PLL_LOCKED (1 << 29) 265 266 static void exynos4_clk_wait_for_pll(u32 reg) 267 { 268 u32 pll_con; 269 270 pll_con = readl(reg_base + reg); 271 if (!(pll_con & PLL_ENABLED)) 272 return; 273 274 while (!(pll_con & PLL_LOCKED)) { 275 cpu_relax(); 276 pll_con = readl(reg_base + reg); 277 } 278 } 279 280 static int exynos4_clk_suspend(void) 281 { 282 samsung_clk_save(reg_base, exynos4_save_common, 283 ARRAY_SIZE(exynos4_clk_regs)); 284 samsung_clk_save(reg_base, exynos4_save_pll, 285 ARRAY_SIZE(exynos4_clk_pll_regs)); 286 287 if (exynos4_soc == EXYNOS4210) { 288 samsung_clk_save(reg_base, exynos4_save_soc, 289 ARRAY_SIZE(exynos4210_clk_save)); 290 samsung_clk_restore(reg_base, src_mask_suspend_e4210, 291 ARRAY_SIZE(src_mask_suspend_e4210)); 292 } else { 293 samsung_clk_save(reg_base, exynos4_save_soc, 294 ARRAY_SIZE(exynos4x12_clk_save)); 295 } 296 297 samsung_clk_restore(reg_base, src_mask_suspend, 298 ARRAY_SIZE(src_mask_suspend)); 299 300 return 0; 301 } 302 303 static void exynos4_clk_resume(void) 304 { 305 samsung_clk_restore(reg_base, exynos4_save_pll, 306 ARRAY_SIZE(exynos4_clk_pll_regs)); 307 308 exynos4_clk_wait_for_pll(EPLL_CON0); 309 exynos4_clk_wait_for_pll(VPLL_CON0); 310 311 samsung_clk_restore(reg_base, exynos4_save_common, 312 ARRAY_SIZE(exynos4_clk_regs)); 313 314 if (exynos4_soc == EXYNOS4210) 315 samsung_clk_restore(reg_base, exynos4_save_soc, 316 ARRAY_SIZE(exynos4210_clk_save)); 317 else 318 samsung_clk_restore(reg_base, exynos4_save_soc, 319 ARRAY_SIZE(exynos4x12_clk_save)); 320 } 321 322 static struct syscore_ops exynos4_clk_syscore_ops = { 323 .suspend = exynos4_clk_suspend, 324 .resume = exynos4_clk_resume, 325 }; 326 327 static void exynos4_clk_sleep_init(void) 328 { 329 exynos4_save_common = samsung_clk_alloc_reg_dump(exynos4_clk_regs, 330 ARRAY_SIZE(exynos4_clk_regs)); 331 if (!exynos4_save_common) 332 goto err_warn; 333 334 if (exynos4_soc == EXYNOS4210) 335 exynos4_save_soc = samsung_clk_alloc_reg_dump( 336 exynos4210_clk_save, 337 ARRAY_SIZE(exynos4210_clk_save)); 338 else 339 exynos4_save_soc = samsung_clk_alloc_reg_dump( 340 exynos4x12_clk_save, 341 ARRAY_SIZE(exynos4x12_clk_save)); 342 if (!exynos4_save_soc) 343 goto err_common; 344 345 exynos4_save_pll = samsung_clk_alloc_reg_dump(exynos4_clk_pll_regs, 346 ARRAY_SIZE(exynos4_clk_pll_regs)); 347 if (!exynos4_save_pll) 348 goto err_soc; 349 350 register_syscore_ops(&exynos4_clk_syscore_ops); 351 return; 352 353 err_soc: 354 kfree(exynos4_save_soc); 355 err_common: 356 kfree(exynos4_save_common); 357 err_warn: 358 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 359 __func__); 360 } 361 #else 362 static void exynos4_clk_sleep_init(void) {} 363 #endif 364 365 /* list of all parent clock list */ 366 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 367 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; 368 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; 369 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", }; 370 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", }; 371 PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", }; 372 PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", }; 373 PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", }; 374 PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", }; 375 PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", }; 376 PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", }; 377 PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", 378 "spdif_extclk", }; 379 PNAME(mout_onenand_p) = {"aclk133", "aclk160", }; 380 PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", }; 381 382 /* Exynos 4210-specific parent groups */ 383 PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", }; 384 PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", }; 385 PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", }; 386 PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", 387 "sclk_usbphy0", "none", "sclk_hdmiphy", 388 "sclk_mpll", "sclk_epll", "sclk_vpll", }; 389 PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m", 390 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 391 "sclk_epll", "sclk_vpll" }; 392 PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m", 393 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 394 "sclk_epll", "sclk_vpll", }; 395 PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m", 396 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 397 "sclk_epll", "sclk_vpll", }; 398 PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", }; 399 PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", }; 400 401 /* Exynos 4x12-specific parent groups */ 402 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", }; 403 PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", }; 404 PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", }; 405 PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", 406 "none", "sclk_hdmiphy", "mout_mpll_user_t", 407 "sclk_epll", "sclk_vpll", }; 408 PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m", 409 "sclk_usbphy0", "xxti", "xusbxti", 410 "mout_mpll_user_t", "sclk_epll", "sclk_vpll" }; 411 PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m", 412 "sclk_usbphy0", "xxti", "xusbxti", 413 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; 414 PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m", 415 "sclk_usbphy0", "xxti", "xusbxti", 416 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; 417 PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", }; 418 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", }; 419 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", }; 420 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; 421 422 /* fixed rate clocks generated outside the soc */ 423 static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { 424 FRATE(CLK_XXTI, "xxti", NULL, CLK_IS_ROOT, 0), 425 FRATE(CLK_XUSBXTI, "xusbxti", NULL, CLK_IS_ROOT, 0), 426 }; 427 428 /* fixed rate clocks generated inside the soc */ 429 static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { 430 FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), 431 FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 432 FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 433 }; 434 435 static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { 436 FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), 437 }; 438 439 /* list of mux clocks supported in all exynos4 soc's */ 440 static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 441 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 442 CLK_SET_RATE_PARENT, 0, "mout_apll"), 443 MUX(0, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), 444 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), 445 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), 446 MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, 447 CLK_SET_RATE_PARENT, 0), 448 MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, 449 CLK_SET_RATE_PARENT, 0), 450 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), 451 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), 452 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1), 453 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), 454 }; 455 456 /* list of mux clocks supported in exynos4210 soc */ 457 static struct samsung_mux_clock exynos4210_mux_early[] __initdata = { 458 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), 459 }; 460 461 static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 462 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), 463 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), 464 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), 465 MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), 466 MUX(0, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), 467 MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), 468 MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), 469 MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), 470 MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), 471 MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), 472 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), 473 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), 474 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), 475 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), 476 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), 477 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), 478 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), 479 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), 480 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), 481 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), 482 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), 483 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), 484 MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), 485 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, 486 CLK_SET_RATE_PARENT, 0), 487 MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), 488 MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), 489 MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), 490 MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), 491 MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), 492 MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), 493 MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), 494 MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), 495 MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), 496 MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), 497 MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), 498 MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), 499 MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), 500 MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), 501 MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), 502 MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), 503 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), 504 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), 505 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), 506 }; 507 508 /* list of mux clocks supported in exynos4x12 soc */ 509 static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 510 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12, 511 SRC_CPU, 24, 1), 512 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), 513 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), 514 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12, 515 SRC_TOP1, 12, 1), 516 MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, 517 SRC_TOP1, 16, 1), 518 MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), 519 MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp", 520 mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1), 521 MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), 522 MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), 523 MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), 524 MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), 525 MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), 526 MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), 527 MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), 528 MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), 529 MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), 530 MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), 531 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), 532 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1), 533 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), 534 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), 535 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), 536 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), 537 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), 538 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), 539 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), 540 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), 541 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), 542 MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), 543 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, 544 CLK_SET_RATE_PARENT, 0), 545 MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), 546 MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), 547 MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), 548 MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), 549 MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), 550 MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), 551 MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), 552 MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), 553 MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), 554 MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), 555 MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), 556 MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), 557 MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), 558 MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), 559 MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), 560 MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), 561 MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), 562 MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), 563 MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), 564 MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), 565 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), 566 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), 567 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), 568 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), 569 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), 570 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), 571 }; 572 573 /* list of divider clocks supported in all exynos4 soc's */ 574 static struct samsung_div_clock exynos4_div_clks[] __initdata = { 575 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3), 576 DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3), 577 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), 578 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), 579 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), 580 DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), 581 DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), 582 DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), 583 DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), 584 DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), 585 DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), 586 DIV_F(0, "div_g3d", "mout_g3d", DIV_G3D, 0, 4, 587 CLK_SET_RATE_PARENT, 0), 588 DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), 589 DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), 590 DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), 591 DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), 592 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 593 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 594 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 595 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 596 DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), 597 DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), 598 DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), 599 DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), 600 DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), 601 DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), 602 DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), 603 DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), 604 DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), 605 DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), 606 DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), 607 DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8, 608 CLK_SET_RATE_PARENT, 0), 609 DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 610 DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 611 DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), 612 DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), 613 DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), 614 DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), 615 DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), 616 DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), 617 DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), 618 DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), 619 DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), 620 DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), 621 DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), 622 DIV(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3), 623 DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 624 DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, 625 CLK_SET_RATE_PARENT, 0), 626 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, 627 CLK_SET_RATE_PARENT, 0), 628 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, 629 CLK_SET_RATE_PARENT, 0), 630 DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, 631 CLK_SET_RATE_PARENT, 0), 632 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, 633 CLK_SET_RATE_PARENT, 0), 634 }; 635 636 /* list of divider clocks supported in exynos4210 soc */ 637 static struct samsung_div_clock exynos4210_div_clks[] __initdata = { 638 DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), 639 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), 640 DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), 641 DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), 642 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 643 DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, 644 CLK_SET_RATE_PARENT, 0), 645 }; 646 647 /* list of divider clocks supported in exynos4x12 soc */ 648 static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { 649 DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), 650 DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), 651 DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), 652 DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), 653 DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), 654 DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), 655 DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), 656 DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", 657 DIV_TOP, 24, 3), 658 DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), 659 DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), 660 DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), 661 DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), 662 DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), 663 DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), 664 DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, 665 CLK_GET_RATE_NOCACHE, 0), 666 DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, 667 CLK_GET_RATE_NOCACHE, 0), 668 DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), 669 DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 670 4, 3, CLK_GET_RATE_NOCACHE, 0), 671 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 672 8, 3, CLK_GET_RATE_NOCACHE, 0), 673 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 674 }; 675 676 /* list of gate clocks supported in all exynos4 soc's */ 677 static struct samsung_gate_clock exynos4_gate_clks[] __initdata = { 678 /* 679 * After all Exynos4 based platforms are migrated to use device tree, 680 * the device name and clock alias names specified below for some 681 * of the clocks can be removed. 682 */ 683 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), 684 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 685 0), 686 GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), 687 GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), 688 GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), 689 GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), 690 GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), 691 GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), 692 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 693 0), 694 GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), 695 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), 696 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, 697 CLK_SET_RATE_PARENT, 0), 698 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), 699 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), 700 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), 701 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), 702 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), 703 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), 704 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, 705 CLK_SET_RATE_PARENT, 0), 706 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, 707 CLK_SET_RATE_PARENT, 0), 708 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0", 709 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), 710 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, 711 CLK_SET_RATE_PARENT, 0), 712 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, 713 CLK_SET_RATE_PARENT, 0), 714 GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0), 715 GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), 716 GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), 717 GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0), 718 GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0), 719 GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0), 720 GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0, 721 CLK_SET_RATE_PARENT, 0), 722 GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4, 723 CLK_SET_RATE_PARENT, 0), 724 GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8, 725 CLK_SET_RATE_PARENT, 0), 726 GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12, 727 CLK_SET_RATE_PARENT, 0), 728 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24, 729 CLK_SET_RATE_PARENT, 0), 730 GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28, 731 CLK_SET_RATE_PARENT, 0), 732 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0, 733 CLK_SET_RATE_PARENT, 0), 734 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, 735 CLK_SET_RATE_PARENT, 0), 736 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4, 737 CLK_SET_RATE_PARENT, 0), 738 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8, 739 CLK_SET_RATE_PARENT, 0), 740 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12, 741 CLK_SET_RATE_PARENT, 0), 742 GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16, 743 CLK_SET_RATE_PARENT, 0), 744 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0, 745 CLK_SET_RATE_PARENT, 0), 746 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4, 747 CLK_SET_RATE_PARENT, 0), 748 GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8, 749 CLK_SET_RATE_PARENT, 0), 750 GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12, 751 CLK_SET_RATE_PARENT, 0), 752 GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16, 753 CLK_SET_RATE_PARENT, 0), 754 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, 755 CLK_SET_RATE_PARENT, 0), 756 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16, 757 CLK_SET_RATE_PARENT, 0), 758 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20, 759 CLK_SET_RATE_PARENT, 0), 760 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24, 761 CLK_SET_RATE_PARENT, 0), 762 GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0, 763 0, 0), 764 GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1, 765 0, 0), 766 GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2, 767 0, 0), 768 GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3, 769 0, 0), 770 GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4, 771 0, 0), 772 GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5, 773 0, 0), 774 GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7, 775 0, 0), 776 GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8, 777 0, 0), 778 GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9, 779 0, 0), 780 GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10, 781 0, 0), 782 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, 783 0, 0), 784 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), 785 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), 786 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4, 787 0, 0), 788 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0), 789 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1, 790 0, 0), 791 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2, 792 0, 0), 793 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0, 794 0, 0), 795 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4, 796 0, 0), 797 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0, 798 0, 0), 799 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1, 800 0, 0), 801 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5, 802 0, 0), 803 GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6, 804 0, 0), 805 GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7, 806 0, 0), 807 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8, 808 0, 0), 809 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0, 810 0, 0), 811 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1, 812 0, 0), 813 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2, 814 0, 0), 815 GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3, 816 0, 0), 817 GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4, 818 0, 0), 819 GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6, 820 0, 0), 821 GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7, 822 0, 0), 823 GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8, 824 0, 0), 825 GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9, 826 0, 0), 827 GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10, 828 0, 0), 829 GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11, 830 0, 0), 831 GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12, 832 0, 0), 833 GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13, 834 0, 0), 835 GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14, 836 0, 0), 837 GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16, 838 0, 0), 839 GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17, 840 0, 0), 841 GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18, 842 0, 0), 843 GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20, 844 0, 0), 845 GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21, 846 0, 0), 847 GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22, 848 0, 0), 849 GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23, 850 0, 0), 851 GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26, 852 0, 0), 853 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27, 854 0, 0), 855 }; 856 857 /* list of gate clocks supported in exynos4210 soc */ 858 static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 859 GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), 860 GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), 861 GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), 862 GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), 863 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), 864 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 865 0), 866 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), 867 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), 868 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), 869 GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), 870 GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), 871 GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), 872 GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), 873 GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 874 CLK_IGNORE_UNUSED, 0), 875 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 876 0), 877 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200", 878 E4210_GATE_IP_IMAGE, 4, 0, 0), 879 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1", 880 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), 881 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata", 882 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 883 GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), 884 GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), 885 GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15, 886 0, 0), 887 GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 888 0, 0), 889 GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 890 0, 0), 891 GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 892 0, 0), 893 GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 894 0, 0), 895 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, 896 CLK_SET_RATE_PARENT, 0), 897 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 898 0), 899 }; 900 901 /* list of gate clocks supported in exynos4x12 soc */ 902 static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 903 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), 904 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), 905 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), 906 GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), 907 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 908 0), 909 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 910 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), 911 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 912 CLK_IGNORE_UNUSED, 0), 913 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 914 0), 915 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0", 916 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), 917 GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", 918 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), 919 GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi", 920 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 921 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200", 922 E4X12_GATE_IP_IMAGE, 4, 0, 0), 923 GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 924 0, 0), 925 GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 926 0, 0), 927 GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0), 928 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "div_pwm_isp", 929 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0), 930 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp_pre", 931 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0), 932 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp_pre", 933 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0), 934 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp", 935 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0), 936 GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "sclk_pwm_isp", 937 E4X12_GATE_IP_ISP, 0, 0, 0), 938 GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "sclk_spi0_isp", 939 E4X12_GATE_IP_ISP, 1, 0, 0), 940 GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "sclk_spi1_isp", 941 E4X12_GATE_IP_ISP, 2, 0, 0), 942 GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "sclk_uart_isp", 943 E4X12_GATE_IP_ISP, 3, 0, 0), 944 GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0), 945 GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2, 946 0, 0), 947 GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 948 0, 0), 949 GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 950 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 951 GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 952 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 953 GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 954 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 955 GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 956 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 957 GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 958 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 959 GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 960 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 961 GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 962 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 963 GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 964 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 965 GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 966 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 967 GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 968 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 969 GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, 970 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 971 GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, 972 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 973 GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, 974 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 975 GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, 976 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 977 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, 978 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 979 GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, 980 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 981 GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, 982 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 983 GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, 984 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 985 GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, 986 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 987 GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 988 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 989 GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 990 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 991 GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, 992 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 993 GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, 994 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 995 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, 996 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 997 GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, 998 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 999 GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 1000 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1001 GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), 1002 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 1003 0), 1004 }; 1005 1006 static struct samsung_clock_alias exynos4_aliases[] __initdata = { 1007 ALIAS(CLK_MOUT_CORE, NULL, "moutcore"), 1008 ALIAS(CLK_ARM_CLK, NULL, "armclk"), 1009 ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"), 1010 }; 1011 1012 static struct samsung_clock_alias exynos4210_aliases[] __initdata = { 1013 ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"), 1014 }; 1015 1016 static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { 1017 ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"), 1018 }; 1019 1020 /* 1021 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit 1022 * resides in chipid register space, outside of the clock controller memory 1023 * mapped space. So to determine the parent of fin_pll clock, the chipid 1024 * controller is first remapped and the value of XOM[0] bit is read to 1025 * determine the parent clock. 1026 */ 1027 static unsigned long exynos4_get_xom(void) 1028 { 1029 unsigned long xom = 0; 1030 void __iomem *chipid_base; 1031 struct device_node *np; 1032 1033 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid"); 1034 if (np) { 1035 chipid_base = of_iomap(np, 0); 1036 1037 if (chipid_base) 1038 xom = readl(chipid_base + 8); 1039 1040 iounmap(chipid_base); 1041 } 1042 1043 return xom; 1044 } 1045 1046 static void __init exynos4_clk_register_finpll(void) 1047 { 1048 struct samsung_fixed_rate_clock fclk; 1049 struct clk *clk; 1050 unsigned long finpll_f = 24000000; 1051 char *parent_name; 1052 unsigned int xom = exynos4_get_xom(); 1053 1054 parent_name = xom & 1 ? "xusbxti" : "xxti"; 1055 clk = clk_get(NULL, parent_name); 1056 if (IS_ERR(clk)) { 1057 pr_err("%s: failed to lookup parent clock %s, assuming " 1058 "fin_pll clock frequency is 24MHz\n", __func__, 1059 parent_name); 1060 } else { 1061 finpll_f = clk_get_rate(clk); 1062 } 1063 1064 fclk.id = CLK_FIN_PLL; 1065 fclk.name = "fin_pll"; 1066 fclk.parent_name = NULL; 1067 fclk.flags = CLK_IS_ROOT; 1068 fclk.fixed_rate = finpll_f; 1069 samsung_clk_register_fixed_rate(&fclk, 1); 1070 1071 } 1072 1073 static struct of_device_id ext_clk_match[] __initdata = { 1074 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 1075 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, 1076 {}, 1077 }; 1078 1079 /* PLLs PMS values */ 1080 static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = { 1081 PLL_45XX_RATE(1200000000, 150, 3, 1, 28), 1082 PLL_45XX_RATE(1000000000, 250, 6, 1, 28), 1083 PLL_45XX_RATE( 800000000, 200, 6, 1, 28), 1084 PLL_45XX_RATE( 666857142, 389, 14, 1, 13), 1085 PLL_45XX_RATE( 600000000, 100, 4, 1, 13), 1086 PLL_45XX_RATE( 533000000, 533, 24, 1, 5), 1087 PLL_45XX_RATE( 500000000, 250, 6, 2, 28), 1088 PLL_45XX_RATE( 400000000, 200, 6, 2, 28), 1089 PLL_45XX_RATE( 200000000, 200, 6, 3, 28), 1090 { /* sentinel */ } 1091 }; 1092 1093 static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = { 1094 PLL_4600_RATE(192000000, 48, 3, 1, 0, 0), 1095 PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0), 1096 PLL_4600_RATE(180000000, 45, 3, 1, 0, 0), 1097 PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1), 1098 PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1), 1099 PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0), 1100 PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0), 1101 { /* sentinel */ } 1102 }; 1103 1104 static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = { 1105 PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0), 1106 PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1), 1107 PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1), 1108 PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0), 1109 PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0), 1110 { /* sentinel */ } 1111 }; 1112 1113 static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = { 1114 PLL_35XX_RATE(1500000000, 250, 4, 0), 1115 PLL_35XX_RATE(1400000000, 175, 3, 0), 1116 PLL_35XX_RATE(1300000000, 325, 6, 0), 1117 PLL_35XX_RATE(1200000000, 200, 4, 0), 1118 PLL_35XX_RATE(1100000000, 275, 6, 0), 1119 PLL_35XX_RATE(1000000000, 125, 3, 0), 1120 PLL_35XX_RATE( 900000000, 150, 4, 0), 1121 PLL_35XX_RATE( 800000000, 100, 3, 0), 1122 PLL_35XX_RATE( 700000000, 175, 3, 1), 1123 PLL_35XX_RATE( 600000000, 200, 4, 1), 1124 PLL_35XX_RATE( 500000000, 125, 3, 1), 1125 PLL_35XX_RATE( 400000000, 100, 3, 1), 1126 PLL_35XX_RATE( 300000000, 200, 4, 2), 1127 PLL_35XX_RATE( 200000000, 100, 3, 2), 1128 { /* sentinel */ } 1129 }; 1130 1131 static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = { 1132 PLL_36XX_RATE(192000000, 48, 3, 1, 0), 1133 PLL_36XX_RATE(180633605, 45, 3, 1, 10381), 1134 PLL_36XX_RATE(180000000, 45, 3, 1, 0), 1135 PLL_36XX_RATE( 73727996, 73, 3, 3, 47710), 1136 PLL_36XX_RATE( 67737602, 90, 4, 3, 20762), 1137 PLL_36XX_RATE( 49151992, 49, 3, 3, 9961), 1138 PLL_36XX_RATE( 45158401, 45, 3, 3, 10381), 1139 { /* sentinel */ } 1140 }; 1141 1142 static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = { 1143 PLL_36XX_RATE(533000000, 133, 3, 1, 16384), 1144 PLL_36XX_RATE(440000000, 110, 3, 1, 0), 1145 PLL_36XX_RATE(350000000, 175, 3, 2, 0), 1146 PLL_36XX_RATE(266000000, 133, 3, 2, 0), 1147 PLL_36XX_RATE(160000000, 160, 3, 3, 0), 1148 PLL_36XX_RATE(106031250, 53, 3, 2, 1024), 1149 PLL_36XX_RATE( 53015625, 53, 3, 3, 1024), 1150 { /* sentinel */ } 1151 }; 1152 1153 static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { 1154 [apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll", 1155 APLL_LOCK, APLL_CON0, "fout_apll", NULL), 1156 [mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 1157 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL), 1158 [epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 1159 EPLL_LOCK, EPLL_CON0, "fout_epll", NULL), 1160 [vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc", 1161 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL), 1162 }; 1163 1164 static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { 1165 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 1166 APLL_LOCK, APLL_CON0, NULL), 1167 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 1168 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL), 1169 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 1170 EPLL_LOCK, EPLL_CON0, NULL), 1171 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", 1172 VPLL_LOCK, VPLL_CON0, NULL), 1173 }; 1174 1175 /* register exynos4 clocks */ 1176 static void __init exynos4_clk_init(struct device_node *np, 1177 enum exynos4_soc soc) 1178 { 1179 exynos4_soc = soc; 1180 1181 reg_base = of_iomap(np, 0); 1182 if (!reg_base) 1183 panic("%s: failed to map registers\n", __func__); 1184 1185 samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1186 1187 samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks, 1188 ARRAY_SIZE(exynos4_fixed_rate_ext_clks), 1189 ext_clk_match); 1190 1191 exynos4_clk_register_finpll(); 1192 1193 if (exynos4_soc == EXYNOS4210) { 1194 samsung_clk_register_mux(exynos4210_mux_early, 1195 ARRAY_SIZE(exynos4210_mux_early)); 1196 1197 if (_get_rate("fin_pll") == 24000000) { 1198 exynos4210_plls[apll].rate_table = 1199 exynos4210_apll_rates; 1200 exynos4210_plls[epll].rate_table = 1201 exynos4210_epll_rates; 1202 } 1203 1204 if (_get_rate("mout_vpllsrc") == 24000000) 1205 exynos4210_plls[vpll].rate_table = 1206 exynos4210_vpll_rates; 1207 1208 samsung_clk_register_pll(exynos4210_plls, 1209 ARRAY_SIZE(exynos4210_plls), reg_base); 1210 } else { 1211 if (_get_rate("fin_pll") == 24000000) { 1212 exynos4x12_plls[apll].rate_table = 1213 exynos4x12_apll_rates; 1214 exynos4x12_plls[epll].rate_table = 1215 exynos4x12_epll_rates; 1216 exynos4x12_plls[vpll].rate_table = 1217 exynos4x12_vpll_rates; 1218 } 1219 1220 samsung_clk_register_pll(exynos4x12_plls, 1221 ARRAY_SIZE(exynos4x12_plls), reg_base); 1222 } 1223 1224 samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks, 1225 ARRAY_SIZE(exynos4_fixed_rate_clks)); 1226 samsung_clk_register_mux(exynos4_mux_clks, 1227 ARRAY_SIZE(exynos4_mux_clks)); 1228 samsung_clk_register_div(exynos4_div_clks, 1229 ARRAY_SIZE(exynos4_div_clks)); 1230 samsung_clk_register_gate(exynos4_gate_clks, 1231 ARRAY_SIZE(exynos4_gate_clks)); 1232 1233 if (exynos4_soc == EXYNOS4210) { 1234 samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks, 1235 ARRAY_SIZE(exynos4210_fixed_rate_clks)); 1236 samsung_clk_register_mux(exynos4210_mux_clks, 1237 ARRAY_SIZE(exynos4210_mux_clks)); 1238 samsung_clk_register_div(exynos4210_div_clks, 1239 ARRAY_SIZE(exynos4210_div_clks)); 1240 samsung_clk_register_gate(exynos4210_gate_clks, 1241 ARRAY_SIZE(exynos4210_gate_clks)); 1242 samsung_clk_register_alias(exynos4210_aliases, 1243 ARRAY_SIZE(exynos4210_aliases)); 1244 } else { 1245 samsung_clk_register_mux(exynos4x12_mux_clks, 1246 ARRAY_SIZE(exynos4x12_mux_clks)); 1247 samsung_clk_register_div(exynos4x12_div_clks, 1248 ARRAY_SIZE(exynos4x12_div_clks)); 1249 samsung_clk_register_gate(exynos4x12_gate_clks, 1250 ARRAY_SIZE(exynos4x12_gate_clks)); 1251 samsung_clk_register_alias(exynos4x12_aliases, 1252 ARRAY_SIZE(exynos4x12_aliases)); 1253 } 1254 1255 samsung_clk_register_alias(exynos4_aliases, 1256 ARRAY_SIZE(exynos4_aliases)); 1257 1258 exynos4_clk_sleep_init(); 1259 1260 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" 1261 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", 1262 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", 1263 _get_rate("sclk_apll"), _get_rate("sclk_mpll"), 1264 _get_rate("sclk_epll"), _get_rate("sclk_vpll"), 1265 _get_rate("arm_clk")); 1266 } 1267 1268 1269 static void __init exynos4210_clk_init(struct device_node *np) 1270 { 1271 exynos4_clk_init(np, EXYNOS4210); 1272 } 1273 CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init); 1274 1275 static void __init exynos4412_clk_init(struct device_node *np) 1276 { 1277 exynos4_clk_init(np, EXYNOS4X12); 1278 } 1279 CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init); 1280