1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2013 Linaro Ltd. 4 * Author: Thomas Abraham <thomas.ab@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for all Exynos4 SoCs. 11 */ 12 13 #include <dt-bindings/clock/exynos4.h> 14 #include <linux/clk.h> 15 #include <linux/clkdev.h> 16 #include <linux/clk-provider.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 20 #include "clk.h" 21 22 /* Exynos4 clock controller register offsets */ 23 #define SRC_LEFTBUS 0x4200 24 #define DIV_LEFTBUS 0x4500 25 #define GATE_IP_LEFTBUS 0x4800 26 #define E4X12_GATE_IP_IMAGE 0x4930 27 #define SRC_RIGHTBUS 0x8200 28 #define DIV_RIGHTBUS 0x8500 29 #define GATE_IP_RIGHTBUS 0x8800 30 #define E4X12_GATE_IP_PERIR 0x8960 31 #define EPLL_LOCK 0xc010 32 #define VPLL_LOCK 0xc020 33 #define EPLL_CON0 0xc110 34 #define EPLL_CON1 0xc114 35 #define EPLL_CON2 0xc118 36 #define VPLL_CON0 0xc120 37 #define VPLL_CON1 0xc124 38 #define VPLL_CON2 0xc128 39 #define SRC_TOP0 0xc210 40 #define SRC_TOP1 0xc214 41 #define SRC_CAM 0xc220 42 #define SRC_TV 0xc224 43 #define SRC_MFC 0xc228 44 #define SRC_G3D 0xc22c 45 #define E4210_SRC_IMAGE 0xc230 46 #define SRC_LCD0 0xc234 47 #define E4210_SRC_LCD1 0xc238 48 #define E4X12_SRC_ISP 0xc238 49 #define SRC_MAUDIO 0xc23c 50 #define SRC_FSYS 0xc240 51 #define SRC_PERIL0 0xc250 52 #define SRC_PERIL1 0xc254 53 #define E4X12_SRC_CAM1 0xc258 54 #define SRC_MASK_TOP 0xc310 55 #define SRC_MASK_CAM 0xc320 56 #define SRC_MASK_TV 0xc324 57 #define SRC_MASK_LCD0 0xc334 58 #define E4210_SRC_MASK_LCD1 0xc338 59 #define E4X12_SRC_MASK_ISP 0xc338 60 #define SRC_MASK_MAUDIO 0xc33c 61 #define SRC_MASK_FSYS 0xc340 62 #define SRC_MASK_PERIL0 0xc350 63 #define SRC_MASK_PERIL1 0xc354 64 #define DIV_TOP 0xc510 65 #define DIV_CAM 0xc520 66 #define DIV_TV 0xc524 67 #define DIV_MFC 0xc528 68 #define DIV_G3D 0xc52c 69 #define DIV_IMAGE 0xc530 70 #define DIV_LCD0 0xc534 71 #define E4210_DIV_LCD1 0xc538 72 #define E4X12_DIV_ISP 0xc538 73 #define DIV_MAUDIO 0xc53c 74 #define DIV_FSYS0 0xc540 75 #define DIV_FSYS1 0xc544 76 #define DIV_FSYS2 0xc548 77 #define DIV_FSYS3 0xc54c 78 #define DIV_PERIL0 0xc550 79 #define DIV_PERIL1 0xc554 80 #define DIV_PERIL2 0xc558 81 #define DIV_PERIL3 0xc55c 82 #define DIV_PERIL4 0xc560 83 #define DIV_PERIL5 0xc564 84 #define E4X12_DIV_CAM1 0xc568 85 #define GATE_SCLK_CAM 0xc820 86 #define GATE_IP_CAM 0xc920 87 #define GATE_IP_TV 0xc924 88 #define GATE_IP_MFC 0xc928 89 #define GATE_IP_G3D 0xc92c 90 #define E4210_GATE_IP_IMAGE 0xc930 91 #define GATE_IP_LCD0 0xc934 92 #define E4210_GATE_IP_LCD1 0xc938 93 #define E4X12_GATE_IP_ISP 0xc938 94 #define E4X12_GATE_IP_MAUDIO 0xc93c 95 #define GATE_IP_FSYS 0xc940 96 #define GATE_IP_GPS 0xc94c 97 #define GATE_IP_PERIL 0xc950 98 #define E4210_GATE_IP_PERIR 0xc960 99 #define GATE_BLOCK 0xc970 100 #define E4X12_MPLL_LOCK 0x10008 101 #define E4X12_MPLL_CON0 0x10108 102 #define SRC_DMC 0x10200 103 #define SRC_MASK_DMC 0x10300 104 #define DIV_DMC0 0x10500 105 #define DIV_DMC1 0x10504 106 #define GATE_IP_DMC 0x10900 107 #define APLL_LOCK 0x14000 108 #define E4210_MPLL_LOCK 0x14008 109 #define APLL_CON0 0x14100 110 #define E4210_MPLL_CON0 0x14108 111 #define SRC_CPU 0x14200 112 #define DIV_CPU0 0x14500 113 #define DIV_CPU1 0x14504 114 #define GATE_SCLK_CPU 0x14800 115 #define GATE_IP_CPU 0x14900 116 #define E4X12_DIV_ISP0 0x18300 117 #define E4X12_DIV_ISP1 0x18304 118 #define E4X12_GATE_ISP0 0x18800 119 #define E4X12_GATE_ISP1 0x18804 120 121 /* the exynos4 soc type */ 122 enum exynos4_soc { 123 EXYNOS4210, 124 EXYNOS4X12, 125 }; 126 127 /* list of PLLs to be registered */ 128 enum exynos4_plls { 129 apll, mpll, epll, vpll, 130 nr_plls /* number of PLLs */ 131 }; 132 133 /* 134 * list of controller registers to be saved and restored during a 135 * suspend/resume cycle. 136 */ 137 static unsigned long exynos4210_clk_save[] __initdata = { 138 E4210_SRC_IMAGE, 139 E4210_SRC_LCD1, 140 E4210_SRC_MASK_LCD1, 141 E4210_DIV_LCD1, 142 E4210_GATE_IP_IMAGE, 143 E4210_GATE_IP_LCD1, 144 E4210_GATE_IP_PERIR, 145 E4210_MPLL_CON0, 146 }; 147 148 static unsigned long exynos4x12_clk_save[] __initdata = { 149 E4X12_GATE_IP_IMAGE, 150 E4X12_GATE_IP_PERIR, 151 E4X12_SRC_CAM1, 152 E4X12_DIV_ISP, 153 E4X12_DIV_CAM1, 154 E4X12_MPLL_CON0, 155 }; 156 157 static unsigned long exynos4_clk_regs[] __initdata = { 158 SRC_LEFTBUS, 159 DIV_LEFTBUS, 160 GATE_IP_LEFTBUS, 161 SRC_RIGHTBUS, 162 DIV_RIGHTBUS, 163 GATE_IP_RIGHTBUS, 164 EPLL_CON0, 165 EPLL_CON1, 166 EPLL_CON2, 167 VPLL_CON0, 168 VPLL_CON1, 169 VPLL_CON2, 170 SRC_TOP0, 171 SRC_TOP1, 172 SRC_CAM, 173 SRC_TV, 174 SRC_MFC, 175 SRC_G3D, 176 SRC_LCD0, 177 SRC_MAUDIO, 178 SRC_FSYS, 179 SRC_PERIL0, 180 SRC_PERIL1, 181 SRC_MASK_TOP, 182 SRC_MASK_CAM, 183 SRC_MASK_TV, 184 SRC_MASK_LCD0, 185 SRC_MASK_MAUDIO, 186 SRC_MASK_FSYS, 187 SRC_MASK_PERIL0, 188 SRC_MASK_PERIL1, 189 DIV_TOP, 190 DIV_CAM, 191 DIV_TV, 192 DIV_MFC, 193 DIV_G3D, 194 DIV_IMAGE, 195 DIV_LCD0, 196 DIV_MAUDIO, 197 DIV_FSYS0, 198 DIV_FSYS1, 199 DIV_FSYS2, 200 DIV_FSYS3, 201 DIV_PERIL0, 202 DIV_PERIL1, 203 DIV_PERIL2, 204 DIV_PERIL3, 205 DIV_PERIL4, 206 DIV_PERIL5, 207 GATE_SCLK_CAM, 208 GATE_IP_CAM, 209 GATE_IP_TV, 210 GATE_IP_MFC, 211 GATE_IP_G3D, 212 GATE_IP_LCD0, 213 GATE_IP_FSYS, 214 GATE_IP_GPS, 215 GATE_IP_PERIL, 216 GATE_BLOCK, 217 SRC_MASK_DMC, 218 SRC_DMC, 219 DIV_DMC0, 220 DIV_DMC1, 221 GATE_IP_DMC, 222 APLL_CON0, 223 SRC_CPU, 224 DIV_CPU0, 225 DIV_CPU1, 226 GATE_SCLK_CPU, 227 GATE_IP_CPU, 228 }; 229 230 /* list of all parent clock list */ 231 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 232 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; 233 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; 234 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", }; 235 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", }; 236 PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", }; 237 PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", }; 238 PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", }; 239 PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", }; 240 PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", }; 241 PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", }; 242 PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", 243 "spdif_extclk", }; 244 PNAME(mout_onenand_p) = {"aclk133", "aclk160", }; 245 PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", }; 246 247 /* Exynos 4210-specific parent groups */ 248 PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", }; 249 PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", }; 250 PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", }; 251 PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", 252 "sclk_usbphy0", "none", "sclk_hdmiphy", 253 "sclk_mpll", "sclk_epll", "sclk_vpll", }; 254 PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m", 255 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 256 "sclk_epll", "sclk_vpll" }; 257 PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m", 258 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 259 "sclk_epll", "sclk_vpll", }; 260 PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m", 261 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 262 "sclk_epll", "sclk_vpll", }; 263 PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", }; 264 PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", }; 265 266 /* Exynos 4x12-specific parent groups */ 267 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", }; 268 PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", }; 269 PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", }; 270 PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", 271 "none", "sclk_hdmiphy", "mout_mpll_user_t", 272 "sclk_epll", "sclk_vpll", }; 273 PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m", 274 "sclk_usbphy0", "xxti", "xusbxti", 275 "mout_mpll_user_t", "sclk_epll", "sclk_vpll" }; 276 PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m", 277 "sclk_usbphy0", "xxti", "xusbxti", 278 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; 279 PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m", 280 "sclk_usbphy0", "xxti", "xusbxti", 281 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; 282 PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", }; 283 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", }; 284 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", }; 285 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; 286 287 /* fixed rate clocks generated outside the soc */ 288 static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { 289 FRATE(CLK_XXTI, "xxti", NULL, CLK_IS_ROOT, 0), 290 FRATE(CLK_XUSBXTI, "xusbxti", NULL, CLK_IS_ROOT, 0), 291 }; 292 293 /* fixed rate clocks generated inside the soc */ 294 static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { 295 FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), 296 FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 297 FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 298 }; 299 300 static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { 301 FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), 302 }; 303 304 /* list of mux clocks supported in all exynos4 soc's */ 305 static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 306 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 307 CLK_SET_RATE_PARENT, 0, "mout_apll"), 308 MUX(0, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), 309 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), 310 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), 311 MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, 312 CLK_SET_RATE_PARENT, 0), 313 MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, 314 CLK_SET_RATE_PARENT, 0), 315 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), 316 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), 317 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1), 318 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), 319 }; 320 321 /* list of mux clocks supported in exynos4210 soc */ 322 static struct samsung_mux_clock exynos4210_mux_early[] __initdata = { 323 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), 324 }; 325 326 static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 327 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), 328 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), 329 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), 330 MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), 331 MUX(0, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), 332 MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), 333 MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), 334 MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), 335 MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), 336 MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), 337 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), 338 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), 339 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), 340 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), 341 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), 342 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), 343 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), 344 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), 345 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), 346 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), 347 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), 348 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), 349 MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), 350 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, 351 CLK_SET_RATE_PARENT, 0), 352 MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), 353 MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), 354 MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), 355 MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), 356 MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), 357 MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), 358 MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), 359 MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), 360 MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), 361 MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), 362 MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), 363 MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), 364 MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), 365 MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), 366 MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), 367 MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), 368 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), 369 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), 370 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), 371 }; 372 373 /* list of mux clocks supported in exynos4x12 soc */ 374 static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 375 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12, 376 SRC_CPU, 24, 1), 377 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), 378 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), 379 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12, 380 SRC_TOP1, 12, 1), 381 MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, 382 SRC_TOP1, 16, 1), 383 MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), 384 MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp", 385 mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1), 386 MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), 387 MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), 388 MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), 389 MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), 390 MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), 391 MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), 392 MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), 393 MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), 394 MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), 395 MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), 396 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), 397 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1), 398 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), 399 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), 400 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), 401 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), 402 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), 403 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), 404 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), 405 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), 406 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), 407 MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), 408 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, 409 CLK_SET_RATE_PARENT, 0), 410 MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), 411 MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), 412 MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), 413 MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), 414 MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), 415 MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), 416 MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), 417 MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), 418 MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), 419 MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), 420 MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), 421 MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), 422 MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), 423 MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), 424 MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), 425 MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), 426 MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), 427 MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), 428 MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), 429 MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), 430 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), 431 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), 432 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), 433 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), 434 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), 435 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), 436 }; 437 438 /* list of divider clocks supported in all exynos4 soc's */ 439 static struct samsung_div_clock exynos4_div_clks[] __initdata = { 440 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3), 441 DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3), 442 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), 443 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), 444 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), 445 DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), 446 DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), 447 DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), 448 DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), 449 DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), 450 DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), 451 DIV_F(0, "div_g3d", "mout_g3d", DIV_G3D, 0, 4, 452 CLK_SET_RATE_PARENT, 0), 453 DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), 454 DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), 455 DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), 456 DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), 457 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 458 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 459 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 460 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 461 DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), 462 DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), 463 DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), 464 DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), 465 DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), 466 DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), 467 DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), 468 DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), 469 DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), 470 DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), 471 DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), 472 DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8, 473 CLK_SET_RATE_PARENT, 0), 474 DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 475 DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 476 DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), 477 DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), 478 DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), 479 DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), 480 DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), 481 DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), 482 DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), 483 DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), 484 DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), 485 DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), 486 DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), 487 DIV(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3), 488 DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 489 DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, 490 CLK_SET_RATE_PARENT, 0), 491 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, 492 CLK_SET_RATE_PARENT, 0), 493 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, 494 CLK_SET_RATE_PARENT, 0), 495 DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, 496 CLK_SET_RATE_PARENT, 0), 497 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, 498 CLK_SET_RATE_PARENT, 0), 499 }; 500 501 /* list of divider clocks supported in exynos4210 soc */ 502 static struct samsung_div_clock exynos4210_div_clks[] __initdata = { 503 DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), 504 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), 505 DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), 506 DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), 507 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 508 DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, 509 CLK_SET_RATE_PARENT, 0), 510 }; 511 512 /* list of divider clocks supported in exynos4x12 soc */ 513 static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { 514 DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), 515 DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), 516 DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), 517 DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), 518 DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), 519 DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), 520 DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), 521 DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", 522 DIV_TOP, 24, 3), 523 DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), 524 DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), 525 DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), 526 DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), 527 DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), 528 DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), 529 DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, 530 CLK_GET_RATE_NOCACHE, 0), 531 DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, 532 CLK_GET_RATE_NOCACHE, 0), 533 DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), 534 DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 535 4, 3, CLK_GET_RATE_NOCACHE, 0), 536 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 537 8, 3, CLK_GET_RATE_NOCACHE, 0), 538 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 539 }; 540 541 /* list of gate clocks supported in all exynos4 soc's */ 542 static struct samsung_gate_clock exynos4_gate_clks[] __initdata = { 543 /* 544 * After all Exynos4 based platforms are migrated to use device tree, 545 * the device name and clock alias names specified below for some 546 * of the clocks can be removed. 547 */ 548 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), 549 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 550 0), 551 GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), 552 GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), 553 GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), 554 GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), 555 GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), 556 GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), 557 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 558 0), 559 GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), 560 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), 561 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, 562 CLK_SET_RATE_PARENT, 0), 563 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), 564 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), 565 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), 566 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), 567 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), 568 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), 569 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, 570 CLK_SET_RATE_PARENT, 0), 571 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, 572 CLK_SET_RATE_PARENT, 0), 573 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0", 574 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), 575 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, 576 CLK_SET_RATE_PARENT, 0), 577 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, 578 CLK_SET_RATE_PARENT, 0), 579 GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0), 580 GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), 581 GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), 582 GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0), 583 GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0), 584 GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0), 585 GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0, 586 CLK_SET_RATE_PARENT, 0), 587 GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4, 588 CLK_SET_RATE_PARENT, 0), 589 GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8, 590 CLK_SET_RATE_PARENT, 0), 591 GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12, 592 CLK_SET_RATE_PARENT, 0), 593 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24, 594 CLK_SET_RATE_PARENT, 0), 595 GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28, 596 CLK_SET_RATE_PARENT, 0), 597 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0, 598 CLK_SET_RATE_PARENT, 0), 599 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, 600 CLK_SET_RATE_PARENT, 0), 601 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4, 602 CLK_SET_RATE_PARENT, 0), 603 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8, 604 CLK_SET_RATE_PARENT, 0), 605 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12, 606 CLK_SET_RATE_PARENT, 0), 607 GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16, 608 CLK_SET_RATE_PARENT, 0), 609 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0, 610 CLK_SET_RATE_PARENT, 0), 611 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4, 612 CLK_SET_RATE_PARENT, 0), 613 GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8, 614 CLK_SET_RATE_PARENT, 0), 615 GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12, 616 CLK_SET_RATE_PARENT, 0), 617 GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16, 618 CLK_SET_RATE_PARENT, 0), 619 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, 620 CLK_SET_RATE_PARENT, 0), 621 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16, 622 CLK_SET_RATE_PARENT, 0), 623 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20, 624 CLK_SET_RATE_PARENT, 0), 625 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24, 626 CLK_SET_RATE_PARENT, 0), 627 GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0, 628 0, 0), 629 GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1, 630 0, 0), 631 GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2, 632 0, 0), 633 GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3, 634 0, 0), 635 GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4, 636 0, 0), 637 GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5, 638 0, 0), 639 GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7, 640 0, 0), 641 GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8, 642 0, 0), 643 GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9, 644 0, 0), 645 GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10, 646 0, 0), 647 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, 648 0, 0), 649 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), 650 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), 651 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4, 652 0, 0), 653 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0), 654 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1, 655 0, 0), 656 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2, 657 0, 0), 658 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0, 659 0, 0), 660 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4, 661 0, 0), 662 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0, 663 0, 0), 664 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1, 665 0, 0), 666 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5, 667 0, 0), 668 GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6, 669 0, 0), 670 GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7, 671 0, 0), 672 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8, 673 0, 0), 674 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0, 675 0, 0), 676 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1, 677 0, 0), 678 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2, 679 0, 0), 680 GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3, 681 0, 0), 682 GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4, 683 0, 0), 684 GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6, 685 0, 0), 686 GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7, 687 0, 0), 688 GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8, 689 0, 0), 690 GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9, 691 0, 0), 692 GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10, 693 0, 0), 694 GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11, 695 0, 0), 696 GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12, 697 0, 0), 698 GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13, 699 0, 0), 700 GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14, 701 0, 0), 702 GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16, 703 0, 0), 704 GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17, 705 0, 0), 706 GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18, 707 0, 0), 708 GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20, 709 0, 0), 710 GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21, 711 0, 0), 712 GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22, 713 0, 0), 714 GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23, 715 0, 0), 716 GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26, 717 0, 0), 718 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27, 719 0, 0), 720 }; 721 722 /* list of gate clocks supported in exynos4210 soc */ 723 static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 724 GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), 725 GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), 726 GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), 727 GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), 728 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), 729 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 730 0), 731 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), 732 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), 733 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), 734 GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), 735 GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), 736 GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), 737 GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), 738 GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 739 CLK_IGNORE_UNUSED, 0), 740 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 741 0), 742 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200", 743 E4210_GATE_IP_IMAGE, 4, 0, 0), 744 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1", 745 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), 746 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata", 747 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 748 GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), 749 GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), 750 GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15, 751 0, 0), 752 GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 753 0, 0), 754 GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 755 0, 0), 756 GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 757 0, 0), 758 GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 759 0, 0), 760 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, 761 CLK_SET_RATE_PARENT, 0), 762 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 763 0), 764 }; 765 766 /* list of gate clocks supported in exynos4x12 soc */ 767 static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 768 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), 769 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), 770 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), 771 GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), 772 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 773 0), 774 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 775 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), 776 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 777 CLK_IGNORE_UNUSED, 0), 778 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 779 0), 780 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0", 781 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), 782 GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", 783 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), 784 GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi", 785 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 786 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200", 787 E4X12_GATE_IP_IMAGE, 4, 0, 0), 788 GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 789 0, 0), 790 GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 791 0, 0), 792 GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0), 793 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "div_pwm_isp", 794 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0), 795 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp_pre", 796 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0), 797 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp_pre", 798 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0), 799 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp", 800 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0), 801 GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "sclk_pwm_isp", 802 E4X12_GATE_IP_ISP, 0, 0, 0), 803 GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "sclk_spi0_isp", 804 E4X12_GATE_IP_ISP, 1, 0, 0), 805 GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "sclk_spi1_isp", 806 E4X12_GATE_IP_ISP, 2, 0, 0), 807 GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "sclk_uart_isp", 808 E4X12_GATE_IP_ISP, 3, 0, 0), 809 GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0), 810 GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2, 811 0, 0), 812 GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 813 0, 0), 814 GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 815 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 816 GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 817 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 818 GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 819 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 820 GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 821 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 822 GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 823 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 824 GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 825 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 826 GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 827 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 828 GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 829 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 830 GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 831 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 832 GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 833 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 834 GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, 835 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 836 GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, 837 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 838 GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, 839 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 840 GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, 841 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 842 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, 843 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 844 GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, 845 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 846 GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, 847 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 848 GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, 849 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 850 GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, 851 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 852 GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 853 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 854 GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 855 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 856 GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, 857 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 858 GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, 859 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 860 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, 861 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 862 GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, 863 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 864 GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 865 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 866 GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), 867 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 868 0), 869 }; 870 871 static struct samsung_clock_alias exynos4_aliases[] __initdata = { 872 ALIAS(CLK_MOUT_CORE, NULL, "moutcore"), 873 ALIAS(CLK_ARM_CLK, NULL, "armclk"), 874 ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"), 875 }; 876 877 static struct samsung_clock_alias exynos4210_aliases[] __initdata = { 878 ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"), 879 }; 880 881 static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { 882 ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"), 883 }; 884 885 /* 886 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit 887 * resides in chipid register space, outside of the clock controller memory 888 * mapped space. So to determine the parent of fin_pll clock, the chipid 889 * controller is first remapped and the value of XOM[0] bit is read to 890 * determine the parent clock. 891 */ 892 static unsigned long exynos4_get_xom(void) 893 { 894 unsigned long xom = 0; 895 void __iomem *chipid_base; 896 struct device_node *np; 897 898 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid"); 899 if (np) { 900 chipid_base = of_iomap(np, 0); 901 902 if (chipid_base) 903 xom = readl(chipid_base + 8); 904 905 iounmap(chipid_base); 906 } 907 908 return xom; 909 } 910 911 static void __init exynos4_clk_register_finpll(unsigned long xom) 912 { 913 struct samsung_fixed_rate_clock fclk; 914 struct clk *clk; 915 unsigned long finpll_f = 24000000; 916 char *parent_name; 917 918 parent_name = xom & 1 ? "xusbxti" : "xxti"; 919 clk = clk_get(NULL, parent_name); 920 if (IS_ERR(clk)) { 921 pr_err("%s: failed to lookup parent clock %s, assuming " 922 "fin_pll clock frequency is 24MHz\n", __func__, 923 parent_name); 924 } else { 925 finpll_f = clk_get_rate(clk); 926 } 927 928 fclk.id = CLK_FIN_PLL; 929 fclk.name = "fin_pll"; 930 fclk.parent_name = NULL; 931 fclk.flags = CLK_IS_ROOT; 932 fclk.fixed_rate = finpll_f; 933 samsung_clk_register_fixed_rate(&fclk, 1); 934 935 } 936 937 static struct of_device_id ext_clk_match[] __initdata = { 938 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 939 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, 940 {}, 941 }; 942 943 /* PLLs PMS values */ 944 static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = { 945 PLL_45XX_RATE(1200000000, 150, 3, 1, 28), 946 PLL_45XX_RATE(1000000000, 250, 6, 1, 28), 947 PLL_45XX_RATE( 800000000, 200, 6, 1, 28), 948 PLL_45XX_RATE( 666857142, 389, 14, 1, 13), 949 PLL_45XX_RATE( 600000000, 100, 4, 1, 13), 950 PLL_45XX_RATE( 533000000, 533, 24, 1, 5), 951 PLL_45XX_RATE( 500000000, 250, 6, 2, 28), 952 PLL_45XX_RATE( 400000000, 200, 6, 2, 28), 953 PLL_45XX_RATE( 200000000, 200, 6, 3, 28), 954 { /* sentinel */ } 955 }; 956 957 static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = { 958 PLL_4600_RATE(192000000, 48, 3, 1, 0, 0), 959 PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0), 960 PLL_4600_RATE(180000000, 45, 3, 1, 0, 0), 961 PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1), 962 PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1), 963 PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0), 964 PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0), 965 { /* sentinel */ } 966 }; 967 968 static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = { 969 PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0), 970 PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1), 971 PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1), 972 PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0), 973 PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0), 974 { /* sentinel */ } 975 }; 976 977 static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = { 978 PLL_35XX_RATE(1500000000, 250, 4, 0), 979 PLL_35XX_RATE(1400000000, 175, 3, 0), 980 PLL_35XX_RATE(1300000000, 325, 6, 0), 981 PLL_35XX_RATE(1200000000, 200, 4, 0), 982 PLL_35XX_RATE(1100000000, 275, 6, 0), 983 PLL_35XX_RATE(1000000000, 125, 3, 0), 984 PLL_35XX_RATE( 900000000, 150, 4, 0), 985 PLL_35XX_RATE( 800000000, 100, 3, 0), 986 PLL_35XX_RATE( 700000000, 175, 3, 1), 987 PLL_35XX_RATE( 600000000, 200, 4, 1), 988 PLL_35XX_RATE( 500000000, 125, 3, 1), 989 PLL_35XX_RATE( 400000000, 100, 3, 1), 990 PLL_35XX_RATE( 300000000, 200, 4, 2), 991 PLL_35XX_RATE( 200000000, 100, 3, 2), 992 { /* sentinel */ } 993 }; 994 995 static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = { 996 PLL_36XX_RATE(192000000, 48, 3, 1, 0), 997 PLL_36XX_RATE(180633605, 45, 3, 1, 10381), 998 PLL_36XX_RATE(180000000, 45, 3, 1, 0), 999 PLL_36XX_RATE( 73727996, 73, 3, 3, 47710), 1000 PLL_36XX_RATE( 67737602, 90, 4, 3, 20762), 1001 PLL_36XX_RATE( 49151992, 49, 3, 3, 9961), 1002 PLL_36XX_RATE( 45158401, 45, 3, 3, 10381), 1003 { /* sentinel */ } 1004 }; 1005 1006 static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = { 1007 PLL_36XX_RATE(533000000, 133, 3, 1, 16384), 1008 PLL_36XX_RATE(440000000, 110, 3, 1, 0), 1009 PLL_36XX_RATE(350000000, 175, 3, 2, 0), 1010 PLL_36XX_RATE(266000000, 133, 3, 2, 0), 1011 PLL_36XX_RATE(160000000, 160, 3, 3, 0), 1012 PLL_36XX_RATE(106031250, 53, 3, 2, 1024), 1013 PLL_36XX_RATE( 53015625, 53, 3, 3, 1024), 1014 { /* sentinel */ } 1015 }; 1016 1017 static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { 1018 [apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll", 1019 APLL_LOCK, APLL_CON0, "fout_apll", NULL), 1020 [mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 1021 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL), 1022 [epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 1023 EPLL_LOCK, EPLL_CON0, "fout_epll", NULL), 1024 [vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc", 1025 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL), 1026 }; 1027 1028 static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { 1029 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 1030 APLL_LOCK, APLL_CON0, NULL), 1031 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 1032 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL), 1033 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 1034 EPLL_LOCK, EPLL_CON0, NULL), 1035 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", 1036 VPLL_LOCK, VPLL_CON0, NULL), 1037 }; 1038 1039 /* register exynos4 clocks */ 1040 static void __init exynos4_clk_init(struct device_node *np, 1041 enum exynos4_soc exynos4_soc, 1042 void __iomem *reg_base, unsigned long xom) 1043 { 1044 reg_base = of_iomap(np, 0); 1045 if (!reg_base) 1046 panic("%s: failed to map registers\n", __func__); 1047 1048 if (exynos4_soc == EXYNOS4210) 1049 samsung_clk_init(np, reg_base, CLK_NR_CLKS, 1050 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), 1051 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save)); 1052 else 1053 samsung_clk_init(np, reg_base, CLK_NR_CLKS, 1054 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), 1055 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save)); 1056 1057 samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks, 1058 ARRAY_SIZE(exynos4_fixed_rate_ext_clks), 1059 ext_clk_match); 1060 1061 exynos4_clk_register_finpll(xom); 1062 1063 if (exynos4_soc == EXYNOS4210) { 1064 samsung_clk_register_mux(exynos4210_mux_early, 1065 ARRAY_SIZE(exynos4210_mux_early)); 1066 1067 if (_get_rate("fin_pll") == 24000000) { 1068 exynos4210_plls[apll].rate_table = 1069 exynos4210_apll_rates; 1070 exynos4210_plls[epll].rate_table = 1071 exynos4210_epll_rates; 1072 } 1073 1074 if (_get_rate("mout_vpllsrc") == 24000000) 1075 exynos4210_plls[vpll].rate_table = 1076 exynos4210_vpll_rates; 1077 1078 samsung_clk_register_pll(exynos4210_plls, 1079 ARRAY_SIZE(exynos4210_plls), reg_base); 1080 } else { 1081 if (_get_rate("fin_pll") == 24000000) { 1082 exynos4x12_plls[apll].rate_table = 1083 exynos4x12_apll_rates; 1084 exynos4x12_plls[epll].rate_table = 1085 exynos4x12_epll_rates; 1086 exynos4x12_plls[vpll].rate_table = 1087 exynos4x12_vpll_rates; 1088 } 1089 1090 samsung_clk_register_pll(exynos4x12_plls, 1091 ARRAY_SIZE(exynos4x12_plls), reg_base); 1092 } 1093 1094 samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks, 1095 ARRAY_SIZE(exynos4_fixed_rate_clks)); 1096 samsung_clk_register_mux(exynos4_mux_clks, 1097 ARRAY_SIZE(exynos4_mux_clks)); 1098 samsung_clk_register_div(exynos4_div_clks, 1099 ARRAY_SIZE(exynos4_div_clks)); 1100 samsung_clk_register_gate(exynos4_gate_clks, 1101 ARRAY_SIZE(exynos4_gate_clks)); 1102 1103 if (exynos4_soc == EXYNOS4210) { 1104 samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks, 1105 ARRAY_SIZE(exynos4210_fixed_rate_clks)); 1106 samsung_clk_register_mux(exynos4210_mux_clks, 1107 ARRAY_SIZE(exynos4210_mux_clks)); 1108 samsung_clk_register_div(exynos4210_div_clks, 1109 ARRAY_SIZE(exynos4210_div_clks)); 1110 samsung_clk_register_gate(exynos4210_gate_clks, 1111 ARRAY_SIZE(exynos4210_gate_clks)); 1112 samsung_clk_register_alias(exynos4210_aliases, 1113 ARRAY_SIZE(exynos4210_aliases)); 1114 } else { 1115 samsung_clk_register_mux(exynos4x12_mux_clks, 1116 ARRAY_SIZE(exynos4x12_mux_clks)); 1117 samsung_clk_register_div(exynos4x12_div_clks, 1118 ARRAY_SIZE(exynos4x12_div_clks)); 1119 samsung_clk_register_gate(exynos4x12_gate_clks, 1120 ARRAY_SIZE(exynos4x12_gate_clks)); 1121 samsung_clk_register_alias(exynos4x12_aliases, 1122 ARRAY_SIZE(exynos4x12_aliases)); 1123 } 1124 1125 samsung_clk_register_alias(exynos4_aliases, 1126 ARRAY_SIZE(exynos4_aliases)); 1127 1128 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" 1129 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", 1130 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", 1131 _get_rate("sclk_apll"), _get_rate("sclk_mpll"), 1132 _get_rate("sclk_epll"), _get_rate("sclk_vpll"), 1133 _get_rate("arm_clk")); 1134 } 1135 1136 1137 static void __init exynos4210_clk_init(struct device_node *np) 1138 { 1139 exynos4_clk_init(np, EXYNOS4210, NULL, exynos4_get_xom()); 1140 } 1141 CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init); 1142 1143 static void __init exynos4412_clk_init(struct device_node *np) 1144 { 1145 exynos4_clk_init(np, EXYNOS4X12, NULL, exynos4_get_xom()); 1146 } 1147 CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init); 1148