1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2013 Linaro Ltd. 4 * Author: Thomas Abraham <thomas.ab@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for all Exynos4 SoCs. 11 */ 12 13 #include <dt-bindings/clock/exynos4.h> 14 #include <linux/slab.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 21 #include "clk.h" 22 #include "clk-cpu.h" 23 24 /* Exynos4 clock controller register offsets */ 25 #define SRC_LEFTBUS 0x4200 26 #define DIV_LEFTBUS 0x4500 27 #define GATE_IP_LEFTBUS 0x4800 28 #define E4X12_GATE_IP_IMAGE 0x4930 29 #define CLKOUT_CMU_LEFTBUS 0x4a00 30 #define SRC_RIGHTBUS 0x8200 31 #define DIV_RIGHTBUS 0x8500 32 #define GATE_IP_RIGHTBUS 0x8800 33 #define E4X12_GATE_IP_PERIR 0x8960 34 #define CLKOUT_CMU_RIGHTBUS 0x8a00 35 #define EPLL_LOCK 0xc010 36 #define VPLL_LOCK 0xc020 37 #define EPLL_CON0 0xc110 38 #define EPLL_CON1 0xc114 39 #define EPLL_CON2 0xc118 40 #define VPLL_CON0 0xc120 41 #define VPLL_CON1 0xc124 42 #define VPLL_CON2 0xc128 43 #define SRC_TOP0 0xc210 44 #define SRC_TOP1 0xc214 45 #define SRC_CAM 0xc220 46 #define SRC_TV 0xc224 47 #define SRC_MFC 0xc228 48 #define SRC_G3D 0xc22c 49 #define E4210_SRC_IMAGE 0xc230 50 #define SRC_LCD0 0xc234 51 #define E4210_SRC_LCD1 0xc238 52 #define E4X12_SRC_ISP 0xc238 53 #define SRC_MAUDIO 0xc23c 54 #define SRC_FSYS 0xc240 55 #define SRC_PERIL0 0xc250 56 #define SRC_PERIL1 0xc254 57 #define E4X12_SRC_CAM1 0xc258 58 #define SRC_MASK_TOP 0xc310 59 #define SRC_MASK_CAM 0xc320 60 #define SRC_MASK_TV 0xc324 61 #define SRC_MASK_LCD0 0xc334 62 #define E4210_SRC_MASK_LCD1 0xc338 63 #define E4X12_SRC_MASK_ISP 0xc338 64 #define SRC_MASK_MAUDIO 0xc33c 65 #define SRC_MASK_FSYS 0xc340 66 #define SRC_MASK_PERIL0 0xc350 67 #define SRC_MASK_PERIL1 0xc354 68 #define DIV_TOP 0xc510 69 #define DIV_CAM 0xc520 70 #define DIV_TV 0xc524 71 #define DIV_MFC 0xc528 72 #define DIV_G3D 0xc52c 73 #define DIV_IMAGE 0xc530 74 #define DIV_LCD0 0xc534 75 #define E4210_DIV_LCD1 0xc538 76 #define E4X12_DIV_ISP 0xc538 77 #define DIV_MAUDIO 0xc53c 78 #define DIV_FSYS0 0xc540 79 #define DIV_FSYS1 0xc544 80 #define DIV_FSYS2 0xc548 81 #define DIV_FSYS3 0xc54c 82 #define DIV_PERIL0 0xc550 83 #define DIV_PERIL1 0xc554 84 #define DIV_PERIL2 0xc558 85 #define DIV_PERIL3 0xc55c 86 #define DIV_PERIL4 0xc560 87 #define DIV_PERIL5 0xc564 88 #define E4X12_DIV_CAM1 0xc568 89 #define E4X12_GATE_BUS_FSYS1 0xc744 90 #define GATE_SCLK_CAM 0xc820 91 #define GATE_IP_CAM 0xc920 92 #define GATE_IP_TV 0xc924 93 #define GATE_IP_MFC 0xc928 94 #define GATE_IP_G3D 0xc92c 95 #define E4210_GATE_IP_IMAGE 0xc930 96 #define GATE_IP_LCD0 0xc934 97 #define E4210_GATE_IP_LCD1 0xc938 98 #define E4X12_GATE_IP_ISP 0xc938 99 #define E4X12_GATE_IP_MAUDIO 0xc93c 100 #define GATE_IP_FSYS 0xc940 101 #define GATE_IP_GPS 0xc94c 102 #define GATE_IP_PERIL 0xc950 103 #define E4210_GATE_IP_PERIR 0xc960 104 #define GATE_BLOCK 0xc970 105 #define CLKOUT_CMU_TOP 0xca00 106 #define E4X12_MPLL_LOCK 0x10008 107 #define E4X12_MPLL_CON0 0x10108 108 #define SRC_DMC 0x10200 109 #define SRC_MASK_DMC 0x10300 110 #define DIV_DMC0 0x10500 111 #define DIV_DMC1 0x10504 112 #define GATE_IP_DMC 0x10900 113 #define CLKOUT_CMU_DMC 0x10a00 114 #define APLL_LOCK 0x14000 115 #define E4210_MPLL_LOCK 0x14008 116 #define APLL_CON0 0x14100 117 #define E4210_MPLL_CON0 0x14108 118 #define SRC_CPU 0x14200 119 #define DIV_CPU0 0x14500 120 #define DIV_CPU1 0x14504 121 #define GATE_SCLK_CPU 0x14800 122 #define GATE_IP_CPU 0x14900 123 #define CLKOUT_CMU_CPU 0x14a00 124 #define PWR_CTRL1 0x15020 125 #define E4X12_PWR_CTRL2 0x15024 126 127 /* Below definitions are used for PWR_CTRL settings */ 128 #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28) 129 #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16) 130 #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) 131 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) 132 #define PWR_CTRL1_USE_CORE3_WFE (1 << 7) 133 #define PWR_CTRL1_USE_CORE2_WFE (1 << 6) 134 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5) 135 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4) 136 #define PWR_CTRL1_USE_CORE3_WFI (1 << 3) 137 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2) 138 #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) 139 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) 140 141 /* the exynos4 soc type */ 142 enum exynos4_soc { 143 EXYNOS4210, 144 EXYNOS4X12, 145 }; 146 147 /* list of PLLs to be registered */ 148 enum exynos4_plls { 149 apll, mpll, epll, vpll, 150 nr_plls /* number of PLLs */ 151 }; 152 153 static void __iomem *reg_base; 154 static enum exynos4_soc exynos4_soc; 155 156 /* 157 * list of controller registers to be saved and restored during a 158 * suspend/resume cycle. 159 */ 160 static const unsigned long exynos4210_clk_save[] __initconst = { 161 E4210_SRC_IMAGE, 162 E4210_SRC_LCD1, 163 E4210_SRC_MASK_LCD1, 164 E4210_DIV_LCD1, 165 E4210_GATE_IP_IMAGE, 166 E4210_GATE_IP_LCD1, 167 E4210_GATE_IP_PERIR, 168 E4210_MPLL_CON0, 169 PWR_CTRL1, 170 }; 171 172 static const unsigned long exynos4x12_clk_save[] __initconst = { 173 E4X12_GATE_IP_IMAGE, 174 E4X12_GATE_IP_PERIR, 175 E4X12_SRC_CAM1, 176 E4X12_DIV_ISP, 177 E4X12_DIV_CAM1, 178 E4X12_MPLL_CON0, 179 PWR_CTRL1, 180 E4X12_PWR_CTRL2, 181 }; 182 183 static const unsigned long exynos4_clk_regs[] __initconst = { 184 EPLL_LOCK, 185 VPLL_LOCK, 186 EPLL_CON0, 187 EPLL_CON1, 188 EPLL_CON2, 189 VPLL_CON0, 190 VPLL_CON1, 191 VPLL_CON2, 192 SRC_LEFTBUS, 193 DIV_LEFTBUS, 194 GATE_IP_LEFTBUS, 195 SRC_RIGHTBUS, 196 DIV_RIGHTBUS, 197 GATE_IP_RIGHTBUS, 198 SRC_TOP0, 199 SRC_TOP1, 200 SRC_CAM, 201 SRC_TV, 202 SRC_MFC, 203 SRC_G3D, 204 SRC_LCD0, 205 SRC_MAUDIO, 206 SRC_FSYS, 207 SRC_PERIL0, 208 SRC_PERIL1, 209 SRC_MASK_TOP, 210 SRC_MASK_CAM, 211 SRC_MASK_TV, 212 SRC_MASK_LCD0, 213 SRC_MASK_MAUDIO, 214 SRC_MASK_FSYS, 215 SRC_MASK_PERIL0, 216 SRC_MASK_PERIL1, 217 DIV_TOP, 218 DIV_CAM, 219 DIV_TV, 220 DIV_MFC, 221 DIV_G3D, 222 DIV_IMAGE, 223 DIV_LCD0, 224 DIV_MAUDIO, 225 DIV_FSYS0, 226 DIV_FSYS1, 227 DIV_FSYS2, 228 DIV_FSYS3, 229 DIV_PERIL0, 230 DIV_PERIL1, 231 DIV_PERIL2, 232 DIV_PERIL3, 233 DIV_PERIL4, 234 DIV_PERIL5, 235 GATE_SCLK_CAM, 236 GATE_IP_CAM, 237 GATE_IP_TV, 238 GATE_IP_MFC, 239 GATE_IP_G3D, 240 GATE_IP_LCD0, 241 GATE_IP_FSYS, 242 GATE_IP_GPS, 243 GATE_IP_PERIL, 244 GATE_BLOCK, 245 SRC_MASK_DMC, 246 SRC_DMC, 247 DIV_DMC0, 248 DIV_DMC1, 249 GATE_IP_DMC, 250 APLL_CON0, 251 SRC_CPU, 252 DIV_CPU0, 253 DIV_CPU1, 254 GATE_SCLK_CPU, 255 GATE_IP_CPU, 256 CLKOUT_CMU_LEFTBUS, 257 CLKOUT_CMU_RIGHTBUS, 258 CLKOUT_CMU_TOP, 259 CLKOUT_CMU_DMC, 260 CLKOUT_CMU_CPU, 261 }; 262 263 static const struct samsung_clk_reg_dump src_mask_suspend[] = { 264 { .offset = VPLL_CON0, .value = 0x80600302, }, 265 { .offset = EPLL_CON0, .value = 0x806F0302, }, 266 { .offset = SRC_MASK_TOP, .value = 0x00000001, }, 267 { .offset = SRC_MASK_CAM, .value = 0x11111111, }, 268 { .offset = SRC_MASK_TV, .value = 0x00000111, }, 269 { .offset = SRC_MASK_LCD0, .value = 0x00001111, }, 270 { .offset = SRC_MASK_MAUDIO, .value = 0x00000001, }, 271 { .offset = SRC_MASK_FSYS, .value = 0x01011111, }, 272 { .offset = SRC_MASK_PERIL0, .value = 0x01111111, }, 273 { .offset = SRC_MASK_PERIL1, .value = 0x01110111, }, 274 { .offset = SRC_MASK_DMC, .value = 0x00010000, }, 275 }; 276 277 static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { 278 { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, }, 279 }; 280 281 /* list of all parent clock list */ 282 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 283 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; 284 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; 285 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", }; 286 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", }; 287 PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", }; 288 PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", }; 289 PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", }; 290 PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", }; 291 PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", }; 292 PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", }; 293 PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", 294 "spdif_extclk", }; 295 PNAME(mout_onenand_p) = {"aclk133", "aclk160", }; 296 PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", }; 297 298 /* Exynos 4210-specific parent groups */ 299 PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", }; 300 PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", }; 301 PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", }; 302 PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", 303 "sclk_usbphy0", "none", "sclk_hdmiphy", 304 "sclk_mpll", "sclk_epll", "sclk_vpll", }; 305 PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m", 306 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 307 "sclk_epll", "sclk_vpll" }; 308 PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m", 309 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 310 "sclk_epll", "sclk_vpll", }; 311 PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m", 312 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", 313 "sclk_epll", "sclk_vpll", }; 314 PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", }; 315 PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", }; 316 PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", 317 "sclk_usbphy1", "sclk_hdmiphy", "none", 318 "sclk_epll", "sclk_vpll" }; 319 PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2", 320 "div_gdl", "div_gpl" }; 321 PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2", 322 "div_gdr", "div_gpr" }; 323 PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m", 324 "sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy", 325 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk", 326 "aclk160", "aclk133", "aclk200", "aclk100", 327 "sclk_mfc", "sclk_g3d", "sclk_g2d", 328 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l", 329 "s_rxbyteclkhs0_4l" }; 330 PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc", 331 "div_dphy", "none", "div_pwi" }; 332 PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2", 333 "none", "arm_clk_div_2", "div_corem0", 334 "div_corem1", "div_corem0", "div_atb", 335 "div_periph", "div_pclk_dbg", "div_hpm" }; 336 337 /* Exynos 4x12-specific parent groups */ 338 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", }; 339 PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", }; 340 PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", }; 341 PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", }; 342 PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", }; 343 PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", 344 "none", "sclk_hdmiphy", "mout_mpll_user_t", 345 "sclk_epll", "sclk_vpll", }; 346 PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m", 347 "sclk_usbphy0", "xxti", "xusbxti", 348 "mout_mpll_user_t", "sclk_epll", "sclk_vpll" }; 349 PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m", 350 "sclk_usbphy0", "xxti", "xusbxti", 351 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; 352 PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m", 353 "sclk_usbphy0", "xxti", "xusbxti", 354 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; 355 PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", }; 356 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", }; 357 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", }; 358 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; 359 PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", 360 "none", "sclk_hdmiphy", "sclk_mpll", 361 "sclk_epll", "sclk_vpll" }; 362 PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2", 363 "div_gdl", "div_gpl" }; 364 PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2", 365 "div_gdr", "div_gpr" }; 366 PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m", 367 "sclk_usbphy0", "none", "sclk_hdmiphy", 368 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk", 369 "aclk160", "aclk133", "aclk200", "aclk100", 370 "sclk_mfc", "sclk_g3d", "aclk400_mcuisp", 371 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l", 372 "s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0", 373 "rx_half_byte_clk_csis1", "div_jpeg", 374 "sclk_pwm_isp", "sclk_spi0_isp", 375 "sclk_spi1_isp", "sclk_uart_isp", 376 "sclk_mipihsi", "sclk_hdmi", "sclk_fimd0", 377 "sclk_pcm0" }; 378 PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk", 379 "div_dmc", "div_dphy", "fout_mpll_div_2", 380 "div_pwi", "none", "div_c2c", "div_c2c_aclk" }; 381 PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none", 382 "arm_clk_div_2", "div_corem0", "div_corem1", 383 "div_cores", "div_atb", "div_periph", 384 "div_pclk_dbg", "div_hpm" }; 385 386 /* fixed rate clocks generated outside the soc */ 387 static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { 388 FRATE(CLK_XXTI, "xxti", NULL, 0, 0), 389 FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0), 390 }; 391 392 /* fixed rate clocks generated inside the soc */ 393 static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = { 394 FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000), 395 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000), 396 FRATE(0, "sclk_usbphy0", NULL, 0, 48000000), 397 }; 398 399 static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = { 400 FRATE(0, "sclk_usbphy1", NULL, 0, 48000000), 401 }; 402 403 static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = { 404 FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0), 405 FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0), 406 FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0), 407 FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0), 408 }; 409 410 static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = { 411 FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0), 412 }; 413 414 static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = { 415 FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0), 416 FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0), 417 FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0), 418 FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0), 419 }; 420 421 /* list of mux clocks supported in all exynos4 soc's */ 422 static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = { 423 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 424 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 425 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), 426 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), 427 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), 428 MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, 429 CLK_SET_RATE_PARENT, 0), 430 MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, 431 CLK_SET_RATE_PARENT, 0), 432 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), 433 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), 434 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1), 435 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), 436 437 MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1), 438 MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1), 439 }; 440 441 /* list of mux clocks supported in exynos4210 soc */ 442 static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = { 443 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), 444 }; 445 446 static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = { 447 MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1), 448 MUX(0, "mout_clkout_leftbus", clkout_left_p4210, 449 CLKOUT_CMU_LEFTBUS, 0, 5), 450 451 MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1), 452 MUX(0, "mout_clkout_rightbus", clkout_right_p4210, 453 CLKOUT_CMU_RIGHTBUS, 0, 5), 454 455 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), 456 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), 457 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), 458 MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), 459 MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), 460 MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), 461 MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), 462 MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), 463 MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), 464 MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), 465 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), 466 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), 467 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), 468 MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1), 469 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), 470 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), 471 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), 472 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), 473 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), 474 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), 475 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), 476 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), 477 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), 478 MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), 479 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, 480 CLK_SET_RATE_PARENT, 0), 481 MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), 482 MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), 483 MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), 484 MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), 485 MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), 486 MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), 487 MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), 488 MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), 489 MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), 490 MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), 491 MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), 492 MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), 493 MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), 494 MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), 495 MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), 496 MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), 497 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), 498 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), 499 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), 500 MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5), 501 502 MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4), 503 MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5), 504 505 MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5), 506 }; 507 508 /* list of mux clocks supported in exynos4x12 soc */ 509 static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = { 510 MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1), 511 MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1), 512 MUX(0, "mout_clkout_leftbus", clkout_left_p4x12, 513 CLKOUT_CMU_LEFTBUS, 0, 5), 514 515 MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1), 516 MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1), 517 MUX(0, "mout_clkout_rightbus", clkout_right_p4x12, 518 CLKOUT_CMU_RIGHTBUS, 0, 5), 519 520 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12, 521 SRC_CPU, 24, 1), 522 MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5), 523 524 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), 525 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), 526 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12, 527 SRC_TOP1, 12, 1), 528 MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, 529 SRC_TOP1, 16, 1), 530 MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), 531 MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp", 532 mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1), 533 MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), 534 MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), 535 MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), 536 MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), 537 MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), 538 MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), 539 MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), 540 MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), 541 MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), 542 MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), 543 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), 544 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1), 545 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), 546 MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1), 547 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), 548 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), 549 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), 550 MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), 551 MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), 552 MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), 553 MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), 554 MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), 555 MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), 556 MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, 557 CLK_SET_RATE_PARENT, 0), 558 MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), 559 MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), 560 MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), 561 MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), 562 MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), 563 MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), 564 MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), 565 MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), 566 MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), 567 MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), 568 MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), 569 MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), 570 MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), 571 MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), 572 MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), 573 MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), 574 MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), 575 MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), 576 MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), 577 MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), 578 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), 579 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), 580 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), 581 MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5), 582 583 MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1), 584 MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4), 585 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), 586 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), 587 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), 588 MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5), 589 }; 590 591 /* list of divider clocks supported in all exynos4 soc's */ 592 static const struct samsung_div_clock exynos4_div_clks[] __initconst = { 593 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3), 594 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3), 595 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus", 596 CLKOUT_CMU_LEFTBUS, 8, 6), 597 598 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3), 599 DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3), 600 DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus", 601 CLKOUT_CMU_RIGHTBUS, 8, 6), 602 603 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3), 604 DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3), 605 DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3), 606 DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3), 607 DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3), 608 DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3), 609 DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3), 610 DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), 611 DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3), 612 DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6), 613 614 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), 615 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), 616 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), 617 DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), 618 DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), 619 DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), 620 DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), 621 DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), 622 DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), 623 DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4), 624 DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), 625 DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), 626 DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), 627 DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), 628 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 629 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 630 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 631 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 632 DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), 633 DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), 634 DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), 635 DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), 636 DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), 637 DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), 638 DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), 639 DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), 640 DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), 641 DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), 642 DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), 643 DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8, 644 CLK_SET_RATE_PARENT, 0), 645 DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 646 DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 647 DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), 648 DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), 649 DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), 650 DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), 651 DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), 652 DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), 653 DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), 654 DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), 655 DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), 656 DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), 657 DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), 658 DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 659 DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, 660 CLK_SET_RATE_PARENT, 0), 661 DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, 662 CLK_SET_RATE_PARENT, 0), 663 DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, 664 CLK_SET_RATE_PARENT, 0), 665 DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, 666 CLK_SET_RATE_PARENT, 0), 667 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, 668 CLK_SET_RATE_PARENT, 0), 669 DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6), 670 671 DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3), 672 DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3), 673 DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3), 674 DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3), 675 DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3), 676 DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3), 677 DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4), 678 DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6), 679 }; 680 681 /* list of divider clocks supported in exynos4210 soc */ 682 static const struct samsung_div_clock exynos4210_div_clks[] __initconst = { 683 DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), 684 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), 685 DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), 686 DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), 687 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 688 DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, 689 CLK_SET_RATE_PARENT, 0), 690 }; 691 692 /* list of divider clocks supported in exynos4x12 soc */ 693 static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { 694 DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), 695 DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), 696 DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), 697 DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), 698 DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), 699 DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), 700 DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), 701 DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", 702 DIV_TOP, 24, 3), 703 DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), 704 DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), 705 DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), 706 DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), 707 DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), 708 DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), 709 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 710 DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), 711 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), 712 }; 713 714 /* list of gate clocks supported in all exynos4 soc's */ 715 static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = { 716 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0), 717 GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0), 718 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), 719 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 720 0), 721 GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), 722 GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), 723 GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), 724 GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), 725 GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), 726 GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), 727 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 728 0), 729 GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), 730 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), 731 GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0), 732 GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0), 733 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), 734 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), 735 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), 736 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), 737 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), 738 GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0), 739 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), 740 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, 741 CLK_SET_RATE_PARENT, 0), 742 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, 743 CLK_SET_RATE_PARENT, 0), 744 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0", 745 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), 746 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, 747 CLK_SET_RATE_PARENT, 0), 748 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, 749 CLK_SET_RATE_PARENT, 0), 750 GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0), 751 GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), 752 GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), 753 GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0), 754 GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0), 755 GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0), 756 GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0, 757 CLK_SET_RATE_PARENT, 0), 758 GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4, 759 CLK_SET_RATE_PARENT, 0), 760 GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8, 761 CLK_SET_RATE_PARENT, 0), 762 GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12, 763 CLK_SET_RATE_PARENT, 0), 764 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24, 765 CLK_SET_RATE_PARENT, 0), 766 GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28, 767 CLK_SET_RATE_PARENT, 0), 768 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0, 769 CLK_SET_RATE_PARENT, 0), 770 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, 771 CLK_SET_RATE_PARENT, 0), 772 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4, 773 CLK_SET_RATE_PARENT, 0), 774 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8, 775 CLK_SET_RATE_PARENT, 0), 776 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12, 777 CLK_SET_RATE_PARENT, 0), 778 GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16, 779 CLK_SET_RATE_PARENT, 0), 780 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0, 781 CLK_SET_RATE_PARENT, 0), 782 GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4, 783 CLK_SET_RATE_PARENT, 0), 784 GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8, 785 CLK_SET_RATE_PARENT, 0), 786 GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12, 787 CLK_SET_RATE_PARENT, 0), 788 GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16, 789 CLK_SET_RATE_PARENT, 0), 790 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, 791 CLK_SET_RATE_PARENT, 0), 792 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16, 793 CLK_SET_RATE_PARENT, 0), 794 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20, 795 CLK_SET_RATE_PARENT, 0), 796 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24, 797 CLK_SET_RATE_PARENT, 0), 798 GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0, 799 0, 0), 800 GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1, 801 0, 0), 802 GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2, 803 0, 0), 804 GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3, 805 0, 0), 806 GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4, 807 0, 0), 808 GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5, 809 0, 0), 810 GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7, 811 0, 0), 812 GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8, 813 0, 0), 814 GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9, 815 0, 0), 816 GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10, 817 0, 0), 818 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, 819 0, 0), 820 GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0), 821 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), 822 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), 823 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4, 824 0, 0), 825 GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0), 826 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0), 827 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1, 828 0, 0), 829 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2, 830 0, 0), 831 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0), 832 GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0), 833 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0, 834 0, 0), 835 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4, 836 0, 0), 837 GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0), 838 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0, 839 0, 0), 840 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1, 841 0, 0), 842 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5, 843 0, 0), 844 GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6, 845 0, 0), 846 GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7, 847 0, 0), 848 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8, 849 0, 0), 850 GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0), 851 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0, 852 0, 0), 853 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1, 854 0, 0), 855 GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2, 856 0, 0), 857 GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3, 858 0, 0), 859 GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4, 860 0, 0), 861 GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6, 862 0, 0), 863 GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7, 864 0, 0), 865 GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8, 866 0, 0), 867 GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9, 868 0, 0), 869 GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10, 870 0, 0), 871 GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11, 872 0, 0), 873 GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12, 874 0, 0), 875 GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13, 876 0, 0), 877 GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14, 878 0, 0), 879 GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16, 880 0, 0), 881 GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17, 882 0, 0), 883 GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18, 884 0, 0), 885 GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20, 886 0, 0), 887 GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21, 888 0, 0), 889 GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22, 890 0, 0), 891 GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23, 892 0, 0), 893 GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26, 894 0, 0), 895 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27, 896 0, 0), 897 GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0), 898 GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0), 899 GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0), 900 GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0), 901 GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0), 902 903 GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus", 904 CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0), 905 GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus", 906 CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0), 907 GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top", 908 CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0), 909 GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc", 910 CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0), 911 GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu", 912 CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0), 913 }; 914 915 /* list of gate clocks supported in exynos4210 soc */ 916 static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = { 917 GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), 918 GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), 919 GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), 920 GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), 921 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), 922 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 923 0), 924 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0, 925 0), 926 GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0), 927 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), 928 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), 929 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), 930 GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), 931 GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), 932 GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), 933 GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), 934 GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 935 CLK_IGNORE_UNUSED, 0), 936 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 937 0), 938 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200", 939 E4210_GATE_IP_IMAGE, 4, 0, 0), 940 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1", 941 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), 942 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata", 943 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 944 GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), 945 GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), 946 GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15, 947 0, 0), 948 GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 949 0, 0), 950 GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 951 0, 0), 952 GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 953 0, 0), 954 GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 955 0, 0), 956 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, 957 CLK_SET_RATE_PARENT, 0), 958 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 959 0), 960 }; 961 962 /* list of gate clocks supported in exynos4x12 soc */ 963 static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { 964 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), 965 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), 966 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), 967 GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), 968 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 969 0), 970 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0, 971 0), 972 GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0), 973 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 974 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), 975 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 976 CLK_IGNORE_UNUSED, 0), 977 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 978 0), 979 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0", 980 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), 981 GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", 982 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), 983 GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi", 984 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 985 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200", 986 E4X12_GATE_IP_IMAGE, 4, 0, 0), 987 GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 988 0, 0), 989 GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 990 0, 0), 991 GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0), 992 GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp", 993 E4X12_GATE_IP_ISP, 0, 0, 0), 994 GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre", 995 E4X12_GATE_IP_ISP, 1, 0, 0), 996 GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre", 997 E4X12_GATE_IP_ISP, 2, 0, 0), 998 GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp", 999 E4X12_GATE_IP_ISP, 3, 0, 0), 1000 GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0), 1001 GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2, 1002 0, 0), 1003 GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 1004 0, 0), 1005 GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), 1006 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0), 1007 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 1008 0), 1009 }; 1010 1011 /* 1012 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit 1013 * resides in chipid register space, outside of the clock controller memory 1014 * mapped space. So to determine the parent of fin_pll clock, the chipid 1015 * controller is first remapped and the value of XOM[0] bit is read to 1016 * determine the parent clock. 1017 */ 1018 static unsigned long __init exynos4_get_xom(void) 1019 { 1020 unsigned long xom = 0; 1021 void __iomem *chipid_base; 1022 struct device_node *np; 1023 1024 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid"); 1025 if (np) { 1026 chipid_base = of_iomap(np, 0); 1027 1028 if (chipid_base) 1029 xom = readl(chipid_base + 8); 1030 1031 iounmap(chipid_base); 1032 of_node_put(np); 1033 } 1034 1035 return xom; 1036 } 1037 1038 static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) 1039 { 1040 struct samsung_fixed_rate_clock fclk; 1041 struct clk *clk; 1042 unsigned long finpll_f = 24000000; 1043 char *parent_name; 1044 unsigned int xom = exynos4_get_xom(); 1045 1046 parent_name = xom & 1 ? "xusbxti" : "xxti"; 1047 clk = clk_get(NULL, parent_name); 1048 if (IS_ERR(clk)) { 1049 pr_err("%s: failed to lookup parent clock %s, assuming " 1050 "fin_pll clock frequency is 24MHz\n", __func__, 1051 parent_name); 1052 } else { 1053 finpll_f = clk_get_rate(clk); 1054 } 1055 1056 fclk.id = CLK_FIN_PLL; 1057 fclk.name = "fin_pll"; 1058 fclk.parent_name = NULL; 1059 fclk.flags = 0; 1060 fclk.fixed_rate = finpll_f; 1061 samsung_clk_register_fixed_rate(ctx, &fclk, 1); 1062 1063 } 1064 1065 static const struct of_device_id ext_clk_match[] __initconst = { 1066 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 1067 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, 1068 {}, 1069 }; 1070 1071 /* PLLs PMS values */ 1072 static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = { 1073 PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28), 1074 PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28), 1075 PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28), 1076 PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13), 1077 PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13), 1078 PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5), 1079 PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28), 1080 PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28), 1081 PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28), 1082 { /* sentinel */ } 1083 }; 1084 1085 static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = { 1086 PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0), 1087 PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0), 1088 PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1, 0, 0), 1089 PLL_4600_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710, 1), 1090 PLL_4600_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762, 1), 1091 PLL_4600_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961, 0), 1092 PLL_4600_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381, 0), 1093 { /* sentinel */ } 1094 }; 1095 1096 static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = { 1097 PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0), 1098 PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1, 1, 1), 1099 PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1), 1100 PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0), 1101 PLL_4650_RATE(24 * MHZ, 55360351, 53, 3, 3, 2417, 0, 17, 0), 1102 { /* sentinel */ } 1103 }; 1104 1105 static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = { 1106 PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0), 1107 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 1108 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 1109 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 1110 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 1111 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0), 1112 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0), 1113 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0), 1114 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0), 1115 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0), 1116 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 1117 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1), 1118 PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1), 1119 PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1), 1120 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2), 1121 PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2), 1122 { /* sentinel */ } 1123 }; 1124 1125 static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = { 1126 PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690), 1127 PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0), 1128 PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381), 1129 PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0), 1130 PLL_36XX_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710), 1131 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762), 1132 PLL_36XX_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961), 1133 PLL_36XX_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381), 1134 { /* sentinel */ } 1135 }; 1136 1137 static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = { 1138 PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384), 1139 PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1, 0), 1140 PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2, 0), 1141 PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2, 0), 1142 PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0), 1143 PLL_36XX_RATE(24 * MHZ, 106031250, 53, 3, 2, 1024), 1144 PLL_36XX_RATE(24 * MHZ, 53015625, 53, 3, 3, 1024), 1145 { /* sentinel */ } 1146 }; 1147 1148 static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { 1149 [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll", 1150 APLL_LOCK, APLL_CON0, NULL), 1151 [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 1152 E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL), 1153 [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 1154 EPLL_LOCK, EPLL_CON0, NULL), 1155 [vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc", 1156 VPLL_LOCK, VPLL_CON0, NULL), 1157 }; 1158 1159 static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { 1160 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 1161 APLL_LOCK, APLL_CON0, NULL), 1162 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 1163 E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL), 1164 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 1165 EPLL_LOCK, EPLL_CON0, NULL), 1166 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", 1167 VPLL_LOCK, VPLL_CON0, NULL), 1168 }; 1169 1170 static void __init exynos4x12_core_down_clock(void) 1171 { 1172 unsigned int tmp; 1173 1174 /* 1175 * Enable arm clock down (in idle) and set arm divider 1176 * ratios in WFI/WFE state. 1177 */ 1178 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) | 1179 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN | 1180 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE | 1181 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI); 1182 /* On Exynos4412 enable it also on core 2 and 3 */ 1183 if (num_possible_cpus() == 4) 1184 tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE | 1185 PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI; 1186 writel_relaxed(tmp, reg_base + PWR_CTRL1); 1187 1188 /* 1189 * Disable the clock up feature in case it was enabled by bootloader. 1190 */ 1191 writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2); 1192 } 1193 1194 #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \ 1195 (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1196 ((periph) << 12) | ((corem1) << 8) | ((corem0) << 4)) 1197 #define E4210_CPU_DIV1(hpm, copy) \ 1198 (((hpm) << 4) | ((copy) << 0)) 1199 1200 static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { 1201 { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), }, 1202 { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), }, 1203 { 800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, 1204 { 500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, 1205 { 400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, 1206 { 200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), }, 1207 { 0 }, 1208 }; 1209 1210 #define E4412_CPU_DIV1(cores, hpm, copy) \ 1211 (((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) 1212 1213 static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { 1214 { 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), }, 1215 { 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, 1216 { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, 1217 { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), }, 1218 { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), }, 1219 { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), }, 1220 { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), }, 1221 { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), }, 1222 { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), }, 1223 { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), }, 1224 { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), }, 1225 { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, 1226 { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, 1227 { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, 1228 { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, 1229 { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), }, 1230 { 0 }, 1231 }; 1232 1233 /* register exynos4 clocks */ 1234 static void __init exynos4_clk_init(struct device_node *np, 1235 enum exynos4_soc soc) 1236 { 1237 struct samsung_clk_provider *ctx; 1238 exynos4_soc = soc; 1239 1240 reg_base = of_iomap(np, 0); 1241 if (!reg_base) 1242 panic("%s: failed to map registers\n", __func__); 1243 1244 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1245 1246 samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks, 1247 ARRAY_SIZE(exynos4_fixed_rate_ext_clks), 1248 ext_clk_match); 1249 1250 exynos4_clk_register_finpll(ctx); 1251 1252 if (exynos4_soc == EXYNOS4210) { 1253 samsung_clk_register_mux(ctx, exynos4210_mux_early, 1254 ARRAY_SIZE(exynos4210_mux_early)); 1255 1256 if (_get_rate("fin_pll") == 24000000) { 1257 exynos4210_plls[apll].rate_table = 1258 exynos4210_apll_rates; 1259 exynos4210_plls[epll].rate_table = 1260 exynos4210_epll_rates; 1261 } 1262 1263 if (_get_rate("mout_vpllsrc") == 24000000) 1264 exynos4210_plls[vpll].rate_table = 1265 exynos4210_vpll_rates; 1266 1267 samsung_clk_register_pll(ctx, exynos4210_plls, 1268 ARRAY_SIZE(exynos4210_plls), reg_base); 1269 } else { 1270 if (_get_rate("fin_pll") == 24000000) { 1271 exynos4x12_plls[apll].rate_table = 1272 exynos4x12_apll_rates; 1273 exynos4x12_plls[epll].rate_table = 1274 exynos4x12_epll_rates; 1275 exynos4x12_plls[vpll].rate_table = 1276 exynos4x12_vpll_rates; 1277 } 1278 1279 samsung_clk_register_pll(ctx, exynos4x12_plls, 1280 ARRAY_SIZE(exynos4x12_plls), reg_base); 1281 } 1282 1283 samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks, 1284 ARRAY_SIZE(exynos4_fixed_rate_clks)); 1285 samsung_clk_register_mux(ctx, exynos4_mux_clks, 1286 ARRAY_SIZE(exynos4_mux_clks)); 1287 samsung_clk_register_div(ctx, exynos4_div_clks, 1288 ARRAY_SIZE(exynos4_div_clks)); 1289 samsung_clk_register_gate(ctx, exynos4_gate_clks, 1290 ARRAY_SIZE(exynos4_gate_clks)); 1291 samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks, 1292 ARRAY_SIZE(exynos4_fixed_factor_clks)); 1293 1294 if (exynos4_soc == EXYNOS4210) { 1295 samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks, 1296 ARRAY_SIZE(exynos4210_fixed_rate_clks)); 1297 samsung_clk_register_mux(ctx, exynos4210_mux_clks, 1298 ARRAY_SIZE(exynos4210_mux_clks)); 1299 samsung_clk_register_div(ctx, exynos4210_div_clks, 1300 ARRAY_SIZE(exynos4210_div_clks)); 1301 samsung_clk_register_gate(ctx, exynos4210_gate_clks, 1302 ARRAY_SIZE(exynos4210_gate_clks)); 1303 samsung_clk_register_fixed_factor(ctx, 1304 exynos4210_fixed_factor_clks, 1305 ARRAY_SIZE(exynos4210_fixed_factor_clks)); 1306 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1307 mout_core_p4210[0], mout_core_p4210[1], 0x14200, 1308 e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), 1309 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); 1310 } else { 1311 samsung_clk_register_mux(ctx, exynos4x12_mux_clks, 1312 ARRAY_SIZE(exynos4x12_mux_clks)); 1313 samsung_clk_register_div(ctx, exynos4x12_div_clks, 1314 ARRAY_SIZE(exynos4x12_div_clks)); 1315 samsung_clk_register_gate(ctx, exynos4x12_gate_clks, 1316 ARRAY_SIZE(exynos4x12_gate_clks)); 1317 samsung_clk_register_fixed_factor(ctx, 1318 exynos4x12_fixed_factor_clks, 1319 ARRAY_SIZE(exynos4x12_fixed_factor_clks)); 1320 1321 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1322 mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, 1323 e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d), 1324 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); 1325 } 1326 1327 if (soc == EXYNOS4X12) 1328 exynos4x12_core_down_clock(); 1329 1330 samsung_clk_extended_sleep_init(reg_base, 1331 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), 1332 src_mask_suspend, ARRAY_SIZE(src_mask_suspend)); 1333 if (exynos4_soc == EXYNOS4210) 1334 samsung_clk_extended_sleep_init(reg_base, 1335 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save), 1336 src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210)); 1337 else 1338 samsung_clk_sleep_init(reg_base, exynos4x12_clk_save, 1339 ARRAY_SIZE(exynos4x12_clk_save)); 1340 1341 samsung_clk_of_add_provider(np, ctx); 1342 1343 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" 1344 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", 1345 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", 1346 _get_rate("sclk_apll"), _get_rate("sclk_mpll"), 1347 _get_rate("sclk_epll"), _get_rate("sclk_vpll"), 1348 _get_rate("div_core2")); 1349 } 1350 1351 1352 static void __init exynos4210_clk_init(struct device_node *np) 1353 { 1354 exynos4_clk_init(np, EXYNOS4210); 1355 } 1356 CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init); 1357 1358 static void __init exynos4412_clk_init(struct device_node *np) 1359 { 1360 exynos4_clk_init(np, EXYNOS4X12); 1361 } 1362 CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init); 1363