1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Common Clock Framework support for Exynos3250 SoC. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/clkdev.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/platform_device.h> 17 #include <linux/syscore_ops.h> 18 19 #include <dt-bindings/clock/exynos3250.h> 20 21 #include "clk.h" 22 #include "clk-pll.h" 23 24 #define SRC_LEFTBUS 0x4200 25 #define DIV_LEFTBUS 0x4500 26 #define GATE_IP_LEFTBUS 0x4800 27 #define SRC_RIGHTBUS 0x8200 28 #define DIV_RIGHTBUS 0x8500 29 #define GATE_IP_RIGHTBUS 0x8800 30 #define GATE_IP_PERIR 0x8960 31 #define MPLL_LOCK 0xc010 32 #define MPLL_CON0 0xc110 33 #define VPLL_LOCK 0xc020 34 #define VPLL_CON0 0xc120 35 #define UPLL_LOCK 0xc030 36 #define UPLL_CON0 0xc130 37 #define SRC_TOP0 0xc210 38 #define SRC_TOP1 0xc214 39 #define SRC_CAM 0xc220 40 #define SRC_MFC 0xc228 41 #define SRC_G3D 0xc22c 42 #define SRC_LCD 0xc234 43 #define SRC_ISP 0xc238 44 #define SRC_FSYS 0xc240 45 #define SRC_PERIL0 0xc250 46 #define SRC_PERIL1 0xc254 47 #define SRC_MASK_TOP 0xc310 48 #define SRC_MASK_CAM 0xc320 49 #define SRC_MASK_LCD 0xc334 50 #define SRC_MASK_ISP 0xc338 51 #define SRC_MASK_FSYS 0xc340 52 #define SRC_MASK_PERIL0 0xc350 53 #define SRC_MASK_PERIL1 0xc354 54 #define DIV_TOP 0xc510 55 #define DIV_CAM 0xc520 56 #define DIV_MFC 0xc528 57 #define DIV_G3D 0xc52c 58 #define DIV_LCD 0xc534 59 #define DIV_ISP 0xc538 60 #define DIV_FSYS0 0xc540 61 #define DIV_FSYS1 0xc544 62 #define DIV_FSYS2 0xc548 63 #define DIV_PERIL0 0xc550 64 #define DIV_PERIL1 0xc554 65 #define DIV_PERIL3 0xc55c 66 #define DIV_PERIL4 0xc560 67 #define DIV_PERIL5 0xc564 68 #define DIV_CAM1 0xc568 69 #define CLKDIV2_RATIO 0xc580 70 #define GATE_SCLK_CAM 0xc820 71 #define GATE_SCLK_MFC 0xc828 72 #define GATE_SCLK_G3D 0xc82c 73 #define GATE_SCLK_LCD 0xc834 74 #define GATE_SCLK_ISP_TOP 0xc838 75 #define GATE_SCLK_FSYS 0xc840 76 #define GATE_SCLK_PERIL 0xc850 77 #define GATE_IP_CAM 0xc920 78 #define GATE_IP_MFC 0xc928 79 #define GATE_IP_G3D 0xc92c 80 #define GATE_IP_LCD 0xc934 81 #define GATE_IP_ISP 0xc938 82 #define GATE_IP_FSYS 0xc940 83 #define GATE_IP_PERIL 0xc950 84 #define GATE_BLOCK 0xc970 85 #define APLL_LOCK 0x14000 86 #define APLL_CON0 0x14100 87 #define SRC_CPU 0x14200 88 #define DIV_CPU0 0x14500 89 #define DIV_CPU1 0x14504 90 #define PWR_CTRL1 0x15020 91 #define PWR_CTRL2 0x15024 92 93 /* Below definitions are used for PWR_CTRL settings */ 94 #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28) 95 #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16) 96 #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) 97 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) 98 #define PWR_CTRL1_USE_CORE3_WFE (1 << 7) 99 #define PWR_CTRL1_USE_CORE2_WFE (1 << 6) 100 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5) 101 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4) 102 #define PWR_CTRL1_USE_CORE3_WFI (1 << 3) 103 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2) 104 #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) 105 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) 106 107 static unsigned long exynos3250_cmu_clk_regs[] __initdata = { 108 SRC_LEFTBUS, 109 DIV_LEFTBUS, 110 GATE_IP_LEFTBUS, 111 SRC_RIGHTBUS, 112 DIV_RIGHTBUS, 113 GATE_IP_RIGHTBUS, 114 GATE_IP_PERIR, 115 MPLL_LOCK, 116 MPLL_CON0, 117 VPLL_LOCK, 118 VPLL_CON0, 119 UPLL_LOCK, 120 UPLL_CON0, 121 SRC_TOP0, 122 SRC_TOP1, 123 SRC_CAM, 124 SRC_MFC, 125 SRC_G3D, 126 SRC_LCD, 127 SRC_ISP, 128 SRC_FSYS, 129 SRC_PERIL0, 130 SRC_PERIL1, 131 SRC_MASK_TOP, 132 SRC_MASK_CAM, 133 SRC_MASK_LCD, 134 SRC_MASK_ISP, 135 SRC_MASK_FSYS, 136 SRC_MASK_PERIL0, 137 SRC_MASK_PERIL1, 138 DIV_TOP, 139 DIV_CAM, 140 DIV_MFC, 141 DIV_G3D, 142 DIV_LCD, 143 DIV_ISP, 144 DIV_FSYS0, 145 DIV_FSYS1, 146 DIV_FSYS2, 147 DIV_PERIL0, 148 DIV_PERIL1, 149 DIV_PERIL3, 150 DIV_PERIL4, 151 DIV_PERIL5, 152 DIV_CAM1, 153 CLKDIV2_RATIO, 154 GATE_SCLK_CAM, 155 GATE_SCLK_MFC, 156 GATE_SCLK_G3D, 157 GATE_SCLK_LCD, 158 GATE_SCLK_ISP_TOP, 159 GATE_SCLK_FSYS, 160 GATE_SCLK_PERIL, 161 GATE_IP_CAM, 162 GATE_IP_MFC, 163 GATE_IP_G3D, 164 GATE_IP_LCD, 165 GATE_IP_ISP, 166 GATE_IP_FSYS, 167 GATE_IP_PERIL, 168 GATE_BLOCK, 169 APLL_LOCK, 170 SRC_CPU, 171 DIV_CPU0, 172 DIV_CPU1, 173 PWR_CTRL1, 174 PWR_CTRL2, 175 }; 176 177 /* list of all parent clock list */ 178 PNAME(mout_vpllsrc_p) = { "fin_pll", }; 179 180 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 181 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; 182 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", }; 183 PNAME(mout_upll_p) = { "fin_pll", "fout_upll", }; 184 185 PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", }; 186 PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", }; 187 PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", }; 188 PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", }; 189 190 PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", }; 191 PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_vpll", }; 192 193 PNAME(mout_gdl_p) = { "mout_mpll_user_l", }; 194 PNAME(mout_gdr_p) = { "mout_mpll_user_r", }; 195 196 PNAME(mout_aclk_400_mcuisp_sub_p) 197 = { "fin_pll", "div_aclk_400_mcuisp", }; 198 PNAME(mout_aclk_266_0_p) = { "div_mpll_pre", "mout_vpll", }; 199 PNAME(mout_aclk_266_1_p) = { "mout_epll_user", }; 200 PNAME(mout_aclk_266_p) = { "mout_aclk_266_0", "mout_aclk_266_1", }; 201 PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", }; 202 203 PNAME(group_div_mpll_pre_p) = { "div_mpll_pre", }; 204 PNAME(group_epll_vpll_p) = { "mout_epll_user", "mout_vpll" }; 205 PNAME(group_sclk_p) = { "xxti", "xusbxti", 206 "none", "none", 207 "none", "none", "div_mpll_pre", 208 "mout_epll_user", "mout_vpll", }; 209 PNAME(group_sclk_audio_p) = { "audiocdclk", "none", 210 "none", "none", 211 "xxti", "xusbxti", 212 "div_mpll_pre", "mout_epll_user", 213 "mout_vpll", }; 214 PNAME(group_sclk_cam_blk_p) = { "xxti", "xusbxti", 215 "none", "none", "none", 216 "none", "div_mpll_pre", 217 "mout_epll_user", "mout_vpll", 218 "none", "none", "none", 219 "div_cam_blk_320", }; 220 PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti", 221 "m_bitclkhsdiv4_2l", "none", 222 "none", "none", "div_mpll_pre", 223 "mout_epll_user", "mout_vpll", 224 "none", "none", "none", 225 "div_lcd_blk_145", }; 226 227 PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" }; 228 PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" }; 229 230 static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = { 231 FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0), 232 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0), 233 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0), 234 FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0), 235 FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0), 236 237 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */ 238 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0), 239 }; 240 241 static struct samsung_mux_clock mux_clks[] __initdata = { 242 /* 243 * NOTE: Following table is sorted by register address in ascending 244 * order and then bitfield shift in descending order, as it is done 245 * in the User's Manual. When adding new entries, please make sure 246 * that the order is preserved, to avoid merge conflicts and make 247 * further work with defined data easier. 248 */ 249 250 /* SRC_LEFTBUS */ 251 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p, 252 SRC_LEFTBUS, 4, 1), 253 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1), 254 255 /* SRC_RIGHTBUS */ 256 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p, 257 SRC_RIGHTBUS, 4, 1), 258 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1), 259 260 /* SRC_TOP0 */ 261 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1), 262 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1), 263 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1), 264 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1), 265 MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1), 266 MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1), 267 MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1), 268 MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1), 269 MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1), 270 MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1), 271 272 /* SRC_TOP1 */ 273 MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1), 274 MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p, 275 SRC_TOP1, 24, 1), 276 MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1), 277 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1), 278 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1), 279 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), 280 281 /* SRC_CAM */ 282 MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4), 283 MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4), 284 285 /* SRC_MFC */ 286 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), 287 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1), 288 MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1), 289 290 /* SRC_G3D */ 291 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1), 292 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1), 293 MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1), 294 295 /* SRC_LCD */ 296 MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4), 297 MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4), 298 299 /* SRC_ISP */ 300 MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4), 301 MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4), 302 MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4), 303 304 /* SRC_FSYS */ 305 MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4), 306 MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4), 307 MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), 308 309 /* SRC_PERIL0 */ 310 MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4), 311 MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4), 312 313 /* SRC_PERIL1 */ 314 MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4), 315 MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4), 316 MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4), 317 318 /* SRC_CPU */ 319 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p, 320 SRC_CPU, 24, 1), 321 MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1), 322 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1), 323 MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), 324 }; 325 326 static struct samsung_div_clock div_clks[] __initdata = { 327 /* 328 * NOTE: Following table is sorted by register address in ascending 329 * order and then bitfield shift in descending order, as it is done 330 * in the User's Manual. When adding new entries, please make sure 331 * that the order is preserved, to avoid merge conflicts and make 332 * further work with defined data easier. 333 */ 334 335 /* DIV_LEFTBUS */ 336 DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3), 337 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4), 338 339 /* DIV_RIGHTBUS */ 340 DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3), 341 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4), 342 343 /* DIV_TOP */ 344 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2), 345 DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp", 346 "mout_aclk_400_mcuisp", DIV_TOP, 24, 3), 347 DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3), 348 DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3), 349 DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3), 350 DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4), 351 DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3), 352 353 /* DIV_CAM */ 354 DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), 355 DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4), 356 357 /* DIV_MFC */ 358 DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4), 359 360 /* DIV_G3D */ 361 DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4), 362 363 /* DIV_LCD */ 364 DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4, 365 CLK_SET_RATE_PARENT, 0), 366 DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4), 367 DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4), 368 369 /* DIV_ISP */ 370 DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4), 371 DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp", 372 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0), 373 DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4), 374 DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp", 375 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0), 376 DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4), 377 378 /* DIV_FSYS0 */ 379 DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8, 380 CLK_SET_RATE_PARENT, 0), 381 DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4), 382 383 /* DIV_FSYS1 */ 384 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8, 385 CLK_SET_RATE_PARENT, 0), 386 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 387 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8, 388 CLK_SET_RATE_PARENT, 0), 389 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 390 391 /* DIV_PERIL0 */ 392 DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 393 DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 394 395 /* DIV_PERIL1 */ 396 DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8, 397 CLK_SET_RATE_PARENT, 0), 398 DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), 399 DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8, 400 CLK_SET_RATE_PARENT, 0), 401 DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), 402 403 /* DIV_PERIL4 */ 404 DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8), 405 DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4), 406 407 /* DIV_PERIL5 */ 408 DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6), 409 410 /* DIV_CPU0 */ 411 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3), 412 DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3), 413 DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3), 414 DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3), 415 DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3), 416 DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3), 417 418 /* DIV_CPU1 */ 419 DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3), 420 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), 421 }; 422 423 static struct samsung_gate_clock gate_clks[] __initdata = { 424 /* 425 * NOTE: Following table is sorted by register address in ascending 426 * order and then bitfield shift in descending order, as it is done 427 * in the User's Manual. When adding new entries, please make sure 428 * that the order is preserved, to avoid merge conflicts and make 429 * further work with defined data easier. 430 */ 431 432 /* GATE_IP_LEFTBUS */ 433 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6, 434 CLK_IGNORE_UNUSED, 0), 435 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4, 436 CLK_IGNORE_UNUSED, 0), 437 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1, 438 CLK_IGNORE_UNUSED, 0), 439 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0, 440 CLK_IGNORE_UNUSED, 0), 441 442 /* GATE_IP_RIGHTBUS */ 443 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100", 444 GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0), 445 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100", 446 GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0), 447 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100", 448 GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0), 449 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2, 450 CLK_IGNORE_UNUSED, 0), 451 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1, 452 CLK_IGNORE_UNUSED, 0), 453 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0, 454 CLK_IGNORE_UNUSED, 0), 455 456 /* GATE_IP_PERIR */ 457 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22, 458 CLK_IGNORE_UNUSED, 0), 459 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21, 460 CLK_IGNORE_UNUSED, 0), 461 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100", 462 GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0), 463 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100", 464 GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0), 465 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18, 466 CLK_IGNORE_UNUSED, 0), 467 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100", 468 GATE_IP_PERIR, 17, 0, 0), 469 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0), 470 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0), 471 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0), 472 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0), 473 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12, 474 CLK_IGNORE_UNUSED, 0), 475 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10, 476 CLK_IGNORE_UNUSED, 0), 477 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9, 478 CLK_IGNORE_UNUSED, 0), 479 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8, 480 CLK_IGNORE_UNUSED, 0), 481 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7, 482 CLK_IGNORE_UNUSED, 0), 483 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6, 484 CLK_IGNORE_UNUSED, 0), 485 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5, 486 CLK_IGNORE_UNUSED, 0), 487 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4, 488 CLK_IGNORE_UNUSED, 0), 489 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3, 490 CLK_IGNORE_UNUSED, 0), 491 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2, 492 CLK_IGNORE_UNUSED, 0), 493 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1, 494 CLK_IGNORE_UNUSED, 0), 495 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0, 496 CLK_IGNORE_UNUSED, 0), 497 498 /* GATE_SCLK_CAM */ 499 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk", 500 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0), 501 GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk", 502 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0), 503 GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk", 504 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0), 505 GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk", 506 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0), 507 508 /* GATE_SCLK_MFC */ 509 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc", 510 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0), 511 512 /* GATE_SCLK_G3D */ 513 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", 514 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0), 515 516 /* GATE_SCLK_LCD */ 517 GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0", 518 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0), 519 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre", 520 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0), 521 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", 522 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0), 523 524 /* GATE_SCLK_ISP_TOP */ 525 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", 526 GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0), 527 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp", 528 GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0), 529 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp", 530 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0), 531 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp", 532 GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0), 533 534 /* GATE_SCLK_FSYS */ 535 GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0), 536 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre", 537 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 538 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi", 539 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0), 540 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre", 541 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 542 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre", 543 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 544 545 /* GATE_SCLK_PERIL */ 546 GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s", 547 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0), 548 GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm", 549 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0), 550 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre", 551 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0), 552 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre", 553 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0), 554 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", 555 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0), 556 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", 557 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0), 558 559 /* GATE_IP_CAM */ 560 GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19, 561 CLK_IGNORE_UNUSED, 0), 562 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320", 563 GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0), 564 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320", 565 GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0), 566 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320", 567 GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0), 568 GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320", 569 GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0), 570 GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320", 571 GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0), 572 GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320", 573 GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0), 574 GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320", 575 GATE_IP_CAM, 11, 0, 0), 576 GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320", 577 GATE_IP_CAM, 9, 0, 0), 578 GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320", 579 GATE_IP_CAM, 8, 0, 0), 580 GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320", 581 GATE_IP_CAM, 7, 0, 0), 582 GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0), 583 GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320", 584 GATE_IP_CAM, 2, 0, 0), 585 GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0), 586 GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0), 587 588 /* GATE_IP_MFC */ 589 GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5, 590 CLK_IGNORE_UNUSED, 0), 591 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3, 592 CLK_IGNORE_UNUSED, 0), 593 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0), 594 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0), 595 596 /* GATE_IP_G3D */ 597 GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0), 598 GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2, 599 CLK_IGNORE_UNUSED, 0), 600 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1, 601 CLK_IGNORE_UNUSED, 0), 602 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0), 603 604 /* GATE_IP_LCD */ 605 GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7, 606 CLK_IGNORE_UNUSED, 0), 607 GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6, 608 CLK_IGNORE_UNUSED, 0), 609 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5, 610 CLK_IGNORE_UNUSED, 0), 611 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0), 612 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0), 613 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0), 614 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0), 615 616 /* GATE_IP_ISP */ 617 GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0), 618 GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub", 619 GATE_IP_ISP, 3, 0, 0), 620 GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub", 621 GATE_IP_ISP, 2, 0, 0), 622 GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub", 623 GATE_IP_ISP, 1, 0, 0), 624 625 /* GATE_IP_FSYS */ 626 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0), 627 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17, 628 CLK_IGNORE_UNUSED, 0), 629 GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0), 630 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0), 631 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0), 632 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0), 633 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0), 634 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0), 635 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0), 636 637 /* GATE_IP_PERIL */ 638 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0), 639 GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0), 640 GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0), 641 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0), 642 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0), 643 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0), 644 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0), 645 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0), 646 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0), 647 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0), 648 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0), 649 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0), 650 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0), 651 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0), 652 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0), 653 }; 654 655 /* APLL & MPLL & BPLL & UPLL */ 656 static struct samsung_pll_rate_table exynos3250_pll_rates[] = { 657 PLL_35XX_RATE(1200000000, 400, 4, 1), 658 PLL_35XX_RATE(1100000000, 275, 3, 1), 659 PLL_35XX_RATE(1066000000, 533, 6, 1), 660 PLL_35XX_RATE(1000000000, 250, 3, 1), 661 PLL_35XX_RATE( 960000000, 320, 4, 1), 662 PLL_35XX_RATE( 900000000, 300, 4, 1), 663 PLL_35XX_RATE( 850000000, 425, 6, 1), 664 PLL_35XX_RATE( 800000000, 200, 3, 1), 665 PLL_35XX_RATE( 700000000, 175, 3, 1), 666 PLL_35XX_RATE( 667000000, 667, 12, 1), 667 PLL_35XX_RATE( 600000000, 400, 4, 2), 668 PLL_35XX_RATE( 533000000, 533, 6, 2), 669 PLL_35XX_RATE( 520000000, 260, 3, 2), 670 PLL_35XX_RATE( 500000000, 250, 3, 2), 671 PLL_35XX_RATE( 400000000, 200, 3, 2), 672 PLL_35XX_RATE( 200000000, 200, 3, 3), 673 PLL_35XX_RATE( 100000000, 200, 3, 4), 674 { /* sentinel */ } 675 }; 676 677 /* EPLL */ 678 static struct samsung_pll_rate_table exynos3250_epll_rates[] = { 679 PLL_36XX_RATE(800000000, 200, 3, 1, 0), 680 PLL_36XX_RATE(288000000, 96, 2, 2, 0), 681 PLL_36XX_RATE(192000000, 128, 2, 3, 0), 682 PLL_36XX_RATE(144000000, 96, 2, 3, 0), 683 PLL_36XX_RATE( 96000000, 128, 2, 4, 0), 684 PLL_36XX_RATE( 84000000, 112, 2, 4, 0), 685 PLL_36XX_RATE( 80000004, 106, 2, 4, 43691), 686 PLL_36XX_RATE( 73728000, 98, 2, 4, 19923), 687 PLL_36XX_RATE( 67737598, 270, 3, 5, 62285), 688 PLL_36XX_RATE( 65535999, 174, 2, 5, 49982), 689 PLL_36XX_RATE( 50000000, 200, 3, 5, 0), 690 PLL_36XX_RATE( 49152002, 131, 2, 5, 4719), 691 PLL_36XX_RATE( 48000000, 128, 2, 5, 0), 692 PLL_36XX_RATE( 45158401, 180, 3, 5, 41524), 693 { /* sentinel */ } 694 }; 695 696 /* VPLL */ 697 static struct samsung_pll_rate_table exynos3250_vpll_rates[] = { 698 PLL_36XX_RATE(600000000, 100, 2, 1, 0), 699 PLL_36XX_RATE(533000000, 266, 3, 2, 32768), 700 PLL_36XX_RATE(519230987, 173, 2, 2, 5046), 701 PLL_36XX_RATE(500000000, 250, 3, 2, 0), 702 PLL_36XX_RATE(445500000, 148, 2, 2, 32768), 703 PLL_36XX_RATE(445055007, 148, 2, 2, 23047), 704 PLL_36XX_RATE(400000000, 200, 3, 2, 0), 705 PLL_36XX_RATE(371250000, 123, 2, 2, 49152), 706 PLL_36XX_RATE(370878997, 185, 3, 2, 28803), 707 PLL_36XX_RATE(340000000, 170, 3, 2, 0), 708 PLL_36XX_RATE(335000015, 111, 2, 2, 43691), 709 PLL_36XX_RATE(333000000, 111, 2, 2, 0), 710 PLL_36XX_RATE(330000000, 110, 2, 2, 0), 711 PLL_36XX_RATE(320000015, 106, 2, 2, 43691), 712 PLL_36XX_RATE(300000000, 100, 2, 2, 0), 713 PLL_36XX_RATE(275000000, 275, 3, 3, 0), 714 PLL_36XX_RATE(222750000, 148, 2, 3, 32768), 715 PLL_36XX_RATE(222528007, 148, 2, 3, 23069), 716 PLL_36XX_RATE(160000000, 160, 3, 3, 0), 717 PLL_36XX_RATE(148500000, 99, 2, 3, 0), 718 PLL_36XX_RATE(148352005, 98, 2, 3, 59070), 719 PLL_36XX_RATE(108000000, 144, 2, 4, 0), 720 PLL_36XX_RATE( 74250000, 99, 2, 4, 0), 721 PLL_36XX_RATE( 74176002, 98, 3, 4, 59070), 722 PLL_36XX_RATE( 54054000, 216, 3, 5, 14156), 723 PLL_36XX_RATE( 54000000, 144, 2, 5, 0), 724 { /* sentinel */ } 725 }; 726 727 static struct samsung_pll_clock exynos3250_plls[] __initdata = { 728 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 729 APLL_LOCK, APLL_CON0, exynos3250_pll_rates), 730 PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 731 MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates), 732 PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", 733 VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates), 734 PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll", 735 UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates), 736 }; 737 738 static void __init exynos3_core_down_clock(void __iomem *reg_base) 739 { 740 unsigned int tmp; 741 742 /* 743 * Enable arm clock down (in idle) and set arm divider 744 * ratios in WFI/WFE state. 745 */ 746 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) | 747 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN | 748 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE | 749 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI); 750 __raw_writel(tmp, reg_base + PWR_CTRL1); 751 752 /* 753 * Disable the clock up feature on Exynos4x12, in case it was 754 * enabled by bootloader. 755 */ 756 __raw_writel(0x0, reg_base + PWR_CTRL2); 757 } 758 759 static struct samsung_cmu_info cmu_info __initdata = { 760 .pll_clks = exynos3250_plls, 761 .nr_pll_clks = ARRAY_SIZE(exynos3250_plls), 762 .mux_clks = mux_clks, 763 .nr_mux_clks = ARRAY_SIZE(mux_clks), 764 .div_clks = div_clks, 765 .nr_div_clks = ARRAY_SIZE(div_clks), 766 .gate_clks = gate_clks, 767 .nr_gate_clks = ARRAY_SIZE(gate_clks), 768 .fixed_factor_clks = fixed_factor_clks, 769 .nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks), 770 .nr_clk_ids = CLK_NR_CLKS, 771 .clk_regs = exynos3250_cmu_clk_regs, 772 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs), 773 }; 774 775 static void __init exynos3250_cmu_init(struct device_node *np) 776 { 777 struct samsung_clk_provider *ctx; 778 779 ctx = samsung_cmu_register_one(np, &cmu_info); 780 if (!ctx) 781 return; 782 783 exynos3_core_down_clock(ctx->reg_base); 784 } 785 CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); 786 787 /* 788 * CMU DMC 789 */ 790 791 #define BPLL_LOCK 0x0118 792 #define BPLL_CON0 0x0218 793 #define BPLL_CON1 0x021c 794 #define BPLL_CON2 0x0220 795 #define SRC_DMC 0x0300 796 #define DIV_DMC1 0x0504 797 #define GATE_BUS_DMC0 0x0700 798 #define GATE_BUS_DMC1 0x0704 799 #define GATE_BUS_DMC2 0x0708 800 #define GATE_BUS_DMC3 0x070c 801 #define GATE_SCLK_DMC 0x0800 802 #define GATE_IP_DMC0 0x0900 803 #define GATE_IP_DMC1 0x0904 804 #define EPLL_LOCK 0x1110 805 #define EPLL_CON0 0x1114 806 #define EPLL_CON1 0x1118 807 #define EPLL_CON2 0x111c 808 #define SRC_EPLL 0x1120 809 810 static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = { 811 BPLL_LOCK, 812 BPLL_CON0, 813 BPLL_CON1, 814 BPLL_CON2, 815 SRC_DMC, 816 DIV_DMC1, 817 GATE_BUS_DMC0, 818 GATE_BUS_DMC1, 819 GATE_BUS_DMC2, 820 GATE_BUS_DMC3, 821 GATE_SCLK_DMC, 822 GATE_IP_DMC0, 823 GATE_IP_DMC1, 824 EPLL_LOCK, 825 EPLL_CON0, 826 EPLL_CON1, 827 EPLL_CON2, 828 SRC_EPLL, 829 }; 830 831 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; 832 PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", }; 833 PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", }; 834 PNAME(mout_dphy_p) = { "mout_mpll_mif", "mout_bpll", }; 835 836 static struct samsung_mux_clock dmc_mux_clks[] __initdata = { 837 /* 838 * NOTE: Following table is sorted by register address in ascending 839 * order and then bitfield shift in descending order, as it is done 840 * in the User's Manual. When adding new entries, please make sure 841 * that the order is preserved, to avoid merge conflicts and make 842 * further work with defined data easier. 843 */ 844 845 /* SRC_DMC */ 846 MUX(CLK_MOUT_MPLL_MIF, "mout_mpll_mif", mout_mpll_mif_p, SRC_DMC, 12, 1), 847 MUX(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1), 848 MUX(CLK_MOUT_DPHY, "mout_dphy", mout_dphy_p, SRC_DMC, 8, 1), 849 MUX(CLK_MOUT_DMC_BUS, "mout_dmc_bus", mout_dphy_p, SRC_DMC, 4, 1), 850 851 /* SRC_EPLL */ 852 MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1), 853 }; 854 855 static struct samsung_div_clock dmc_div_clks[] __initdata = { 856 /* 857 * NOTE: Following table is sorted by register address in ascending 858 * order and then bitfield shift in descending order, as it is done 859 * in the User's Manual. When adding new entries, please make sure 860 * that the order is preserved, to avoid merge conflicts and make 861 * further work with defined data easier. 862 */ 863 864 /* DIV_DMC1 */ 865 DIV(CLK_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3), 866 DIV(CLK_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3), 867 DIV(CLK_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", DIV_DMC1, 19, 2), 868 DIV(CLK_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3), 869 DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3), 870 }; 871 872 static struct samsung_pll_clock exynos3250_dmc_plls[] __initdata = { 873 PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", 874 BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates), 875 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 876 EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates), 877 }; 878 879 static struct samsung_cmu_info dmc_cmu_info __initdata = { 880 .pll_clks = exynos3250_dmc_plls, 881 .nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls), 882 .mux_clks = dmc_mux_clks, 883 .nr_mux_clks = ARRAY_SIZE(dmc_mux_clks), 884 .div_clks = dmc_div_clks, 885 .nr_div_clks = ARRAY_SIZE(dmc_div_clks), 886 .nr_clk_ids = NR_CLKS_DMC, 887 .clk_regs = exynos3250_cmu_dmc_clk_regs, 888 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs), 889 }; 890 891 static void __init exynos3250_cmu_dmc_init(struct device_node *np) 892 { 893 samsung_cmu_register_one(np, &dmc_cmu_info); 894 } 895 CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc", 896 exynos3250_cmu_dmc_init); 897 898 899 /* 900 * CMU ISP 901 */ 902 903 #define DIV_ISP0 0x300 904 #define DIV_ISP1 0x304 905 #define GATE_IP_ISP0 0x800 906 #define GATE_IP_ISP1 0x804 907 #define GATE_SCLK_ISP 0x900 908 909 static struct samsung_div_clock isp_div_clks[] __initdata = { 910 /* 911 * NOTE: Following table is sorted by register address in ascending 912 * order and then bitfield shift in descending order, as it is done 913 * in the User's Manual. When adding new entries, please make sure 914 * that the order is preserved, to avoid merge conflicts and make 915 * further work with defined data easier. 916 */ 917 /* DIV_ISP0 */ 918 DIV(CLK_DIV_ISP1, "div_isp1", "mout_aclk_266_sub", DIV_ISP0, 4, 3), 919 DIV(CLK_DIV_ISP0, "div_isp0", "mout_aclk_266_sub", DIV_ISP0, 0, 3), 920 921 /* DIV_ISP1 */ 922 DIV(CLK_DIV_MCUISP1, "div_mcuisp1", "mout_aclk_400_mcuisp_sub", 923 DIV_ISP1, 8, 3), 924 DIV(CLK_DIV_MCUISP0, "div_mcuisp0", "mout_aclk_400_mcuisp_sub", 925 DIV_ISP1, 4, 3), 926 DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3), 927 }; 928 929 static struct samsung_gate_clock isp_gate_clks[] __initdata = { 930 /* 931 * NOTE: Following table is sorted by register address in ascending 932 * order and then bitfield shift in descending order, as it is done 933 * in the User's Manual. When adding new entries, please make sure 934 * that the order is preserved, to avoid merge conflicts and make 935 * further work with defined data easier. 936 */ 937 938 /* GATE_IP_ISP0 */ 939 GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top", 940 GATE_IP_ISP0, 31, CLK_IGNORE_UNUSED, 0), 941 GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub", 942 GATE_IP_ISP0, 30, CLK_IGNORE_UNUSED, 0), 943 GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub", 944 GATE_IP_ISP0, 28, CLK_IGNORE_UNUSED, 0), 945 GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub", 946 GATE_IP_ISP0, 26, CLK_IGNORE_UNUSED, 0), 947 GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub", 948 GATE_IP_ISP0, 25, CLK_IGNORE_UNUSED, 0), 949 GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub", 950 GATE_IP_ISP0, 24, CLK_IGNORE_UNUSED, 0), 951 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub", 952 GATE_IP_ISP0, 23, CLK_IGNORE_UNUSED, 0), 953 GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub", 954 GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0), 955 GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub", 956 GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0), 957 GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub", 958 GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0), 959 GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub", 960 GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0), 961 GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub", 962 GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0), 963 GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub", 964 GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0), 965 GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub", 966 GATE_IP_ISP0, 14, CLK_IGNORE_UNUSED, 0), 967 GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub", 968 GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0), 969 GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub", 970 GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0), 971 GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub", 972 GATE_IP_ISP0, 11, CLK_IGNORE_UNUSED, 0), 973 GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub", 974 GATE_IP_ISP0, 10, CLK_IGNORE_UNUSED, 0), 975 GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub", 976 GATE_IP_ISP0, 9, CLK_IGNORE_UNUSED, 0), 977 GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub", 978 GATE_IP_ISP0, 8, CLK_IGNORE_UNUSED, 0), 979 GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub", 980 GATE_IP_ISP0, 7, CLK_IGNORE_UNUSED, 0), 981 GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub", 982 GATE_IP_ISP0, 6, CLK_IGNORE_UNUSED, 0), 983 GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub", 984 GATE_IP_ISP0, 5, CLK_IGNORE_UNUSED, 0), 985 GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub", 986 GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0), 987 GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub", 988 GATE_IP_ISP0, 3, CLK_IGNORE_UNUSED, 0), 989 GATE(CLK_FD, "fd", "mout_aclk_266_sub", 990 GATE_IP_ISP0, 2, CLK_IGNORE_UNUSED, 0), 991 GATE(CLK_DRC, "drc", "mout_aclk_266_sub", 992 GATE_IP_ISP0, 1, CLK_IGNORE_UNUSED, 0), 993 GATE(CLK_ISP, "isp", "mout_aclk_266_sub", 994 GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0), 995 996 /* GATE_IP_ISP1 */ 997 GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top", 998 GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0), 999 GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top", 1000 GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0), 1001 GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top", 1002 GATE_IP_ISP0, 19, CLK_IGNORE_UNUSED, 0), 1003 GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top", 1004 GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0), 1005 GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top", 1006 GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0), 1007 GATE(CLK_SCALERP, "scalerp", "uart_isp_top", 1008 GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0), 1009 GATE(CLK_SCALERC, "scalerc", "uart_isp_top", 1010 GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0), 1011 GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top", 1012 GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0), 1013 GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top", 1014 GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0), 1015 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top", 1016 GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0), 1017 GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top", 1018 GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0), 1019 1020 /* GATE_SCLK_ISP */ 1021 GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm", 1022 GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0), 1023 }; 1024 1025 static struct samsung_cmu_info isp_cmu_info __initdata = { 1026 .div_clks = isp_div_clks, 1027 .nr_div_clks = ARRAY_SIZE(isp_div_clks), 1028 .gate_clks = isp_gate_clks, 1029 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), 1030 .nr_clk_ids = NR_CLKS_ISP, 1031 }; 1032 1033 static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev) 1034 { 1035 struct device_node *np = pdev->dev.of_node; 1036 1037 samsung_cmu_register_one(np, &isp_cmu_info); 1038 return 0; 1039 } 1040 1041 static const struct of_device_id exynos3250_cmu_isp_of_match[] = { 1042 { .compatible = "samsung,exynos3250-cmu-isp", }, 1043 { /* sentinel */ } 1044 }; 1045 1046 static struct platform_driver exynos3250_cmu_isp_driver = { 1047 .driver = { 1048 .name = "exynos3250-cmu-isp", 1049 .of_match_table = exynos3250_cmu_isp_of_match, 1050 }, 1051 }; 1052 1053 static int __init exynos3250_cmu_platform_init(void) 1054 { 1055 return platform_driver_probe(&exynos3250_cmu_isp_driver, 1056 exynos3250_cmu_isp_probe); 1057 } 1058 subsys_initcall(exynos3250_cmu_platform_init); 1059 1060