1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Common Clock Framework support for Exynos3250 SoC. 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/platform_device.h> 15 #include <linux/syscore_ops.h> 16 17 #include <dt-bindings/clock/exynos3250.h> 18 19 #include "clk.h" 20 #include "clk-cpu.h" 21 #include "clk-pll.h" 22 23 #define SRC_LEFTBUS 0x4200 24 #define DIV_LEFTBUS 0x4500 25 #define GATE_IP_LEFTBUS 0x4800 26 #define SRC_RIGHTBUS 0x8200 27 #define DIV_RIGHTBUS 0x8500 28 #define GATE_IP_RIGHTBUS 0x8800 29 #define GATE_IP_PERIR 0x8960 30 #define MPLL_LOCK 0xc010 31 #define MPLL_CON0 0xc110 32 #define VPLL_LOCK 0xc020 33 #define VPLL_CON0 0xc120 34 #define UPLL_LOCK 0xc030 35 #define UPLL_CON0 0xc130 36 #define SRC_TOP0 0xc210 37 #define SRC_TOP1 0xc214 38 #define SRC_CAM 0xc220 39 #define SRC_MFC 0xc228 40 #define SRC_G3D 0xc22c 41 #define SRC_LCD 0xc234 42 #define SRC_ISP 0xc238 43 #define SRC_FSYS 0xc240 44 #define SRC_PERIL0 0xc250 45 #define SRC_PERIL1 0xc254 46 #define SRC_MASK_TOP 0xc310 47 #define SRC_MASK_CAM 0xc320 48 #define SRC_MASK_LCD 0xc334 49 #define SRC_MASK_ISP 0xc338 50 #define SRC_MASK_FSYS 0xc340 51 #define SRC_MASK_PERIL0 0xc350 52 #define SRC_MASK_PERIL1 0xc354 53 #define DIV_TOP 0xc510 54 #define DIV_CAM 0xc520 55 #define DIV_MFC 0xc528 56 #define DIV_G3D 0xc52c 57 #define DIV_LCD 0xc534 58 #define DIV_ISP 0xc538 59 #define DIV_FSYS0 0xc540 60 #define DIV_FSYS1 0xc544 61 #define DIV_FSYS2 0xc548 62 #define DIV_PERIL0 0xc550 63 #define DIV_PERIL1 0xc554 64 #define DIV_PERIL3 0xc55c 65 #define DIV_PERIL4 0xc560 66 #define DIV_PERIL5 0xc564 67 #define DIV_CAM1 0xc568 68 #define CLKDIV2_RATIO 0xc580 69 #define GATE_SCLK_CAM 0xc820 70 #define GATE_SCLK_MFC 0xc828 71 #define GATE_SCLK_G3D 0xc82c 72 #define GATE_SCLK_LCD 0xc834 73 #define GATE_SCLK_ISP_TOP 0xc838 74 #define GATE_SCLK_FSYS 0xc840 75 #define GATE_SCLK_PERIL 0xc850 76 #define GATE_IP_CAM 0xc920 77 #define GATE_IP_MFC 0xc928 78 #define GATE_IP_G3D 0xc92c 79 #define GATE_IP_LCD 0xc934 80 #define GATE_IP_ISP 0xc938 81 #define GATE_IP_FSYS 0xc940 82 #define GATE_IP_PERIL 0xc950 83 #define GATE_BLOCK 0xc970 84 #define APLL_LOCK 0x14000 85 #define APLL_CON0 0x14100 86 #define SRC_CPU 0x14200 87 #define DIV_CPU0 0x14500 88 #define DIV_CPU1 0x14504 89 #define PWR_CTRL1 0x15020 90 #define PWR_CTRL2 0x15024 91 92 /* Below definitions are used for PWR_CTRL settings */ 93 #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28) 94 #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16) 95 #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) 96 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) 97 #define PWR_CTRL1_USE_CORE3_WFE (1 << 7) 98 #define PWR_CTRL1_USE_CORE2_WFE (1 << 6) 99 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5) 100 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4) 101 #define PWR_CTRL1_USE_CORE3_WFI (1 << 3) 102 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2) 103 #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) 104 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) 105 106 static unsigned long exynos3250_cmu_clk_regs[] __initdata = { 107 SRC_LEFTBUS, 108 DIV_LEFTBUS, 109 GATE_IP_LEFTBUS, 110 SRC_RIGHTBUS, 111 DIV_RIGHTBUS, 112 GATE_IP_RIGHTBUS, 113 GATE_IP_PERIR, 114 MPLL_LOCK, 115 MPLL_CON0, 116 VPLL_LOCK, 117 VPLL_CON0, 118 UPLL_LOCK, 119 UPLL_CON0, 120 SRC_TOP0, 121 SRC_TOP1, 122 SRC_CAM, 123 SRC_MFC, 124 SRC_G3D, 125 SRC_LCD, 126 SRC_ISP, 127 SRC_FSYS, 128 SRC_PERIL0, 129 SRC_PERIL1, 130 SRC_MASK_TOP, 131 SRC_MASK_CAM, 132 SRC_MASK_LCD, 133 SRC_MASK_ISP, 134 SRC_MASK_FSYS, 135 SRC_MASK_PERIL0, 136 SRC_MASK_PERIL1, 137 DIV_TOP, 138 DIV_CAM, 139 DIV_MFC, 140 DIV_G3D, 141 DIV_LCD, 142 DIV_ISP, 143 DIV_FSYS0, 144 DIV_FSYS1, 145 DIV_FSYS2, 146 DIV_PERIL0, 147 DIV_PERIL1, 148 DIV_PERIL3, 149 DIV_PERIL4, 150 DIV_PERIL5, 151 DIV_CAM1, 152 CLKDIV2_RATIO, 153 GATE_SCLK_CAM, 154 GATE_SCLK_MFC, 155 GATE_SCLK_G3D, 156 GATE_SCLK_LCD, 157 GATE_SCLK_ISP_TOP, 158 GATE_SCLK_FSYS, 159 GATE_SCLK_PERIL, 160 GATE_IP_CAM, 161 GATE_IP_MFC, 162 GATE_IP_G3D, 163 GATE_IP_LCD, 164 GATE_IP_ISP, 165 GATE_IP_FSYS, 166 GATE_IP_PERIL, 167 GATE_BLOCK, 168 APLL_LOCK, 169 SRC_CPU, 170 DIV_CPU0, 171 DIV_CPU1, 172 PWR_CTRL1, 173 PWR_CTRL2, 174 }; 175 176 /* list of all parent clock list */ 177 PNAME(mout_vpllsrc_p) = { "fin_pll", }; 178 179 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 180 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; 181 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", }; 182 PNAME(mout_upll_p) = { "fin_pll", "fout_upll", }; 183 184 PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", }; 185 PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", }; 186 PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", }; 187 PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", }; 188 189 PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", }; 190 PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_vpll", }; 191 192 PNAME(mout_gdl_p) = { "mout_mpll_user_l", }; 193 PNAME(mout_gdr_p) = { "mout_mpll_user_r", }; 194 195 PNAME(mout_aclk_400_mcuisp_sub_p) 196 = { "fin_pll", "div_aclk_400_mcuisp", }; 197 PNAME(mout_aclk_266_0_p) = { "div_mpll_pre", "mout_vpll", }; 198 PNAME(mout_aclk_266_1_p) = { "mout_epll_user", }; 199 PNAME(mout_aclk_266_p) = { "mout_aclk_266_0", "mout_aclk_266_1", }; 200 PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", }; 201 202 PNAME(group_div_mpll_pre_p) = { "div_mpll_pre", }; 203 PNAME(group_epll_vpll_p) = { "mout_epll_user", "mout_vpll" }; 204 PNAME(group_sclk_p) = { "xxti", "xusbxti", 205 "none", "none", 206 "none", "none", "div_mpll_pre", 207 "mout_epll_user", "mout_vpll", }; 208 PNAME(group_sclk_audio_p) = { "audiocdclk", "none", 209 "none", "none", 210 "xxti", "xusbxti", 211 "div_mpll_pre", "mout_epll_user", 212 "mout_vpll", }; 213 PNAME(group_sclk_cam_blk_p) = { "xxti", "xusbxti", 214 "none", "none", "none", 215 "none", "div_mpll_pre", 216 "mout_epll_user", "mout_vpll", 217 "none", "none", "none", 218 "div_cam_blk_320", }; 219 PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti", 220 "m_bitclkhsdiv4_2l", "none", 221 "none", "none", "div_mpll_pre", 222 "mout_epll_user", "mout_vpll", 223 "none", "none", "none", 224 "div_lcd_blk_145", }; 225 226 PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" }; 227 PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" }; 228 229 static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = { 230 FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0), 231 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0), 232 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0), 233 FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0), 234 FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0), 235 236 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */ 237 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0), 238 }; 239 240 static struct samsung_mux_clock mux_clks[] __initdata = { 241 /* 242 * NOTE: Following table is sorted by register address in ascending 243 * order and then bitfield shift in descending order, as it is done 244 * in the User's Manual. When adding new entries, please make sure 245 * that the order is preserved, to avoid merge conflicts and make 246 * further work with defined data easier. 247 */ 248 249 /* SRC_LEFTBUS */ 250 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p, 251 SRC_LEFTBUS, 4, 1), 252 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1), 253 254 /* SRC_RIGHTBUS */ 255 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p, 256 SRC_RIGHTBUS, 4, 1), 257 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1), 258 259 /* SRC_TOP0 */ 260 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1), 261 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1), 262 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1), 263 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1), 264 MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1), 265 MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1), 266 MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1), 267 MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1), 268 MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1), 269 MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1), 270 271 /* SRC_TOP1 */ 272 MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1), 273 MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p, 274 SRC_TOP1, 24, 1), 275 MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1), 276 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1), 277 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1), 278 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), 279 280 /* SRC_CAM */ 281 MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4), 282 MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4), 283 284 /* SRC_MFC */ 285 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), 286 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1), 287 MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1), 288 289 /* SRC_G3D */ 290 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1), 291 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1), 292 MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1), 293 294 /* SRC_LCD */ 295 MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4), 296 MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4), 297 298 /* SRC_ISP */ 299 MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4), 300 MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4), 301 MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4), 302 303 /* SRC_FSYS */ 304 MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4), 305 MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4), 306 MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), 307 308 /* SRC_PERIL0 */ 309 MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4), 310 MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4), 311 312 /* SRC_PERIL1 */ 313 MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4), 314 MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4), 315 MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4), 316 317 /* SRC_CPU */ 318 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p, 319 SRC_CPU, 24, 1), 320 MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1), 321 MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, 322 CLK_SET_RATE_PARENT, 0), 323 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 324 CLK_SET_RATE_PARENT, 0), 325 }; 326 327 static struct samsung_div_clock div_clks[] __initdata = { 328 /* 329 * NOTE: Following table is sorted by register address in ascending 330 * order and then bitfield shift in descending order, as it is done 331 * in the User's Manual. When adding new entries, please make sure 332 * that the order is preserved, to avoid merge conflicts and make 333 * further work with defined data easier. 334 */ 335 336 /* DIV_LEFTBUS */ 337 DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3), 338 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4), 339 340 /* DIV_RIGHTBUS */ 341 DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3), 342 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4), 343 344 /* DIV_TOP */ 345 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2), 346 DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp", 347 "mout_aclk_400_mcuisp", DIV_TOP, 24, 3), 348 DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3), 349 DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3), 350 DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3), 351 DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4), 352 DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3), 353 354 /* DIV_CAM */ 355 DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), 356 DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4), 357 358 /* DIV_MFC */ 359 DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4), 360 361 /* DIV_G3D */ 362 DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4), 363 364 /* DIV_LCD */ 365 DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4, 366 CLK_SET_RATE_PARENT, 0), 367 DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4), 368 DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4), 369 370 /* DIV_ISP */ 371 DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4), 372 DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp", 373 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0), 374 DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4), 375 DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp", 376 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0), 377 DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4), 378 379 /* DIV_FSYS0 */ 380 DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8, 381 CLK_SET_RATE_PARENT, 0), 382 DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4), 383 384 /* DIV_FSYS1 */ 385 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8, 386 CLK_SET_RATE_PARENT, 0), 387 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 388 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8, 389 CLK_SET_RATE_PARENT, 0), 390 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 391 392 /* DIV_PERIL0 */ 393 DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 394 DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 395 396 /* DIV_PERIL1 */ 397 DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8, 398 CLK_SET_RATE_PARENT, 0), 399 DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), 400 DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8, 401 CLK_SET_RATE_PARENT, 0), 402 DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), 403 404 /* DIV_PERIL4 */ 405 DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8), 406 DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4), 407 408 /* DIV_PERIL5 */ 409 DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6), 410 411 /* DIV_CPU0 */ 412 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3), 413 DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3), 414 DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3), 415 DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3), 416 DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3), 417 DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3), 418 419 /* DIV_CPU1 */ 420 DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3), 421 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), 422 }; 423 424 static struct samsung_gate_clock gate_clks[] __initdata = { 425 /* 426 * NOTE: Following table is sorted by register address in ascending 427 * order and then bitfield shift in descending order, as it is done 428 * in the User's Manual. When adding new entries, please make sure 429 * that the order is preserved, to avoid merge conflicts and make 430 * further work with defined data easier. 431 */ 432 433 /* GATE_IP_LEFTBUS */ 434 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6, 435 CLK_IGNORE_UNUSED, 0), 436 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4, 437 CLK_IGNORE_UNUSED, 0), 438 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1, 439 CLK_IGNORE_UNUSED, 0), 440 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0, 441 CLK_IGNORE_UNUSED, 0), 442 443 /* GATE_IP_RIGHTBUS */ 444 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100", 445 GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0), 446 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100", 447 GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0), 448 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100", 449 GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0), 450 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2, 451 CLK_IGNORE_UNUSED, 0), 452 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1, 453 CLK_IGNORE_UNUSED, 0), 454 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0, 455 CLK_IGNORE_UNUSED, 0), 456 457 /* GATE_IP_PERIR */ 458 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22, 459 CLK_IGNORE_UNUSED, 0), 460 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21, 461 CLK_IGNORE_UNUSED, 0), 462 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100", 463 GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0), 464 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100", 465 GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0), 466 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18, 467 CLK_IGNORE_UNUSED, 0), 468 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100", 469 GATE_IP_PERIR, 17, 0, 0), 470 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0), 471 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0), 472 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0), 473 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0), 474 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12, 475 CLK_IGNORE_UNUSED, 0), 476 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10, 477 CLK_IGNORE_UNUSED, 0), 478 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9, 479 CLK_IGNORE_UNUSED, 0), 480 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8, 481 CLK_IGNORE_UNUSED, 0), 482 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7, 483 CLK_IGNORE_UNUSED, 0), 484 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6, 485 CLK_IGNORE_UNUSED, 0), 486 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5, 487 CLK_IGNORE_UNUSED, 0), 488 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4, 489 CLK_IGNORE_UNUSED, 0), 490 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3, 491 CLK_IGNORE_UNUSED, 0), 492 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2, 493 CLK_IGNORE_UNUSED, 0), 494 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1, 495 CLK_IGNORE_UNUSED, 0), 496 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0, 497 CLK_IGNORE_UNUSED, 0), 498 499 /* GATE_SCLK_CAM */ 500 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk", 501 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0), 502 GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk", 503 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0), 504 GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk", 505 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0), 506 GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk", 507 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0), 508 509 /* GATE_SCLK_MFC */ 510 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc", 511 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0), 512 513 /* GATE_SCLK_G3D */ 514 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", 515 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0), 516 517 /* GATE_SCLK_LCD */ 518 GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0", 519 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0), 520 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre", 521 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0), 522 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", 523 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0), 524 525 /* GATE_SCLK_ISP_TOP */ 526 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", 527 GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0), 528 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp", 529 GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0), 530 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp", 531 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0), 532 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp", 533 GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0), 534 535 /* GATE_SCLK_FSYS */ 536 GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0), 537 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre", 538 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 539 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi", 540 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0), 541 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre", 542 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 543 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre", 544 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 545 546 /* GATE_SCLK_PERIL */ 547 GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s", 548 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0), 549 GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm", 550 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0), 551 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre", 552 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0), 553 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre", 554 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0), 555 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", 556 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0), 557 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", 558 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0), 559 560 /* GATE_IP_CAM */ 561 GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19, 562 CLK_IGNORE_UNUSED, 0), 563 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320", 564 GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0), 565 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320", 566 GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0), 567 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320", 568 GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0), 569 GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320", 570 GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0), 571 GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320", 572 GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0), 573 GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320", 574 GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0), 575 GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320", 576 GATE_IP_CAM, 11, 0, 0), 577 GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320", 578 GATE_IP_CAM, 9, 0, 0), 579 GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320", 580 GATE_IP_CAM, 8, 0, 0), 581 GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320", 582 GATE_IP_CAM, 7, 0, 0), 583 GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0), 584 GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320", 585 GATE_IP_CAM, 2, 0, 0), 586 GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0), 587 GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0), 588 589 /* GATE_IP_MFC */ 590 GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5, 591 CLK_IGNORE_UNUSED, 0), 592 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3, 593 CLK_IGNORE_UNUSED, 0), 594 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0), 595 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0), 596 597 /* GATE_IP_G3D */ 598 GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0), 599 GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2, 600 CLK_IGNORE_UNUSED, 0), 601 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1, 602 CLK_IGNORE_UNUSED, 0), 603 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0), 604 605 /* GATE_IP_LCD */ 606 GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7, 607 CLK_IGNORE_UNUSED, 0), 608 GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6, 609 CLK_IGNORE_UNUSED, 0), 610 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5, 611 CLK_IGNORE_UNUSED, 0), 612 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0), 613 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0), 614 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0), 615 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0), 616 617 /* GATE_IP_ISP */ 618 GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0), 619 GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub", 620 GATE_IP_ISP, 3, 0, 0), 621 GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub", 622 GATE_IP_ISP, 2, 0, 0), 623 GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub", 624 GATE_IP_ISP, 1, 0, 0), 625 626 /* GATE_IP_FSYS */ 627 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0), 628 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17, 629 CLK_IGNORE_UNUSED, 0), 630 GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0), 631 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0), 632 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0), 633 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0), 634 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0), 635 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0), 636 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0), 637 638 /* GATE_IP_PERIL */ 639 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0), 640 GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0), 641 GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0), 642 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0), 643 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0), 644 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0), 645 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0), 646 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0), 647 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0), 648 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0), 649 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0), 650 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0), 651 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0), 652 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0), 653 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0), 654 }; 655 656 /* APLL & MPLL & BPLL & UPLL */ 657 static struct samsung_pll_rate_table exynos3250_pll_rates[] = { 658 PLL_35XX_RATE(1200000000, 400, 4, 1), 659 PLL_35XX_RATE(1100000000, 275, 3, 1), 660 PLL_35XX_RATE(1066000000, 533, 6, 1), 661 PLL_35XX_RATE(1000000000, 250, 3, 1), 662 PLL_35XX_RATE( 960000000, 320, 4, 1), 663 PLL_35XX_RATE( 900000000, 300, 4, 1), 664 PLL_35XX_RATE( 850000000, 425, 6, 1), 665 PLL_35XX_RATE( 800000000, 200, 3, 1), 666 PLL_35XX_RATE( 700000000, 175, 3, 1), 667 PLL_35XX_RATE( 667000000, 667, 12, 1), 668 PLL_35XX_RATE( 600000000, 400, 4, 2), 669 PLL_35XX_RATE( 533000000, 533, 6, 2), 670 PLL_35XX_RATE( 520000000, 260, 3, 2), 671 PLL_35XX_RATE( 500000000, 250, 3, 2), 672 PLL_35XX_RATE( 400000000, 200, 3, 2), 673 PLL_35XX_RATE( 200000000, 200, 3, 3), 674 PLL_35XX_RATE( 100000000, 200, 3, 4), 675 { /* sentinel */ } 676 }; 677 678 /* EPLL */ 679 static struct samsung_pll_rate_table exynos3250_epll_rates[] = { 680 PLL_36XX_RATE(800000000, 200, 3, 1, 0), 681 PLL_36XX_RATE(288000000, 96, 2, 2, 0), 682 PLL_36XX_RATE(192000000, 128, 2, 3, 0), 683 PLL_36XX_RATE(144000000, 96, 2, 3, 0), 684 PLL_36XX_RATE( 96000000, 128, 2, 4, 0), 685 PLL_36XX_RATE( 84000000, 112, 2, 4, 0), 686 PLL_36XX_RATE( 80000004, 106, 2, 4, 43691), 687 PLL_36XX_RATE( 73728000, 98, 2, 4, 19923), 688 PLL_36XX_RATE( 67737598, 270, 3, 5, 62285), 689 PLL_36XX_RATE( 65535999, 174, 2, 5, 49982), 690 PLL_36XX_RATE( 50000000, 200, 3, 5, 0), 691 PLL_36XX_RATE( 49152002, 131, 2, 5, 4719), 692 PLL_36XX_RATE( 48000000, 128, 2, 5, 0), 693 PLL_36XX_RATE( 45158401, 180, 3, 5, 41524), 694 { /* sentinel */ } 695 }; 696 697 /* VPLL */ 698 static struct samsung_pll_rate_table exynos3250_vpll_rates[] = { 699 PLL_36XX_RATE(600000000, 100, 2, 1, 0), 700 PLL_36XX_RATE(533000000, 266, 3, 2, 32768), 701 PLL_36XX_RATE(519230987, 173, 2, 2, 5046), 702 PLL_36XX_RATE(500000000, 250, 3, 2, 0), 703 PLL_36XX_RATE(445500000, 148, 2, 2, 32768), 704 PLL_36XX_RATE(445055007, 148, 2, 2, 23047), 705 PLL_36XX_RATE(400000000, 200, 3, 2, 0), 706 PLL_36XX_RATE(371250000, 123, 2, 2, 49152), 707 PLL_36XX_RATE(370878997, 185, 3, 2, 28803), 708 PLL_36XX_RATE(340000000, 170, 3, 2, 0), 709 PLL_36XX_RATE(335000015, 111, 2, 2, 43691), 710 PLL_36XX_RATE(333000000, 111, 2, 2, 0), 711 PLL_36XX_RATE(330000000, 110, 2, 2, 0), 712 PLL_36XX_RATE(320000015, 106, 2, 2, 43691), 713 PLL_36XX_RATE(300000000, 100, 2, 2, 0), 714 PLL_36XX_RATE(275000000, 275, 3, 3, 0), 715 PLL_36XX_RATE(222750000, 148, 2, 3, 32768), 716 PLL_36XX_RATE(222528007, 148, 2, 3, 23069), 717 PLL_36XX_RATE(160000000, 160, 3, 3, 0), 718 PLL_36XX_RATE(148500000, 99, 2, 3, 0), 719 PLL_36XX_RATE(148352005, 98, 2, 3, 59070), 720 PLL_36XX_RATE(108000000, 144, 2, 4, 0), 721 PLL_36XX_RATE( 74250000, 99, 2, 4, 0), 722 PLL_36XX_RATE( 74176002, 98, 3, 4, 59070), 723 PLL_36XX_RATE( 54054000, 216, 3, 5, 14156), 724 PLL_36XX_RATE( 54000000, 144, 2, 5, 0), 725 { /* sentinel */ } 726 }; 727 728 static struct samsung_pll_clock exynos3250_plls[] __initdata = { 729 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 730 APLL_LOCK, APLL_CON0, exynos3250_pll_rates), 731 PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 732 MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates), 733 PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", 734 VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates), 735 PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll", 736 UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates), 737 }; 738 739 static void __init exynos3_core_down_clock(void __iomem *reg_base) 740 { 741 unsigned int tmp; 742 743 /* 744 * Enable arm clock down (in idle) and set arm divider 745 * ratios in WFI/WFE state. 746 */ 747 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) | 748 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN | 749 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE | 750 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI); 751 __raw_writel(tmp, reg_base + PWR_CTRL1); 752 753 /* 754 * Disable the clock up feature on Exynos4x12, in case it was 755 * enabled by bootloader. 756 */ 757 __raw_writel(0x0, reg_base + PWR_CTRL2); 758 } 759 760 static struct samsung_cmu_info cmu_info __initdata = { 761 .pll_clks = exynos3250_plls, 762 .nr_pll_clks = ARRAY_SIZE(exynos3250_plls), 763 .mux_clks = mux_clks, 764 .nr_mux_clks = ARRAY_SIZE(mux_clks), 765 .div_clks = div_clks, 766 .nr_div_clks = ARRAY_SIZE(div_clks), 767 .gate_clks = gate_clks, 768 .nr_gate_clks = ARRAY_SIZE(gate_clks), 769 .fixed_factor_clks = fixed_factor_clks, 770 .nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks), 771 .nr_clk_ids = CLK_NR_CLKS, 772 .clk_regs = exynos3250_cmu_clk_regs, 773 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs), 774 }; 775 776 #define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \ 777 (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 778 ((corem) << 4)) 779 #define E3250_CPU_DIV1(hpm, copy) \ 780 (((hpm) << 4) | ((copy) << 0)) 781 782 static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = { 783 { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), }, 784 { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, 785 { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, 786 { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, 787 { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, 788 { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, 789 { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, 790 { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), }, 791 { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), }, 792 { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), }, 793 { 0 }, 794 }; 795 796 static void __init exynos3250_cmu_init(struct device_node *np) 797 { 798 struct samsung_clk_provider *ctx; 799 800 ctx = samsung_cmu_register_one(np, &cmu_info); 801 if (!ctx) 802 return; 803 804 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 805 mout_core_p[0], mout_core_p[1], 0x14200, 806 e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d), 807 CLK_CPU_HAS_DIV1); 808 809 exynos3_core_down_clock(ctx->reg_base); 810 } 811 CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); 812 813 /* 814 * CMU DMC 815 */ 816 817 #define BPLL_LOCK 0x0118 818 #define BPLL_CON0 0x0218 819 #define BPLL_CON1 0x021c 820 #define BPLL_CON2 0x0220 821 #define SRC_DMC 0x0300 822 #define DIV_DMC1 0x0504 823 #define GATE_BUS_DMC0 0x0700 824 #define GATE_BUS_DMC1 0x0704 825 #define GATE_BUS_DMC2 0x0708 826 #define GATE_BUS_DMC3 0x070c 827 #define GATE_SCLK_DMC 0x0800 828 #define GATE_IP_DMC0 0x0900 829 #define GATE_IP_DMC1 0x0904 830 #define EPLL_LOCK 0x1110 831 #define EPLL_CON0 0x1114 832 #define EPLL_CON1 0x1118 833 #define EPLL_CON2 0x111c 834 #define SRC_EPLL 0x1120 835 836 static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = { 837 BPLL_LOCK, 838 BPLL_CON0, 839 BPLL_CON1, 840 BPLL_CON2, 841 SRC_DMC, 842 DIV_DMC1, 843 GATE_BUS_DMC0, 844 GATE_BUS_DMC1, 845 GATE_BUS_DMC2, 846 GATE_BUS_DMC3, 847 GATE_SCLK_DMC, 848 GATE_IP_DMC0, 849 GATE_IP_DMC1, 850 EPLL_LOCK, 851 EPLL_CON0, 852 EPLL_CON1, 853 EPLL_CON2, 854 SRC_EPLL, 855 }; 856 857 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; 858 PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", }; 859 PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", }; 860 PNAME(mout_dphy_p) = { "mout_mpll_mif", "mout_bpll", }; 861 862 static struct samsung_mux_clock dmc_mux_clks[] __initdata = { 863 /* 864 * NOTE: Following table is sorted by register address in ascending 865 * order and then bitfield shift in descending order, as it is done 866 * in the User's Manual. When adding new entries, please make sure 867 * that the order is preserved, to avoid merge conflicts and make 868 * further work with defined data easier. 869 */ 870 871 /* SRC_DMC */ 872 MUX(CLK_MOUT_MPLL_MIF, "mout_mpll_mif", mout_mpll_mif_p, SRC_DMC, 12, 1), 873 MUX(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1), 874 MUX(CLK_MOUT_DPHY, "mout_dphy", mout_dphy_p, SRC_DMC, 8, 1), 875 MUX(CLK_MOUT_DMC_BUS, "mout_dmc_bus", mout_dphy_p, SRC_DMC, 4, 1), 876 877 /* SRC_EPLL */ 878 MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1), 879 }; 880 881 static struct samsung_div_clock dmc_div_clks[] __initdata = { 882 /* 883 * NOTE: Following table is sorted by register address in ascending 884 * order and then bitfield shift in descending order, as it is done 885 * in the User's Manual. When adding new entries, please make sure 886 * that the order is preserved, to avoid merge conflicts and make 887 * further work with defined data easier. 888 */ 889 890 /* DIV_DMC1 */ 891 DIV(CLK_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3), 892 DIV(CLK_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3), 893 DIV(CLK_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", DIV_DMC1, 19, 2), 894 DIV(CLK_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3), 895 DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3), 896 }; 897 898 static struct samsung_pll_clock exynos3250_dmc_plls[] __initdata = { 899 PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", 900 BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates), 901 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 902 EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates), 903 }; 904 905 static struct samsung_cmu_info dmc_cmu_info __initdata = { 906 .pll_clks = exynos3250_dmc_plls, 907 .nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls), 908 .mux_clks = dmc_mux_clks, 909 .nr_mux_clks = ARRAY_SIZE(dmc_mux_clks), 910 .div_clks = dmc_div_clks, 911 .nr_div_clks = ARRAY_SIZE(dmc_div_clks), 912 .nr_clk_ids = NR_CLKS_DMC, 913 .clk_regs = exynos3250_cmu_dmc_clk_regs, 914 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs), 915 }; 916 917 static void __init exynos3250_cmu_dmc_init(struct device_node *np) 918 { 919 samsung_cmu_register_one(np, &dmc_cmu_info); 920 } 921 CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc", 922 exynos3250_cmu_dmc_init); 923 924 925 /* 926 * CMU ISP 927 */ 928 929 #define DIV_ISP0 0x300 930 #define DIV_ISP1 0x304 931 #define GATE_IP_ISP0 0x800 932 #define GATE_IP_ISP1 0x804 933 #define GATE_SCLK_ISP 0x900 934 935 static struct samsung_div_clock isp_div_clks[] __initdata = { 936 /* 937 * NOTE: Following table is sorted by register address in ascending 938 * order and then bitfield shift in descending order, as it is done 939 * in the User's Manual. When adding new entries, please make sure 940 * that the order is preserved, to avoid merge conflicts and make 941 * further work with defined data easier. 942 */ 943 /* DIV_ISP0 */ 944 DIV(CLK_DIV_ISP1, "div_isp1", "mout_aclk_266_sub", DIV_ISP0, 4, 3), 945 DIV(CLK_DIV_ISP0, "div_isp0", "mout_aclk_266_sub", DIV_ISP0, 0, 3), 946 947 /* DIV_ISP1 */ 948 DIV(CLK_DIV_MCUISP1, "div_mcuisp1", "mout_aclk_400_mcuisp_sub", 949 DIV_ISP1, 8, 3), 950 DIV(CLK_DIV_MCUISP0, "div_mcuisp0", "mout_aclk_400_mcuisp_sub", 951 DIV_ISP1, 4, 3), 952 DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3), 953 }; 954 955 static struct samsung_gate_clock isp_gate_clks[] __initdata = { 956 /* 957 * NOTE: Following table is sorted by register address in ascending 958 * order and then bitfield shift in descending order, as it is done 959 * in the User's Manual. When adding new entries, please make sure 960 * that the order is preserved, to avoid merge conflicts and make 961 * further work with defined data easier. 962 */ 963 964 /* GATE_IP_ISP0 */ 965 GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top", 966 GATE_IP_ISP0, 31, CLK_IGNORE_UNUSED, 0), 967 GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub", 968 GATE_IP_ISP0, 30, CLK_IGNORE_UNUSED, 0), 969 GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub", 970 GATE_IP_ISP0, 28, CLK_IGNORE_UNUSED, 0), 971 GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub", 972 GATE_IP_ISP0, 26, CLK_IGNORE_UNUSED, 0), 973 GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub", 974 GATE_IP_ISP0, 25, CLK_IGNORE_UNUSED, 0), 975 GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub", 976 GATE_IP_ISP0, 24, CLK_IGNORE_UNUSED, 0), 977 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub", 978 GATE_IP_ISP0, 23, CLK_IGNORE_UNUSED, 0), 979 GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub", 980 GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0), 981 GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub", 982 GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0), 983 GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub", 984 GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0), 985 GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub", 986 GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0), 987 GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub", 988 GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0), 989 GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub", 990 GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0), 991 GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub", 992 GATE_IP_ISP0, 14, CLK_IGNORE_UNUSED, 0), 993 GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub", 994 GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0), 995 GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub", 996 GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0), 997 GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub", 998 GATE_IP_ISP0, 11, CLK_IGNORE_UNUSED, 0), 999 GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub", 1000 GATE_IP_ISP0, 10, CLK_IGNORE_UNUSED, 0), 1001 GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub", 1002 GATE_IP_ISP0, 9, CLK_IGNORE_UNUSED, 0), 1003 GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub", 1004 GATE_IP_ISP0, 8, CLK_IGNORE_UNUSED, 0), 1005 GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub", 1006 GATE_IP_ISP0, 7, CLK_IGNORE_UNUSED, 0), 1007 GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub", 1008 GATE_IP_ISP0, 6, CLK_IGNORE_UNUSED, 0), 1009 GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub", 1010 GATE_IP_ISP0, 5, CLK_IGNORE_UNUSED, 0), 1011 GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub", 1012 GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0), 1013 GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub", 1014 GATE_IP_ISP0, 3, CLK_IGNORE_UNUSED, 0), 1015 GATE(CLK_FD, "fd", "mout_aclk_266_sub", 1016 GATE_IP_ISP0, 2, CLK_IGNORE_UNUSED, 0), 1017 GATE(CLK_DRC, "drc", "mout_aclk_266_sub", 1018 GATE_IP_ISP0, 1, CLK_IGNORE_UNUSED, 0), 1019 GATE(CLK_ISP, "isp", "mout_aclk_266_sub", 1020 GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0), 1021 1022 /* GATE_IP_ISP1 */ 1023 GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top", 1024 GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0), 1025 GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top", 1026 GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0), 1027 GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top", 1028 GATE_IP_ISP0, 19, CLK_IGNORE_UNUSED, 0), 1029 GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top", 1030 GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0), 1031 GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top", 1032 GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0), 1033 GATE(CLK_SCALERP, "scalerp", "uart_isp_top", 1034 GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0), 1035 GATE(CLK_SCALERC, "scalerc", "uart_isp_top", 1036 GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0), 1037 GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top", 1038 GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0), 1039 GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top", 1040 GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0), 1041 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top", 1042 GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0), 1043 GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top", 1044 GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0), 1045 1046 /* GATE_SCLK_ISP */ 1047 GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm", 1048 GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0), 1049 }; 1050 1051 static struct samsung_cmu_info isp_cmu_info __initdata = { 1052 .div_clks = isp_div_clks, 1053 .nr_div_clks = ARRAY_SIZE(isp_div_clks), 1054 .gate_clks = isp_gate_clks, 1055 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), 1056 .nr_clk_ids = NR_CLKS_ISP, 1057 }; 1058 1059 static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev) 1060 { 1061 struct device_node *np = pdev->dev.of_node; 1062 1063 samsung_cmu_register_one(np, &isp_cmu_info); 1064 return 0; 1065 } 1066 1067 static const struct of_device_id exynos3250_cmu_isp_of_match[] = { 1068 { .compatible = "samsung,exynos3250-cmu-isp", }, 1069 { /* sentinel */ } 1070 }; 1071 1072 static struct platform_driver exynos3250_cmu_isp_driver = { 1073 .driver = { 1074 .name = "exynos3250-cmu-isp", 1075 .of_match_table = exynos3250_cmu_isp_of_match, 1076 }, 1077 }; 1078 1079 static int __init exynos3250_cmu_platform_init(void) 1080 { 1081 return platform_driver_probe(&exynos3250_cmu_isp_driver, 1082 exynos3250_cmu_isp_probe); 1083 } 1084 subsys_initcall(exynos3250_cmu_platform_init); 1085 1086